/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: import/chips/p9/common/include/p9n2_xbus_scom_addresses_fld.H $ */
/*                                                                        */
/* OpenPOWER HCODE Project                                                */
/*                                                                        */
/* COPYRIGHT 2017                                                         */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
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/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
///
/// @file p9_xbus_scom_addresses_fld.H
/// @brief  Defines constants for scom addresses
///
// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: SOA
// *HWP Level: 3
// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE

#ifndef __P9N2_XBUS_SCOM_ADDRESSES_FLD_H
#define __P9N2_XBUS_SCOM_ADDRESSES_FLD_H

#include <stdint.h>

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_ACCESS_MODE = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_SCRUB_ENABLE = 1   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_CORRECT_DIS = 2   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_DETECT_DIS = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_INJECT_TYPE = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_INJECT_ERR = 5   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SPARE_6_7 = 6   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SPARE_6_7_LEN = 2   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_SCRUB_INDEX = 47  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_SCRUB_INDEX_LEN = 13  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ERROR = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ERROR_LEN = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_HALTED = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_WATCHDOG_TIMEOUT = 5   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_MMIO_DATA_IN = 6   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ARB_MISSED_SCRUB_TICK = 7   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ARB_ARY_UE = 8   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ARB_ARY_CE = 9   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_RESERVED = 10  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 11  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 12
        ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ERROR = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ERROR_LEN = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_HALTED = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_WATCHDOG_TIMEOUT = 5   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_MMIO_DATA_IN = 6   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ARB_MISSED_SCRUB_TICK = 7   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ARB_ARY_UE = 8   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ARB_ARY_CE = 9   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_RESERVED = 10  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_SCOMFIR_ERROR = 11  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_SCOMFIR_ERROR_CLONE = 12  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_SCOM_PPE_FLAGS_FIELD = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_SCOM_PPE_FLAGS_FIELD_LEN = 16  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSAR_SRAM_ADDRESS                = 16  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSAR_SRAM_ADDRESS_LEN            = 13  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSDR_SRAM_DATA                   = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSDR_SRAM_DATA_LEN               = 64  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_A  = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_B  = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_A  = 16  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_B  = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED       = 36  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED_LEN   = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED_2     = 43  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C1_COUNT_LT  = 52  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C2_COUNT_LT  = 56  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3   ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_TO_CMP_LT    = 20  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_A  = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_B  = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_A  = 16  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_B  = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED       = 36  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED_LEN   = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED_2     = 43  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C1_COUNT_LT  = 52  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C2_COUNT_LT  = 56  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3   ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_TO_CMP_LT    = 20  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_GLB_BRCST            = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_GLB_BRCST_LEN        = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRACE_SEL            = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRACE_SEL_LEN        = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRIG_SEL             = 6   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRIG_SEL_LEN         = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_FREEZE_SEL           = 11  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_SYNC_BRCST           = 12  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_SYNC_BRCST_LEN       = 2   ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_IMM_FREEZE   = 16  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_STOP_ON_ERR  = 17  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_FORCE_TEST   = 19  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_ACCUM_HIST   = 20  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP  = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_PC_TP_TRIG_SEL    = 44  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_ARM_SEL           = 46  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_ARM_SEL_LEN       = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL   = 50  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL   = 54  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_GCR_HANG_ERROR = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED3_7 = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED3_7_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_TRAINING_ERROR
    = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_SPARE_DEPLOYED
    = 9   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_MAX_SPARES_EXCEEDED = 10  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR = 11  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_TOO_MANY_BUS_ERRORS = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED13_15 = 13  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED13_15_LEN = 3
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_TRAINING_ERROR
    = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_SPARE_DEPLOYED
    = 17  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_MAX_SPARES_EXCEEDED = 18  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR = 19  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_TOO_MANY_BUS_ERRORS = 20  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED21_23 = 21  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED21_23_LEN = 3
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_TRAINING_ERROR
    = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_SPARE_DEPLOYED
    = 25  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_MAX_SPARES_EXCEEDED = 26  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR = 27  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_TOO_MANY_BUS_ERRORS = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED29_31 = 29  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED29_31_LEN = 3
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_TRAINING_ERROR
    = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_SPARE_DEPLOYED
    = 33  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_MAX_SPARES_EXCEEDED = 34  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR = 35  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_TOO_MANY_BUS_ERRORS = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED37_39 = 37  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED37_39_LEN = 3
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_TRAINING_ERROR
    = 40  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_SPARE_DEPLOYED
    = 41  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_MAX_SPARES_EXCEEDED = 42  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR = 43  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_TOO_MANY_BUS_ERRORS = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED45_47 = 45  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED45_47_LEN = 3
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_INTERNAL_SCOM_ERROR =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 49  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_GCR_HANG_ERROR = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED3_7 = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED3_7_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_TRAINING_ERROR = 8
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_SPARE_DEPLOYED = 9
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_MAX_SPARES_EXCEEDED
    = 10  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_TOO_MANY_BUS_ERRORS
    = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED13_15 = 13  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED13_15_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_TRAINING_ERROR = 16
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_SPARE_DEPLOYED = 17
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_MAX_SPARES_EXCEEDED
    = 18  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR = 19  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_TOO_MANY_BUS_ERRORS
    = 20  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED21_23 = 21  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED21_23_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_TRAINING_ERROR = 24
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_SPARE_DEPLOYED = 25
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_MAX_SPARES_EXCEEDED
    = 26  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR = 27  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_TOO_MANY_BUS_ERRORS
    = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED29_31 = 29  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED29_31_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_TRAINING_ERROR = 32
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_SPARE_DEPLOYED = 33
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_MAX_SPARES_EXCEEDED
    = 34  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR = 35  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_TOO_MANY_BUS_ERRORS
    = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED37_39 = 37  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED37_39_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_TRAINING_ERROR = 40
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_SPARE_DEPLOYED = 41
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_MAX_SPARES_EXCEEDED
    = 42  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR = 43  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_TOO_MANY_BUS_ERRORS
    = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED45_47 = 45  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED45_47_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_SCOMFIR_ERROR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_SCOMFIR_ERROR_CLONE = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION0_REG_ACTION0         = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION0_REG_ACTION0_LEN     = 50  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION1_REG_ACTION1         = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION1_REG_ACTION1_LEN     = 50  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_WOF_REG_WOF                 = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_WOF_REG_WOF_LEN             = 50  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN = 9   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_RESET = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_START = 58  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WTL_TEST_CLOCK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WTL_TEST_DATA = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WT_BS_CLOCK_EN_BYP = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WT_BS_DATA_EN_BYP = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_EN   = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_WIRETEST = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_DESKEW = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_EYE_OPT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_REPAIR = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_FUNC_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_DC_CALIBRATE = 53  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_WT_CU_PLL_PGOOD = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_WT_CU_BYP_PLL_LOCK = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_WT_PLL_REFCLKSEL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_PLL_REFCLKSEL_SCOM_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_IORESET   = 52  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN = 15  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_DONE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_EN  = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_VAL_GCRMSG = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_CM_CFG  = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_CM_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_A_BIST_EN = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_MASTER_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_FENCE     = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_USE_SLS_AS_SPR = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_DYN_RECAL_SUSPEND = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DDC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_BER_TEST = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_RESULT_CHECK = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_TRACK_ONLY = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H2_H12_CAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_TO_A_CAL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_FINAL_L2U_ADJ = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DONE_SIGNALING = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_BER_TEST = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_RESULT_CHECK = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H2_H12_CAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_TO_A_CAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_PEAK_TUNE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_LTE_EN  = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_IQSPD_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_IQSPD_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_DFEHISPD_EN = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_DFE12_EN = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_VOLTAGE_MODE = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H6_H12_FAST_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_VOLTAGE_MODE = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H6_H12_FAST_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_CAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_TO_A_CAL = 54  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_SERVO_THRESH3 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_SERVO_THRESH3_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_DISABLE_2TO12_CLEAR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_PEAK_ENABLE_DAC_CFG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_AMIN_ENABLE_HDAC = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_USE_PREV_COARSE_VAL = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PSAVE_TIMER_WAKEUP_MODE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PSAVE_WAKEUP_LANE0_ENABLE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_DISABLE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_TX_SLS_DISABLE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_CLR_ERR_CNTR1 = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_DISABLE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_CLR_ERR_CNTR2 = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_DISABLE2 = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_WIRETEST_DONE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_DESKEW_DONE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_EYE_OPT_DONE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_REPAIR_DONE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_FUNC_MODE_DONE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_DC_CALIBRATE_DONE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_WIRETEST_FAILED = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_DESKEW_FAILED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_EYE_OPT_FAILED = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_REPAIR_FAILED = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_DONE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_CU_PLL_ERR = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_INVERTED = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG = 52  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SEED_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_RATE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_RUN_DYN_RECAL_TIMER = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_HALF_RATE_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_BLOCK_ERROR = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL = 49
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL = 50
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL = 51
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL
    = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_0   = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_1   = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_2   = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_3   = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_4   = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_5   = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_6   = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_7   = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN = 7
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL =
    60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN = 16
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN = 16
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_PRBS_DATA_RCV_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_PG_PRBS_SEED_DONE_RO_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN = 15  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_MASK_PG_ERRS        = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_MASK_PG_ERRS_LEN    = 15  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_MASK_PG_ERRS        = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_MASK_PG_ERRS_LEN    = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_ERROR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_STATIC_MAX_SPARES_EXCEEDED = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_REPAIR_ERROR = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_SPARE_DEPLOYED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_ERROR = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_SPARE_DEPLOYED = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_MAX_SPARES_EXCEEDED = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_TOO_MANY_BUS_ERRORS = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_ERROR    = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_STATIC_SPARE_DEPLOYED = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_STATIC_MAX_SPARES_EXCEEDED = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_REPAIR_ERROR = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_SPARE_DEPLOYED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_RECAL_ERROR = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_RECAL_SPARE_DEPLOYED = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_RECAL_MAX_SPARES_EXCEEDED = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_TOO_MANY_BUS_ERRORS = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_REQ_MANUAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_SM_MANUAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_DIS_SYND_TALLYING = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_HALF_RATE_MODE = 58  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL
    = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_DESKEW_SKIP_OFFSET = 56  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_0    = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_1    = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_2    = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_3    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_4    = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_5    = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_6    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_7    = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_DESKEW_BUMP_AFTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_SLS_HNDSHK_DISABLE = 58  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG_SLS_CMD_VAL_HLD = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WT_CU_PLL_LOCK_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL = 48
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_VAL_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_NONSLS_CMD_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_REPAIR_REQ_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_USED_AS_SPR_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE1 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE1_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE2 = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE2_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID1_PG_BUS_ID            = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID1_PG_BUS_ID_LEN        = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_START_LANE_ID     = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_START_LANE_ID_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_END_LANE_ID       = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_END_LANE_ID_LEN   = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_0          = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_1          = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_2          = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_3          = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_4          = 52  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
    = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
    2   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
    3   ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
    = 50  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
    55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
    = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
    58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
    48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
    = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
    54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN = 9   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_RESET = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_START = 58  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WTL_TEST_CLOCK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WTL_TEST_DATA = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WT_BS_CLOCK_EN_BYP = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WT_BS_DATA_EN_BYP = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_EN   = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_WIRETEST = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_DESKEW = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_EYE_OPT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_REPAIR = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_FUNC_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_DC_CALIBRATE = 53  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL2_EO_PG_TRC_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_WT_CU_PLL_PGOOD = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_WT_CU_BYP_PLL_LOCK = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_WT_PLL_REFCLKSEL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_PLL_REFCLKSEL_SCOM_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_IORESET   = 52  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_OP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN = 15  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_DONE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_EN  = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_VAL_GCRMSG = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_CFG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_CM_CFG  = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_CM_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_AMIN_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_USERDEF_CFG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_DAC_BO_CFG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_FILTER_MODE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_MISC_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_VOFF_CFG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH1 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH2 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_CM_TIMEOUT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_BER_TIMEOUT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_HIGH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_LOW = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_AMP_START_VAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_A_BIST_EN = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_MASTER_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_FENCE     = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_USE_SLS_AS_SPR = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_DYN_RECAL_SUSPEND = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DDC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_BER_TEST = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_RESULT_CHECK = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_TRACK_ONLY = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H2_H12_CAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_TO_A_CAL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_FINAL_L2U_ADJ = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DONE_SIGNALING = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_BER_TEST = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_RESULT_CHECK = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H2_H12_CAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_TO_A_CAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_QUAD_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_PEAK_TUNE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_LTE_EN  = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_IQSPD_CFG = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_IQSPD_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_DFEHISPD_EN = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_DFE12_EN = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_H1AP_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_VOLTAGE_MODE = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H6_H12_FAST_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_VOLTAGE_MODE = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H6_H12_FAST_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_CAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_TO_A_CAL = 54  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_HIGH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_LOW = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_DFE_CA_CFG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_SERVO_THRESH3 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_SERVO_THRESH3_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_DISABLE_2TO12_CLEAR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_PEAK_ENABLE_DAC_CFG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_AMIN_ENABLE_HDAC = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_USE_PREV_COARSE_VAL = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PSAVE_TIMER_WAKEUP_MODE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PSAVE_WAKEUP_LANE0_ENABLE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_DISABLE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_TX_SLS_DISABLE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_CLR_ERR_CNTR1 = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_DISABLE = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_CLR_ERR_CNTR2 = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_DISABLE2 = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_EO_PG_SERVO_RESULT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_WIRETEST_DONE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_DESKEW_DONE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_EYE_OPT_DONE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_REPAIR_DONE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_FUNC_MODE_DONE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_DC_CALIBRATE_DONE = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_WIRETEST_FAILED = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_DESKEW_FAILED = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_EYE_OPT_FAILED = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_REPAIR_FAILED = 59  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_DONE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_CU_PLL_ERR = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_INVERTED = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE_LEN = 3   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG = 52  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SEED_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_RATE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_RUN_DYN_RECAL_TIMER = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_HALF_RATE_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_BLOCK_ERROR = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL = 49
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL = 50
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL = 51
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL =
    52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL
    = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_0   = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_1   = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_2   = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_3   = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_4   = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_5   = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_6   = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_7   = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN = 7
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL =
    60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN = 16
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN = 16
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_PRBS_DATA_RCV_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_PG_PRBS_SEED_DONE_RO_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_ERROR_INJECT_PG_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN = 15  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_MASK_PG_ERRS        = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_MASK_PG_ERRS_LEN    = 15  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_MASK_PG_ERRS        = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_MASK_PG_ERRS_LEN    = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_ERROR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_STATIC_MAX_SPARES_EXCEEDED = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_REPAIR_ERROR = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_SPARE_DEPLOYED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_ERROR = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_SPARE_DEPLOYED = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_MAX_SPARES_EXCEEDED = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_TOO_MANY_BUS_ERRORS = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_ERROR    = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_STATIC_SPARE_DEPLOYED = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_STATIC_MAX_SPARES_EXCEEDED = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_REPAIR_ERROR = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_SPARE_DEPLOYED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_RECAL_ERROR = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_RECAL_SPARE_DEPLOYED = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_RECAL_MAX_SPARES_EXCEEDED = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_TOO_MANY_BUS_ERRORS = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_REQ_MANUAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_SM_MANUAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_DIS_SYND_TALLYING = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_HALF_RATE_MODE = 58  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL =
    50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL
    = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_DESKEW_SKIP_OFFSET = 56  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_0    = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_1    = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_2    = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_3    = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_4    = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_5    = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_6    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_7    = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_DESKEW_BUMP_AFTER = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_SLS_HNDSHK_DISABLE = 58  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG_SLS_CMD_VAL_HLD = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WT_CU_PLL_LOCK_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL = 48
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL =
    49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_VAL_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_NONSLS_CMD_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_REPAIR_REQ_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_USED_AS_SPR_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE1 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE1_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE2 = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE2_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID1_PG_BUS_ID            = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID1_PG_BUS_ID_LEN        = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_START_LANE_ID     = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_START_LANE_ID_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_END_LANE_ID       = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_END_LANE_ID_LEN   = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_0          = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_1          = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_2          = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_3          = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_4          = 52  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_AP = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_ERROR_INJECT_PB_ERRS_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_ERROR_INJECT_PB_ERRS_INJ_LEN = 10  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_MASK_PB_ERRS             = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_MASK_PB_ERRS_LEN         = 10  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL_LEN = 10  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_RESET_PB_CLR_PAR_ERRS    = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_RESET_PB_RESET           = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_TEST           = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_ENABLE_GCR_OFL_BUFF = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_IORESET_HARD_BUS0  = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_MMIO_PG_REG_ACCESS = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES1            = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES1_LEN        = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_DET_SEL   = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_DET_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_BUFFER_ENABLED_RO_SIGNAL = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_ERROR_MASK = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_ERROR_INJ = 13  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_PPE_GCR            = 14  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_CHAN_FAIL_MASK     = 15  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_CHAN_FAIL_MASK_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES2            = 23  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES2_LEN        = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_0                 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_1                 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_2                 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_3                 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_4                 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_5                 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_6                 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_7                 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN = 13  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN = 13  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTLG1_E_PG_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_HALF_RATE_MODE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_IORESET   = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_MODE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_ALL_CMD = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_RECAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN = 14  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_DYN_RECAL_TSR_IGNORE_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_PREV_GCRMSG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_USING_REG_SCRAMBLE = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_ENC_SPR1_GCRMSG = 56  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_RPR_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR1_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR2_GCRMSG = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR1_GCRMSG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR2_GCRMSG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLS_LANE_UNSEL_LG_GCRMSG = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SPR_LNS_PDWN_LITE_GCRMSG = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_LGL_RPR_REQ_GCRMSG = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_CLK_SEGS_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_DATA_SEGS_GCRMSG = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_BIST_EN  = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_EXBIST_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_MSBSWAP  = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_PDWN_LITE_DISABLE = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_DESKEW_RATE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_INVERT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_QUIESCE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_RATE  = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_RATE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_CLK_DISABLE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_RUN_COUNT = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_HALF_WIDTH_MODE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_BUS_WIDTH = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_BUS_WIDTH_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG_ERRS         = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG_ERRS_LEN     = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG_PL_ERR       = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_RESET_PG_RESET       = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID1_PG_BUS_ID            = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID1_PG_BUS_ID_LEN        = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_START_LANE_ID     = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_START_LANE_ID_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_END_LANE_ID       = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_END_LANE_ID_LEN   = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_0          = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_1          = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_2          = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_3          = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_4          = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_5          = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_6          = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_7          = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_8_9        = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_8_9_LEN    = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
        ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
    48  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
    53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
    = 55  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_0 = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_1 = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_2 = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_3 = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PDWN_LITE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_CAL_LANE_SEL = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN = 13  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN = 13  ;

static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTLG1_E_PG_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL = 48  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_HALF_RATE_MODE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1 = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2 = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3 = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5 = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6 = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7 = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_IORESET   = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_MODE = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_ALL_CMD = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_RECAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN = 14  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_DYN_RECAL_TSR_IGNORE_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_PREV_GCRMSG = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_USING_REG_SCRAMBLE = 57  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_ENC_SPR1_GCRMSG = 56  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_RPR_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR1_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR2_GCRMSG = 51  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR1_GCRMSG = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR2_GCRMSG = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLS_LANE_UNSEL_LG_GCRMSG = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SPR_LNS_PDWN_LITE_GCRMSG = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_LGL_RPR_REQ_GCRMSG = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_CLK_SEGS_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_DATA_SEGS_GCRMSG = 49  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_BIST_EN  = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_EXBIST_MODE = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_MSBSWAP  = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_PDWN_LITE_DISABLE = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_DESKEW_RATE = 62  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_INVERT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_QUIESCE = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_QUIESCE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_RATE  = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_RATE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_CLK_DISABLE = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_RUN_COUNT = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_HALF_WIDTH_MODE = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_BUS_WIDTH = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_BUS_WIDTH_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG_LEN = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_ERROR_INJECT_PG_ERR_INJ = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG_ERRS         = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG_ERRS_LEN     = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG_PL_ERR       = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_RESET_PG_CLR_PAR_ERRS = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_RESET_PG_RESET       = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID1_PG_BUS_ID            = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID1_PG_BUS_ID_LEN        = 6   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_START_LANE_ID     = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_START_LANE_ID_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_END_LANE_ID       = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_END_LANE_ID_LEN   = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_0          = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_1          = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_2          = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_3          = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_4          = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_5          = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_6          = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_7          = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_8_9        = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_8_9_LEN    = 2   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_TEST_STATUS_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_TEST_DONE_RO_SIGNAL = 55  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_NVAL_PB_ZCAL_N        = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN    = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_DONE_RO_SIGNAL = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_ERROR_RO_SIGNAL = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_BUSY_RO_SIGNAL = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_CMP_OUT_RO_SIGNAL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PVAL_PB_ZCAL_P        = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN    = 9   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_P_4X_PB_ZCAL          = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_P_4X_PB_ZCAL_LEN      = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_EN   = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CAL_SEGS = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_INV = 50  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_OFFSET = 51  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_RESET = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_POWERDOWN = 53  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_TCOIL = 54  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_RANGE_CHECK = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_CYA_DATA_INV = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_2R = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_1R = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_4X_SEG = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_CLK_DIV = 60  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL_LEN = 7   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TRAINED = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TRAINED = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD
    = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD
    = 5   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_CRC_ERROR = 6   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_CRC_ERROR = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_NAK_RECEIVED = 8
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_NAK_RECEIVED = 9
        ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL = 10  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD
    = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD
    = 13  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE = 14  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE = 15  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_UE = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_UE = 17  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TOD_ECC_ERROR =
    18  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TOD_ECC_ERROR =
    19  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD =
    40  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD =
    41  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SPARE_DONE = 44
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SPARE_DONE = 45
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_PSAVE_INVALID_STATE =
    51  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TRAINING_FAILED =
    56  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TRAINING_FAILED =
    57  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR = 58  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR = 59  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_INTERNAL_ERROR =
    60  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_INTERNAL_ERROR =
    61  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_SCOM_ERR_DUP = 62  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_SCOM_ERR = 63  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TRAINED = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TRAINED = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_REPLAY_THRESHOLD = 4
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_REPLAY_THRESHOLD = 5
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_CRC_ERROR = 6   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_CRC_ERROR = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_NAK_RECEIVED = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_NAK_RECEIVED = 9   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_REPLAY_BUFFER_FULL =
    10  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_REPLAY_BUFFER_FULL =
    11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SL_ECC_THRESHOLD = 12
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SL_ECC_THRESHOLD = 13
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SL_ECC_CORRECTABLE =
    14  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SL_ECC_CORRECTABLE =
    15  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SL_ECC_UE = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SL_ECC_UE = 17  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TOD_ECC_ERROR = 18  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TOD_ECC_ERROR = 19  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TCOMPLETE_BAD = 40  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TCOMPLETE_BAD = 41  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SPARE_DONE = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SPARE_DONE = 45  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_PSAVE_INVALID_STATE = 51  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54  ;
static const uint8_t
P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TRAINING_FAILED = 56
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TRAINING_FAILED = 57
        ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_UNRECOVERABLE_ERROR =
    58  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_UNRECOVERABLE_ERROR =
    59  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_INTERNAL_ERROR = 60  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_INTERNAL_ERROR = 61  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_SCOM_ERR_DUP = 62  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_SCOM_ERR = 63  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_LINK_PAIR              = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_DISABLE_SL_ECC         = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_CRC_LANE_ID            = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_EDPL_LANE_ID           = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_SL_UE_CRC_ERR          = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_REPORT_SL_CHKBIT_ERR   = 5   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_BW_SAMPLE_SIZE         = 6   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_BW_WINDOW_SIZE         = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED1                = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED1_LEN            = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PACKET_DELAY_LIMIT     = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PACKET_DELAY_LIMIT_LEN = 5   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TDM_DELAY              = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TDM_DELAY_LEN          = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_TX            = 20  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_RX            = 21  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_AND_NOT_OR    = 22  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED2                = 23  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_BW_DIFF       = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_BW_DIFF_LEN   = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_ERROR_RATE    = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_ERROR_RATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_EXIT_RATE     = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_EXIT_RATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED3                = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED3_LEN            = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PSAVE_TIMEOUT          = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PSAVE_TIMEOUT_LEN      = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMEOUT                = 48  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMEOUT_LEN            = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMER_1US              = 52  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMER_1US_LEN          = 12  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED0A              = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_STARTUP         = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED0B              = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED0B_LEN          = 6   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_COMMAND         = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_COMMAND_LEN     = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED1A              = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_STARTUP         = 33  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED1B              = 34  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED1B_LEN          = 6   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND = 40  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_COMMAND         = 60  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_COMMAND_LEN     = 4   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_CURRENT_STATE = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_CURRENT_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_PRIOR_STATE  = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_PRIOR_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER = 19  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN = 5   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_CURRENT_STATE = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_CURRENT_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_PRIOR_STATE  = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_PRIOR_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER = 43  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN = 5   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_ERR_INJ_LFSR_LFSR             = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_ERR_INJ_LFSR_LFSR_LEN         = 61  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION0_REG_ACTION0       = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION0_REG_ACTION0_LEN   = 64  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION1_REG_ACTION1       = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION1_REG_ACTION1_LEN   = 64  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_WOF_REG_WOF               = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_WOF_REG_WOF_LEN           = 64  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN = 10  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP  = 14  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN = 10  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK = 25  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE = 29  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK = 37  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE = 41  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY = 49  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY = 57  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN = 7   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0 = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1 = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2 = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3 = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4 = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5 = 20  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6 = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7 = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8 = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9 = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10 = 40  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11 = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN = 4   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_RESET_KEEPER = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_CE         = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_CE_LEN     = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UE         = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UE_LEN     = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_TRAIN      = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_TRAIN_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UNRECOV    = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UNRECOV_LEN = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_INTERNAL   = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_INTERNAL_LEN = 18  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_MAX_TIMEOUT        = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_MAX_TIMEOUT_LEN    = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_VALID    = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_INST     = 17  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_ADDR     = 19  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_ADDR_LEN = 5   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_SYN      = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_SYN_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_VALID   = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_INST    = 34  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_ADDR    = 37  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_ADDR_LEN = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_SYN     = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_SYN_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_VALID = 52  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR  = 57  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN = 7   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_TX_BW           = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_TX_BW_LEN       = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_RX_BW           = 13  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_RX_BW_LEN       = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_ERROR_RATE      = 25  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_ERROR_RATE_LEN  = 23  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_VALID = 55  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0 = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1 = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2 = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3 = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4 = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5 = 20  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6 = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7 = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8 = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9 = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10 = 40  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11 = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN = 4   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_RESET_KEEPER = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_CE         = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_CE_LEN     = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UE         = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UE_LEN     = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_TRAIN      = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_TRAIN_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UNRECOV    = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UNRECOV_LEN = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_INTERNAL   = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_INTERNAL_LEN = 18  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_MAX_TIMEOUT        = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_MAX_TIMEOUT_LEN    = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_VALID    = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_INST     = 17  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_ADDR     = 19  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_ADDR_LEN = 5   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_SYN      = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_SYN_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_VALID   = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_INST    = 34  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_ADDR    = 37  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_ADDR_LEN = 7   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_SYN     = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_SYN_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_VALID = 52  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR  = 57  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN = 7   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_TX_BW           = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_TX_BW_LEN       = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_RX_BW           = 13  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_RX_BW_LEN       = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_ERROR_RATE      = 25  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_ERROR_RATE_LEN  = 23  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_VALID = 55  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1 = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2 = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3 = 48  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN = 16  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4 = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5 = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6 = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7 = 48  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN = 16  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_0      = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_0_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_1      = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_1_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_2      = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_2_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_3      = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_3_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_4      = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_4_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_5      = 40  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_5_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_6      = 48  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_6_LEN  = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_7      = 56  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_7_LEN  = 8   ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_0    = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_0_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_1    = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_1_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_2    = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_2_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_3    = 6   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_3_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_4    = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_4_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_5    = 10  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_5_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_6    = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_6_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_7    = 14  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_7_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_0      = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_0_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_1      = 18  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_1_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_2      = 20  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_2_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_3      = 22  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_3_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_4      = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_4_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_5      = 26  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_5_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_6      = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_6_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_7      = 30  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_7_LEN  = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE = 33  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_RESET_MODE  = 34  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE = 35  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW = 36  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE = 37  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE = 38  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_0    = 40  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_0_LEN = 12  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_1    = 52  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_1_LEN = 12  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1 = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN = 15  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR = 26  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR = 27  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP = 30  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED2 = 31  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT = 48  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_ENABLE_ERR_INJ     = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_ENABLE_TRACE       = 1   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED4            = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED4_LEN        = 14  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_SBE_ERROR_RATE     = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_SBE_ERROR_RATE_LEN = 2   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_RAND_ERROR_RATE    = 18  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_RAND_ERROR_RATE_LEN = 6   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED5            = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED5_LEN        = 24  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_EDPL_RATE          = 48  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_EDPL_RATE_LEN      = 16  ;

static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL = 0   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE = 8   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN = 3   ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1 = 11  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN = 15  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR = 26  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR = 27  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR = 28  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP = 30  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED2 = 31  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT = 32  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT = 48  ;
static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TRAINED = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TRAINED = 1   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD = 4   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_CRC_ERROR = 6
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_CRC_ERROR = 7
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_NAK_RECEIVED =
    8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_NAK_RECEIVED =
    9   ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL = 10  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL = 11  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD = 12  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD = 13  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE = 14  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE = 15  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_UE = 16
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_UE = 17
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TOD_ECC_ERROR =
    18  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TOD_ECC_ERROR =
    19  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD =
    40  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD =
    41  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SPARE_DONE = 44
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SPARE_DONE = 45
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_PSAVE_INVALID_STATE =
    51  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TRAINING_FAILED
    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TRAINING_FAILED
    = 57  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR = 58  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_INTERNAL_ERROR
    = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_INTERNAL_ERROR
    = 61  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_SCOM_ERR_DUP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_SCOM_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TRAINED = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TRAINED = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_REPLAY_THRESHOLD = 4
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_REPLAY_THRESHOLD = 5
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_CRC_ERROR = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_CRC_ERROR = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_NAK_RECEIVED = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_NAK_RECEIVED = 9   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_REPLAY_BUFFER_FULL =
    10  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_REPLAY_BUFFER_FULL =
    11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SL_ECC_THRESHOLD =
    12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SL_ECC_THRESHOLD =
    13  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SL_ECC_CORRECTABLE =
    14  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SL_ECC_CORRECTABLE =
    15  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SL_ECC_UE = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SL_ECC_UE = 17  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TOD_ECC_ERROR = 18
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TOD_ECC_ERROR = 19
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TCOMPLETE_BAD = 40
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TCOMPLETE_BAD = 41
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SPARE_DONE = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SPARE_DONE = 45  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_PSAVE_INVALID_STATE = 51
        ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54  ;
static const uint8_t
P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TRAINING_FAILED = 56
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TRAINING_FAILED = 57
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_UNRECOVERABLE_ERROR
    = 58  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_UNRECOVERABLE_ERROR
    = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_INTERNAL_ERROR = 60
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_INTERNAL_ERROR = 61
        ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_SCOM_ERR_DUP = 62  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_SCOM_ERR = 63  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_LINK_PAIR            = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_DISABLE_SL_ECC       = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_CRC_LANE_ID          = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_EDPL_LANE_ID         = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_SL_UE_CRC_ERR        = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_REPORT_SL_CHKBIT_ERR = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_BW_SAMPLE_SIZE       = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_BW_WINDOW_SIZE       = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED1              = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED1_LEN          = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PACKET_DELAY_LIMIT   = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PACKET_DELAY_LIMIT_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TDM_DELAY            = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TDM_DELAY_LEN        = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_TX          = 20  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_RX          = 21  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_AND_NOT_OR  = 22  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED2              = 23  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_BW_DIFF     = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_BW_DIFF_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_ERROR_RATE  = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_ERROR_RATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_EXIT_RATE   = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_EXIT_RATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED3              = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED3_LEN          = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PSAVE_TIMEOUT        = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PSAVE_TIMEOUT_LEN    = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMEOUT              = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMEOUT_LEN          = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMER_1US            = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMER_1US_LEN        = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED0A            = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_STARTUP       = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED0B            = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED0B_LEN        = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_COMMAND       = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_COMMAND_LEN   = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED1A            = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_STARTUP       = 33  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED1B            = 34  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED1B_LEN        = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND = 40  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_COMMAND       = 60  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_COMMAND_LEN   = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_CURRENT_STATE = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_CURRENT_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_PRIOR_STATE = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_PRIOR_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER = 19  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_CURRENT_STATE = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_CURRENT_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_PRIOR_STATE = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_PRIOR_STATE_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER = 43  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_ERR_INJ_LFSR_LFSR           = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_ERR_INJ_LFSR_LFSR_LEN       = 61  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION0_REG_ACTION0     = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION0_REG_ACTION0_LEN = 64  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION1_REG_ACTION1     = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION1_REG_ACTION1_LEN = 64  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_WOF_REG_WOF             = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_WOF_REG_WOF_LEN         = 64  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN = 10  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP = 14  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN = 10  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK = 25  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE = 29  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK = 37  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE = 41  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY = 49  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0 = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1 = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2 = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3 = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4 = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5 = 20  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6 = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7 = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8 = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9 = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10 = 40  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11 = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_RESET_KEEPER = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_CE       = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_CE_LEN   = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UE       = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UE_LEN   = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_TRAIN    = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_TRAIN_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UNRECOV  = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UNRECOV_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_INTERNAL = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_INTERNAL_LEN = 18  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_MAX_TIMEOUT      = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_MAX_TIMEOUT_LEN  = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_VALID  = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_INST   = 17  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_ADDR   = 19  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_ADDR_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_SYN    = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_SYN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_VALID = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_INST  = 34  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_ADDR  = 37  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_ADDR_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_SYN   = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_SYN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_VALID = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_TX_BW         = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_TX_BW_LEN     = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_RX_BW         = 13  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_RX_BW_LEN     = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_ERROR_RATE    = 25  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_ERROR_RATE_LEN = 23  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_VALID = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0 = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1 = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2 = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3 = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4 = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5 = 20  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6 = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7 = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8 = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9 = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10 = 40  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11 = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN = 4   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_RESET_KEEPER = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_CE       = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_CE_LEN   = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UE       = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UE_LEN   = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_TRAIN    = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_TRAIN_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UNRECOV  = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UNRECOV_LEN = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_INTERNAL = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_INTERNAL_LEN = 18  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_MAX_TIMEOUT      = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_MAX_TIMEOUT_LEN  = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_VALID  = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_INST   = 17  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_ADDR   = 19  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_ADDR_LEN = 5   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_SYN    = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_SYN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_VALID = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_INST  = 34  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_ADDR  = 37  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_ADDR_LEN = 7   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_SYN   = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_SYN_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_VALID = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR = 57  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN = 7   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_TX_BW         = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_TX_BW_LEN     = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_RX_BW         = 13  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_RX_BW_LEN     = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_ERROR_RATE    = 25  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_ERROR_RATE_LEN = 23  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_VALID = 55  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1 = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2 = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4 = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5 = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6 = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7 = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_0    = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_0_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_1    = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_1_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_2    = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_2_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_3    = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_3_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_4    = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_4_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_5    = 40  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_5_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_6    = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_6_LEN = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_7    = 56  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_7_LEN = 8   ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_0  = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_0_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_1  = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_1_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_2  = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_2_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_3  = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_3_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_4  = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_4_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_5  = 10  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_5_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_6  = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_6_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_7  = 14  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_7_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_0    = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_0_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_1    = 18  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_1_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_2    = 20  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_2_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_3    = 22  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_3_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_4    = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_4_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_5    = 26  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_5_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_6    = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_6_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_7    = 30  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_7_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE = 33  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_RESET_MODE = 34  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE = 35  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW = 36  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE = 37  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE = 38  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_0  = 40  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_0_LEN = 12  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_1  = 52  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_1_LEN = 12  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1 = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN = 15  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR = 26  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR = 27  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP = 30  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED2 = 31  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_ENABLE_ERR_INJ   = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_ENABLE_TRACE     = 1   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED4          = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED4_LEN      = 14  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_SBE_ERROR_RATE   = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_SBE_ERROR_RATE_LEN = 2   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_RAND_ERROR_RATE  = 18  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_RAND_ERROR_RATE_LEN = 6   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED5          = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED5_LEN      = 24  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_EDPL_RATE        = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_EDPL_RATE_LEN    = 16  ;

static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL = 0   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN = 4   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE = 8   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN = 3   ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1 = 11  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN = 15  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR = 26  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR = 27  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR = 28  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP = 30  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED2 = 31  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT = 32  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT = 48  ;
static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_TAG_ADDR       = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_TAG_ADDR_LEN   = 27  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_ERR            = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_PIB_IFETCH_PENDING    = 34  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_VALID          = 36  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_VALID_LEN      = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE2_VALID    = 40  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE_PTR       = 45  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE2_ERR      = 46  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ADDR               = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ADDR_LEN           = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_R_NW               = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_BUSY               = 33  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_BYTE_ENABLE        = 35  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_BYTE_ENABLE_LEN    = 8   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_LINE_MODE          = 43  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ERROR              = 49  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ERROR_LEN          = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_IFETCH_PENDING     = 62  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_DATAOP_PENDING     = 63  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_STORE_ADDRESS          = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_STORE_ADDRESS_LEN      = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_SGB_BYTE_VALID         = 36  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_SGB_BYTE_VALID_LEN     = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_SGB_FLUSH_PENDING      = 63  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION0_REG_ACTION0      = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION0_REG_ACTION0_LEN  = 13  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION1_REG_ACTION1      = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION1_REG_ACTION1_LEN  = 13  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_WOF_REG_WOF              = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_WOF_REG_WOF_LEN          = 13  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HS              = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HC              = 1   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HC_LEN          = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HCP             = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_RIP             = 5   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_SIP             = 6   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_TRAP            = 7   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_IAC             = 8   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_SIBRC      = 9   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN  = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_DACR            = 12  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_DACW            = 13  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_WE         = 14  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_TRH             = 15  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_SMS             = 16  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_SMS_LEN         = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_LP         = 20  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_EP              = 21  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_PTR             = 24  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_ST              = 25  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_MFE             = 28  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_MCS             = 29  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_MCS_LEN         = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_IAR                 = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_IAR_LEN             = 30  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HS              = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HC              = 1   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HC_LEN          = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HCP             = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_RIP             = 5   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_SIP             = 6   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_TRAP            = 7   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_IAC             = 8   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_SIBRC      = 9   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN  = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_DACR            = 12  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_DACW            = 13  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_WE         = 14  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_TRH             = 15  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_SMS             = 16  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_SMS_LEN         = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_LP         = 20  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_EP              = 21  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_PTR             = 24  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_ST              = 25  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_MFE             = 28  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_MCS             = 29  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_MCS_LEN         = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XIRAMRA_SPRG0       = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN   = 32  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_XIRAMGA_IR          = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_XIRAMGA_IR_LEN      = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_EDR                 = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_EDR_LEN             = 32  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_IR                   = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_IR_LEN               = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_XIRAMRA_SPRG0        = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN    = 32  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_XIXCR_XCR            = 1   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_XIXCR_XCR_LEN        = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_SPRG0                = 32  ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_SPRG0_LEN            = 32  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIXCR_XCR                    = 1   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIXCR_XCR_LEN                = 3   ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_IORESET            = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_PDWN               = 1   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_INTERRUPT          = 2   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR = 3   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_SPARES             = 4   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_SPARES_LEN         = 12  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG1_WORK1         = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG1_WORK1_LEN     = 32  ;

static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG2_WORK2         = 0   ;
static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG2_WORK2_LEN     = 32  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_HI_DATA_REG_DATA   = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN = 64  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_DATA   = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK = 42  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING = 53  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE = 11  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6   ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_HI_DATA_REG_DATA   = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN = 64  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_DATA   = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK = 42  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING = 53  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE = 11  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6   ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_HI_DATA_REG_DATA   = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN = 64  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_DATA   = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK = 42  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING = 53  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE = 11  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6   ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD = 24  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36  ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37  ;

static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_XTRA_TRACE_MODE_DATA              = 0   ;
static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_XTRA_TRACE_MODE_DATA_LEN          = 42  ;

#endif
