/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: import/chips/p9/common/include/p9n2_misc_scom_addresses_fld.H $ */
/*                                                                        */
/* OpenPOWER HCODE Project                                                */
/*                                                                        */
/* COPYRIGHT 2017                                                         */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
///
/// @file p9_misc_scom_addresses_fld.H
/// @brief  Defines constants for scom addresses
///
// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: SOA
// *HWP Level: 3
// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE

#ifndef __P9N2_MISC_SCOM_ADDRESSES_FLD_H
#define __P9N2_MISC_SCOM_ADDRESSES_FLD_H

#include <stdint.h>

static const uint8_t P9N2_PHB_ACT0_REG_AIB_COMMAND_INVALID                        = 0   ;
static const uint8_t P9N2_PHB_ACT0_REG_AIB_ADDRESSING_ERROR                       = 1   ;
static const uint8_t P9N2_PHB_ACT0_REG_AIB_ACCESS_ERROR                           = 2   ;
static const uint8_t P9N2_PHB_ACT0_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED    = 3   ;
static const uint8_t P9N2_PHB_ACT0_REG_AIB_FATAL_CLASS_ERROR                      = 4   ;
static const uint8_t P9N2_PHB_ACT0_REG_AIB_INF_CLASS_ERROR                        = 5   ;
static const uint8_t P9N2_PHB_ACT0_REG_PE_STOP_STATE_ERROR                        = 6   ;
static const uint8_t P9N2_PHB_ACT0_REG_AIB_DAT_ERR_SIGNALED                       = 7   ;
static const uint8_t P9N2_PHB_ACT0_REG_OUT_COMMON_ARRAY_FATAL_ERROR               = 8   ;
static const uint8_t P9N2_PHB_ACT0_REG_OUT_COMMON_LATCH_FATAL_ERROR               = 9   ;
static const uint8_t P9N2_PHB_ACT0_REG_OUT_COMMON_LOGIC_FATAL_ERROR               = 10  ;
static const uint8_t P9N2_PHB_ACT0_REG_BLIF_OUT_INTERFACE_PARITY_ERROR            = 11  ;
static const uint8_t P9N2_PHB_ACT0_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE           = 12  ;
static const uint8_t P9N2_PHB_ACT0_REG_MMIO_REQUEST_TIMEOUT                       = 13  ;
static const uint8_t P9N2_PHB_ACT0_REG_OUT_RRB_SOURCED_ERROR                      = 14  ;
static const uint8_t P9N2_PHB_ACT0_REG_CFG_LOGIC_SIGNALED_ERROR                   = 15  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_REG_REQUEST_ADDRESS_ERROR              = 16  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDA_FATAL_ERROR                        = 17  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDA_INF_ERROR                          = 18  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDB_FATAL_ERROR                        = 19  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDB_INF_ERROR                          = 20  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_ERR_FATAL_ERROR                        = 21  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_ERR_INF_ERROR                          = 22  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_DBG_FATAL_ERROR                        = 23  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_DBG_INF_ERROR                          = 24  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_PCIE_REQUEST_ACCESS_ERROR              = 25  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_BUS_LOGIC_ERROR                        = 26  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_UVI_FATAL_ERROR                        = 27  ;
static const uint8_t P9N2_PHB_ACT0_REG_RSB_UVI_INF_ERROR                          = 28  ;
static const uint8_t P9N2_PHB_ACT0_REG_SCOM_FATAL_ERROR                           = 29  ;
static const uint8_t P9N2_PHB_ACT0_REG_SCOM_INF_ERROR                             = 30  ;
static const uint8_t P9N2_PHB_ACT0_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS             = 31  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_IODA_FATAL_ERROR                       = 32  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_MSI_PE_MATCH_ERROR                     = 33  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_MSI_ADDRESS_ERROR                      = 34  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_TVT_ERROR                              = 35  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_RCVD_FATAL_ERROR_MSG                   = 36  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_RCVD_NONFATAL_ERROR_MSG                = 37  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG             = 38  ;
static const uint8_t P9N2_PHB_ACT0_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED     = 39  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_COMMON_FATAL_ERROR                     = 40  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_TABLE_BAR_DISABLED_ERROR               = 41  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_BLIF_COMPLETION_ERROR                  = 42  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_PCT_TIMEOUT_ERROR                      = 43  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_ECC_CORRECTABLE_ERROR                  = 44  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_ECC_UNCORRECTABLE_ERROR                = 45  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_TLP_POISON_SIGNALED                    = 46  ;
static const uint8_t P9N2_PHB_ACT0_REG_ARB_RTT_PENUM_INVALID_ERROR                = 47  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_COMMON_FATAL_ERROR                     = 48  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_TABLE_BAR_DISABLED_ERROR               = 49  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_ECC_CORRECTABLE_ERROR                  = 50  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_ECC_UNCORRECTABLE_ERROR                = 51  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_AIB2_TX_TIMEOUT_ERROR                  = 52  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_MRT_ERROR                              = 53  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_RESERVED01                             = 54  ;
static const uint8_t P9N2_PHB_ACT0_REG_MRG_RESERVED02                             = 55  ;
static const uint8_t P9N2_PHB_ACT0_REG_TCE_IODA_PAGE_ACCESS_ERROR                 = 56  ;
static const uint8_t P9N2_PHB_ACT0_REG_TCE_REQUEST_TIMEOUT_ERROR                  = 57  ;
static const uint8_t P9N2_PHB_ACT0_REG_TCE_UNEXPECTED_RESPONSE_ERROR              = 58  ;
static const uint8_t P9N2_PHB_ACT0_REG_TCE_COMMON_FATAL_ERRORS                    = 59  ;
static const uint8_t P9N2_PHB_ACT0_REG_TCE_ECC_CORRECTABLE_ERROR                  = 60  ;
static const uint8_t P9N2_PHB_ACT0_REG_TCE_ECC_UNCORRECTABLE_ERROR                = 61  ;
static const uint8_t P9N2_PHB_ACT0_REG_TCE_RESERVED01                             = 62  ;
static const uint8_t P9N2_PHB_ACT0_REG_LEM_FIR_INTERNAL_PARITY_ERROR              = 63  ;

static const uint8_t P9N2_PHB_ACTION1_REG_AIB_COMMAND_INVALID                     = 0   ;
static const uint8_t P9N2_PHB_ACTION1_REG_AIB_ADDRESSING_ERROR                    = 1   ;
static const uint8_t P9N2_PHB_ACTION1_REG_AIB_ACCESS_ERROR                        = 2   ;
static const uint8_t P9N2_PHB_ACTION1_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED = 3   ;
static const uint8_t P9N2_PHB_ACTION1_REG_AIB_FATAL_CLASS_ERROR                   = 4   ;
static const uint8_t P9N2_PHB_ACTION1_REG_AIB_INF_CLASS_ERROR                     = 5   ;
static const uint8_t P9N2_PHB_ACTION1_REG_PE_STOP_STATE_ERROR                     = 6   ;
static const uint8_t P9N2_PHB_ACTION1_REG_AIB_DAT_ERR_SIGNALED                    = 7   ;
static const uint8_t P9N2_PHB_ACTION1_REG_OUT_COMMON_ARRAY_FATAL_ERROR            = 8   ;
static const uint8_t P9N2_PHB_ACTION1_REG_OUT_COMMON_LATCH_FATAL_ERROR            = 9   ;
static const uint8_t P9N2_PHB_ACTION1_REG_OUT_COMMON_LOGIC_FATAL_ERROR            = 10  ;
static const uint8_t P9N2_PHB_ACTION1_REG_BLIF_OUT_INTERFACE_PARITY_ERROR         = 11  ;
static const uint8_t P9N2_PHB_ACTION1_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE        = 12  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MMIO_REQUEST_TIMEOUT                    = 13  ;
static const uint8_t P9N2_PHB_ACTION1_REG_OUT_RRB_SOURCED_ERROR                   = 14  ;
static const uint8_t P9N2_PHB_ACTION1_REG_CFG_LOGIC_SIGNALED_ERROR                = 15  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_REG_REQUEST_ADDRESS_ERROR           = 16  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDA_FATAL_ERROR                     = 17  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDA_INF_ERROR                       = 18  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDB_FATAL_ERROR                     = 19  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDB_INF_ERROR                       = 20  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_ERR_FATAL_ERROR                     = 21  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_ERR_INF_ERROR                       = 22  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_DBG_FATAL_ERROR                     = 23  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_DBG_INF_ERROR                       = 24  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_PCIE_REQUEST_ACCESS_ERROR           = 25  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_BUS_LOGIC_ERROR                     = 26  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_UVI_FATAL_ERROR                     = 27  ;
static const uint8_t P9N2_PHB_ACTION1_REG_RSB_UVI_INF_ERROR                       = 28  ;
static const uint8_t P9N2_PHB_ACTION1_REG_SCOM_FATAL_ERROR                        = 29  ;
static const uint8_t P9N2_PHB_ACTION1_REG_SCOM_INF_ERROR                          = 30  ;
static const uint8_t P9N2_PHB_ACTION1_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS          = 31  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_IODA_FATAL_ERROR                    = 32  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_MSI_PE_MATCH_ERROR                  = 33  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_MSI_ADDRESS_ERROR                   = 34  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_TVT_ERROR                           = 35  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RCVD_FATAL_ERROR_MSG                = 36  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RCVD_NONFATAL_ERROR_MSG             = 37  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG          = 38  ;
static const uint8_t P9N2_PHB_ACTION1_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED  = 39  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_COMMON_FATAL_ERROR                  = 40  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_TABLE_BAR_DISABLED_ERROR            = 41  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_BLIF_COMPLETION_ERROR               = 42  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_PCT_TIMEOUT_ERROR                   = 43  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_ECC_CORRECTABLE_ERROR               = 44  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_ECC_UNCORRECTABLE_ERROR             = 45  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_TLP_POISON_SIGNALED                 = 46  ;
static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RTT_PENUM_INVALID_ERROR             = 47  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_COMMON_FATAL_ERROR                  = 48  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_TABLE_BAR_DISABLED_ERROR            = 49  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_ECC_CORRECTABLE_ERROR               = 50  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_ECC_UNCORRECTABLE_ERROR             = 51  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_AIB2_TX_TIMEOUT_ERROR               = 52  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_MRT_ERROR                           = 53  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_RESERVED01                          = 54  ;
static const uint8_t P9N2_PHB_ACTION1_REG_MRG_RESERVED02                          = 55  ;
static const uint8_t P9N2_PHB_ACTION1_REG_TCE_IODA_PAGE_ACCESS_ERROR              = 56  ;
static const uint8_t P9N2_PHB_ACTION1_REG_TCE_REQUEST_TIMEOUT_ERROR               = 57  ;
static const uint8_t P9N2_PHB_ACTION1_REG_TCE_UNEXPECTED_RESPONSE_ERROR           = 58  ;
static const uint8_t P9N2_PHB_ACTION1_REG_TCE_COMMON_FATAL_ERRORS                 = 59  ;
static const uint8_t P9N2_PHB_ACTION1_REG_TCE_ECC_CORRECTABLE_ERROR               = 60  ;
static const uint8_t P9N2_PHB_ACTION1_REG_TCE_ECC_UNCORRECTABLE_ERROR             = 61  ;
static const uint8_t P9N2_PHB_ACTION1_REG_TCE_RESERVED01                          = 62  ;
static const uint8_t P9N2_PHB_ACTION1_REG_LEM_FIR_INTERNAL_PARITY_ERROR           = 63  ;

static const uint8_t P9N2_PEC_ADDREXTMASK_REG_PE                                  = 0   ;
static const uint8_t P9N2_PEC_ADDREXTMASK_REG_PE_LEN                              = 7   ;

static const uint8_t P9N2_PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS                    = 0   ;
static const uint8_t P9N2_PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS_LEN                = 64  ;

static const uint8_t P9N2_PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS                     = 0   ;
static const uint8_t P9N2_PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS_LEN                 = 64  ;

static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0   ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_RESERVED_LAST_LT                    = 17  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33  ;
static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34  ;

static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0   ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_RESERVED_LAST_LT                    = 17  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33  ;
static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34  ;

static const uint8_t P9N2_PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0   ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_RESERVED_LAST_LT                       = 17  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33  ;
static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34  ;

static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0   ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_RESERVED_LAST_LT                    = 17  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33  ;
static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34  ;

static const uint8_t P9N2_PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0   ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_RESERVED_LAST_LT                      = 17  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33  ;
static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34  ;

static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0   ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_RESERVED_LAST_LT                    = 17  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33  ;
static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34  ;

static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_RNW                                = 0   ;
static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_SIZE                               = 5   ;
static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_SIZE_LEN                           = 7   ;
static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_ADR                                = 30  ;
static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_ADR_LEN                            = 34  ;

static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_DATA                                = 0   ;
static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_DATA_LEN                            = 5   ;
static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_OPER                                = 5   ;
static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_OPER_LEN                            = 5   ;

static const uint8_t P9N2_PU_ALTD_ADDR_REG_FBC_ADDRESS                            = 8   ;
static const uint8_t P9N2_PU_ALTD_ADDR_REG_FBC_ADDRESS_LEN                        = 56  ;

static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_START_OP                            = 2   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_CLEAR_STATUS                        = 3   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_RESET_FSM                           = 4   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_RNW                                 = 5   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_AXTYPE                              = 6   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_DATA_ONLY                           = 7   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCK_PICK                           = 10  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCKED                              = 11  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCK_ID                             = 12  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCK_ID_LEN                         = 4   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_SCOPE                               = 16  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_SCOPE_LEN                           = 3   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_AUTO_INC                            = 19  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_DROP_PRIORITY                       = 20  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_DROP_PRIORITY_MAX                   = 21  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT                    = 22  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_PIB_DIRECT                          = 23  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE                     = 24  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TTYPE                               = 25  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TTYPE_LEN                           = 7   ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TSIZE                               = 32  ;
static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TSIZE_LEN                           = 8   ;

static const uint8_t P9N2_PU_ALTD_DATA_REG_FBC                                    = 0   ;
static const uint8_t P9N2_PU_ALTD_DATA_REG_FBC_LEN                                = 64  ;

static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT             = 22  ;
static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE                 = 23  ;
static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT         = 28  ;
static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN     = 20  ;
static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_POST_INIT                   = 51  ;
static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_FAST_PATH                   = 52  ;
static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT           = 54  ;
static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN       = 10  ;

static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ALTD_BUSY                        = 0   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT                   = 1   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ADDR_DONE                        = 2   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_DATA_DONE                        = 3   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_WAIT_RESP                        = 4   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_OVERRUN_ERROR                    = 5   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_AUTOINC_ERROR                    = 6   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_COMMAND_ERROR                    = 7   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR                    = 8   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_OP_HANG_ERR                   = 9   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_DATA_HANG_ERR                 = 10  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_CRESP_ERR            = 11  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_DATA_ERR             = 12  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_WAIT_PIB_DIRECT                  = 16  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PIB_DIRECT_DONE                  = 17  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PBINIT_MISSING                   = 18  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PIB_ERROR                        = 33  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PIB_ERROR_LEN                    = 5   ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ECC_CE                           = 48  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ECC_UE                           = 49  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ECC_SUE                          = 50  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_CRESP_VALUE                      = 59  ;
static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN                  = 5   ;

static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_ENABLE             = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED           = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN       = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET             = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN         = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN          = 16  ;

static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_ENABLE                   = 0   ;
static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED                 = 1   ;
static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN             = 3   ;
static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET                   = 4   ;
static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN               = 4   ;
static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE                    = 8   ;
static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN                = 16  ;

static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_ENABLE                   = 0   ;
static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED                 = 1   ;
static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN             = 3   ;
static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET                   = 4   ;
static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN               = 4   ;
static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE                    = 8   ;
static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN                = 16  ;

static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_ENABLE             = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED           = 1   ;
static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN       = 3   ;
static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET             = 4   ;
static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN         = 4   ;
static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE              = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN          = 16  ;

static const uint8_t P9N2_CAPP_APCFG_SPARE1                                       = 1   ;
static const uint8_t P9N2_CAPP_APCFG_APCCTL_PHB_SEL                               = 2   ;
static const uint8_t P9N2_CAPP_APCFG_APCCTL_PHB_SEL_LEN                           = 2   ;
static const uint8_t P9N2_CAPP_APCFG_HANG_POLL_SCALE                              = 4   ;
static const uint8_t P9N2_CAPP_APCFG_HANG_POLL_SCALE_LEN                          = 4   ;
static const uint8_t P9N2_CAPP_APCFG_SPEC_HPC_DIR_STATE                           = 8   ;
static const uint8_t P9N2_CAPP_APCFG_SPEC_HPC_DIR_STATE_LEN                       = 5   ;
static const uint8_t P9N2_CAPP_APCFG_SPARE                                        = 13  ;
static const uint8_t P9N2_CAPP_APCFG_APCCTL_P9_MODE                               = 14  ;
static const uint8_t P9N2_CAPP_APCFG_APCCTL_SYSADDR                               = 15  ;
static const uint8_t P9N2_CAPP_APCFG_APCCTL_SYSADDR_LEN                           = 6   ;
static const uint8_t P9N2_CAPP_APCFG_APCCTL_MEM_SEL_MODE                          = 21  ;
static const uint8_t P9N2_CAPP_APCFG_APCCTL_ENB_FRC_ADDR13                        = 22  ;
static const uint8_t P9N2_CAPP_APCFG_DFS_ISUE_DIR_STATE                           = 23  ;
static const uint8_t P9N2_CAPP_APCFG_DFS_ISUE_DIR_STATE_LEN                       = 5   ;

static const uint8_t P9N2_CAPP_APCLCO_TARGET_VALID                                = 0   ;
static const uint8_t P9N2_CAPP_APCLCO_TARGET_VALID_LEN                            = 12  ;
static const uint8_t P9N2_CAPP_APCLCO_TARGET_ID0                                  = 12  ;
static const uint8_t P9N2_CAPP_APCLCO_TARGET_MIN                                  = 13  ;
static const uint8_t P9N2_CAPP_APCLCO_TARGET_MIN_LEN                              = 3   ;

static const uint8_t P9N2_CAPP_APCRDFSMMASK_APC_RDFSM_MASK                        = 0   ;
static const uint8_t P9N2_CAPP_APCRDFSMMASK_APC_RDFSM_MASK_LEN                    = 48  ;

static const uint8_t P9N2_CAPP_APCTL_APCCTL_ENB_CRESP_EXAM                        = 0   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_ADR_BAR_MODE                          = 1   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_NN_RN                         = 2   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_VG_NOT_SYS                    = 3   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_G                             = 4   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_LN                            = 5   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_SKIP_G                                = 6   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_HANG_ARE                              = 7   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_HANG_DEAD                             = 8   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_CFG_BKILL_INC                         = 9   ;
static const uint8_t P9N2_CAPP_APCTL_DCACHE_MODE                                  = 10  ;
static const uint8_t P9N2_CAPP_APCTL_DCACHE_REPORTS_PHYSICAL                      = 11  ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_PSL_CMDQUEUE                  = 12  ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_ENABLE_MASTER_RETRY_BACKOFF           = 13  ;
static const uint8_t P9N2_CAPP_APCTL_SCPTGT_LFSR_MODE                             = 14  ;
static const uint8_t P9N2_CAPP_APCTL_SCPTGT_LFSR_MODE_LEN                         = 3   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT            = 17  ;
static const uint8_t P9N2_CAPP_APCTL_SPARE                                        = 18  ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_SMF_CONFIG                            = 19  ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_SMF_CONFIG_LEN                        = 2   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_CHIP_ADDR_EXTENSION_MASK_ENABLE       = 21  ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_CHIP_ADDR_EXTENSION_MASK_ENABLE_LEN   = 7   ;
static const uint8_t P9N2_CAPP_APCTL_WR_EPSILON_VALUE                             = 39  ;
static const uint8_t P9N2_CAPP_APCTL_WR_EPSILON_VALUE_LEN                         = 7   ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_MAX_RETRY                             = 56  ;
static const uint8_t P9N2_CAPP_APCTL_APCCTL_MAX_RETRY_LEN                         = 8   ;

static const uint8_t P9N2_CAPP_APC_ARRY_ADDR_ENCD_ARRAY_SELECT                    = 2   ;
static const uint8_t P9N2_CAPP_APC_ARRY_ADDR_APCARY_ADDRESS                       = 3   ;
static const uint8_t P9N2_CAPP_APC_ARRY_ADDR_APCARY_ADDRESS_LEN                   = 9   ;

static const uint8_t P9N2_CAPP_APC_ARRY_RDDATA_APCARY                             = 0   ;
static const uint8_t P9N2_CAPP_APC_ARRY_RDDATA_APCARY_LEN                         = 64  ;

static const uint8_t P9N2_CAPP_APC_ARRY_WRDATA_APCARY                             = 0   ;
static const uint8_t P9N2_CAPP_APC_ARRY_WRDATA_APCARY_LEN                         = 64  ;

static const uint8_t P9N2_CAPP_APC_ERRINJ_ENABLE                                  = 0   ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_DBLERR                                  = 1   ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_CONTINUOUS                              = 2   ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_TARGET                                  = 7   ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_TARGET_LEN                              = 5   ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_ERROR_INJECT_ENABLE                 = 12  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_INJECT_DBL_ECC_ERROR                = 13  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_INJECT_CONTINOUS_ERROR              = 14  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET                 = 17  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET_LEN             = 7   ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_INJECT_ENABLE                 = 32  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_TYPE                          = 33  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_TYPE_LEN                      = 2   ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_INJECT_CONTINUOUS_ERROR             = 35  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET                 = 36  ;
static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET_LEN             = 4   ;

static const uint8_t P9N2_CAPP_APC_PMUSEL_GRPSEL                                  = 0   ;
static const uint8_t P9N2_CAPP_APC_PMUSEL_GRPSEL_LEN                              = 4   ;
static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_EVENT_SEL                          = 6   ;
static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_EVENT_SEL_LEN                      = 6   ;
static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_FSM_SEL                            = 13  ;
static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_FSM_SEL_LEN                        = 7   ;

static const uint8_t P9N2_CAPP_ASE_TUPLE0_LPID                                    = 4   ;
static const uint8_t P9N2_CAPP_ASE_TUPLE0_LPID_LEN                                = 12  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE0_PID                                     = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE0_PID_LEN                                 = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE0_TID                                     = 44  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE0_TID_LEN                                 = 16  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE0_VALID                                   = 63  ;

static const uint8_t P9N2_CAPP_ASE_TUPLE1_LPID                                    = 4   ;
static const uint8_t P9N2_CAPP_ASE_TUPLE1_LPID_LEN                                = 12  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE1_PID                                     = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE1_PID_LEN                                 = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE1_TID                                     = 44  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE1_TID_LEN                                 = 16  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE1_VALID                                   = 63  ;

static const uint8_t P9N2_CAPP_ASE_TUPLE2_LPID                                    = 4   ;
static const uint8_t P9N2_CAPP_ASE_TUPLE2_LPID_LEN                                = 12  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE2_PID                                     = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE2_PID_LEN                                 = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE2_TID                                     = 44  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE2_TID_LEN                                 = 16  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE2_VALID                                   = 63  ;

static const uint8_t P9N2_CAPP_ASE_TUPLE3_LPID                                    = 4   ;
static const uint8_t P9N2_CAPP_ASE_TUPLE3_LPID_LEN                                = 12  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE3_PID                                     = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE3_PID_LEN                                 = 20  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE3_TID                                     = 44  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE3_TID_LEN                                 = 16  ;
static const uint8_t P9N2_CAPP_ASE_TUPLE3_VALID                                   = 63  ;

static const uint8_t P9N2_PEC_ASSIST_INTERRUPT_REG_ATTN                           = 0   ;
static const uint8_t P9N2_PEC_ASSIST_INTERRUPT_REG_RECOV                          = 1   ;
static const uint8_t P9N2_PEC_ASSIST_INTERRUPT_REG_XSTOP                          = 2   ;

static const uint8_t P9N2_PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   = 0   ;
static const uint8_t P9N2_PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               = 16  ;

static const uint8_t P9N2_PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   = 0   ;
static const uint8_t P9N2_PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               = 16  ;

static const uint8_t P9N2_PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK                      = 0   ;
static const uint8_t P9N2_PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                  = 16  ;

static const uint8_t P9N2_PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   = 0   ;
static const uint8_t P9N2_PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               = 16  ;

static const uint8_t P9N2_PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK                     = 0   ;
static const uint8_t P9N2_PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                 = 16  ;

static const uint8_t P9N2_PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   = 0   ;
static const uint8_t P9N2_PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               = 16  ;

static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ENABLE                              = 0   ;
static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ID                                  = 1   ;
static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ID_LEN                              = 4   ;
static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ACTIVITY                            = 8   ;
static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ACTIVITY_LEN                        = 8   ;

static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_START                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_START_LEN                         = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_END                               = 17  ;
static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_END_LEN                           = 7   ;

static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_START                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_START_LEN                         = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_END                               = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_END_LEN                           = 7   ;

static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED1_LEN                           = 5   ;
static const uint8_t P9N2__SM2_ATR_HA_PTR_START                                   = 5   ;
static const uint8_t P9N2__SM2_ATR_HA_PTR_START_LEN                               = 7   ;
static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED2_LEN                           = 5   ;
static const uint8_t P9N2__SM2_ATR_HA_PTR_END                                     = 17  ;
static const uint8_t P9N2__SM2_ATR_HA_PTR_END_LEN                                 = 7   ;

static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED1_LEN                           = 5   ;
static const uint8_t P9N2__SM1_ATR_HA_PTR_START                                   = 5   ;
static const uint8_t P9N2__SM1_ATR_HA_PTR_START_LEN                               = 7   ;
static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED2_LEN                           = 5   ;
static const uint8_t P9N2__SM1_ATR_HA_PTR_END                                     = 17  ;
static const uint8_t P9N2__SM1_ATR_HA_PTR_END_LEN                                 = 7   ;

static const uint8_t P9N2__SM0_ATS_CKSW_SPARE                                     = 0   ;
static const uint8_t P9N2__SM0_ATS_CKSW_SPARE_LEN                                 = 64  ;

static const uint8_t P9N2__SM1_ATS_CTRL_ARB_STOP                                  = 0   ;
static const uint8_t P9N2__SM1_ATS_CTRL_ARB_STALL                                 = 1   ;
static const uint8_t P9N2__SM1_ATS_CTRL_TCE_CACHE_DISABLE                         = 2   ;
static const uint8_t P9N2__SM1_ATS_CTRL_TCE_CACHE_1W                              = 3   ;
static const uint8_t P9N2__SM1_ATS_CTRL_CONFIG_BRAZOS                             = 4   ;
static const uint8_t P9N2__SM1_ATS_CTRL_CONFIG_SYNC_WAIT                          = 5   ;
static const uint8_t P9N2__SM1_ATS_CTRL_CONFIG_SYNC_WAIT_LEN                      = 5   ;
static const uint8_t P9N2__SM1_ATS_CTRL_SPARE                                     = 10  ;
static const uint8_t P9N2__SM1_ATS_CTRL_SPARE_LEN                                 = 54  ;

static const uint8_t P9N2__SM0_ATS_HOLD_TVT_ENTRY_INVALID_ESR                     = 0   ;
static const uint8_t P9N2__SM0_ATS_HOLD_TVT_ADDR_RANGE_ERR_ESR                    = 1   ;
static const uint8_t P9N2__SM0_ATS_HOLD_TCE_PAGE_ACCESS_ERR_ESR                   = 2   ;
static const uint8_t P9N2__SM0_ATS_HOLD_TCE_CACHE_MULT_HIT_ERR_ESR                = 3   ;
static const uint8_t P9N2__SM0_ATS_HOLD_MLC_ACCESS_ERR_ESR                        = 4   ;
static const uint8_t P9N2__SM0_ATS_HOLD_TCE_REQ_TO_ERR_ESR                        = 5   ;
static const uint8_t P9N2__SM0_ATS_HOLD_TCD_PERR_ESR                              = 6   ;
static const uint8_t P9N2__SM0_ATS_HOLD_TDR_PERR_ESR                              = 7   ;
static const uint8_t P9N2__SM0_ATS_HOLD_AT_EA_UE_ESR                              = 8   ;
static const uint8_t P9N2__SM0_ATS_HOLD_AT_EA_CE_ESR                              = 9   ;
static const uint8_t P9N2__SM0_ATS_HOLD_AT_TDRMEM_UE_ESR                          = 10  ;
static const uint8_t P9N2__SM0_ATS_HOLD_AT_TDRMEM_CE_ESR                          = 11  ;
static const uint8_t P9N2__SM0_ATS_HOLD_RSPOUT_UE_ESR                             = 12  ;
static const uint8_t P9N2__SM0_ATS_HOLD_RSPOUT_CE_ESR                             = 13  ;
static const uint8_t P9N2__SM0_ATS_HOLD_TVT_PERR_ESR                              = 14  ;
static const uint8_t P9N2__SM0_ATS_HOLD_IODA_ADDR_PERR_ESR                        = 15  ;
static const uint8_t P9N2__SM0_ATS_HOLD_CTRLR_PERR_ESR                            = 16  ;
static const uint8_t P9N2__SM0_ATS_HOLD_TOR_PERR_ESR                              = 17  ;
static const uint8_t P9N2__SM0_ATS_HOLD_INVAL_IODA_TBL_SEL_ESR                    = 18  ;
static const uint8_t P9N2__SM0_ATS_HOLD_ESR_RSVD_19                               = 19  ;

static const uint8_t P9N2__SM0_ATS_MASK_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM0_ATS_MASK_IDIAL_LEN                                 = 20  ;

static const uint8_t P9N2__SM1_ATS_TCR_TCE_TIMEOUT                                = 10  ;
static const uint8_t P9N2__SM1_ATS_TCR_TCE_TIMEOUT_LEN                            = 6   ;

static const uint8_t P9N2_PEC_ATTN_INTERRUPT_REG_ATTN                             = 0   ;

static const uint8_t P9N2_PU_BANK0_MCD_BOT_VALID                                  = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_BOT_CPG                                    = 1   ;
static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_MBR_ID                             = 2   ;
static const uint8_t P9N2_PU_BANK0_MCD_BOT_ALWAYS_RTY                             = 3   ;
static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_SIZE                               = 13  ;
static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_SIZE_LEN                           = 17  ;
static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_BASE                               = 33  ;
static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_BASE_LEN                           = 31  ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_VALID                             = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_CPG                               = 1   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_MBR_ID                        = 2   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_ALWAYS_RTY                        = 3   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_SIZE                          = 13  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_SIZE_LEN                      = 17  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_BASE                          = 33  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_BASE_LEN                      = 31  ;

static const uint8_t P9N2_PU_BANK0_MCD_CHA_VALID                                  = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_CHA_CPG                                    = 1   ;
static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_MBR_ID                             = 2   ;
static const uint8_t P9N2_PU_BANK0_MCD_CHA_ALWAYS_RTY                             = 3   ;
static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_SIZE                               = 13  ;
static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_SIZE_LEN                           = 17  ;
static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_BASE                               = 33  ;
static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_BASE_LEN                           = 31  ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_VALID                             = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_CPG                               = 1   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_MBR_ID                        = 2   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_ALWAYS_RTY                        = 3   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_SIZE                          = 13  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_SIZE_LEN                      = 17  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_BASE                          = 33  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_BASE_LEN                      = 31  ;

static const uint8_t P9N2_PU_BANK0_MCD_CMD_CHECK_CMDS                             = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_CMD_CHECK_CMDS_LEN                         = 19  ;
static const uint8_t P9N2_PU_BANK0_MCD_CMD_CHECK_CMDS_EN                          = 31  ;
static const uint8_t P9N2_PU_BANK0_MCD_CMD_SET_CMDS                               = 32  ;
static const uint8_t P9N2_PU_BANK0_MCD_CMD_SET_CMDS_LEN                           = 19  ;
static const uint8_t P9N2_PU_BANK0_MCD_CMD_SET_CMDS_EN                            = 63  ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS                        = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_LEN                    = 19  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_EN                     = 31  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_SET_CMDS                          = 32  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_SET_CMDS_LEN                      = 19  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_SET_CMDS_EN                       = 63  ;

static const uint8_t P9N2_PU_BANK0_MCD_REC_ENABLE                                 = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_DONE                                   = 1   ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_CONTINUOUS                             = 2   ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_STATUS                                 = 5   ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_PACE                                   = 8   ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_PACE_LEN                               = 12  ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_ADDR_ERROR                             = 20  ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_ADDR                                   = 21  ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_ADDR_LEN                               = 15  ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_RTY_COUNT                              = 40  ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_RTY_COUNT_LEN                          = 4   ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_VG_COUNT                               = 49  ;
static const uint8_t P9N2_PU_BANK0_MCD_REC_VG_COUNT_LEN                           = 15  ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ENABLE                            = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_DONE                              = 1   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_CONTINUOUS                        = 2   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_STATUS                            = 5   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_PACE                              = 8   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_PACE_LEN                          = 12  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ADDR_ERROR                        = 20  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ADDR                              = 21  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ADDR_LEN                          = 15  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_RTY_COUNT                         = 40  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_RTY_COUNT_LEN                     = 4   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_VG_COUNT                          = 49  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_VG_COUNT_LEN                      = 15  ;

static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_ACCESS_EN                          = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_WR_ENABLE                          = 1   ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_REQ_PEND                           = 3   ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_READ_STATUS                        = 4   ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_WRITE_MODE                         = 5   ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_WRITE_STATUS                       = 6   ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_ADDR                               = 17  ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_ADDR_LEN                           = 15  ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_RDWR_DATA                          = 32  ;
static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN                      = 32  ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_ACCESS_EN                     = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_WR_ENABLE                     = 1   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_REQ_PEND                      = 3   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_READ_STATUS                   = 4   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_MODE                    = 5   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_STATUS                  = 6   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_ADDR                          = 17  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_ADDR_LEN                      = 15  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA                     = 32  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN                 = 32  ;

static const uint8_t P9N2_PU_BANK0_MCD_STR_VALID                                  = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_STR_CPG                                    = 1   ;
static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_MBR_ID                             = 2   ;
static const uint8_t P9N2_PU_BANK0_MCD_STR_ALWAYS_RTY                             = 3   ;
static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_SIZE                               = 13  ;
static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_SIZE_LEN                           = 17  ;
static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_BASE                               = 33  ;
static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_BASE_LEN                           = 31  ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_VALID                             = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_CPG                               = 1   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_MBR_ID                        = 2   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_ALWAYS_RTY                        = 3   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_SIZE                          = 13  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_SIZE_LEN                      = 17  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_BASE                          = 33  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_BASE_LEN                      = 31  ;

static const uint8_t P9N2_PU_BANK0_MCD_TOP_VALID                                  = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_TOP_CPG                                    = 1   ;
static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_MBR_ID                             = 2   ;
static const uint8_t P9N2_PU_BANK0_MCD_TOP_ALWAYS_RTY                             = 3   ;
static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_SIZE                               = 13  ;
static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_SIZE_LEN                           = 17  ;
static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_BASE                               = 33  ;
static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_BASE_LEN                           = 31  ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_VALID                             = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_CPG                               = 1   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_MBR_ID                        = 2   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_ALWAYS_RTY                        = 3   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_SIZE                          = 13  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_SIZE_LEN                      = 17  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_BASE                          = 33  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_BASE_LEN                      = 31  ;

static const uint8_t P9N2_PU_BANK0_MCD_VGC_AVAIL_GROUPS                           = 0   ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_AVAIL_GROUPS_LEN                       = 16  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_FAILED_GROUPS                          = 16  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_FAILED_GROUPS_LEN                      = 16  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_4X4_MODE                               = 32  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_HANG_POLL_ENABLE                       = 33  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_RND_BACKOFF_ENABLE                     = 34  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_DROP_PRIORITY_MODE                     = 35  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE                  = 36  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE                = 37  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_P8MODE_ENABLE                          = 38  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_ENABLE                    = 39  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK                      = 40  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK_LEN                  = 7   ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE                    = 47  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE_LEN                = 2   ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_CS_HW400693_DISABLE                    = 49  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_ENABLE_RCV_ADDR_DEBUG                  = 50  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_SPARE                                  = 51  ;
static const uint8_t P9N2_PU_BANK0_MCD_VGC_SPARE_LEN                              = 6   ;

static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS                      = 0   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS_LEN                  = 16  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_FAILED_GROUPS                     = 16  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_FAILED_GROUPS_LEN                 = 16  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_4X4_MODE                          = 32  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_HANG_POLL_ENABLE                  = 33  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_RND_BACKOFF_ENABLE                = 34  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_DROP_PRIORITY_MODE                = 35  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE             = 36  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE           = 37  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_P8MODE_ENABLE                     = 38  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_FAC_ENABLE               = 39  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK                 = 40  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK_LEN             = 7   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE               = 47  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_CS_HW400693_DISABLE               = 49  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_ENABLE_RCV_ADDR_DEBUG             = 50  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_SPARE                             = 51  ;
static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_SPARE_LEN                         = 6   ;

static const uint8_t P9N2_PHB_BARE_REG_PE_MMIO_BAR0_EN                            = 0   ;
static const uint8_t P9N2_PHB_BARE_REG_PE_MMIO_BAR1_EN                            = 1   ;
static const uint8_t P9N2_PHB_BARE_REG_PE_PHB_BAR_EN                              = 2   ;
static const uint8_t P9N2_PHB_BARE_REG_PE_INT_BAR_EN                              = 3   ;

static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_MMIO_BAR0_EN                     = 0   ;
static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_MMIO_BAR1_EN                     = 1   ;
static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_PHB_BAR_EN                       = 2   ;
static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_INT_BAR_EN                       = 3   ;

static const uint8_t P9N2_PU_BCDE_CTL_STOP                                        = 0   ;
static const uint8_t P9N2_PU_BCDE_CTL_START                                       = 1   ;

static const uint8_t P9N2_PU_BCDE_OCIBAR_ADDR                                     = 0   ;
static const uint8_t P9N2_PU_BCDE_OCIBAR_ADDR_LEN                                 = 25  ;

static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_0_1                              = 0   ;
static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_0_1_LEN                          = 2   ;
static const uint8_t P9N2_PU_BCDE_PBADR_PB_OFFSET                                 = 2   ;
static const uint8_t P9N2_PU_BCDE_PBADR_PB_OFFSET_LEN                             = 23  ;
static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_25_26                            = 25  ;
static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_25_26_LEN                        = 2   ;
static const uint8_t P9N2_PU_BCDE_PBADR_EXTADDR                                   = 27  ;
static const uint8_t P9N2_PU_BCDE_PBADR_EXTADDR_LEN                               = 14  ;
static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_41_42                            = 41  ;
static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_41_42_LEN                        = 2   ;

static const uint8_t P9N2_PU_BCDE_SET_RESERVED_0_1                                = 0   ;
static const uint8_t P9N2_PU_BCDE_SET_RESERVED_0_1_LEN                            = 2   ;
static const uint8_t P9N2_PU_BCDE_SET_COPY_LENGTH                                 = 2   ;
static const uint8_t P9N2_PU_BCDE_SET_COPY_LENGTH_LEN                             = 6   ;

static const uint8_t P9N2_PU_BCDE_STAT_RUNNING                                    = 0   ;
static const uint8_t P9N2_PU_BCDE_STAT_WAITING                                    = 1   ;
static const uint8_t P9N2_PU_BCDE_STAT_WRCMP                                      = 2   ;
static const uint8_t P9N2_PU_BCDE_STAT_WRCMP_LEN                                  = 6   ;
static const uint8_t P9N2_PU_BCDE_STAT_RDCMP                                      = 14  ;
static const uint8_t P9N2_PU_BCDE_STAT_RDCMP_LEN                                  = 6   ;
static const uint8_t P9N2_PU_BCDE_STAT_DEBUG                                      = 20  ;
static const uint8_t P9N2_PU_BCDE_STAT_DEBUG_LEN                                  = 9   ;
static const uint8_t P9N2_PU_BCDE_STAT_STOPPED                                    = 29  ;
static const uint8_t P9N2_PU_BCDE_STAT_ERROR                                      = 30  ;
static const uint8_t P9N2_PU_BCDE_STAT_DONE                                       = 31  ;

static const uint8_t P9N2_PU_BCUE_CTL_STOP                                        = 0   ;
static const uint8_t P9N2_PU_BCUE_CTL_START                                       = 1   ;

static const uint8_t P9N2_PU_BCUE_OCIBAR_ADDR                                     = 0   ;
static const uint8_t P9N2_PU_BCUE_OCIBAR_ADDR_LEN                                 = 25  ;

static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_0_1                              = 0   ;
static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_0_1_LEN                          = 2   ;
static const uint8_t P9N2_PU_BCUE_PBADR_PB_OFFSET                                 = 2   ;
static const uint8_t P9N2_PU_BCUE_PBADR_PB_OFFSET_LEN                             = 23  ;
static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_25_26                            = 25  ;
static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_25_26_LEN                        = 2   ;
static const uint8_t P9N2_PU_BCUE_PBADR_EXTADDR                                   = 27  ;
static const uint8_t P9N2_PU_BCUE_PBADR_EXTADDR_LEN                               = 14  ;
static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_41_42                            = 41  ;
static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_41_42_LEN                        = 2   ;

static const uint8_t P9N2_PU_BCUE_SET_RESERVED_0_1                                = 0   ;
static const uint8_t P9N2_PU_BCUE_SET_RESERVED_0_1_LEN                            = 2   ;
static const uint8_t P9N2_PU_BCUE_SET_COPY_LENGTH                                 = 2   ;
static const uint8_t P9N2_PU_BCUE_SET_COPY_LENGTH_LEN                             = 6   ;

static const uint8_t P9N2_PU_BCUE_STAT_RUNNING                                    = 0   ;
static const uint8_t P9N2_PU_BCUE_STAT_WAITING                                    = 1   ;
static const uint8_t P9N2_PU_BCUE_STAT_WRCMP                                      = 2   ;
static const uint8_t P9N2_PU_BCUE_STAT_WRCMP_LEN                                  = 6   ;
static const uint8_t P9N2_PU_BCUE_STAT_RDCMP                                      = 14  ;
static const uint8_t P9N2_PU_BCUE_STAT_RDCMP_LEN                                  = 6   ;
static const uint8_t P9N2_PU_BCUE_STAT_DEBUG                                      = 20  ;
static const uint8_t P9N2_PU_BCUE_STAT_DEBUG_LEN                                  = 9   ;
static const uint8_t P9N2_PU_BCUE_STAT_STOPPED                                    = 29  ;
static const uint8_t P9N2_PU_BCUE_STAT_ERROR                                      = 30  ;
static const uint8_t P9N2_PU_BCUE_STAT_DONE                                       = 31  ;

static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_WILDCARD                  = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_RESERVED                  = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_RESERVED_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_PE                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_PE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_BDF                       = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_BDF_LEN                   = 16  ;

static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_WILDCARD                            = 1   ;
static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_RESERVED                            = 2   ;
static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_RESERVED_LEN                        = 2   ;
static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_RESERVED                  = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_RESERVED_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_PE                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_PE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_BDF                       = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_BDF_LEN                   = 16  ;

static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_RESERVED                  = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_RESERVED_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_PE                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_PE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_BDF                       = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_BDF_LEN                   = 16  ;

static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_WILDCARD                  = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_RESERVED                  = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_RESERVED_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_PE                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_PE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_BDF                       = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_BDF_LEN                   = 16  ;

static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_WILDCARD                            = 1   ;
static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_RESERVED                            = 2   ;
static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_RESERVED_LEN                        = 2   ;
static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_RESERVED                  = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_RESERVED_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_PE                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_PE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_BDF                       = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_BDF_LEN                   = 16  ;

static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_RESERVED                  = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_RESERVED_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_PE                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_PE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_BDF                       = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_BDF_LEN                   = 16  ;

static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_ENABLE                              = 0   ;
static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_RESERVED                            = 1   ;
static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_RESERVED_LEN                        = 3   ;
static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_PE                                  = 4   ;
static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_PE_LEN                              = 4   ;
static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_BDF                                 = 8   ;
static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_BDF_LEN                             = 16  ;

static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_ENABLE                            = 0   ;
static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_RESERVED                          = 1   ;
static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_RESERVED_LEN                      = 3   ;
static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_PE                                = 4   ;
static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_PE_LEN                            = 4   ;
static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_BDF                               = 8   ;
static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_BDF_LEN                           = 16  ;

static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_ENABLE                            = 0   ;
static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_RESERVED                          = 1   ;
static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_RESERVED_LEN                      = 3   ;
static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_PE                                = 4   ;
static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_PE_LEN                            = 4   ;
static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_BDF                               = 8   ;
static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_BDF_LEN                           = 16  ;

static const uint8_t P9N2_PEC_BIST_TC_START_TEST_DC                               = 0   ;
static const uint8_t P9N2_PEC_BIST_TC_SRAM_ABIST_MODE_DC                          = 1   ;
static const uint8_t P9N2_PEC_BIST_TC_EDRAM_ABIST_MODE_DC                         = 2   ;
static const uint8_t P9N2_PEC_BIST_TC_IOBIST_MODE_DC                              = 3   ;
static const uint8_t P9N2_PEC_BIST_PERV                                           = 4   ;
static const uint8_t P9N2_PEC_BIST_UNIT1                                          = 5   ;
static const uint8_t P9N2_PEC_BIST_UNIT2                                          = 6   ;
static const uint8_t P9N2_PEC_BIST_UNIT3                                          = 7   ;
static const uint8_t P9N2_PEC_BIST_UNIT4                                          = 8   ;
static const uint8_t P9N2_PEC_BIST_UNIT5                                          = 9   ;
static const uint8_t P9N2_PEC_BIST_UNIT6                                          = 10  ;
static const uint8_t P9N2_PEC_BIST_UNIT7                                          = 11  ;
static const uint8_t P9N2_PEC_BIST_UNIT8                                          = 12  ;
static const uint8_t P9N2_PEC_BIST_UNIT9                                          = 13  ;
static const uint8_t P9N2_PEC_BIST_UNIT10                                         = 14  ;
static const uint8_t P9N2_PEC_BIST_STROBE_WINDOW_EN                               = 48  ;

static const uint8_t P9N2_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_ENABLE   = 1   ;
static const uint8_t P9N2_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK = 48  ;
static const uint8_t P9N2_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK_LEN = 16  ;

static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_INITIATED   = 0   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_COMPLETE    = 1   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_PSL_DEAD              = 3   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_FENCE                 = 4   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_FAILED            = 5   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_RTAGFLUSH_FAILED           = 6   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_PRECISE_DIR_FLUSH_FAILED   = 7   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_COURSE_DIR_FLUSH_FAILED    = 8   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_HANG_DETECTED     = 9   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE                = 10  ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE_LEN            = 2   ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_FORCE_QUIESCE              = 14  ;
static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_QUIESCE_DONE               = 15  ;

static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ENABLE                           = 0   ;
static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ID                               = 1   ;
static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ID_LEN                           = 4   ;
static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ACTIVITY                         = 8   ;
static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN                     = 8   ;

static const uint8_t P9N2_PEC_CC_PROTECT_MODE_REG_READ_ENABLE                     = 0   ;
static const uint8_t P9N2_PEC_CC_PROTECT_MODE_REG_WRITE_ENABLE                    = 1   ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_FIRST_BITS                        = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_FIRST_BITS_LEN                    = 54  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_UE                  = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_UE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_UE                  = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_UE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_UE                  = 18  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_UE_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_UE                  = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_UE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_UE                  = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_UE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_SUE                 = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN             = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_SUE                 = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN             = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_SUE                 = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_SUE                 = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN             = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_SUE                 = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN             = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_CE                  = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_CE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_CE                  = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_CE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_CE                  = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_CE_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_CE                  = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_CE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_CE                  = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_CE_LEN              = 4   ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_MASK_BITS                         = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_MASK_BITS_LEN                     = 54  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0         = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1         = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2         = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3         = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5         = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7         = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9         = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10        = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11        = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12        = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13        = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14        = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15        = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17        = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18        = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19        = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20        = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21        = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23        = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0         = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1         = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3         = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4         = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5         = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6         = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7         = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0        = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1        = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3        = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0         = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2         = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3         = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4         = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5         = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6         = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7         = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0         = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1         = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3         = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0         = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1         = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2         = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3         = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4         = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5         = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6         = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7         = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8         = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9         = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10        = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11        = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12        = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13        = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15        = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0            = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1            = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2            = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3            = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4            = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5            = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6            = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7            = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8            = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9            = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10           = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11           = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12           = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13           = 61  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15           = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0          = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1          = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3          = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4          = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5          = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6          = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7          = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0          = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1          = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2          = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3          = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4          = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5          = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6          = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7          = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8          = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9          = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10         = 18  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11         = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12         = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13         = 21  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14         = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15         = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16         = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17         = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18         = 26  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19         = 27  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_0          = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_1          = 29  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_2          = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_3          = 31  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_4          = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_5          = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_6          = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_7          = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0         = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1         = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2         = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3         = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4         = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5         = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6         = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7         = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0          = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1          = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2          = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3          = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4          = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5          = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6          = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7          = 51  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0          = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1          = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2          = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3          = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0          = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1          = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2          = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3          = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0          = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1          = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2          = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3          = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0            = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1            = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2            = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3            = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4            = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5            = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6            = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7            = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8            = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9            = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10           = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11           = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12           = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13           = 61  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0            = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1            = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2            = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3            = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4            = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5            = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6            = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7            = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8            = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9            = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10           = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11           = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12           = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13           = 61  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15           = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0         = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1         = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2         = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3         = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5         = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7         = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9         = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10        = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11        = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12        = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13        = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14        = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15        = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17        = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18        = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19        = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20        = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21        = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23        = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0         = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1         = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3         = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4         = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5         = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6         = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7         = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0        = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1        = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3        = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0         = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2         = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3         = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4         = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5         = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6         = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7         = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0         = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1         = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3         = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0         = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1         = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2         = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3         = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4         = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5         = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6         = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7         = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8         = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9         = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10        = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11        = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12        = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13        = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15        = 63  ;

static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0                = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1                = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2                = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3                = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4                = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5                = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6                = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7                = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8                = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9                = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10               = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11               = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12               = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13               = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14               = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15               = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16               = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17               = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18               = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19               = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20               = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21               = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22               = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23               = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0                = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1                = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2                = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3                = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4                = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5                = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6                = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7                = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0               = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1               = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2               = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3               = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0                = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1                = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2                = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3                = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4                = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5                = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6                = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7                = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0                = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1                = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2                = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3                = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0                = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1                = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2                = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3                = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4                = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5                = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6                = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7                = 55  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8                = 56  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9                = 57  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10               = 58  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11               = 59  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12               = 60  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13               = 61  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14               = 62  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15               = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0            = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1            = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2            = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3            = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4            = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5            = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6            = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7            = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8            = 56  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9            = 57  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10           = 58  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11           = 59  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12           = 60  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13           = 61  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15           = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0             = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1             = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2             = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3             = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4             = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5             = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6             = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7             = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8             = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9             = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10            = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11            = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12            = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13            = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14            = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15            = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16            = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17            = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18            = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19            = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20            = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21            = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22            = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23            = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0             = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1             = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2             = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3             = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4             = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5             = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6             = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7             = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0            = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1            = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2            = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3            = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0             = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1             = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2             = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3             = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4             = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5             = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6             = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7             = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_0             = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_1             = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_2             = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_3             = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0             = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1             = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2             = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3             = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4             = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5             = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6             = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7             = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8             = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9             = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10            = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11            = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12            = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13            = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14            = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15            = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0            = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1            = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2            = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3            = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4            = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5            = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6            = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7            = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8            = 56  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9            = 57  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10           = 58  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11           = 59  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12           = 60  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13           = 61  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15           = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0            = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1            = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2            = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3            = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4            = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5            = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6            = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7            = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8            = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9            = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10           = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11           = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12           = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13           = 61  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15           = 63  ;

static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0                    = 0   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1                    = 1   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2                    = 2   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3                    = 3   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4                    = 4   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5                    = 5   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6                    = 6   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7                    = 7   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0                    = 8   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1                    = 9   ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2                    = 10  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3                    = 11  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4                    = 12  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5                    = 13  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6                    = 14  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7                    = 15  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8                    = 16  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9                    = 17  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10                   = 18  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11                   = 19  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12                   = 20  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13                   = 21  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14                   = 22  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15                   = 23  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16                   = 24  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17                   = 25  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18                   = 26  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19                   = 27  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_0                    = 28  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_1                    = 29  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_2                    = 30  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_3                    = 31  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_4                    = 32  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_5                    = 33  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_6                    = 34  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_7                    = 35  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0                   = 36  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1                   = 37  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2                   = 38  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3                   = 39  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4                   = 40  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5                   = 41  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6                   = 42  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7                   = 43  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0                    = 44  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1                    = 45  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2                    = 46  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3                    = 47  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4                    = 48  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5                    = 49  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6                    = 50  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7                    = 51  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0                    = 52  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1                    = 53  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2                    = 54  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3                    = 55  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0                    = 56  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1                    = 57  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2                    = 58  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3                    = 59  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0                    = 60  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1                    = 61  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2                    = 62  ;
static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3                    = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0                = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1                = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2                = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3                = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4                = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5                = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6                = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7                = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8                = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9                = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10               = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11               = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12               = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13               = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14               = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15               = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16               = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17               = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18               = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19               = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20               = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21               = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22               = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23               = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0                = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1                = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2                = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3                = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4                = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5                = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6                = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7                = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0               = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1               = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2               = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3               = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0                = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1                = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2                = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3                = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4                = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5                = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6                = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7                = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0                = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1                = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2                = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3                = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0                = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1                = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2                = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3                = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4                = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5                = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6                = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7                = 55  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8                = 56  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9                = 57  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10               = 58  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11               = 59  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12               = 60  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13               = 61  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14               = 62  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15               = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0         = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1         = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2         = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3         = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5         = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7         = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9         = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10        = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11        = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12        = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13        = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14        = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15        = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17        = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18        = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19        = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20        = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21        = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23        = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0         = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1         = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3         = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4         = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5         = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6         = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7         = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0        = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1        = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3        = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0         = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2         = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3         = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4         = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5         = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6         = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7         = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0         = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1         = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3         = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0         = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1         = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2         = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3         = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4         = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5         = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6         = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7         = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8         = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9         = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10        = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11        = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12        = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13        = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15        = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1        = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2        = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3        = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4        = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5        = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7        = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8        = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9        = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11       = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12       = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13       = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14       = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1         = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2         = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3         = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0         = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1         = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2         = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3         = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0         = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1         = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3         = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4         = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5         = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6         = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7         = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0         = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1         = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2         = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3         = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4         = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6         = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7         = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8         = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9         = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10        = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11        = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0         = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1         = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3         = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4         = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5         = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6         = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7         = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8         = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9         = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10        = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11        = 55  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_0                           = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_1                           = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_2                           = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_3                           = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_4                           = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_5                           = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_6                           = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_7                           = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_8                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_9                           = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_10                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_11                          = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_12                          = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_13                          = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_14                          = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_15                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_16                          = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_17                          = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_18                          = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_19                          = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_20                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_21                          = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_22                          = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_23                          = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_24                          = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_25                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_26                          = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_27                          = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_28                          = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_29                          = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_30                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_31                          = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_32                          = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_33                          = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_34                          = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_35                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_36                          = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_37                          = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_38                          = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_39                          = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_40                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_41                          = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_42                          = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_43                          = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_44                          = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_45                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_46                          = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_47                          = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_48                          = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_49                          = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_50                          = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_51                          = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_52                          = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_53                          = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_54                          = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_55                          = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_56                          = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_57                          = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_58                          = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_59                          = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_60                          = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_61                          = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_62                          = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_63                          = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           = 55  ;

static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_0                                  = 0   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_1                                  = 1   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_2                                  = 2   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_3                                  = 3   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_4                                  = 4   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_5                                  = 5   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_6                                  = 6   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_7                                  = 7   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_8                                  = 8   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_9                                  = 9   ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_10                                 = 10  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_11                                 = 11  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_12                                 = 12  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_13                                 = 13  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_14                                 = 14  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_15                                 = 15  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_16                                 = 16  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_17                                 = 17  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_18                                 = 18  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_19                                 = 19  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_20                                 = 20  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_21                                 = 21  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_22                                 = 22  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_23                                 = 23  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_24                                 = 24  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_25                                 = 25  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_26                                 = 26  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_27                                 = 27  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_28                                 = 28  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_29                                 = 29  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_30                                 = 30  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_31                                 = 31  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_32                                 = 32  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_33                                 = 33  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_34                                 = 34  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_35                                 = 35  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_36                                 = 36  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_37                                 = 37  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_38                                 = 38  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_39                                 = 39  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_40                                 = 40  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_41                                 = 41  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_42                                 = 42  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_43                                 = 43  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_44                                 = 44  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_45                                 = 45  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_46                                 = 46  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_47                                 = 47  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_48                                 = 48  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_49                                 = 49  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_50                                 = 50  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_51                                 = 51  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_52                                 = 52  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_53                                 = 53  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_54                                 = 54  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_55                                 = 55  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_56                                 = 56  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_57                                 = 57  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_58                                 = 58  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_59                                 = 59  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_60                                 = 60  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_61                                 = 61  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_62                                 = 62  ;
static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_63                                 = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           = 55  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0          = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1          = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3          = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4          = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5          = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6          = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7          = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8          = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9          = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10         = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11         = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12         = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13         = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14         = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15         = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0          = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1          = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2          = 18  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3          = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4          = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5          = 21  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6          = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7          = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0          = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1          = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2          = 26  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3          = 27  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4          = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5          = 29  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6          = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7          = 31  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0          = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1          = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2          = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3          = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4          = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5          = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6          = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7          = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0          = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1          = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2          = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3          = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4          = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5          = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6          = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7          = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0          = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1          = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2          = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3          = 51  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4          = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5          = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6          = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7          = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0         = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1         = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2         = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3         = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0         = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1         = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2         = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3         = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           = 55  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           = 55  ;

static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0               = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1               = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2               = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3               = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4               = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5               = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6               = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7               = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8               = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9               = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10              = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11              = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12              = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13              = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14              = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15              = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0                = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1                = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2                = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3                = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0                = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1                = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2                = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3                = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0                = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1                = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2                = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3                = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4                = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5                = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6                = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7                = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0                = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1                = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2                = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3                = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4                = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5                = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6                = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7                = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8                = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9                = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10               = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11               = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0                = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1                = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2                = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3                = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4                = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5                = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6                = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7                = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8                = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9                = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10               = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11               = 55  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1        = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2        = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3        = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4        = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5        = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7        = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8        = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9        = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11       = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12       = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13       = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14       = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1         = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2         = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3         = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0         = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1         = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2         = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3         = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0         = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1         = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3         = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4         = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5         = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6         = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7         = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0         = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1         = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2         = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3         = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4         = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6         = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7         = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8         = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9         = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10        = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11        = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0         = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1         = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3         = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4         = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5         = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6         = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7         = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8         = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9         = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10        = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11        = 55  ;

static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_0                                  = 0   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_1                                  = 1   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_2                                  = 2   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_3                                  = 3   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_4                                  = 4   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_5                                  = 5   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_6                                  = 6   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_7                                  = 7   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_8                                  = 8   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_9                                  = 9   ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_10                                 = 10  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_11                                 = 11  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_12                                 = 12  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_13                                 = 13  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_14                                 = 14  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_15                                 = 15  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_16                                 = 16  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_17                                 = 17  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_18                                 = 18  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_19                                 = 19  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_20                                 = 20  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_21                                 = 21  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_22                                 = 22  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_23                                 = 23  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_24                                 = 24  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_25                                 = 25  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_26                                 = 26  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_27                                 = 27  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_28                                 = 28  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_29                                 = 29  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_30                                 = 30  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_31                                 = 31  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_32                                 = 32  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_33                                 = 33  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_34                                 = 34  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_35                                 = 35  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_36                                 = 36  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_37                                 = 37  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_38                                 = 38  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_39                                 = 39  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_40                                 = 40  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_41                                 = 41  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_42                                 = 42  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_43                                 = 43  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_44                                 = 44  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_45                                 = 45  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_46                                 = 46  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_47                                 = 47  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_48                                 = 48  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_49                                 = 49  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_50                                 = 50  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_51                                 = 51  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_52                                 = 52  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_53                                 = 53  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_54                                 = 54  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_55                                 = 55  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_56                                 = 56  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_57                                 = 57  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_58                                 = 58  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_59                                 = 59  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_60                                 = 60  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_61                                 = 61  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_62                                 = 62  ;
static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_63                                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0            = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1            = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2            = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3            = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4            = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5            = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6            = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7            = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8            = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9            = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10           = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11           = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12           = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13           = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14           = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15           = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0             = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1             = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2             = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3             = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0             = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1             = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2             = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3             = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0             = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1             = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2             = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3             = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4             = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5             = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6             = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7             = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0             = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1             = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2             = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3             = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4             = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5             = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6             = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7             = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8             = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9             = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11            = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0             = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1             = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2             = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3             = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4             = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5             = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6             = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7             = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8             = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9             = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10            = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11            = 55  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           = 55  ;

static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0                    = 0   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1                    = 1   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2                    = 2   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3                    = 3   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4                    = 4   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5                    = 5   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6                    = 6   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7                    = 7   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8                    = 8   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9                    = 9   ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10                   = 10  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11                   = 11  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12                   = 12  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13                   = 13  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14                   = 14  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15                   = 15  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0                    = 16  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1                    = 17  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2                    = 18  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3                    = 19  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4                    = 20  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5                    = 21  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6                    = 22  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7                    = 23  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0                    = 24  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1                    = 25  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2                    = 26  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3                    = 27  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4                    = 28  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5                    = 29  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6                    = 30  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7                    = 31  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0                    = 32  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1                    = 33  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2                    = 34  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3                    = 35  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4                    = 36  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5                    = 37  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6                    = 38  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7                    = 39  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0                    = 40  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1                    = 41  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2                    = 42  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3                    = 43  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4                    = 44  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5                    = 45  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6                    = 46  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7                    = 47  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0                    = 48  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1                    = 49  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2                    = 50  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3                    = 51  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4                    = 52  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5                    = 53  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6                    = 54  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7                    = 55  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0                   = 56  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1                   = 57  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2                   = 58  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3                   = 59  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0                   = 60  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1                   = 61  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2                   = 62  ;
static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3                   = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_0                           = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_1                           = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_2                           = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_3                           = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_4                           = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_5                           = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_6                           = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_7                           = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_8                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_9                           = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_10                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_11                          = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_12                          = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_13                          = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_14                          = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_15                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_16                          = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_17                          = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_18                          = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_19                          = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_20                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_21                          = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_22                          = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_23                          = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_24                          = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_25                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_26                          = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_27                          = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_28                          = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_29                          = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_30                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_31                          = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_32                          = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_33                          = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_34                          = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_35                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_36                          = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_37                          = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_38                          = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_39                          = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_40                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_41                          = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_42                          = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_43                          = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_44                          = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_45                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_46                          = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_47                          = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_48                          = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_49                          = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_50                          = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_51                          = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_52                          = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_53                          = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_54                          = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_55                          = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_56                          = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_57                          = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_58                          = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_59                          = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_60                          = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_61                          = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_62                          = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_63                          = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0               = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1               = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2               = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3               = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4               = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5               = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6               = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7               = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8               = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9               = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10              = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11              = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12              = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13              = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14              = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15              = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0                = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1                = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2                = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3                = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0                = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1                = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2                = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3                = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0                = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1                = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2                = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3                = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4                = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5                = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6                = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7                = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0                = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1                = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2                = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3                = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4                = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5                = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6                = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7                = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8                = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9                = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10               = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11               = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0                = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1                = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2                = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3                = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4                = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5                = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6                = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7                = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8                = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9                = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10               = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11               = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1        = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2        = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3        = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4        = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5        = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7        = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8        = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9        = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11       = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12       = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13       = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14       = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1         = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2         = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3         = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0         = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1         = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2         = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3         = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0         = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1         = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3         = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4         = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5         = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6         = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7         = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0         = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1         = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2         = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3         = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4         = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6         = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7         = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8         = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9         = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10        = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11        = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0         = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1         = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3         = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4         = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5         = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6         = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7         = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8         = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9         = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10        = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11        = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0         = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1         = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2         = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3         = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5         = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7         = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9         = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10        = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11        = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12        = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13        = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14        = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15        = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17        = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18        = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19        = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20        = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21        = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23        = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24        = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25        = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26        = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27        = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28        = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29        = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30        = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31        = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32        = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33        = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35        = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36        = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37        = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38        = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39        = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40        = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41        = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42        = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43        = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44        = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45        = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46        = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47        = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48        = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49        = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50        = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51        = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52        = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53        = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54        = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55        = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56        = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57        = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58        = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59        = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60        = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61        = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63        = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_0                           = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_1                           = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_2                           = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_3                           = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_4                           = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_5                           = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_6                           = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_7                           = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_8                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_9                           = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_10                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_11                          = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_12                          = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_13                          = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_14                          = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_15                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_16                          = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_17                          = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_18                          = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_19                          = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_20                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_21                          = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_22                          = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_23                          = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_24                          = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_25                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_26                          = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_27                          = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_28                          = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_29                          = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_30                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_31                          = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_32                          = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_33                          = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_34                          = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_35                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_36                          = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_37                          = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_38                          = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_39                          = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_40                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_41                          = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_42                          = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_43                          = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_44                          = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_45                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_46                          = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_47                          = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_48                          = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_49                          = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_50                          = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_51                          = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_52                          = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_53                          = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_54                          = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_55                          = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_56                          = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_57                          = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_58                          = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_59                          = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_60                          = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_61                          = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_62                          = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_63                          = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           = 56  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           = 57  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           = 58  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           = 59  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           = 60  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           = 61  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           = 63  ;

static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_0                                  = 0   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_1                                  = 1   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_2                                  = 2   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_3                                  = 3   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_4                                  = 4   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_5                                  = 5   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_6                                  = 6   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_7                                  = 7   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_8                                  = 8   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_9                                  = 9   ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_10                                 = 10  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_11                                 = 11  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_12                                 = 12  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_13                                 = 13  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_14                                 = 14  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_15                                 = 15  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_16                                 = 16  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_17                                 = 17  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_18                                 = 18  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_19                                 = 19  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_20                                 = 20  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_21                                 = 21  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_22                                 = 22  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_23                                 = 23  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_24                                 = 24  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_25                                 = 25  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_26                                 = 26  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_27                                 = 27  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_28                                 = 28  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_29                                 = 29  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_30                                 = 30  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_31                                 = 31  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_32                                 = 32  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_33                                 = 33  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_34                                 = 34  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_35                                 = 35  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_36                                 = 36  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_37                                 = 37  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_38                                 = 38  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_39                                 = 39  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_40                                 = 40  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_41                                 = 41  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_42                                 = 42  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_43                                 = 43  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_44                                 = 44  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_45                                 = 45  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_46                                 = 46  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_47                                 = 47  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_48                                 = 48  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_49                                 = 49  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_50                                 = 50  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_51                                 = 51  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_52                                 = 52  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_53                                 = 53  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_54                                 = 54  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_55                                 = 55  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_56                                 = 56  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_57                                 = 57  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_58                                 = 58  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_59                                 = 59  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_60                                 = 60  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_61                                 = 61  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_62                                 = 62  ;
static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_63                                 = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           = 61  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           = 61  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           = 61  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           = 56  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           = 57  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           = 58  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           = 59  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           = 60  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           = 61  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           = 63  ;

static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0                = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1                = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2                = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3                = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4                = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5                = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6                = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7                = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8                = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9                = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10               = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11               = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12               = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13               = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14               = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15               = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16               = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17               = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18               = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19               = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20               = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21               = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22               = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23               = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24               = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25               = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26               = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27               = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28               = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29               = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30               = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31               = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32               = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33               = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34               = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35               = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36               = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37               = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38               = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39               = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40               = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41               = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42               = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43               = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44               = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45               = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46               = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47               = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48               = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49               = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50               = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51               = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52               = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53               = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54               = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55               = 55  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56               = 56  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57               = 57  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58               = 58  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59               = 59  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60               = 60  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61               = 61  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62               = 62  ;
static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63               = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0         = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1         = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2         = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3         = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5         = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7         = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9         = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10        = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11        = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12        = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13        = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14        = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15        = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17        = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18        = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19        = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20        = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21        = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23        = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24        = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25        = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26        = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27        = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28        = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29        = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30        = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31        = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32        = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33        = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35        = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36        = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37        = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38        = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39        = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40        = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41        = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42        = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43        = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44        = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45        = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46        = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47        = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48        = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49        = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50        = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51        = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52        = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53        = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54        = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55        = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56        = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57        = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58        = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59        = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60        = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61        = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63        = 63  ;

static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_0                                  = 0   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_1                                  = 1   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_2                                  = 2   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_3                                  = 3   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_4                                  = 4   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_5                                  = 5   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_6                                  = 6   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_7                                  = 7   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_8                                  = 8   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_9                                  = 9   ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_10                                 = 10  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_11                                 = 11  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_12                                 = 12  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_13                                 = 13  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_14                                 = 14  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_15                                 = 15  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_16                                 = 16  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_17                                 = 17  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_18                                 = 18  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_19                                 = 19  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_20                                 = 20  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_21                                 = 21  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_22                                 = 22  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_23                                 = 23  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_24                                 = 24  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_25                                 = 25  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_26                                 = 26  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_27                                 = 27  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_28                                 = 28  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_29                                 = 29  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_30                                 = 30  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_31                                 = 31  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_32                                 = 32  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_33                                 = 33  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_34                                 = 34  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_35                                 = 35  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_36                                 = 36  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_37                                 = 37  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_38                                 = 38  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_39                                 = 39  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_40                                 = 40  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_41                                 = 41  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_42                                 = 42  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_43                                 = 43  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_44                                 = 44  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_45                                 = 45  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_46                                 = 46  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_47                                 = 47  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_48                                 = 48  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_49                                 = 49  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_50                                 = 50  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_51                                 = 51  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_52                                 = 52  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_53                                 = 53  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_54                                 = 54  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_55                                 = 55  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_56                                 = 56  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_57                                 = 57  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_58                                 = 58  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_59                                 = 59  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_60                                 = 60  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_61                                 = 61  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_62                                 = 62  ;
static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_63                                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0             = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1             = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2             = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3             = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4             = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5             = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6             = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7             = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8             = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9             = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10            = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11            = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12            = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13            = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14            = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15            = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16            = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17            = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18            = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19            = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20            = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21            = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22            = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23            = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24            = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25            = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26            = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27            = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28            = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29            = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30            = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31            = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32            = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33            = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34            = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35            = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36            = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37            = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38            = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39            = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40            = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41            = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43            = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44            = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45            = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46            = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47            = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48            = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49            = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50            = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51            = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52            = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53            = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54            = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55            = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56            = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57            = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58            = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59            = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60            = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61            = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62            = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63            = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           = 61  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_0                           = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_1                           = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_2                           = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_3                           = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_4                           = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_5                           = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_6                           = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_7                           = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_8                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_9                           = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_10                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_11                          = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_12                          = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_13                          = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_14                          = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_15                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_16                          = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_17                          = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_18                          = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_19                          = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_20                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_21                          = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_22                          = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_23                          = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_24                          = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_25                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_26                          = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_27                          = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_28                          = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_29                          = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_30                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_31                          = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_32                          = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_33                          = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_34                          = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_35                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_36                          = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_37                          = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_38                          = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_39                          = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_40                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_41                          = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_42                          = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_43                          = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_44                          = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_45                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_46                          = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_47                          = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_48                          = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_49                          = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_50                          = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_51                          = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_52                          = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_53                          = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_54                          = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_55                          = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_56                          = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_57                          = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_58                          = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_59                          = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_60                          = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_61                          = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_62                          = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_63                          = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0                = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1                = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2                = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3                = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4                = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5                = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6                = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7                = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8                = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9                = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10               = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11               = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12               = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13               = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14               = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15               = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16               = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17               = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18               = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19               = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20               = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21               = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22               = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23               = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24               = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25               = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26               = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27               = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28               = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29               = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30               = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31               = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32               = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33               = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34               = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35               = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36               = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37               = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38               = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39               = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40               = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41               = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42               = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43               = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44               = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45               = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46               = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47               = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48               = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49               = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50               = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51               = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52               = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53               = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54               = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55               = 55  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56               = 56  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57               = 57  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58               = 58  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59               = 59  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60               = 60  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61               = 61  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62               = 62  ;
static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63               = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0         = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1         = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2         = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3         = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5         = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7         = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9         = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10        = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11        = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12        = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13        = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14        = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15        = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17        = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18        = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19        = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20        = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21        = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23        = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24        = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25        = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26        = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27        = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28        = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29        = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30        = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31        = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32        = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33        = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35        = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36        = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37        = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38        = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39        = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40        = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41        = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42        = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43        = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44        = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45        = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46        = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47        = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48        = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49        = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50        = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51        = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52        = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53        = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54        = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55        = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56        = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57        = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58        = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59        = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60        = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61        = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63        = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_0                      = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_1                      = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_2                      = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_3                      = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_4                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_5                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_6                      = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_7                      = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_8                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_9                      = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_10                     = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_11                     = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_12                     = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_13                     = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_14                     = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_15                     = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_16                     = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_17                     = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_18                     = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_19                     = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_20                     = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_21                     = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_22                     = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_23                     = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_24                     = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_25                     = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_26                     = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_27                     = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_28                     = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_29                     = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_30                     = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_31                     = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_32                     = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_33                     = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_34                     = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_35                     = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_36                     = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_37                     = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_38                     = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_39                     = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_40                     = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_41                     = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_42                     = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_43                     = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_44                     = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_45                     = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_46                     = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_47                     = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_48                     = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_49                     = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_50                     = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_51                     = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_52                     = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_53                     = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_54                     = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_55                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_56                     = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_57                     = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_58                     = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_59                     = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_60                     = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_61                     = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_62                     = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_63                     = 63  ;

static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_0                             = 0   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_1                             = 1   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_2                             = 2   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_3                             = 3   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_4                             = 4   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_5                             = 5   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_6                             = 6   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_7                             = 7   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_8                             = 8   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_9                             = 9   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_10                            = 10  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_11                            = 11  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_12                            = 12  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_13                            = 13  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_14                            = 14  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_15                            = 15  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_16                            = 16  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_17                            = 17  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_18                            = 18  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_19                            = 19  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_20                            = 20  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_21                            = 21  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_22                            = 22  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_23                            = 23  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_24                            = 24  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_25                            = 25  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_26                            = 26  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_27                            = 27  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_28                            = 28  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_29                            = 29  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_30                            = 30  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_31                            = 31  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_32                            = 32  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_33                            = 33  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_34                            = 34  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_35                            = 35  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_36                            = 36  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_37                            = 37  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_38                            = 38  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_39                            = 39  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_40                            = 40  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_41                            = 41  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_42                            = 42  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_43                            = 43  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_44                            = 44  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_45                            = 45  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_46                            = 46  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_47                            = 47  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_48                            = 48  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_49                            = 49  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_50                            = 50  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_51                            = 51  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_52                            = 52  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_53                            = 53  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_54                            = 54  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_55                            = 55  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_56                            = 56  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_57                            = 57  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_58                            = 58  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_59                            = 59  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_60                            = 60  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_61                            = 61  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_62                            = 62  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_0                       = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_1                       = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_2                       = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_3                       = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_4                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_5                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_6                       = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_7                       = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_8                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_9                       = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_10                      = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_11                      = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_12                      = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_13                      = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_14                      = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_15                      = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_16                      = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_17                      = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_18                      = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_19                      = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_20                      = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_21                      = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_22                      = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_23                      = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_24                      = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_25                      = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_26                      = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_27                      = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_28                      = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_29                      = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_30                      = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_31                      = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_32                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_33                      = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_34                      = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_35                      = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_36                      = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_37                      = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_38                      = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_39                      = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_40                      = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_41                      = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_42                      = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_43                      = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_44                      = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_45                      = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_46                      = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_47                      = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_48                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_49                      = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_50                      = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_51                      = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_52                      = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_53                      = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_54                      = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_55                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_56                      = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_57                      = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_58                      = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_59                      = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_60                      = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_61                      = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_62                      = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_63                      = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_0                       = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_1                       = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_2                       = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_3                       = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_4                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_5                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_6                       = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_7                       = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_8                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_9                       = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_10                      = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_11                      = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_12                      = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_13                      = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_14                      = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_15                      = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_16                      = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_17                      = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_18                      = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_19                      = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_20                      = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_21                      = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_22                      = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_23                      = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_24                      = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_25                      = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_26                      = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_27                      = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_28                      = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_29                      = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_30                      = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_31                      = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_32                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_33                      = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_34                      = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_35                      = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_36                      = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_37                      = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_38                      = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_39                      = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_40                      = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_41                      = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_42                      = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_43                      = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_44                      = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_45                      = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_46                      = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_47                      = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_48                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_49                      = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_50                      = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_51                      = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_52                      = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_53                      = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_54                      = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_55                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_56                      = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_57                      = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_58                      = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_59                      = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_60                      = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_61                      = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_62                      = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_63                      = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_0                      = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_1                      = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_2                      = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_3                      = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_4                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_5                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_6                      = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_7                      = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_8                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_9                      = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_10                     = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_11                     = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_12                     = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_13                     = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_14                     = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_15                     = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_16                     = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_17                     = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_18                     = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_19                     = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_20                     = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_21                     = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_22                     = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_23                     = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_24                     = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_25                     = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_26                     = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_27                     = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_28                     = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_29                     = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_30                     = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_31                     = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_32                     = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_33                     = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_34                     = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_35                     = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_36                     = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_37                     = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_38                     = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_39                     = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_40                     = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_41                     = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_42                     = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_43                     = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_44                     = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_45                     = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_46                     = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_47                     = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_48                     = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_49                     = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_50                     = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_51                     = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_52                     = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_53                     = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_54                     = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_55                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_56                     = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_57                     = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_58                     = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_59                     = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_60                     = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_61                     = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_62                     = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_63                     = 63  ;

static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_0                             = 0   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_1                             = 1   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_2                             = 2   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_3                             = 3   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_4                             = 4   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_5                             = 5   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_6                             = 6   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_7                             = 7   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_8                             = 8   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_9                             = 9   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_10                            = 10  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_11                            = 11  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_12                            = 12  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_13                            = 13  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_14                            = 14  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_15                            = 15  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_16                            = 16  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_17                            = 17  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_18                            = 18  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_19                            = 19  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_20                            = 20  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_21                            = 21  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_22                            = 22  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_23                            = 23  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_24                            = 24  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_25                            = 25  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_26                            = 26  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_27                            = 27  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_28                            = 28  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_29                            = 29  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_30                            = 30  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_31                            = 31  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_32                            = 32  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_33                            = 33  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_34                            = 34  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_35                            = 35  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_36                            = 36  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_37                            = 37  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_38                            = 38  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_39                            = 39  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_40                            = 40  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_41                            = 41  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_42                            = 42  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_43                            = 43  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_44                            = 44  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_45                            = 45  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_46                            = 46  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_47                            = 47  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_48                            = 48  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_49                            = 49  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_50                            = 50  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_51                            = 51  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_52                            = 52  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_53                            = 53  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_54                            = 54  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_55                            = 55  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_56                            = 56  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_57                            = 57  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_58                            = 58  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_59                            = 59  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_60                            = 60  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_61                            = 61  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_62                            = 62  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_0                      = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_1                      = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_2                      = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_3                      = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_4                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_5                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_6                      = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_7                      = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_8                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_9                      = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_10                     = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_11                     = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_12                     = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_13                     = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_14                     = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_15                     = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_16                     = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_17                     = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_18                     = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_19                     = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_20                     = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_21                     = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_22                     = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_23                     = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_24                     = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_25                     = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_26                     = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_27                     = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_28                     = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_29                     = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_30                     = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_31                     = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_32                     = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_33                     = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_34                     = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_35                     = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_36                     = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_37                     = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_38                     = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_39                     = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_40                     = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_41                     = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_42                     = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_43                     = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_44                     = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_45                     = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_46                     = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_47                     = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_48                     = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_49                     = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_50                     = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_51                     = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_52                     = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_53                     = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_54                     = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_55                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_56                     = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_57                     = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_58                     = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_59                     = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_60                     = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_61                     = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_62                     = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_63                     = 63  ;

static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_0                             = 0   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_1                             = 1   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_2                             = 2   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_3                             = 3   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_4                             = 4   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_5                             = 5   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_6                             = 6   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_7                             = 7   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_8                             = 8   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_9                             = 9   ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_10                            = 10  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_11                            = 11  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_12                            = 12  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_13                            = 13  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_14                            = 14  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_15                            = 15  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_16                            = 16  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_17                            = 17  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_18                            = 18  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_19                            = 19  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_20                            = 20  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_21                            = 21  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_22                            = 22  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_23                            = 23  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_24                            = 24  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_25                            = 25  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_26                            = 26  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_27                            = 27  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_28                            = 28  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_29                            = 29  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_30                            = 30  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_31                            = 31  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_32                            = 32  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_33                            = 33  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_34                            = 34  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_35                            = 35  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_36                            = 36  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_37                            = 37  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_38                            = 38  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_39                            = 39  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_40                            = 40  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_41                            = 41  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_42                            = 42  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_43                            = 43  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_44                            = 44  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_45                            = 45  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_46                            = 46  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_47                            = 47  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_48                            = 48  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_49                            = 49  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_50                            = 50  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_51                            = 51  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_52                            = 52  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_53                            = 53  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_54                            = 54  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_55                            = 55  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_56                            = 56  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_57                            = 57  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_58                            = 58  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_59                            = 59  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_60                            = 60  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_61                            = 61  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_62                            = 62  ;
static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_0                       = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_1                       = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_2                       = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_3                       = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_4                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_5                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_6                       = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_7                       = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_8                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_9                       = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_10                      = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_11                      = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_12                      = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_13                      = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_14                      = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_15                      = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_16                      = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_17                      = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_18                      = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_19                      = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_20                      = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_21                      = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_22                      = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_23                      = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_24                      = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_25                      = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_26                      = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_27                      = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_28                      = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_29                      = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_30                      = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_31                      = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_32                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_33                      = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_34                      = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_35                      = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_36                      = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_37                      = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_38                      = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_39                      = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_40                      = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_41                      = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_42                      = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_43                      = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_44                      = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_45                      = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_46                      = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_47                      = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_48                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_49                      = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_50                      = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_51                      = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_52                      = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_53                      = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_54                      = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_55                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_56                      = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_57                      = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_58                      = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_59                      = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_60                      = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_61                      = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_62                      = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_63                      = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_0                       = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_1                       = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_2                       = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_3                       = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_4                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_5                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_6                       = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_7                       = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_8                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_9                       = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_10                      = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_11                      = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_12                      = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_13                      = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_14                      = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_15                      = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_16                      = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_17                      = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_18                      = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_19                      = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_20                      = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_21                      = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_22                      = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_23                      = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_24                      = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_25                      = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_26                      = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_27                      = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_28                      = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_29                      = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_30                      = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_31                      = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_32                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_33                      = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_34                      = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_35                      = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_36                      = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_37                      = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_38                      = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_39                      = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_40                      = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_41                      = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_42                      = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_43                      = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_44                      = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_45                      = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_46                      = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_47                      = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_48                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_49                      = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_50                      = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_51                      = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_52                      = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_53                      = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_54                      = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_55                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_56                      = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_57                      = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_58                      = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_59                      = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_60                      = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_61                      = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_62                      = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_63                      = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_0                      = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_1                      = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_2                      = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_3                      = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_4                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_5                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_6                      = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_7                      = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_8                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_9                      = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_10                     = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_11                     = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_12                     = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_13                     = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_14                     = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_15                     = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_16                     = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_17                     = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_18                     = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_19                     = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_20                     = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_21                     = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_22                     = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_23                     = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_24                     = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_25                     = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_26                     = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_27                     = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_28                     = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_29                     = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_30                     = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_31                     = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_32                     = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_33                     = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_34                     = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_35                     = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_36                     = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_37                     = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_38                     = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_39                     = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_40                     = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_41                     = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_42                     = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_43                     = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_44                     = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_45                     = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_46                     = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_47                     = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_48                     = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_49                     = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_50                     = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_51                     = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_52                     = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_53                     = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_54                     = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_55                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_56                     = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_57                     = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_58                     = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_59                     = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_60                     = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_61                     = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_62                     = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_63                     = 63  ;

static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_0                             = 0   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_1                             = 1   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_2                             = 2   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_3                             = 3   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_4                             = 4   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_5                             = 5   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_6                             = 6   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_7                             = 7   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_8                             = 8   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_9                             = 9   ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_10                            = 10  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_11                            = 11  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_12                            = 12  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_13                            = 13  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_14                            = 14  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_15                            = 15  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_16                            = 16  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_17                            = 17  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_18                            = 18  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_19                            = 19  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_20                            = 20  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_21                            = 21  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_22                            = 22  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_23                            = 23  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_24                            = 24  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_25                            = 25  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_26                            = 26  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_27                            = 27  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_28                            = 28  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_29                            = 29  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_30                            = 30  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_31                            = 31  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_32                            = 32  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_33                            = 33  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_34                            = 34  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_35                            = 35  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_36                            = 36  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_37                            = 37  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_38                            = 38  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_39                            = 39  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_40                            = 40  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_41                            = 41  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_42                            = 42  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_43                            = 43  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_44                            = 44  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_45                            = 45  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_46                            = 46  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_47                            = 47  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_48                            = 48  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_49                            = 49  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_50                            = 50  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_51                            = 51  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_52                            = 52  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_53                            = 53  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_54                            = 54  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_55                            = 55  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_56                            = 56  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_57                            = 57  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_58                            = 58  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_59                            = 59  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_60                            = 60  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_61                            = 61  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_62                            = 62  ;
static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7           = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8           = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9           = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15          = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0            = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1            = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2            = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3            = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4            = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5            = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6            = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7            = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8            = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9            = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10           = 18  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11           = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12           = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13           = 21  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14           = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15           = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16           = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17           = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18           = 26  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19           = 27  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_0            = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_1            = 29  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_2            = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_3            = 31  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_4            = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_5            = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_6            = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_7            = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0           = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1           = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2           = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3           = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4           = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5           = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6           = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7           = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4            = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5            = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6            = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7            = 51  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0            = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1            = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2            = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3            = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0            = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1            = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2            = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3            = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0            = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1            = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2            = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3            = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7           = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8           = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9           = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15          = 63  ;

static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0                  = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1                  = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2                  = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3                  = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4                  = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5                  = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7                  = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8                  = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9                  = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10                 = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11                 = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13                 = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14                 = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15                 = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16                 = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17                 = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18                 = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19                 = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20                 = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21                 = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22                 = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23                 = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0                  = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1                  = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2                  = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3                  = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4                  = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5                  = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6                  = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7                  = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0                 = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1                 = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2                 = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3                 = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0                  = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1                  = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2                  = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3                  = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4                  = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5                  = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6                  = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7                  = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0                  = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1                  = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2                  = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3                  = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0                  = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1                  = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2                  = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3                  = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4                  = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5                  = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6                  = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7                  = 55  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8                  = 56  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9                  = 57  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10                 = 58  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11                 = 59  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12                 = 60  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13                 = 61  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14                 = 62  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15                 = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0               = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1               = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2               = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7               = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9               = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10              = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11              = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14              = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15              = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16              = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17              = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18              = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19              = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20              = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21              = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22              = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23              = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0               = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1               = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2               = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3               = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4               = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5               = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6               = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7               = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0              = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1              = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2              = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3              = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0               = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1               = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4               = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6               = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7               = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_0               = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_1               = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_2               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_3               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0               = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1               = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2               = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3               = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4               = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5               = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6               = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7               = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8               = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9               = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10              = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11              = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12              = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13              = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14              = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15              = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15             = 63  ;

static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0                      = 0   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1                      = 1   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2                      = 2   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3                      = 3   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4                      = 4   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5                      = 5   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6                      = 6   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7                      = 7   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0                      = 8   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1                      = 9   ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2                      = 10  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3                      = 11  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4                      = 12  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5                      = 13  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6                      = 14  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7                      = 15  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8                      = 16  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9                      = 17  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10                     = 18  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11                     = 19  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12                     = 20  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13                     = 21  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14                     = 22  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15                     = 23  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16                     = 24  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17                     = 25  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18                     = 26  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19                     = 27  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_0                      = 28  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_1                      = 29  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_2                      = 30  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_3                      = 31  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_4                      = 32  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_5                      = 33  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_6                      = 34  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_7                      = 35  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0                     = 36  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1                     = 37  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2                     = 38  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3                     = 39  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4                     = 40  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5                     = 41  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6                     = 42  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7                     = 43  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0                      = 44  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1                      = 45  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2                      = 46  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3                      = 47  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4                      = 48  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5                      = 49  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6                      = 50  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7                      = 51  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0                      = 52  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1                      = 53  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2                      = 54  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3                      = 55  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0                      = 56  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1                      = 57  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2                      = 58  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3                      = 59  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0                      = 60  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1                      = 61  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2                      = 62  ;
static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3                      = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0                  = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1                  = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2                  = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3                  = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4                  = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5                  = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7                  = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8                  = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9                  = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10                 = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11                 = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13                 = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14                 = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15                 = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16                 = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17                 = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18                 = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19                 = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20                 = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21                 = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22                 = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23                 = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0                  = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1                  = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2                  = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3                  = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4                  = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5                  = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6                  = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7                  = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0                 = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1                 = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2                 = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3                 = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0                  = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1                  = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2                  = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3                  = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4                  = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5                  = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6                  = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7                  = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0                  = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1                  = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2                  = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3                  = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0                  = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1                  = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2                  = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3                  = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4                  = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5                  = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6                  = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7                  = 55  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8                  = 56  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9                  = 57  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10                 = 58  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11                 = 59  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12                 = 60  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13                 = 61  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14                 = 62  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7           = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8           = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9           = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15          = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1          = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5          = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7          = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9          = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11         = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13         = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14         = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15         = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0           = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2           = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3           = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0           = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1           = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2           = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3           = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11          = 55  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             = 55  ;

static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4            = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5            = 21  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6            = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7            = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0            = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1            = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2            = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3            = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4            = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5            = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6            = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7            = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0            = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1            = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2            = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3            = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4            = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5            = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6            = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7            = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0            = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1            = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2            = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3            = 51  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4            = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5            = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6            = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7            = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0           = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1           = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2           = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3           = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0           = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1           = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2           = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0                 = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1                 = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2                 = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3                 = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4                 = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5                 = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6                 = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7                 = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8                 = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9                 = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10                = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11                = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12                = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13                = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14                = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15                = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0                  = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1                  = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2                  = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3                  = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0                  = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1                  = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2                  = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3                  = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0                  = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1                  = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2                  = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3                  = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4                  = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5                  = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6                  = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7                  = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0                  = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1                  = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2                  = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3                  = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4                  = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5                  = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6                  = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7                  = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8                  = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9                  = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10                 = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11                 = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0                  = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1                  = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2                  = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3                  = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4                  = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5                  = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6                  = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7                  = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8                  = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9                  = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10                 = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11                 = 55  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1          = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5          = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7          = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9          = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11         = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13         = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14         = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15         = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0           = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2           = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3           = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0           = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1           = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2           = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3           = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11          = 55  ;

static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1              = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2              = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3              = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5              = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7              = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9              = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10             = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11             = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12             = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13             = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14             = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15             = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0               = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1               = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2               = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3               = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0               = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1               = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2               = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3               = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0               = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1               = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2               = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3               = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4               = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5               = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6               = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7               = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0               = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1               = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2               = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3               = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4               = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5               = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8               = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10              = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11              = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0               = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1               = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4               = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5               = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6               = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7               = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8               = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9               = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11              = 55  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             = 55  ;

static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0                      = 0   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1                      = 1   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2                      = 2   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3                      = 3   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4                      = 4   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5                      = 5   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6                      = 6   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7                      = 7   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8                      = 8   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9                      = 9   ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10                     = 10  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11                     = 11  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12                     = 12  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13                     = 13  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14                     = 14  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15                     = 15  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0                      = 16  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1                      = 17  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2                      = 18  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3                      = 19  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4                      = 20  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5                      = 21  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6                      = 22  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7                      = 23  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0                      = 24  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1                      = 25  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2                      = 26  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3                      = 27  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4                      = 28  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5                      = 29  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6                      = 30  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7                      = 31  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0                      = 32  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1                      = 33  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2                      = 34  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3                      = 35  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4                      = 36  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5                      = 37  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6                      = 38  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7                      = 39  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0                      = 40  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1                      = 41  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2                      = 42  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3                      = 43  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4                      = 44  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5                      = 45  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6                      = 46  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7                      = 47  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0                      = 48  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1                      = 49  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2                      = 50  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3                      = 51  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4                      = 52  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5                      = 53  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6                      = 54  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7                      = 55  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0                     = 56  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1                     = 57  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2                     = 58  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3                     = 59  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0                     = 60  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1                     = 61  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2                     = 62  ;
static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3                     = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0                 = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1                 = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2                 = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3                 = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4                 = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5                 = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6                 = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7                 = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8                 = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9                 = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10                = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11                = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12                = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13                = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14                = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15                = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0                  = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1                  = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2                  = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3                  = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0                  = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1                  = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2                  = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3                  = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0                  = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1                  = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2                  = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3                  = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4                  = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5                  = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6                  = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7                  = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0                  = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1                  = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2                  = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3                  = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4                  = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5                  = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6                  = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7                  = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8                  = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9                  = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10                 = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11                 = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0                  = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1                  = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2                  = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3                  = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4                  = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5                  = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6                  = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7                  = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8                  = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9                  = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10                 = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11                 = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1          = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5          = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7          = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9          = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11         = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13         = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14         = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15         = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0           = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2           = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3           = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0           = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1           = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2           = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3           = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11          = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26          = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31          = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37          = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38          = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39          = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41          = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44          = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45          = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46          = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47          = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48          = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49          = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50          = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51          = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52          = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53          = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55          = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56          = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57          = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63          = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             = 63  ;

static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0                  = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1                  = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2                  = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3                  = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4                  = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5                  = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7                  = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8                  = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9                  = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10                 = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11                 = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13                 = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14                 = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15                 = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16                 = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17                 = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18                 = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19                 = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20                 = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21                 = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22                 = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23                 = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24                 = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25                 = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26                 = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27                 = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28                 = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29                 = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30                 = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31                 = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32                 = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33                 = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34                 = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35                 = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36                 = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37                 = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38                 = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39                 = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40                 = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41                 = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42                 = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43                 = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44                 = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45                 = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46                 = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47                 = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48                 = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49                 = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50                 = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51                 = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52                 = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53                 = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54                 = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55                 = 55  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56                 = 56  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57                 = 57  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58                 = 58  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59                 = 59  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60                 = 60  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61                 = 61  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62                 = 62  ;
static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26          = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31          = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37          = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38          = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39          = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41          = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44          = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45          = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46          = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47          = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48          = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49          = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50          = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51          = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52          = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53          = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55          = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56          = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57          = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63          = 63  ;

static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0               = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1               = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2               = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7               = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9               = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10              = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11              = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14              = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15              = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16              = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17              = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18              = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19              = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20              = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21              = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22              = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23              = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24              = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25              = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26              = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27              = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28              = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29              = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30              = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31              = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32              = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33              = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34              = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35              = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36              = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37              = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38              = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39              = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40              = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41              = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42              = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43              = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44              = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45              = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46              = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47              = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48              = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49              = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50              = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51              = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52              = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53              = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55              = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56              = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57              = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58              = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59              = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60              = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61              = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62              = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63              = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0                  = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1                  = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2                  = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3                  = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4                  = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5                  = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7                  = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8                  = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9                  = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10                 = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11                 = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13                 = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14                 = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15                 = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16                 = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17                 = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18                 = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19                 = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20                 = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21                 = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22                 = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23                 = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24                 = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25                 = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26                 = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27                 = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28                 = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29                 = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30                 = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31                 = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32                 = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33                 = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34                 = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35                 = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36                 = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37                 = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38                 = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39                 = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40                 = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41                 = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42                 = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43                 = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44                 = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45                 = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46                 = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47                 = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48                 = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49                 = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50                 = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51                 = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52                 = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53                 = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54                 = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55                 = 55  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56                 = 56  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57                 = 57  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58                 = 58  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59                 = 59  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60                 = 60  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61                 = 61  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62                 = 62  ;
static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26          = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31          = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37          = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38          = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39          = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41          = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44          = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45          = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46          = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47          = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48          = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49          = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50          = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51          = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52          = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53          = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55          = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56          = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57          = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63          = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_FIRST_BITS                        = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_FIRST_BITS_LEN                    = 17  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_BBUF_RDWR              = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_RDWR              = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_OBUF_RDWR              = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_RQIN_OVF               = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE          = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_PBTX_PIPE              = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE            = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE            = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_AMO_ADDR               = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_PBRX_RTAG              = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_WRITE             = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_WARB              = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_MASK_BITS                         = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_MASK_BITS_LEN                     = 17  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7           = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_0           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_1           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_2           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_3           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_4           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_5           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_6           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_7           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_8           = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_9           = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_10          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_11          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_12          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_13          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_14          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_15          = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_0            = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_1            = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_2            = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_3            = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_4            = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_5            = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_6            = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_7            = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_8            = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_9            = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_10           = 18  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_11           = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_12           = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_13           = 21  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_14           = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_15           = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_16           = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_17           = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_18           = 26  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_19           = 27  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_0            = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_1            = 29  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_2            = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_3            = 31  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_4            = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_5            = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_6            = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_7            = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0           = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1           = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2           = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3           = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4           = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5           = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6           = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7           = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_0            = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_1            = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_2            = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_3            = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_4            = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_5            = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_6            = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_7            = 51  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_0            = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_1            = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_2            = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_3            = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_0            = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_1            = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_2            = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_3            = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_0            = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_1            = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_2            = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_3            = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7           = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_0           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_1           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_2           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_3           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_4           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_5           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_6           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_7           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_8           = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_9           = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_10          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_11          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_12          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_13          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_14          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_15          = 63  ;

static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_0                  = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_1                  = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_2                  = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_3                  = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_4                  = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_5                  = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_6                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_7                  = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_8                  = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_9                  = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_10                 = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_11                 = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_12                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_13                 = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_14                 = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_15                 = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_16                 = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_17                 = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_18                 = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_19                 = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_20                 = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_21                 = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_22                 = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_23                 = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_0                  = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_1                  = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_2                  = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_3                  = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_4                  = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_5                  = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_6                  = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_7                  = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0                 = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1                 = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2                 = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3                 = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_0                  = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_1                  = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_2                  = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_3                  = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_4                  = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_5                  = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_6                  = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_7                  = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_0                  = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_1                  = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_2                  = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_3                  = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_0                  = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_1                  = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_2                  = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_3                  = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_4                  = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_5                  = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_6                  = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_7                  = 55  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_8                  = 56  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_9                  = 57  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_10                 = 58  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_11                 = 59  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_12                 = 60  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_13                 = 61  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_14                 = 62  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_15                 = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_0               = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_1               = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_2               = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_3               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_4               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_5               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_6               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_7               = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_8               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_9               = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_10              = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_11              = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_12              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_13              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_14              = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_15              = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_16              = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_17              = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_18              = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_19              = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_20              = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_21              = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_22              = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_23              = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_0               = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_1               = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_2               = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_3               = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_4               = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_5               = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_6               = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_7               = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_0              = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_1              = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_2              = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_3              = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_0               = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_1               = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_2               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_3               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_4               = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_5               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_6               = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_7               = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_0               = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_1               = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_2               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_3               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_0               = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_1               = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_2               = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_3               = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_4               = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_5               = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_6               = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_7               = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_8               = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_9               = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_10              = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_11              = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_12              = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_13              = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_14              = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_15              = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_15             = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7              = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_0              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_1              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_2              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_3              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_4              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_5              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_6              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_7              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_8              = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_9              = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_10             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_11             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_12             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_13             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_14             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_15             = 63  ;

static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_0                      = 0   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_1                      = 1   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_2                      = 2   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_3                      = 3   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_4                      = 4   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_5                      = 5   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_6                      = 6   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_7                      = 7   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_0                      = 8   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_1                      = 9   ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_2                      = 10  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_3                      = 11  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_4                      = 12  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_5                      = 13  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_6                      = 14  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_7                      = 15  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_8                      = 16  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_9                      = 17  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_10                     = 18  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_11                     = 19  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_12                     = 20  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_13                     = 21  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_14                     = 22  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_15                     = 23  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_16                     = 24  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_17                     = 25  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_18                     = 26  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_19                     = 27  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_0                      = 28  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_1                      = 29  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_2                      = 30  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_3                      = 31  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_4                      = 32  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_5                      = 33  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_6                      = 34  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_7                      = 35  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0                     = 36  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1                     = 37  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2                     = 38  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3                     = 39  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4                     = 40  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5                     = 41  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6                     = 42  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7                     = 43  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_0                      = 44  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_1                      = 45  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_2                      = 46  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_3                      = 47  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_4                      = 48  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_5                      = 49  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_6                      = 50  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_7                      = 51  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_0                      = 52  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_1                      = 53  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_2                      = 54  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_3                      = 55  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_0                      = 56  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_1                      = 57  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_2                      = 58  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_3                      = 59  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_0                      = 60  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_1                      = 61  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_2                      = 62  ;
static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_3                      = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_0                  = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_1                  = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_2                  = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_3                  = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_4                  = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_5                  = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_6                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_7                  = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_8                  = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_9                  = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_10                 = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_11                 = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_12                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_13                 = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_14                 = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_15                 = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_16                 = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_17                 = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_18                 = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_19                 = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_20                 = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_21                 = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_22                 = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_23                 = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_0                  = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_1                  = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_2                  = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_3                  = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_4                  = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_5                  = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_6                  = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_7                  = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0                 = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1                 = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2                 = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3                 = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_0                  = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_1                  = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_2                  = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_3                  = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_4                  = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_5                  = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_6                  = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_7                  = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_0                  = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_1                  = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_2                  = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_3                  = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_0                  = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_1                  = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_2                  = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_3                  = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_4                  = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_5                  = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_6                  = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_7                  = 55  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_8                  = 56  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_9                  = 57  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_10                 = 58  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_11                 = 59  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_12                 = 60  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_13                 = 61  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_14                 = 62  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_15                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7           = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_0           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_1           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_2           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_3           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_4           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_5           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_6           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_7           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_8           = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_9           = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_10          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_11          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_12          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_13          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_14          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_15          = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1          = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5          = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7          = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9          = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11         = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13         = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14         = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15         = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0           = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2           = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3           = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0           = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1           = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2           = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3           = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11          = 55  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11             = 55  ;

static const uint8_t P9N2__SM1_CERR_MASK1_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM1_CERR_MASK1_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_0            = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_1            = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_2            = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_3            = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_4            = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_5            = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_6            = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_7            = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_8            = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_9            = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_10           = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_11           = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_12           = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_13           = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_14           = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_15           = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_0            = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_1            = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_2            = 18  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_3            = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_4            = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_5            = 21  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_6            = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_7            = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_0            = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_1            = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_2            = 26  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_3            = 27  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_4            = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_5            = 29  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_6            = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_7            = 31  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_0            = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_1            = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_2            = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_3            = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_4            = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_5            = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_6            = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_7            = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_0            = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_1            = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_2            = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_3            = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_4            = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_5            = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_6            = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_7            = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_0            = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_1            = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_2            = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_3            = 51  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_4            = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_5            = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_6            = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_7            = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0           = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1           = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2           = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3           = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0           = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1           = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2           = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0                 = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1                 = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2                 = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3                 = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4                 = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5                 = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6                 = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7                 = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8                 = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9                 = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10                = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11                = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12                = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13                = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14                = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15                = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_0                  = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_1                  = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_2                  = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_3                  = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_0                  = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_1                  = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_2                  = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_3                  = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_0                  = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_1                  = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_2                  = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_3                  = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_4                  = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_5                  = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_6                  = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_7                  = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_0                  = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_1                  = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_2                  = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_3                  = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_4                  = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_5                  = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_6                  = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_7                  = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_8                  = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_9                  = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_10                 = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_11                 = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_0                  = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_1                  = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_2                  = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_3                  = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_4                  = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_5                  = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_6                  = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_7                  = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_8                  = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_9                  = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_10                 = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_11                 = 55  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11             = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1          = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5          = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7          = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9          = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11         = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13         = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14         = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15         = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0           = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2           = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3           = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0           = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1           = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2           = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3           = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11          = 55  ;

static const uint8_t P9N2__SM0_CERR_MASK1_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM0_CERR_MASK1_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_0              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_1              = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_2              = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_3              = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_4              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_5              = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_6              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_7              = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_8              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_9              = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_10             = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_11             = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_12             = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_13             = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_14             = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_15             = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_0               = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_1               = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_2               = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_3               = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_0               = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_1               = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_2               = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_3               = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_0               = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_1               = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_2               = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_3               = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_4               = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_5               = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_6               = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_7               = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_0               = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_1               = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_2               = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_3               = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_4               = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_5               = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_6               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_7               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_8               = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_9               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_10              = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_11              = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_0               = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_1               = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_2               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_3               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_4               = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_5               = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_6               = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_7               = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_8               = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_9               = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_10              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_11              = 55  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0              = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2              = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3              = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1              = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2              = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3              = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4              = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5              = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0              = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1              = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2              = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3              = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7              = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8              = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9              = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0              = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1              = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2              = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3              = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5              = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6              = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7              = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8              = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9              = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11             = 55  ;

static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_0                      = 0   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_1                      = 1   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_2                      = 2   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_3                      = 3   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_4                      = 4   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_5                      = 5   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_6                      = 6   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_7                      = 7   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_8                      = 8   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_9                      = 9   ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_10                     = 10  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_11                     = 11  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_12                     = 12  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_13                     = 13  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_14                     = 14  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_15                     = 15  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_0                      = 16  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_1                      = 17  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_2                      = 18  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_3                      = 19  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_4                      = 20  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_5                      = 21  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_6                      = 22  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_7                      = 23  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_0                      = 24  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_1                      = 25  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_2                      = 26  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_3                      = 27  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_4                      = 28  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_5                      = 29  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_6                      = 30  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_7                      = 31  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_0                      = 32  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_1                      = 33  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_2                      = 34  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_3                      = 35  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_4                      = 36  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_5                      = 37  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_6                      = 38  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_7                      = 39  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_0                      = 40  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_1                      = 41  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_2                      = 42  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_3                      = 43  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_4                      = 44  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_5                      = 45  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_6                      = 46  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_7                      = 47  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_0                      = 48  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_1                      = 49  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_2                      = 50  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_3                      = 51  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_4                      = 52  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_5                      = 53  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_6                      = 54  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_7                      = 55  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0                     = 56  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1                     = 57  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2                     = 58  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3                     = 59  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0                     = 60  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1                     = 61  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2                     = 62  ;
static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3                     = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0                 = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1                 = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2                 = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3                 = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4                 = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5                 = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6                 = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7                 = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8                 = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9                 = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10                = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11                = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12                = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13                = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14                = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15                = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_0                  = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_1                  = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_2                  = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_3                  = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_0                  = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_1                  = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_2                  = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_3                  = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_0                  = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_1                  = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_2                  = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_3                  = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_4                  = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_5                  = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_6                  = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_7                  = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_0                  = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_1                  = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_2                  = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_3                  = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_4                  = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_5                  = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_6                  = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_7                  = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_8                  = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_9                  = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_10                 = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_11                 = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_0                  = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_1                  = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_2                  = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_3                  = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_4                  = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_5                  = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_6                  = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_7                  = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_8                  = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_9                  = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_10                 = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_11                 = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1          = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5          = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7          = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9          = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11         = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13         = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14         = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15         = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0           = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2           = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3           = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1           = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2           = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3           = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4           = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5           = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0           = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1           = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2           = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3           = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7           = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8           = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9           = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0           = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1           = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2           = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3           = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5           = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6           = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7           = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8           = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9           = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11          = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26          = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31          = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37          = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38          = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39          = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41          = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44          = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45          = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46          = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47          = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48          = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49          = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50          = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51          = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52          = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53          = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55          = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56          = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57          = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63          = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63             = 63  ;

static const uint8_t P9N2__SM1_CERR_MASK2_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM1_CERR_MASK2_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_0                  = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_1                  = 1   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_2                  = 2   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_3                  = 3   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_4                  = 4   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_5                  = 5   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_6                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_7                  = 7   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_8                  = 8   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_9                  = 9   ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_10                 = 10  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_11                 = 11  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_12                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_13                 = 13  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_14                 = 14  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_15                 = 15  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_16                 = 16  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_17                 = 17  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_18                 = 18  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_19                 = 19  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_20                 = 20  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_21                 = 21  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_22                 = 22  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_23                 = 23  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_24                 = 24  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_25                 = 25  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_26                 = 26  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_27                 = 27  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_28                 = 28  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_29                 = 29  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_30                 = 30  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_31                 = 31  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_32                 = 32  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_33                 = 33  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_34                 = 34  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_35                 = 35  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_36                 = 36  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_37                 = 37  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_38                 = 38  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_39                 = 39  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_40                 = 40  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_41                 = 41  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_42                 = 42  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_43                 = 43  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_44                 = 44  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_45                 = 45  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_46                 = 46  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_47                 = 47  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_48                 = 48  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_49                 = 49  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_50                 = 50  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_51                 = 51  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_52                 = 52  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_53                 = 53  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_54                 = 54  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_55                 = 55  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_56                 = 56  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_57                 = 57  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_58                 = 58  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_59                 = 59  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_60                 = 60  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_61                 = 61  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_62                 = 62  ;
static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_63                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26          = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31          = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37          = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38          = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39          = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41          = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44          = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45          = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46          = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47          = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48          = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49          = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50          = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51          = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52          = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53          = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55          = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56          = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57          = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63          = 63  ;

static const uint8_t P9N2__SM0_CERR_MASK2_NTL_0                                   = 0   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_1                                   = 1   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_2                                   = 2   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_3                                   = 3   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_4                                   = 4   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_5                                   = 5   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_6                                   = 6   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_7                                   = 7   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_8                                   = 8   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_9                                   = 9   ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_10                                  = 10  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_11                                  = 11  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_12                                  = 12  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_13                                  = 13  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_14                                  = 14  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_15                                  = 15  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_16                                  = 16  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_17                                  = 17  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_18                                  = 18  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_19                                  = 19  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_20                                  = 20  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_21                                  = 21  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_22                                  = 22  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_23                                  = 23  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_24                                  = 24  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_25                                  = 25  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_26                                  = 26  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_27                                  = 27  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_28                                  = 28  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_29                                  = 29  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_30                                  = 30  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_31                                  = 31  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_32                                  = 32  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_33                                  = 33  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_34                                  = 34  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_35                                  = 35  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_36                                  = 36  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_37                                  = 37  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_38                                  = 38  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_39                                  = 39  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_40                                  = 40  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_41                                  = 41  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_42                                  = 42  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_43                                  = 43  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_44                                  = 44  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_45                                  = 45  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_46                                  = 46  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_47                                  = 47  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_48                                  = 48  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_49                                  = 49  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_50                                  = 50  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_51                                  = 51  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_52                                  = 52  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_53                                  = 53  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_54                                  = 54  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_55                                  = 55  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_56                                  = 56  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_57                                  = 57  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_58                                  = 58  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_59                                  = 59  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_60                                  = 60  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_61                                  = 61  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_62                                  = 62  ;
static const uint8_t P9N2__SM0_CERR_MASK2_NTL_63                                  = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_0               = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_1               = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_2               = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_3               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_4               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_5               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_6               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_7               = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_8               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_9               = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_10              = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_11              = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_12              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_13              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_14              = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_15              = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_16              = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_17              = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_18              = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_19              = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_20              = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_21              = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_22              = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_23              = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_24              = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_25              = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_26              = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_27              = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_28              = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_29              = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_30              = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_31              = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_32              = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_33              = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_34              = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_35              = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_36              = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_37              = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_38              = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_39              = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_40              = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_41              = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_42              = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_43              = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_44              = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_45              = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_46              = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_47              = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_48              = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_49              = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_50              = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_51              = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_52              = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_53              = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_54              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_55              = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_56              = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_57              = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_58              = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_59              = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_60              = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_61              = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_62              = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_63              = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2              = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7              = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8              = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9              = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10             = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11             = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13             = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14             = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15             = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16             = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17             = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19             = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20             = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21             = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22             = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23             = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26             = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31             = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32             = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37             = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38             = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39             = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41             = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42             = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43             = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44             = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45             = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46             = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47             = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48             = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49             = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50             = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51             = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52             = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53             = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54             = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55             = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56             = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57             = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58             = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59             = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60             = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61             = 61  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62             = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63             = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_1                             = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_2                             = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_3                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_4                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_5                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_6                             = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_7                             = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_8                             = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_9                             = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_10                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_11                            = 11  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_12                            = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_13                            = 13  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_14                            = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_15                            = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_16                            = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_17                            = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_18                            = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_19                            = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_20                            = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_21                            = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_22                            = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_23                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_24                            = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_25                            = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_26                            = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_27                            = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_28                            = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_29                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_30                            = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_31                            = 31  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_32                            = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_33                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_34                            = 34  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_35                            = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_36                            = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_37                            = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_38                            = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_39                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_40                            = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_41                            = 41  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_42                            = 42  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_43                            = 43  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_44                            = 44  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_45                            = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_46                            = 46  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_47                            = 47  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_48                            = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_49                            = 49  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_50                            = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_51                            = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_52                            = 52  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_53                            = 53  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_54                            = 54  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_55                            = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_56                            = 56  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_57                            = 57  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_58                            = 58  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_59                            = 59  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_60                            = 60  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_61                            = 61  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_62                            = 62  ;
static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_63                            = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_0                            = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_1                            = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_2                            = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_3                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_4                            = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_5                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_6                            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_7                            = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_8                            = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_9                            = 9   ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_10                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_11                           = 11  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_12                           = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_13                           = 13  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_14                           = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_15                           = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_16                           = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_17                           = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_18                           = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_19                           = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_20                           = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_21                           = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_22                           = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_23                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_24                           = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_25                           = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_26                           = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_27                           = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_28                           = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_29                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_30                           = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_31                           = 31  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_32                           = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_33                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_34                           = 34  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_35                           = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_36                           = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_37                           = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_38                           = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_39                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_40                           = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_41                           = 41  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_42                           = 42  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_43                           = 43  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_44                           = 44  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_45                           = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_46                           = 46  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_47                           = 47  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_48                           = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_49                           = 49  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_50                           = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_51                           = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_52                           = 52  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_53                           = 53  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_54                           = 54  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_55                           = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_56                           = 56  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_57                           = 57  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_58                           = 58  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_59                           = 59  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_60                           = 60  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_61                           = 61  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_62                           = 62  ;
static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_63                           = 63  ;

static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_0                  = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_1                  = 1   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_2                  = 2   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_3                  = 3   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_4                  = 4   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_5                  = 5   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_6                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_7                  = 7   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_8                  = 8   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_9                  = 9   ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_10                 = 10  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_11                 = 11  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_12                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_13                 = 13  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_14                 = 14  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_15                 = 15  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_16                 = 16  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_17                 = 17  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_18                 = 18  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_19                 = 19  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_20                 = 20  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_21                 = 21  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_22                 = 22  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_23                 = 23  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_24                 = 24  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_25                 = 25  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_26                 = 26  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_27                 = 27  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_28                 = 28  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_29                 = 29  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_30                 = 30  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_31                 = 31  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_32                 = 32  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_33                 = 33  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_34                 = 34  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_35                 = 35  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_36                 = 36  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_37                 = 37  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_38                 = 38  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_39                 = 39  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_40                 = 40  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_41                 = 41  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_42                 = 42  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_43                 = 43  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_44                 = 44  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_45                 = 45  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_46                 = 46  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_47                 = 47  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_48                 = 48  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_49                 = 49  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_50                 = 50  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_51                 = 51  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_52                 = 52  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_53                 = 53  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_54                 = 54  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_55                 = 55  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_56                 = 56  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_57                 = 57  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_58                 = 58  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_59                 = 59  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_60                 = 60  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_61                 = 61  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_62                 = 62  ;
static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_63                 = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2           = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7           = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8           = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9           = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10          = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11          = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13          = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14          = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15          = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16          = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17          = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19          = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20          = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21          = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22          = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23          = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26          = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31          = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32          = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37          = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38          = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39          = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41          = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42          = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43          = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44          = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45          = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46          = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47          = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48          = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49          = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50          = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51          = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52          = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53          = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54          = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55          = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56          = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57          = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58          = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59          = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60          = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61          = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62          = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63          = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE0_MESSAGE_BITS0              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE0_MESSAGE_BITS0                = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE0_MESSAGE_BITS0_LEN            = 64  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE0_MESSAGE_BITS0              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE0_MESSAGE_BITS0                     = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE0_MESSAGE_BITS0_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE0_MESSAGE_BITS0                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE0_MESSAGE_BITS0_LEN              = 64  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN             = 64  ;

static const uint8_t P9N2_NV_CERR_MESSAGE0_MESSAGE_BITS0                          = 0   ;
static const uint8_t P9N2_NV_CERR_MESSAGE0_MESSAGE_BITS0_LEN                      = 64  ;

static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE0_MESSAGE_BITS0                     = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE0_MESSAGE_BITS0_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE0_MESSAGE_BITS0              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE1_MESSAGE_BITS1              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE1_MESSAGE_BITS1                = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE1_MESSAGE_BITS1_LEN            = 64  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE1_MESSAGE_BITS1              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE1_MESSAGE_BITS1                     = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE1_MESSAGE_BITS1_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE1_MESSAGE_BITS1                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE1_MESSAGE_BITS1_LEN              = 64  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN             = 64  ;

static const uint8_t P9N2_NV_CERR_MESSAGE1_MESSAGE_BITS1                          = 0   ;
static const uint8_t P9N2_NV_CERR_MESSAGE1_MESSAGE_BITS1_LEN                      = 64  ;

static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE1_MESSAGE_BITS1                     = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE1_MESSAGE_BITS1_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE1_MESSAGE_BITS1              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE2_MESSAGE_BITS2              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE2_MESSAGE_BITS2              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE2_MESSAGE_BITS2                     = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE2_MESSAGE_BITS2_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE2_MESSAGE_BITS2                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE2_MESSAGE_BITS2_LEN              = 64  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE2_MESSAGE_BITS2                     = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE2_MESSAGE_BITS2_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE2_MESSAGE_BITS2              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE3_MESSAGE_BITS3              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE3_MESSAGE_BITS3              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE3_MESSAGE_BITS3                     = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE3_MESSAGE_BITS3_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE3_MESSAGE_BITS3                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE3_MESSAGE_BITS3_LEN              = 64  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE3_MESSAGE_BITS3                     = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE3_MESSAGE_BITS3_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE3_MESSAGE_BITS3              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE4_MESSAGE_BITS4              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE4_MESSAGE_BITS4              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE4_MESSAGE_BITS4                     = 0   ;
static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE4_MESSAGE_BITS4_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE4_MESSAGE_BITS4                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE4_MESSAGE_BITS4_LEN              = 64  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE4_MESSAGE_BITS4                     = 0   ;
static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE4_MESSAGE_BITS4_LEN                 = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE4_MESSAGE_BITS4              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE5_MESSAGE_BITS5              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE5_MESSAGE_BITS5_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE5_MESSAGE_BITS5              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE5_MESSAGE_BITS5_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE5_MESSAGE_BITS5              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE5_MESSAGE_BITS5_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE5_MESSAGE_BITS5              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE5_MESSAGE_BITS5_LEN          = 64  ;

static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE5_MESSAGE_BITS5                 = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE5_MESSAGE_BITS5_LEN             = 64  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE6_MESSAGE_BITS6              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE6_MESSAGE_BITS6_LEN          = 24  ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE6_MESSAGE_BITS6              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE6_MESSAGE_BITS6_LEN          = 24  ;

static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE6_MESSAGE_BITS6              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE6_MESSAGE_BITS6_LEN          = 24  ;

static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE6_MESSAGE_BITS6              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE6_MESSAGE_BITS6_LEN          = 24  ;

static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE6_MESSAGE_BITS6                 = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE6_MESSAGE_BITS6_LEN             = 24  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_FIRST_BITS                        = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_FIRST_BITS_LEN                    = 27  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG         = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_MISC_STATE             = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_MRG_STATE              = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_OBUF_STATE             = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBTX_STATE             = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_RQIN_STATE             = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_IBUF_STATE             = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_ERRINJ                 = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBTX_AMO               = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN           = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_IBRD                   = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_IBRD_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_OBRD                   = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_OBRD_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_BBRD                   = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_BBRD_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBRX_RTAG              = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_ECC_CONFIG             = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_CONFIG1                = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG          = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG          = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_MASK_BITS                         = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_MASK_BITS_LEN                     = 27  ;

static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_EN                     = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD        = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN    = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD       = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN   = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP       = 7   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN   = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP      = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN  = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS       = 13  ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ         = 14  ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW00                    = 15  ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW00_LEN                = 17  ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW01                    = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW01_LEN                = 32  ;

static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_EN                     = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD        = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN    = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD       = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN   = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP       = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN   = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP      = 10  ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN  = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS       = 13  ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ         = 14  ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW00                    = 15  ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW00_LEN                = 17  ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW01                    = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW01_LEN                = 32  ;

static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_EN                           = 0   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD              = 1   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN          = 3   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD             = 4   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN         = 3   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP             = 7   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN         = 3   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP            = 10  ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN        = 3   ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS             = 13  ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ               = 14  ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW00                          = 15  ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW00_LEN                      = 17  ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW01                          = 32  ;
static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW01_LEN                      = 32  ;

static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_EN                           = 0   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD              = 1   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN          = 3   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD             = 4   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN         = 3   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP             = 7   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN         = 3   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP            = 10  ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN        = 3   ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS             = 13  ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ               = 14  ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW00                          = 15  ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW00_LEN                      = 17  ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW01                          = 32  ;
static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW01_LEN                      = 32  ;

static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_CMD                                = 0   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_CMD_LEN                            = 2   ;
static const uint8_t P9N2_PEC_CLK_REGION_SLAVE_MODE                               = 2   ;
static const uint8_t P9N2_PEC_CLK_REGION_MASTER_MODE                              = 3   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_PERV                               = 4   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT1                              = 5   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT2                              = 6   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT3                              = 7   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT4                              = 8   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT5                              = 9   ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT6                              = 10  ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT7                              = 11  ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT8                              = 12  ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT9                              = 13  ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT10                             = 14  ;
static const uint8_t P9N2_PEC_CLK_REGION_SEL_THOLD_SL                             = 48  ;
static const uint8_t P9N2_PEC_CLK_REGION_SEL_THOLD_NSL                            = 49  ;
static const uint8_t P9N2_PEC_CLK_REGION_SEL_THOLD_ARY                            = 50  ;
static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_PULSE_USE_EVEN                     = 52  ;

static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_PERV                          = 4   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT1                         = 5   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT2                         = 6   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT3                         = 7   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT4                         = 8   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT5                         = 9   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT6                         = 10  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT7                         = 11  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT8                         = 12  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT9                         = 13  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT10                        = 14  ;

static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_PERV                          = 4   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT1                         = 5   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT2                         = 6   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT3                         = 7   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT4                         = 8   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT5                         = 9   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT6                         = 10  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT7                         = 11  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT8                         = 12  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT9                         = 13  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT10                        = 14  ;

static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_PERV                           = 4   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT1                          = 5   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT2                          = 6   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT3                          = 7   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT4                          = 8   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT5                          = 9   ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT6                          = 10  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT7                          = 11  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT8                          = 12  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT9                          = 13  ;
static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT10                         = 14  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN                                 = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_HALT_ON_XSTOP                      = 1   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_HALT_ON_TRIG                       = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED3                          = 3   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_INTR_ADDR                       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_TRACE_EXTRA                     = 5   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_TRACE_STALL                     = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_WAIT_CYCLES                     = 7   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_FULL_SPEED                      = 8   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED9                          = 9   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL                     = 10  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED12_15                      = 12  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED12_15_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_FIR_TRIGGER                        = 16  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_MIB_GPIO                           = 17  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_MIB_GPIO_LEN                       = 3   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL                     = 20  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_HALT_INPUT                         = 24  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN                                 = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_HALT_ON_XSTOP                      = 1   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_HALT_ON_TRIG                       = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED3                          = 3   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_INTR_ADDR                       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_TRACE_EXTRA                     = 5   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_TRACE_STALL                     = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_WAIT_CYCLES                     = 7   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_FULL_SPEED                      = 8   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED9                          = 9   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL                     = 10  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED12_15                      = 12  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED12_15_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_FIR_TRIGGER                        = 16  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_MIB_GPIO                           = 17  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_MIB_GPIO_LEN                       = 3   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL                     = 20  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_HALT_INPUT                         = 24  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN                                  = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_HALT_ON_XSTOP                       = 1   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_HALT_ON_TRIG                        = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_INTR_ADDR                        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_TRACE_EXTRA                      = 5   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_TRACE_STALL                      = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_WAIT_CYCLES                      = 7   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_FULL_SPEED                       = 8   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED9                           = 9   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL                      = 10  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED12_15                       = 12  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED12_15_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_FIR_TRIGGER                         = 16  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_MIB_GPIO                            = 17  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_MIB_GPIO_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL                      = 20  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_HALT_INPUT                          = 24  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK_LEN                = 44  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK_LEN                = 44  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT                   = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT_LEN               = 44  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT                   = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT_LEN               = 44  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT                    = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT_LEN                = 44  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY                = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN            = 44  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY                = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN            = 44  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY                 = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             = 44  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DEBUGGER                          = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DEBUG_TRIGGER                     = 1   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_QUAD_CHECKSTOP                    = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PVREF_FAIL                        = 3   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_OCC_HEARTBEAT_LOST                = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_CORE_CHECKSTOP                    = 5   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DROPOUT_DETECT                    = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_0              = 7   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BCE_BUSY_HIGH                     = 8   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BCE_TIMEOUT                       = 9   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL3_C0                      = 10  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL3_C1                      = 11  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C0                = 12  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C1                = 13  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C0                 = 14  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C1                 = 15  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_REG_WAKEUP_C0                     = 16  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_REG_WAKEUP_C1                     = 17  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL2_C0                      = 18  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL2_C1                      = 19  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0             = 20  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1             = 21  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_L2_PURGE_DONE                     = 22  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_NCU_PURGE_DONE                    = 23  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C0                = 24  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C1                = 25  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BCE_BUSY_LOW                      = 26  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01                  = 27  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01_LEN              = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_COMM_RECVD                        = 29  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_COMM_SEND_ACK                     = 30  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_COMM_SEND_NACK                    = 31  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0               = 32  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1               = 33  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C0                    = 34  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C1                    = 35  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL0_C0                      = 36  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL0_C1                      = 37  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2            = 38  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN        = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL1_C0                      = 40  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL1_C1                      = 41  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_RESERVED_42_43                    = 42  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_RESERVED_42_43_LEN                = 2   ;

static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DEBUGGER                          = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DEBUG_TRIGGER                     = 1   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_QUAD_CHECKSTOP                    = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PVREF_FAIL                        = 3   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_OCC_HEARTBEAT_LOST                = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_CORE_CHECKSTOP                    = 5   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DROPOUT_DETECT                    = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_0              = 7   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BCE_BUSY_HIGH                     = 8   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BCE_TIMEOUT                       = 9   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL3_C0                      = 10  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL3_C1                      = 11  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C0                = 12  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C1                = 13  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C0                 = 14  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C1                 = 15  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_REG_WAKEUP_C0                     = 16  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_REG_WAKEUP_C1                     = 17  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL2_C0                      = 18  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL2_C1                      = 19  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0             = 20  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1             = 21  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_L2_PURGE_DONE                     = 22  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_NCU_PURGE_DONE                    = 23  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C0                = 24  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C1                = 25  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BCE_BUSY_LOW                      = 26  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01                  = 27  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01_LEN              = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_COMM_RECVD                        = 29  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_COMM_SEND_ACK                     = 30  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_COMM_SEND_NACK                    = 31  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0               = 32  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1               = 33  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C0                    = 34  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C1                    = 35  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL0_C0                      = 36  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL0_C1                      = 37  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2            = 38  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN        = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL1_C0                      = 40  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL1_C1                      = 41  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_RESERVED_42_43                    = 42  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_RESERVED_42_43_LEN                = 2   ;

static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DEBUGGER                           = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DEBUG_TRIGGER                      = 1   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_QUAD_CHECKSTOP                     = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PVREF_FAIL                         = 3   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_CORE_CHECKSTOP                     = 5   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DROPOUT_DETECT                     = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_0               = 7   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BCE_BUSY_HIGH                      = 8   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BCE_TIMEOUT                        = 9   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL3_C0                       = 10  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL3_C1                       = 11  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C0                 = 12  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C1                 = 13  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  = 14  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  = 15  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_REG_WAKEUP_C0                      = 16  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_REG_WAKEUP_C1                      = 17  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL2_C0                       = 18  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL2_C1                       = 19  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              = 20  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              = 21  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_L2_PURGE_DONE                      = 22  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_NCU_PURGE_DONE                     = 23  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 = 24  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 = 25  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BCE_BUSY_LOW                       = 26  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01                   = 27  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_COMM_RECVD                         = 29  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_COMM_SEND_ACK                      = 30  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_COMM_SEND_NACK                     = 31  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0                = 32  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1                = 33  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C0                     = 34  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C1                     = 35  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL0_C0                       = 36  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL0_C1                       = 37  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             = 38  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL1_C0                       = 40  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL1_C1                       = 41  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_RESERVED_42_43                     = 42  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_RESERVED_42_43_LEN                 = 2   ;

static const uint8_t P9N2_PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS                 = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS_LEN             = 44  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS                 = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS_LEN             = 44  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS                  = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS_LEN              = 44  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE_LEN                = 44  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE_LEN                = 44  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 = 44  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_COMM_ACK                          = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_COMM_NACK                         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT          = 5   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN      = 3   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN       = 3   ;

static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_COMM_ACK                          = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_COMM_NACK                         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT          = 5   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN      = 3   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN       = 3   ;

static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_COMM_ACK                           = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_COMM_NACK                          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           = 5   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       = 3   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        = 3   ;

static const uint8_t P9N2_PU_CME4_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_ICRR_COMM_RECV                         = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_ICRR_COMM_RECV_LEN                     = 32  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_ICRR_COMM_RECV                         = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_ICRR_COMM_RECV_LEN                     = 32  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_ICRR_COMM_RECV                          = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_ICRR_COMM_RECV_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME3_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME11_CME_LCL_ICSR_COMM_SEND                         = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_ICSR_COMM_SEND_LEN                     = 32  ;

static const uint8_t P9N2_PU_CME2_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME5_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME9_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME6_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME10_CME_LCL_ICSR_COMM_SEND                         = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_ICSR_COMM_SEND_LEN                     = 32  ;

static const uint8_t P9N2_PU_CME8_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME1_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME0_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME7_CME_LCL_ICSR_COMM_SEND                          = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_ICSR_COMM_SEND_LEN                      = 32  ;

static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1                    = 8   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2                    = 16  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3                    = 24  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_USE_PECE                       = 32  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_USE_PECE_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1                    = 8   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2                    = 16  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3                    = 24  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_USE_PECE                       = 32  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_USE_PECE_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1                    = 8   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2                    = 16  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3                    = 24  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3_LEN                = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_USE_PECE                       = 32  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_USE_PECE_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1                    = 8   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2                    = 16  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3                    = 24  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3_LEN                = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_USE_PECE                       = 32  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_USE_PECE_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1                     = 8   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2                     = 16  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3                     = 24  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_USE_PECE                        = 32  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_USE_PECE_LEN                    = 4   ;

static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL            = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL            = 1   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL     = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL     = 3   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                 = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                 = 5   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_6_8                      = 6   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_6_8_LEN                  = 3   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_FUSED_CORE_MODE                   = 9   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C0                   = 10  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C1                   = 11  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C0               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL     = 16  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL     = 17  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_18_19                    = 18  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_18_19_LEN                = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1        = 24  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_28_29                    = 28  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_28_29_LEN                = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1      = 30  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN  = 2   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0               = 32  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1               = 33  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C0                = 34  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C1                = 35  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C0                       = 36  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C0_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C1                       = 40  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C1_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C0                = 44  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C1                = 45  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C0               = 46  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C1               = 47  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0              = 48  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN          = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1              = 52  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN          = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0               = 56  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1               = 57  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_9_C0                  = 58  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_9_C1                  = 59  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C1               = 60  ;
static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN           = 4   ;

static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL            = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL            = 1   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL     = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL     = 3   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                 = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                 = 5   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_6_8                      = 6   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_6_8_LEN                  = 3   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_FUSED_CORE_MODE                   = 9   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C0                   = 10  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C1                   = 11  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C0               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL     = 16  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL     = 17  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_18_19                    = 18  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_18_19_LEN                = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1        = 24  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_28_29                    = 28  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_28_29_LEN                = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1      = 30  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN  = 2   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0               = 32  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1               = 33  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C0                = 34  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C1                = 35  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C0                       = 36  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C0_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C1                       = 40  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C1_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C0                = 44  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C1                = 45  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C0               = 46  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C1               = 47  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0              = 48  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN          = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1              = 52  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN          = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0               = 56  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1               = 57  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_9_C0                  = 58  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_9_C1                  = 59  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C1               = 60  ;
static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN           = 4   ;

static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             = 1   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      = 3   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  = 5   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_6_8                       = 6   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_6_8_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_FUSED_CORE_MODE                    = 9   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C0                    = 10  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C1                    = 11  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C0                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN            = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      = 16  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      = 17  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_18_19                     = 18  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_18_19_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1         = 24  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_28_29                     = 28  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_28_29_LEN                 = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       = 30  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   = 2   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                = 32  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                = 33  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 = 34  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 = 35  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C0                        = 36  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C0_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C1                        = 40  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C1_LEN                    = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 = 44  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 = 45  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C0                = 46  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C1                = 47  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               = 48  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               = 52  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                = 56  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                = 57  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_9_C0                   = 58  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_9_C1                   = 59  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C1                = 60  ;
static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN            = 4   ;

static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_FIT_SEL                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_FIT_SEL_LEN                       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL                      = 4   ;
static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL_LEN                  = 4   ;

static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_FIT_SEL                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_FIT_SEL_LEN                       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL                      = 4   ;
static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL_LEN                  = 4   ;

static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_FIT_SEL                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_FIT_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL                       = 4   ;
static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN            = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                 = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_SAMPLE_VALID                     = 63  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN            = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                 = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_SAMPLE_VALID                     = 63  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_SAMPLE_VALID                      = 63  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                 = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN             = 20  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                 = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN             = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                 = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN             = 20  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              = 20  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_BUSY                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_ERROR                          = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_RNW                            = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_BARSEL                         = 5   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_PRIORITY                       = 6   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_INJECT_ERR                     = 7   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_TYPE                           = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_TYPE_LEN                       = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS                     = 17  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                 = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_SBASE                          = 28  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_SBASE_LEN                      = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_MBASE                          = 42  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_MBASE_LEN                      = 22  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_BUSY                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_ERROR                          = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_RNW                            = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_BARSEL                         = 5   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_PRIORITY                       = 6   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_INJECT_ERR                     = 7   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_TYPE                           = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_TYPE_LEN                       = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS                     = 17  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                 = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_SBASE                          = 28  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_SBASE_LEN                      = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_MBASE                          = 42  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_MBASE_LEN                      = 22  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_BUSY                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_ERROR                           = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_RNW                             = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_BARSEL                          = 5   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_PRIORITY                        = 6   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_INJECT_ERR                      = 7   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_TYPE                            = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_TYPE_LEN                        = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS                      = 17  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_SBASE                           = 28  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_SBASE_LEN                       = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_MBASE                           = 42  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_MBASE_LEN                       = 22  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT          = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN      = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT         = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN     = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT          = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN      = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT         = 56  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN     = 8   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT          = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN      = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT         = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN     = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT          = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN      = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT         = 56  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN     = 8   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          = 56  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      = 8   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_FLAGS_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_FLAGS_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_FLAGS_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_FLAGS_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_FLAGS_DATA                             = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_FLAGS_DATA_LEN                         = 32  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD          = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN      = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD         = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN     = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_TIMER_MODE               = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                = 33  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE      = 34  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN  = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE              = 36  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN          = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE             = 38  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SPARE                            = 39  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE            = 40  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SPARE41_43                       = 41  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SPARE41_43_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE              = 59  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN          = 5   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD          = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN      = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD         = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN     = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_TIMER_MODE               = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                = 33  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE      = 34  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN  = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE              = 36  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN          = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE             = 38  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SPARE                            = 39  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE            = 40  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SPARE41_43                       = 41  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SPARE41_43_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE              = 59  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN          = 5   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 = 33  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       = 34  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               = 36  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              = 38  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SPARE                             = 39  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             = 40  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               = 59  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           = 5   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                 = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                 = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                 = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN               = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                = 5   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN               = 6   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                  = 7   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_QUEUED_WR_EN                     = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_QUEUED_RD_EN                     = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_MASK_PURGE_INTERFACE             = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE    = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE   = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE   = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE  = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE  = 15  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_STOP_OVERRIDE_MODE               = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_STOP_ACTIVE_MASK                 = 17  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AUTO_STOP1_DISABLE               = 18  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE              = 19  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_FENCE_EISR                       = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PC_DISABLE_DROOP                 = 21  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE            = 22  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_23                         = 23  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL                    = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_28_31                      = 28  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_28_31_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_RESET_IMPRECISE_QERR             = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SET_ECC_INJECT_ERR               = 33  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_34                         = 34  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_OOB_ERR_DISABLE                  = 35  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN              = 5   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                 = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                 = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                 = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN               = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                = 5   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN               = 6   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                  = 7   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_QUEUED_WR_EN                     = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_QUEUED_RD_EN                     = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_MASK_PURGE_INTERFACE             = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE    = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE   = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE   = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE  = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE  = 15  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_STOP_OVERRIDE_MODE               = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_STOP_ACTIVE_MASK                 = 17  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AUTO_STOP1_DISABLE               = 18  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE              = 19  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_FENCE_EISR                       = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PC_DISABLE_DROOP                 = 21  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE            = 22  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_23                         = 23  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL                    = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_28_31                      = 28  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_28_31_LEN                  = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_RESET_IMPRECISE_QERR             = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SET_ECC_INJECT_ERR               = 33  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_34                         = 34  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_OOB_ERR_DISABLE                  = 35  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN              = 5   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PMCR_OVERRIDE_EN                  = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PSCR_OVERRIDE_EN                  = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PMSR_OVERRIDE_EN                  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN                = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN                 = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN                 = 5   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN                = 6   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_LOCK_PCB_ON_ERR                   = 7   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_QUEUED_WR_EN                      = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_QUEUED_RD_EN                      = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_MASK_PURGE_INTERFACE              = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE     = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE    = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE    = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   = 15  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_STOP_OVERRIDE_MODE                = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_STOP_ACTIVE_MASK                  = 17  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AUTO_STOP1_DISABLE                = 18  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE               = 19  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_FENCE_EISR                        = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PC_DISABLE_DROOP                  = 21  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE             = 22  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_23                          = 23  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL                     = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN                 = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_28_31                       = 28  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_28_31_LEN                   = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_RESET_IMPRECISE_QERR              = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SET_ECC_INJECT_ERR                = 33  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_34                          = 34  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_OOB_ERR_DISABLE                   = 35  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN               = 5   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS0_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS0_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS0_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS0_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS1_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS1_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS1_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS1_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS0_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS0_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS0_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS0_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS0_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS1_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS1_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS1_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS1_DATA_LEN                       = 64  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS1_DATA_LEN                        = 64  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_SPARE0                        = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N         = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N         = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N            = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN    = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE           = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE        = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE               = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE               = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE               = 13  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N     = 14  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N         = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N        = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN    = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_SPARE0                         = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                = 13  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      = 14  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_TIMEBASE                         = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_TIMEBASE_LEN                     = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_CYCLES                           = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_CYCLES_LEN                       = 32  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_TIMEBASE                         = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_TIMEBASE_LEN                     = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_CYCLES                           = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_CYCLES_LEN                       = 32  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_TIMEBASE                          = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_TIMEBASE_LEN                      = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_CYCLES                            = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_CYCLES_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT       = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN   = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT      = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN  = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN              = 3   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT       = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN   = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT      = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN  = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE                  = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN              = 3   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               = 3   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C0                  = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C1                  = 1   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0           = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1           = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_EXIT_C0                       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_EXIT_C1                       = 5   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0         = 6   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1         = 7   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0          = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1          = 9   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C0                    = 10  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C1                    = 11  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_12_15                   = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_12_15_LEN               = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0             = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1             = 17  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_PURGE                         = 18  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT                   = 19  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PC_THROTTLE_REQ                  = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                = 21  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_NCU_PURGE                        = 22  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_NCU_PURGE_ABORT                  = 23  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C0                    = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C1                    = 25  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C0                   = 26  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C1                   = 27  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C0                 = 28  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C1                 = 29  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_30_31                   = 30  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_30_31_LEN               = 2   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C0                  = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C1                  = 1   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0           = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1           = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_EXIT_C0                       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_EXIT_C1                       = 5   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0         = 6   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1         = 7   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0          = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1          = 9   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C0                    = 10  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C1                    = 11  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_12_15                   = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_12_15_LEN               = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0             = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1             = 17  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_PURGE                         = 18  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT                   = 19  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PC_THROTTLE_REQ                  = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                = 21  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_NCU_PURGE                        = 22  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_NCU_PURGE_ABORT                  = 23  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C0                    = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C1                    = 25  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C0                   = 26  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C1                   = 27  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C0                 = 28  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C1                 = 29  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_30_31                   = 30  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_30_31_LEN               = 2   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   = 1   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_EXIT_C0                        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_EXIT_C1                        = 5   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          = 6   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          = 7   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           = 9   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C0                     = 10  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C1                     = 11  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_12_15                    = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_12_15_LEN                = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              = 17  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_PURGE                          = 18  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT                    = 19  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PC_THROTTLE_REQ                   = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 = 21  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_NCU_PURGE                         = 22  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_NCU_PURGE_ABORT                   = 23  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C0                     = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C1                     = 25  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C0                    = 26  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C1                    = 27  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  = 28  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  = 29  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_30_31                    = 30  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_30_31_LEN                = 2   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH0_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH0_DATA_LEN                       = 32  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH0_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH0_DATA_LEN                       = 32  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH0_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH0_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH1_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH1_DATA_LEN                       = 32  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH1_DATA                           = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH1_DATA_LEN                       = 32  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH1_DATA                            = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH1_DATA_LEN                        = 32  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD            = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN        = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD            = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN        = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD          = 28  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE               = 36  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_TIMER_MODE                 = 38  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_CHAR_MODE                  = 39  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE              = 40  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SPARE41_43                       = 41  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SPARE41_43_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                = 59  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN            = 5   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD            = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN        = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD            = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN        = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD          = 28  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN      = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE               = 36  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN           = 2   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_TIMER_MODE                 = 38  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_CHAR_MODE                  = 39  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE              = 40  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SPARE41_43                       = 41  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SPARE41_43_LEN                   = 3   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                = 59  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN            = 5   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           = 28  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                = 36  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            = 2   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_TIMER_MODE                  = 38  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_CHAR_MODE                   = 39  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               = 40  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SPARE41_43                        = 41  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SPARE41_43_LEN                    = 3   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 = 59  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             = 5   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR            = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN        = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR              = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN          = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR              = 40  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN          = 24  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR            = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN        = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR              = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN          = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR              = 40  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN          = 24  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               = 40  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           = 24  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY      = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN  = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA           = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA           = 8   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA           = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA           = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA           = 20  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY       = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA            = 36  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA            = 40  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA            = 44  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA            = 48  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA            = 52  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN        = 4   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY      = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN  = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA           = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA           = 8   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA           = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA           = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA           = 20  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN       = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY       = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA            = 36  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA            = 40  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA            = 44  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA            = 48  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA            = 52  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN        = 4   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            = 8   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            = 20  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             = 36  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             = 40  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             = 44  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             = 48  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         = 4   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             = 52  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         = 4   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR            = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN        = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR          = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN      = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR           = 32  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR          = 44  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN      = 12  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR          = 56  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN      = 8   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR            = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN        = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR          = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN      = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR           = 32  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR          = 44  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN      = 12  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR          = 56  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN      = 8   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            = 32  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           = 44  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       = 12  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           = 56  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       = 8   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                 = 16  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN             = 24  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                 = 40  ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN             = 24  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                 = 16  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN             = 24  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                 = 40  ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN             = 24  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  = 16  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              = 24  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  = 40  ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              = 24  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                = 27  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                = 27  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                = 27  ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                = 27  ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN                 = 27  ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                = 7   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                = 7   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO                    = 0   ;
static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                = 7   ;

static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO                    = 0   ;
static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                = 7   ;

static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO                     = 0   ;
static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN                 = 7   ;

static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART               = 0   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_WITHADDR                = 1   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_READCONT                = 2   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTOP                = 3   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_LENGTH                      = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_LENGTH_LEN                  = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_8_14                         = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_8_14_LEN                     = 7   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_RNW                     = 15  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_16_22                        = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_16_22_LEN                    = 7   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_REG_ADDR_LENGTH                     = 23  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_REG_ADDR_LENGTH_LEN                 = 3   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_26_31                        = 26  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_26_31_LEN                    = 6   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_1                      = 32  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_1_LEN                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_2                      = 40  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_2_LEN                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_3                      = 48  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_3_LEN                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_4                      = 56  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_4_LEN                  = 8   ;

static const uint8_t P9N2_PU_COMMAND_REGISTER_B_WITH_START_0                      = 0   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_WITH_ADDRESS_0                    = 1   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_READ_CONTINUE_0                   = 2   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_WITH_STOP_0                       = 3   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_NOT_USED_0                        = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_NOT_USED_0_LEN                    = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0_LEN              = 7   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_READ_NOT_WRITE_0                  = 15  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0                 = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0_LEN             = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_PEEK_DATA1_0                      = 32  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_PEEK_DATA1_0_LEN                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_B_LBUS_PARITY_ERR1_0                = 40  ;

static const uint8_t P9N2_PU_COMMAND_REGISTER_C_WITH_START_1                      = 0   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_WITH_ADDRESS_1                    = 1   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_READ_CONTINUE_1                   = 2   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_WITH_STOP_1                       = 3   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_NOT_USED_1                        = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_NOT_USED_1_LEN                    = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1_LEN              = 7   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_READ_NOT_WRITE_1                  = 15  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1                 = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1_LEN             = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_PEEK_DATA1_1                      = 32  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_PEEK_DATA1_1_LEN                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_C_LBUS_PARITY_ERR1_1                = 40  ;

static const uint8_t P9N2_PU_COMMAND_REGISTER_D_WITH_START_2                      = 0   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_WITH_ADDRESS_2                    = 1   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_READ_CONTINUE_2                   = 2   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_WITH_STOP_2                       = 3   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_NOT_USED_2                        = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_NOT_USED_2_LEN                    = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2_LEN              = 7   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_READ_NOT_WRITE_2                  = 15  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2                 = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2_LEN             = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_PEEK_DATA1_2                      = 32  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_PEEK_DATA1_2_LEN                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_D_LBUS_PARITY_ERR1_2                = 40  ;

static const uint8_t P9N2_PU_COMMAND_REGISTER_E_WITH_START_3                      = 0   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_WITH_ADDRESS_3                    = 1   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_READ_CONTINUE_3                   = 2   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_WITH_STOP_3                       = 3   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_NOT_USED_3                        = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_NOT_USED_3_LEN                    = 4   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3_LEN              = 7   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_READ_NOT_WRITE_3                  = 15  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3                 = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3_LEN             = 16  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_PEEK_DATA1_3                      = 32  ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_PEEK_DATA1_3_LEN                  = 8   ;
static const uint8_t P9N2_PU_COMMAND_REGISTER_E_LBUS_PARITY_ERR1_3                = 40  ;

static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_EN                        = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE           = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BRICKID                   = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BRICKID_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_PE_MASK                   = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_PE_MASK_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0               = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1               = 14  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2               = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3               = 26  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1         = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2         = 33  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1         = 34  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2         = 35  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1            = 36  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2            = 37  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1             = 38  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2             = 39  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1             = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2             = 41  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1         = 42  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2         = 43  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1         = 44  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2         = 45  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1         = 46  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2         = 47  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1         = 48  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2         = 49  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE        = 50  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_SPARE                     = 51  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_SPARE_LEN                 = 13  ;

static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_EN                              = 0   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE                 = 1   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BRICKID                         = 2   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BRICKID_LEN                     = 2   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_PE_MASK                         = 4   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_PE_MASK_LEN                     = 4   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0                     = 8   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN                 = 6   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1                     = 14  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN                 = 6   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2                     = 20  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN                 = 6   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3                     = 26  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN                 = 6   ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1               = 32  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2               = 33  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1               = 34  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2               = 35  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1                  = 36  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2                  = 37  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1                   = 38  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2                   = 39  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1                   = 40  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2                   = 41  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1               = 42  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2               = 43  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1               = 44  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2               = 45  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1               = 46  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2               = 47  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1               = 48  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2               = 49  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE              = 50  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_SPARE                           = 51  ;
static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_SPARE_LEN                       = 13  ;

static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED1_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_ADR_BAR_MODE                = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_GEN_HEAD_DELAY              = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN          = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP     = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP     = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ           = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ           = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ       = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ       = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH1               = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH1_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH2               = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH2_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH1               = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH1_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH2               = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH2_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_MAX_LEVEL             = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN         = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_MAX_LEVEL             = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN         = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_BRAZOS_MODE                 = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR         = 49  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01         = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23         = 51  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_OCAPI_MODE                  = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_NVLINK_MODE                 = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_RANDOMIZE_INT_SLICE         = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_OTL0_ENABLE                 = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_OTL1_ENABLE                 = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_DISABLE_2CREDS_TO_OTL       = 57  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_RESTRICT_RSPIN_CREDIT_TO1   = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED2                          = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED2_LEN                      = 5   ;

static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR       = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE        = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ADR_BAR_MODE              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_NN_RN             = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_G                 = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_LN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_SKIP_G                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_INC_PRI_MASK              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_RESERVED2                        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_RESERVED4                        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MACH_CORRENAB             = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1       = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RXO_CORRENAB              = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1        = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2        = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_CORRENAB              = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1        = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2        = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM      = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ENABLE_PBUS               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_BRAZOS_MODE               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0            = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1            = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1            = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_XATS            = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_INJECT            = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DCACHE_MODE               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL   = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB              = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_P9P9_MODE                 = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC        = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MRBCP_TRACK_ALL           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP       = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_OCAPI_MODE                = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_NVLINK_MODE               = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_INTS            = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PWR0            = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PWR1            = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE      = 63  ;

static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_EN                        = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE           = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BRICKID                   = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BRICKID_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_PE_MASK                   = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_PE_MASK_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0               = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1               = 14  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2               = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3               = 26  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1         = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2         = 33  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1         = 34  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2         = 35  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1            = 36  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2            = 37  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1             = 38  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2             = 39  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1             = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2             = 41  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1         = 42  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2         = 43  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1         = 44  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2         = 45  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1         = 46  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2         = 47  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1         = 48  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2         = 49  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE        = 50  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_SPARE                     = 51  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_SPARE_LEN                 = 13  ;

static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_EN                              = 0   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE                 = 1   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BRICKID                         = 2   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BRICKID_LEN                     = 2   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_PE_MASK                         = 4   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_PE_MASK_LEN                     = 4   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0                     = 8   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN                 = 6   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1                     = 14  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN                 = 6   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2                     = 20  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN                 = 6   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3                     = 26  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN                 = 6   ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1               = 32  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2               = 33  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1               = 34  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2               = 35  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1                  = 36  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2                  = 37  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1                   = 38  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2                   = 39  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1                   = 40  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2                   = 41  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1               = 42  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2               = 43  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1               = 44  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2               = 45  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1               = 46  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2               = 47  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1               = 48  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2               = 49  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE              = 50  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_SPARE                           = 51  ;
static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_SPARE_LEN                       = 13  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR       = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE        = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ADR_BAR_MODE              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_NN_RN             = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_G                 = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_LN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_SKIP_G                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_INC_PRI_MASK              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_RESERVED2                        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_RESERVED4                        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MACH_CORRENAB             = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1       = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RXO_CORRENAB              = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1        = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2        = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_CORRENAB              = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1        = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2        = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM      = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ENABLE_PBUS               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_BRAZOS_MODE               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0            = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1            = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1            = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_XATS            = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_INJECT            = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DCACHE_MODE               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL   = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB              = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_P9P9_MODE                 = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC        = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MRBCP_TRACK_ALL           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP       = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_OCAPI_MODE                = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_NVLINK_MODE               = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_INTS            = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PWR0            = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PWR1            = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE      = 63  ;

static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_NN_RN                = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_G                    = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_LN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_SKIP_G                       = 9   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        = 11  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_INC_PRI_MASK                 = 13  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_INC_PRI_MASK_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_RESERVED2                           = 16  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              = 17  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_A              = 19  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_B              = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_C              = 21  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_RESERVED4                           = 22  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MACH_CORRENAB                = 23  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          = 25  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RXO_CORRENAB                 = 26  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           = 27  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           = 28  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_CORRENAB                 = 29  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           = 31  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           = 34  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_EVAPORATE_BY_LCO             = 35  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_TRACK_ALL              = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_TRACK_ALL              = 37  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ENABLE_PBUS                  = 38  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  = 39  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ENABLE_SNARF_CPM             = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_REQ0               = 41  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PRB0               = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_REQ1               = 43  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PRB1               = 44  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_XATS               = 45  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_INJECT               = 46  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DCACHE_MODE                  = 47  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      = 48  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   = 49  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PCKT_BLK_PRB                 = 50  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_P9P9_MODE                    = 51  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       = 52  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           = 53  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_OPT_SNOOP_CP                 = 54  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MRBCP_TRACK_ALL              = 55  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP          = 56  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_OCAPI_MODE                   = 57  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_NVLINK_MODE                  = 58  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_INTS               = 59  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PWR0               = 60  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PWR1               = 61  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO           = 62  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE         = 63  ;

static const uint8_t P9N2_NV_CONFIG0_RESERVED0                                    = 0   ;
static const uint8_t P9N2_NV_CONFIG0_RESERVED1                                    = 1   ;
static const uint8_t P9N2_NV_CONFIG0_RESERVED1_LEN                                = 3   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_ADR_BAR_MODE                          = 4   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_GEN_HEAD_DELAY                        = 5   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN                    = 5   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP               = 10  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP               = 11  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ                     = 12  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ                     = 13  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ                 = 14  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ                 = 15  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH1                         = 16  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH1_LEN                     = 6   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH2                         = 22  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH2_LEN                     = 6   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH1                         = 28  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH1_LEN                     = 6   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH2                         = 34  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH2_LEN                     = 6   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_MAX_LEVEL                       = 40  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN                   = 4   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_MAX_LEVEL                       = 44  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN                   = 4   ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_BRAZOS_MODE                           = 48  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR                   = 49  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01                   = 50  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23                   = 51  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_OCAPI_MODE                            = 52  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_NVLINK_MODE                           = 53  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_RANDOMIZE_INT_SLICE                   = 54  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_OTL0_ENABLE                           = 55  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_OTL1_ENABLE                           = 56  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_DISABLE_2CREDS_TO_OTL                 = 57  ;
static const uint8_t P9N2_NV_CONFIG0_CONFIG_RESTRICT_RSPIN_CREDIT_TO1             = 58  ;
static const uint8_t P9N2_NV_CONFIG0_RESERVED2                                    = 59  ;
static const uint8_t P9N2_NV_CONFIG0_RESERVED2_LEN                                = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR       = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE        = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ADR_BAR_MODE              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_NN_RN             = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_G                 = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_LN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_SKIP_G                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_INC_PRI_MASK              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_INC_PRI_MASK_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_RESERVED2                        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_B           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_C           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_A           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_B           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_C           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_RESERVED4                        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MACH_CORRENAB             = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE1       = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE2       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RXO_CORRENAB              = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE1        = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE2        = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_CORRENAB              = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE1        = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE2        = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM      = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_EVAPORATE_BY_LCO          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MRBGP_TRACK_ALL           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MRBSP_TRACK_ALL           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ENABLE_PBUS               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_BRAZOS_MODE               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ENABLE_SNARF_CPM          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_REQ0            = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PRB0            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_REQ1            = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PRB1            = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_XATS            = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_INJECT            = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DCACHE_MODE               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL   = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PCKT_BLK_PRB              = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_P9P9_MODE                 = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC        = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_OPT_SNOOP_CP              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MRBCP_TRACK_ALL           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP       = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_OCAPI_MODE                = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_NVLINK_MODE               = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_INTS            = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PWR0            = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PWR1            = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE      = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR       = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE        = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ADR_BAR_MODE              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_NN_RN             = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_G                 = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_LN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_SKIP_G                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP         = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_INC_PRI_MASK              = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_RESERVED2                        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B           = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A           = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B           = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C           = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_RESERVED4                        = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MACH_CORRENAB             = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1       = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RXO_CORRENAB              = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1        = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2        = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_CORRENAB              = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1        = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2        = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM      = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG        = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL           = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ENABLE_PBUS               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_BRAZOS_MODE               = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0            = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1            = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1            = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_XATS            = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_INJECT            = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DCACHE_MODE               = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL   = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB              = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_P9P9_MODE                 = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC        = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP              = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MRBCP_TRACK_ALL           = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP       = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_OCAPI_MODE                = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_NVLINK_MODE               = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_INTS            = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PWR0            = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PWR1            = 61  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO        = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE      = 63  ;

static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_COMPRESSED_RSP_ENA                  = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED1_LEN                       = 3   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_CREQ_AE_ALWAYS                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_DGD_AE_ALWAYS                       = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RSP_AE_ALWAYS                       = 6   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED2                           = 7   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_NTL_RESET                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_NTL_RESET_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED3                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED3_LEN                       = 54  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MGR_CREDIT                         = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MGR_CREDIT_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_PBTX_NBUF                      = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_PBTX_NBUF_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_RDBF_NBUF                      = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_RDBF_NBUF_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBWR_NBUF                      = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBWR_NBUF_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBRD_NBUF                      = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBRD_NBUF_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_BBRD_NBUF                      = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_BBRD_NBUF_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_OBRD_NBUF                      = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_OBRD_NBUF_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_CR_DIS                         = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_CTLW_CR_DIS                    = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLR_PAUSE_THRESH                  = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLR_PAUSE_THRESH_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLR_HP_THRESH                     = 26  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLR_HP_THRESH_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLW_PAUSE_THRESH                  = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLW_PAUSE_THRESH_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLW_HP_THRESH                     = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLW_HP_THRESH_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_REDUCE_RTAG                   = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_DELAY_BDONE                   = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_FLIP_IMIN_BIG                 = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_FLIP_IMIN_LITTLE              = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_ALU_SAFE_LATENCY                   = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_ALU_FLIP_ENDIAN_BIG                = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_ALU_FLIP_ENDIAN_LITTLE             = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_EARLY_AFTAG                   = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CONFIG_OCAPI_MODE                  = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CONFIG_NVLINK_MODE                 = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CHKNSW_HW405659                    = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_RESERVED1                          = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_RESERVED1_LEN                      = 21  ;

static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_COMPRESSED_RSP_ENA                  = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED1_LEN                       = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_CREQ_AE_ALWAYS                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_DGD_AE_ALWAYS                       = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RSP_AE_ALWAYS                       = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED2                           = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_NTL_RESET                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_NTL_RESET_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED3                           = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED3_LEN                       = 54  ;

static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2__SM2_CONFIG1_COMPRESSED_RSP_ENA                         = 0   ;
static const uint8_t P9N2__SM2_CONFIG1_RESERVED1                                  = 1   ;
static const uint8_t P9N2__SM2_CONFIG1_RESERVED1_LEN                              = 3   ;
static const uint8_t P9N2__SM2_CONFIG1_CREQ_AE_ALWAYS                             = 4   ;
static const uint8_t P9N2__SM2_CONFIG1_DGD_AE_ALWAYS                              = 5   ;
static const uint8_t P9N2__SM2_CONFIG1_RSP_AE_ALWAYS                              = 6   ;
static const uint8_t P9N2__SM2_CONFIG1_RESERVED2                                  = 7   ;
static const uint8_t P9N2__SM2_CONFIG1_NTL_RESET                                  = 8   ;
static const uint8_t P9N2__SM2_CONFIG1_NTL_RESET_LEN                              = 2   ;
static const uint8_t P9N2__SM2_CONFIG1_RESERVED3                                  = 10  ;
static const uint8_t P9N2__SM2_CONFIG1_RESERVED3_LEN                              = 54  ;

static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2__SM1_CONFIG1_COMPRESSED_RSP_ENA                         = 0   ;
static const uint8_t P9N2__SM1_CONFIG1_RESERVED1                                  = 1   ;
static const uint8_t P9N2__SM1_CONFIG1_RESERVED1_LEN                              = 3   ;
static const uint8_t P9N2__SM1_CONFIG1_CREQ_AE_ALWAYS                             = 4   ;
static const uint8_t P9N2__SM1_CONFIG1_DGD_AE_ALWAYS                              = 5   ;
static const uint8_t P9N2__SM1_CONFIG1_RSP_AE_ALWAYS                              = 6   ;
static const uint8_t P9N2__SM1_CONFIG1_RESERVED2                                  = 7   ;
static const uint8_t P9N2__SM1_CONFIG1_NTL_RESET                                  = 8   ;
static const uint8_t P9N2__SM1_CONFIG1_NTL_RESET_LEN                              = 2   ;
static const uint8_t P9N2__SM1_CONFIG1_RESERVED3                                  = 10  ;
static const uint8_t P9N2__SM1_CONFIG1_RESERVED3_LEN                              = 54  ;

static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_DIV2_COUNT_AT_EXP     = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_DIS_DYN_ADJ           = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_DIS_DYN_LVL_ADJ       = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH1               = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH1_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH2               = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH2_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_MAX_LEVEL             = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_MAX_LEVEL_LEN         = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_RESERVED1                          = 19  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK     = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK_LEN = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK  = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK  = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_CHICKEN_HW405869_DISABLE_PATCH = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_RESERVED2                          = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_RESERVED2_LEN                      = 25  ;

static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_COMPRESSED_RSP_ENA                   = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED1                            = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED1_LEN                        = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_CREQ_AE_ALWAYS                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_DGD_AE_ALWAYS                        = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RSP_AE_ALWAYS                        = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED2                            = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_NTL_RESET                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_NTL_RESET_LEN                        = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED3                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED3_LEN                        = 54  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA       = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ      = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ      = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_USES_HANG       = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT      = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE      = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE       = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_RESERVED                         = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_RESERVED_LEN                     = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA       = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ      = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ      = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_USES_HANG       = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT      = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE      = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE       = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_RESERVED                         = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_RESERVED_LEN                     = 4   ;

static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_COMPRESSED_RSP_ENA                   = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED1                            = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED1_LEN                        = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_CREQ_AE_ALWAYS                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_DGD_AE_ALWAYS                        = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RSP_AE_ALWAYS                        = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED2                            = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_NTL_RESET                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_NTL_RESET_LEN                        = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED3                            = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED3_LEN                        = 54  ;

static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT            = 16  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          = 28  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN         = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ         = 43  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ         = 44  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT          = 45  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_USES_HANG          = 51  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG          = 52  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT         = 54  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE         = 56  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE          = 57  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_RESERVED                            = 60  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_RESERVED_LEN                        = 4   ;

static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_DIV2_COUNT_AT_EXP               = 0   ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_DIS_DYN_ADJ                     = 1   ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_DIS_DYN_LVL_ADJ                 = 2   ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH1                         = 3   ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH1_LEN                     = 6   ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH2                         = 9   ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH2_LEN                     = 6   ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_MAX_LEVEL                       = 15  ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_MAX_LEVEL_LEN                   = 4   ;
static const uint8_t P9N2_NV_CONFIG1_RESERVED1                                    = 19  ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK               = 20  ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK_LEN           = 16  ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK            = 36  ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK            = 37  ;
static const uint8_t P9N2_NV_CONFIG1_CONFIG_CHICKEN_HW405869_DISABLE_PATCH        = 38  ;
static const uint8_t P9N2_NV_CONFIG1_RESERVED2                                    = 39  ;
static const uint8_t P9N2_NV_CONFIG1_RESERVED2_LEN                                = 25  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA       = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ      = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ      = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_USES_HANG       = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT      = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE      = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE       = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_RESERVED                         = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_RESERVED_LEN                     = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY         = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN     = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA       = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ      = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ      = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_USES_HANG       = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT      = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE      = 56  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE       = 57  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_RESERVED                         = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_RESERVED_LEN                     = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN   = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_RESERVED                         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_RESERVED_LEN                     = 48  ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN   = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_RESERVED                         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_RESERVED_LEN                     = 48  ;

static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_BRICK_ENABLE                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA             = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CREQ_BE_128                         = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DGD_BE_128                          = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_WR_SPLIT_UT0_ENA                    = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_WR_SPLIT_UT1_ENA                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_BRICK_DEBUG_MODE                    = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_P9_TO_P9_MODE                       = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED1                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CAM256_MAX_CNT                      = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CAM256_MAX_CNT_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_NDL_RX_PARITY_ENA                   = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_NDL_TX_PARITY_ENA                   = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_NDL_PRI_PARITY_ENA                  = 18  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA             = 19  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_HDR_ARR_ECC_CORR_ENA                = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DAT_ARR_ECC_CORR_ENA                = 21  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_TX_DATA_ECC_CORR_ENA                = 22  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED2                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_PARITY_ERROR_SUE_ENA                = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DATA_POISON_SUE_ENA                 = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_HDR_ARR_ECC_SUE_ENA                 = 26  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DAT_ARR_ECC_SUE_ENA                 = 27  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_TX_ECC_DATA_POISON_ENA              = 28  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED3                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED3_LEN                       = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_PRI_STATE_MACHINE_RESET             = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED4                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED4_LEN                       = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA            = 36  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DGD_CTL_CRED_SINGLE_ENA             = 37  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA            = 38  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED5                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED5_LEN                       = 25  ;

static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2__SM1_CONFIG2_BRICK_ENABLE                               = 0   ;
static const uint8_t P9N2__SM1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA                    = 1   ;
static const uint8_t P9N2__SM1_CONFIG2_CREQ_BE_128                                = 2   ;
static const uint8_t P9N2__SM1_CONFIG2_DGD_BE_128                                 = 3   ;
static const uint8_t P9N2__SM1_CONFIG2_WR_SPLIT_UT0_ENA                           = 4   ;
static const uint8_t P9N2__SM1_CONFIG2_WR_SPLIT_UT1_ENA                           = 5   ;
static const uint8_t P9N2__SM1_CONFIG2_BRICK_DEBUG_MODE                           = 6   ;
static const uint8_t P9N2__SM1_CONFIG2_P9_TO_P9_MODE                              = 7   ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED1                                  = 8   ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED1_LEN                              = 2   ;
static const uint8_t P9N2__SM1_CONFIG2_CAM256_MAX_CNT                             = 10  ;
static const uint8_t P9N2__SM1_CONFIG2_CAM256_MAX_CNT_LEN                         = 6   ;
static const uint8_t P9N2__SM1_CONFIG2_NDL_RX_PARITY_ENA                          = 16  ;
static const uint8_t P9N2__SM1_CONFIG2_NDL_TX_PARITY_ENA                          = 17  ;
static const uint8_t P9N2__SM1_CONFIG2_NDL_PRI_PARITY_ENA                         = 18  ;
static const uint8_t P9N2__SM1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA                    = 19  ;
static const uint8_t P9N2__SM1_CONFIG2_HDR_ARR_ECC_CORR_ENA                       = 20  ;
static const uint8_t P9N2__SM1_CONFIG2_DAT_ARR_ECC_CORR_ENA                       = 21  ;
static const uint8_t P9N2__SM1_CONFIG2_TX_DATA_ECC_CORR_ENA                       = 22  ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED2                                  = 23  ;
static const uint8_t P9N2__SM1_CONFIG2_PARITY_ERROR_SUE_ENA                       = 24  ;
static const uint8_t P9N2__SM1_CONFIG2_DATA_POISON_SUE_ENA                        = 25  ;
static const uint8_t P9N2__SM1_CONFIG2_HDR_ARR_ECC_SUE_ENA                        = 26  ;
static const uint8_t P9N2__SM1_CONFIG2_DAT_ARR_ECC_SUE_ENA                        = 27  ;
static const uint8_t P9N2__SM1_CONFIG2_TX_ECC_DATA_POISON_ENA                     = 28  ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED3                                  = 29  ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED3_LEN                              = 3   ;
static const uint8_t P9N2__SM1_CONFIG2_PRI_STATE_MACHINE_RESET                    = 32  ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED4                                  = 33  ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED4_LEN                              = 3   ;
static const uint8_t P9N2__SM1_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA                   = 36  ;
static const uint8_t P9N2__SM1_CONFIG2_DGD_CTL_CRED_SINGLE_ENA                    = 37  ;
static const uint8_t P9N2__SM1_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA                   = 38  ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED5                                  = 39  ;
static const uint8_t P9N2__SM1_CONFIG2_RESERVED5_LEN                              = 25  ;

static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG2_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG2_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2__SM0_CONFIG2_BRICK_ENABLE                               = 0   ;
static const uint8_t P9N2__SM0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA                    = 1   ;
static const uint8_t P9N2__SM0_CONFIG2_CREQ_BE_128                                = 2   ;
static const uint8_t P9N2__SM0_CONFIG2_DGD_BE_128                                 = 3   ;
static const uint8_t P9N2__SM0_CONFIG2_WR_SPLIT_UT0_ENA                           = 4   ;
static const uint8_t P9N2__SM0_CONFIG2_WR_SPLIT_UT1_ENA                           = 5   ;
static const uint8_t P9N2__SM0_CONFIG2_BRICK_DEBUG_MODE                           = 6   ;
static const uint8_t P9N2__SM0_CONFIG2_P9_TO_P9_MODE                              = 7   ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED1                                  = 8   ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED1_LEN                              = 2   ;
static const uint8_t P9N2__SM0_CONFIG2_CAM256_MAX_CNT                             = 10  ;
static const uint8_t P9N2__SM0_CONFIG2_CAM256_MAX_CNT_LEN                         = 6   ;
static const uint8_t P9N2__SM0_CONFIG2_NDL_RX_PARITY_ENA                          = 16  ;
static const uint8_t P9N2__SM0_CONFIG2_NDL_TX_PARITY_ENA                          = 17  ;
static const uint8_t P9N2__SM0_CONFIG2_NDL_PRI_PARITY_ENA                         = 18  ;
static const uint8_t P9N2__SM0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA                    = 19  ;
static const uint8_t P9N2__SM0_CONFIG2_HDR_ARR_ECC_CORR_ENA                       = 20  ;
static const uint8_t P9N2__SM0_CONFIG2_DAT_ARR_ECC_CORR_ENA                       = 21  ;
static const uint8_t P9N2__SM0_CONFIG2_TX_DATA_ECC_CORR_ENA                       = 22  ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED2                                  = 23  ;
static const uint8_t P9N2__SM0_CONFIG2_PARITY_ERROR_SUE_ENA                       = 24  ;
static const uint8_t P9N2__SM0_CONFIG2_DATA_POISON_SUE_ENA                        = 25  ;
static const uint8_t P9N2__SM0_CONFIG2_HDR_ARR_ECC_SUE_ENA                        = 26  ;
static const uint8_t P9N2__SM0_CONFIG2_DAT_ARR_ECC_SUE_ENA                        = 27  ;
static const uint8_t P9N2__SM0_CONFIG2_TX_ECC_DATA_POISON_ENA                     = 28  ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED3                                  = 29  ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED3_LEN                              = 3   ;
static const uint8_t P9N2__SM0_CONFIG2_PRI_STATE_MACHINE_RESET                    = 32  ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED4                                  = 33  ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED4_LEN                              = 3   ;
static const uint8_t P9N2__SM0_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA                   = 36  ;
static const uint8_t P9N2__SM0_CONFIG2_DGD_CTL_CRED_SINGLE_ENA                    = 37  ;
static const uint8_t P9N2__SM0_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA                   = 38  ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED5                                  = 39  ;
static const uint8_t P9N2__SM0_CONFIG2_RESERVED5_LEN                              = 25  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN   = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_RESERVED                         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_RESERVED_LEN                     = 48  ;

static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_BRICK_ENABLE                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA              = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CREQ_BE_128                          = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DGD_BE_128                           = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_WR_SPLIT_UT0_ENA                     = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_WR_SPLIT_UT1_ENA                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_BRICK_DEBUG_MODE                     = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_P9_TO_P9_MODE                        = 7   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED1                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED1_LEN                        = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CAM256_MAX_CNT                       = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CAM256_MAX_CNT_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_NDL_RX_PARITY_ENA                    = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_NDL_TX_PARITY_ENA                    = 17  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_NDL_PRI_PARITY_ENA                   = 18  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA              = 19  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_HDR_ARR_ECC_CORR_ENA                 = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DAT_ARR_ECC_CORR_ENA                 = 21  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_TX_DATA_ECC_CORR_ENA                 = 22  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED2                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_PARITY_ERROR_SUE_ENA                 = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DATA_POISON_SUE_ENA                  = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_HDR_ARR_ECC_SUE_ENA                  = 26  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DAT_ARR_ECC_SUE_ENA                  = 27  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_TX_ECC_DATA_POISON_ENA               = 28  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED3                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED3_LEN                        = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_PRI_STATE_MACHINE_RESET              = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED4                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED4_LEN                        = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DGD_CTL_CRED_SINGLE_ENA              = 37  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA             = 38  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED5                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED5_LEN                        = 25  ;

static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_BRICK_ENABLE                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA              = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CREQ_BE_128                          = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DGD_BE_128                           = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_WR_SPLIT_UT0_ENA                     = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_WR_SPLIT_UT1_ENA                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_BRICK_DEBUG_MODE                     = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_P9_TO_P9_MODE                        = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED1                            = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED1_LEN                        = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CAM256_MAX_CNT                       = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CAM256_MAX_CNT_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_NDL_RX_PARITY_ENA                    = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_NDL_TX_PARITY_ENA                    = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_NDL_PRI_PARITY_ENA                   = 18  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA              = 19  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_HDR_ARR_ECC_CORR_ENA                 = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DAT_ARR_ECC_CORR_ENA                 = 21  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_TX_DATA_ECC_CORR_ENA                 = 22  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED2                            = 23  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_PARITY_ERROR_SUE_ENA                 = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DATA_POISON_SUE_ENA                  = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_HDR_ARR_ECC_SUE_ENA                  = 26  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DAT_ARR_ECC_SUE_ENA                  = 27  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_TX_ECC_DATA_POISON_ENA               = 28  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED3                            = 29  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED3_LEN                        = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_PRI_STATE_MACHINE_RESET              = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED4                            = 33  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED4_LEN                        = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA             = 36  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DGD_CTL_CRED_SINGLE_ENA              = 37  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA             = 38  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED5                            = 39  ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED5_LEN                        = 25  ;

static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK          = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN      = 14  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK   = 14  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK   = 15  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_RESERVED                            = 16  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_RESERVED_LEN                        = 48  ;

static const uint8_t P9N2_NV_CONFIG2_IDIAL                                        = 0   ;
static const uint8_t P9N2_NV_CONFIG2_IDIAL_LEN                                    = 64  ;

static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_BRICK_ENABLE                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA             = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CREQ_BE_128                         = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DGD_BE_128                          = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_WR_SPLIT_UT0_ENA                    = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_WR_SPLIT_UT1_ENA                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_BRICK_DEBUG_MODE                    = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_P9_TO_P9_MODE                       = 7   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED1                           = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CAM256_MAX_CNT                      = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CAM256_MAX_CNT_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_NDL_RX_PARITY_ENA                   = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_NDL_TX_PARITY_ENA                   = 17  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_NDL_PRI_PARITY_ENA                  = 18  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA             = 19  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_HDR_ARR_ECC_CORR_ENA                = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DAT_ARR_ECC_CORR_ENA                = 21  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_TX_DATA_ECC_CORR_ENA                = 22  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED2                           = 23  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_PARITY_ERROR_SUE_ENA                = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DATA_POISON_SUE_ENA                 = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_HDR_ARR_ECC_SUE_ENA                 = 26  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DAT_ARR_ECC_SUE_ENA                 = 27  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_TX_ECC_DATA_POISON_ENA              = 28  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED3                           = 29  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED3_LEN                       = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_PRI_STATE_MACHINE_RESET             = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED4                           = 33  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED4_LEN                       = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA            = 36  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DGD_CTL_CRED_SINGLE_ENA             = 37  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA            = 38  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED5                           = 39  ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED5_LEN                       = 25  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN   = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_RESERVED                         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_RESERVED_LEN                     = 48  ;

static const uint8_t P9N2_PU_NPU1_SM1_CONFIG3_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CONFIG3_RESERVED1_LEN                       = 64  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG3_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG3_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2__SM0_CONFIG3_RESERVED1                                  = 0   ;
static const uint8_t P9N2__SM0_CONFIG3_RESERVED1_LEN                              = 64  ;

static const uint8_t P9N2_PU_NPU_SM0_CONFIG3_RESERVED1                            = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_CONFIG3_RESERVED1_LEN                        = 64  ;

static const uint8_t P9N2_PU_NPU_SM1_CONFIG3_RESERVED1                            = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CONFIG3_RESERVED1_LEN                        = 64  ;

static const uint8_t P9N2_NV_CONFIG3_IDIAL                                        = 0   ;
static const uint8_t P9N2_NV_CONFIG3_IDIAL_LEN                                    = 64  ;

static const uint8_t P9N2_PU_NPU1_SM0_CONFIG3_RESERVED1                           = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_CONFIG3_RESERVED1_LEN                       = 64  ;

static const uint8_t P9N2__SM1_CONFIG3_RESERVED1                                  = 0   ;
static const uint8_t P9N2__SM1_CONFIG3_RESERVED1_LEN                              = 64  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_ENABLE                        = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_STATUS                        = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_STATUS_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_BUS_NUMBER                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_BUS_NUMBER_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_DEVICE_NUMBER                 = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_DEVICE_NUMBER_LEN             = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_FUNCTION_NUMBER               = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_FUNCTION_NUMBER_LEN           = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_REGISTER_NUMBER               = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_REGISTER_NUMBER_LEN           = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_TYPE                          = 32  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_ENABLE                        = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_STATUS                        = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_STATUS_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_BUS_NUMBER                    = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_BUS_NUMBER_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_DEVICE_NUMBER                 = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_DEVICE_NUMBER_LEN             = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_FUNCTION_NUMBER               = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_FUNCTION_NUMBER_LEN           = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_REGISTER_NUMBER               = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_REGISTER_NUMBER_LEN           = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_TYPE                          = 32  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA0_DATA                          = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA0_DATA_LEN                      = 32  ;

static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA1_DATA                          = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA1_DATA_LEN                      = 32  ;

static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE0                          = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE1                          = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE2                          = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE3                          = 15  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE4                          = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE5                          = 25  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE6                          = 30  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE7                          = 35  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE8                          = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE9                          = 45  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE10                         = 50  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_RESERVED                       = 55  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_RESERVED_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_DEBUG_ACT                      = 63  ;

static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE0                          = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE1                          = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE2                          = 10  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE3                          = 15  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE4                          = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE5                          = 25  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE6                          = 30  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE7                          = 35  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE8                          = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE9                          = 45  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE10                         = 50  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_RESERVED                       = 55  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_RESERVED_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_DEBUG_ACT                      = 63  ;

static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE0                                = 0   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE0_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE1                                = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE1_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE2                                = 10  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE2_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE3                                = 15  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE3_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE4                                = 20  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE4_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE5                                = 25  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE5_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE6                                = 30  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE6_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE7                                = 35  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE7_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE8                                = 40  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE8_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE9                                = 45  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE9_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE10                               = 50  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE10_LEN                           = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_RESERVED                             = 55  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_RESERVED_LEN                         = 8   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG0_DEBUG_ACT                            = 63  ;

static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE0                                = 0   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE0_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE1                                = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE1_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE2                                = 10  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE2_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE3                                = 15  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE3_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE4                                = 20  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE4_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE5                                = 25  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE5_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE6                                = 30  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE6_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE7                                = 35  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE7_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE8                                = 40  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE8_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE9                                = 45  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE9_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE10                               = 50  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE10_LEN                           = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_RESERVED                             = 55  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_RESERVED_LEN                         = 8   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG0_DEBUG_ACT                            = 63  ;

static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE0                          = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE1                          = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE2                          = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE3                          = 15  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE4                          = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE5                          = 25  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE6                          = 30  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE7                          = 35  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE8                          = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE9                          = 45  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE10                         = 50  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_RESERVED                       = 55  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_RESERVED_LEN                   = 9   ;

static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE0                          = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE1                          = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE2                          = 10  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE3                          = 15  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE4                          = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE5                          = 25  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE6                          = 30  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE7                          = 35  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE8                          = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE9                          = 45  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE10                         = 50  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_RESERVED                       = 55  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_RESERVED_LEN                   = 9   ;

static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE0                                = 0   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE0_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE1                                = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE1_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE2                                = 10  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE2_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE3                                = 15  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE3_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE4                                = 20  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE4_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE5                                = 25  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE5_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE6                                = 30  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE6_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE7                                = 35  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE7_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE8                                = 40  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE8_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE9                                = 45  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE9_LEN                            = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE10                               = 50  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE10_LEN                           = 5   ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_RESERVED                             = 55  ;
static const uint8_t P9N2__CTL_CONFIG_DEBUG1_RESERVED_LEN                         = 9   ;

static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE0                                = 0   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE0_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE1                                = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE1_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE2                                = 10  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE2_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE3                                = 15  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE3_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE4                                = 20  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE4_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE5                                = 25  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE5_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE6                                = 30  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE6_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE7                                = 35  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE7_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE8                                = 40  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE8_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE9                                = 45  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE9_LEN                            = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE10                               = 50  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE10_LEN                           = 5   ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_RESERVED                             = 55  ;
static const uint8_t P9N2__SM2_CONFIG_DEBUG1_RESERVED_LEN                         = 9   ;

static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL      = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX       = 15  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX       = 26  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN  = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP      = 38  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN   = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX       = 58  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN   = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA    = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL   = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX    = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX    = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP   = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX    = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6   ;

static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP  = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR      = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR     = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND    = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR     = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR    = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E  = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1        = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA    = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA    = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA    = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA    = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA    = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA    = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA    = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA    = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA    = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA    = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA    = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA    = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2        = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN    = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP  = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR      = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR     = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND    = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR     = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR    = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E  = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1        = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA    = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA    = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA    = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA    = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA    = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA    = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA    = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA    = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA    = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA    = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA    = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA    = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2        = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN    = 4   ;

static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        = 11  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        = 13  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       = 19  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       = 21  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     = 22  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1           = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN       = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA       = 28  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA       = 29  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA       = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA       = 31  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA       = 33  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA       = 34  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA       = 35  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA       = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA       = 37  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA       = 38  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA       = 39  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA       = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA       = 41  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA       = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA       = 43  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA       = 44  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA       = 45  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA       = 46  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA       = 47  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2           = 48  ;
static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN       = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP  = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR      = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR     = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND    = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR     = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR    = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E  = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1        = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA    = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA    = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA    = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA    = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA    = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA    = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA    = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA    = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA    = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA    = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA    = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA    = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2        = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN    = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP  = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND     = 11  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR      = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR     = 13  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND    = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR     = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR    = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E  = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1        = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA    = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA    = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA    = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA    = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA    = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA    = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA    = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA    = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA    = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA    = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA    = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA    = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA    = 43  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA    = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA    = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA    = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA    = 47  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2        = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN    = 4   ;

static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC0                       = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC0_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC1                       = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC1_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC2                       = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC2_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC3                       = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC3_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP0                      = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP0_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_SPARE                     = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_SPARE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP2                      = 48  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP2_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP3                      = 56  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP3_LEN                  = 8   ;

static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC0                       = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC0_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC1                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC1_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC2                       = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC2_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC3                       = 24  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC3_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP0                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP0_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_SPARE                     = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_SPARE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP2                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP2_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP3                      = 56  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP3_LEN                  = 8   ;

static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC0                             = 0   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC0_LEN                         = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC1                             = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC1_LEN                         = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC2                             = 16  ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC2_LEN                         = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC3                             = 24  ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC3_LEN                         = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP0                            = 32  ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP0_LEN                        = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_SPARE                           = 40  ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_SPARE_LEN                       = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP2                            = 48  ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP2_LEN                        = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP3                            = 56  ;
static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP3_LEN                        = 8   ;

static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC0                             = 0   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC0_LEN                         = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC1                             = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC1_LEN                         = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC2                             = 16  ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC2_LEN                         = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC3                             = 24  ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC3_LEN                         = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP0                            = 32  ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP0_LEN                        = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_SPARE                           = 40  ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_SPARE_LEN                       = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP2                            = 48  ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP2_LEN                        = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP3                            = 56  ;
static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP3_LEN                        = 8   ;

static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE0                             = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP1_EN                           = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP2_EN                           = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP3_EN                           = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE1                             = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DRDY_WAIT                          = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DRDY_WAIT_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP0_RATE                         = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP0_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP1_RATE                         = 12  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP1_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP2_RATE                         = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP2_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP3_RATE                         = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP3_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE2                             = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE2_LEN                         = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_CRET_FREQ                          = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_CRET_FREQ_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_AGE_FREQ                           = 35  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_AGE_FREQ_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RS2_HPWAIT                         = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RS2_HPWAIT_LEN                     = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ4_HPWAIT                         = 46  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ4_HPWAIT_LEN                     = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ6_HPWAIT                         = 52  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ6_HPWAIT_LEN                     = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_CBUF_ECC_DIS                       = 58  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_STOP_LINK                          = 59  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_STOP_ON_UE                         = 60  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_T0_MASK_CRTN0                      = 61  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_T123_MASK_CRTN0                    = 62  ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE3                             = 63  ;

static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE0                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP1_EN                           = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP2_EN                           = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP3_EN                           = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE1                             = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DRDY_WAIT                          = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DRDY_WAIT_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP0_RATE                         = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP0_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP1_RATE                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP1_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP2_RATE                         = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP2_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP3_RATE                         = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP3_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE2                             = 24  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE2_LEN                         = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_CRET_FREQ                          = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_CRET_FREQ_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_AGE_FREQ                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_AGE_FREQ_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RS2_HPWAIT                         = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RS2_HPWAIT_LEN                     = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ4_HPWAIT                         = 46  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ4_HPWAIT_LEN                     = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ6_HPWAIT                         = 52  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ6_HPWAIT_LEN                     = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_CBUF_ECC_DIS                       = 58  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_STOP_LINK                          = 59  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_STOP_ON_UE                         = 60  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_T0_MASK_CRTN0                      = 61  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_T123_MASK_CRTN0                    = 62  ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE3                             = 63  ;

static const uint8_t P9N2__CTL_CONFIG_TX_SPARE0                                   = 0   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP1_EN                                 = 1   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP2_EN                                 = 2   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP3_EN                                 = 3   ;
static const uint8_t P9N2__CTL_CONFIG_TX_SPARE1                                   = 4   ;
static const uint8_t P9N2__CTL_CONFIG_TX_DRDY_WAIT                                = 5   ;
static const uint8_t P9N2__CTL_CONFIG_TX_DRDY_WAIT_LEN                            = 3   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP0_RATE                               = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP0_RATE_LEN                           = 4   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP1_RATE                               = 12  ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP1_RATE_LEN                           = 4   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP2_RATE                               = 16  ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP2_RATE_LEN                           = 4   ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP3_RATE                               = 20  ;
static const uint8_t P9N2__CTL_CONFIG_TX_TEMP3_RATE_LEN                           = 4   ;
static const uint8_t P9N2__CTL_CONFIG_TX_SPARE2                                   = 24  ;
static const uint8_t P9N2__CTL_CONFIG_TX_SPARE2_LEN                               = 8   ;
static const uint8_t P9N2__CTL_CONFIG_TX_CRET_FREQ                                = 32  ;
static const uint8_t P9N2__CTL_CONFIG_TX_CRET_FREQ_LEN                            = 3   ;
static const uint8_t P9N2__CTL_CONFIG_TX_AGE_FREQ                                 = 35  ;
static const uint8_t P9N2__CTL_CONFIG_TX_AGE_FREQ_LEN                             = 5   ;
static const uint8_t P9N2__CTL_CONFIG_TX_RS2_HPWAIT                               = 40  ;
static const uint8_t P9N2__CTL_CONFIG_TX_RS2_HPWAIT_LEN                           = 6   ;
static const uint8_t P9N2__CTL_CONFIG_TX_RQ4_HPWAIT                               = 46  ;
static const uint8_t P9N2__CTL_CONFIG_TX_RQ4_HPWAIT_LEN                           = 6   ;
static const uint8_t P9N2__CTL_CONFIG_TX_RQ6_HPWAIT                               = 52  ;
static const uint8_t P9N2__CTL_CONFIG_TX_RQ6_HPWAIT_LEN                           = 6   ;
static const uint8_t P9N2__CTL_CONFIG_TX_CBUF_ECC_DIS                             = 58  ;
static const uint8_t P9N2__CTL_CONFIG_TX_STOP_LINK                                = 59  ;
static const uint8_t P9N2__CTL_CONFIG_TX_STOP_ON_UE                               = 60  ;
static const uint8_t P9N2__CTL_CONFIG_TX_T0_MASK_CRTN0                            = 61  ;
static const uint8_t P9N2__CTL_CONFIG_TX_T123_MASK_CRTN0                          = 62  ;
static const uint8_t P9N2__CTL_CONFIG_TX_SPARE3                                   = 63  ;

static const uint8_t P9N2__SM2_CONFIG_TX_SPARE0                                   = 0   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP1_EN                                 = 1   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP2_EN                                 = 2   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP3_EN                                 = 3   ;
static const uint8_t P9N2__SM2_CONFIG_TX_SPARE1                                   = 4   ;
static const uint8_t P9N2__SM2_CONFIG_TX_DRDY_WAIT                                = 5   ;
static const uint8_t P9N2__SM2_CONFIG_TX_DRDY_WAIT_LEN                            = 3   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP0_RATE                               = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP0_RATE_LEN                           = 4   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP1_RATE                               = 12  ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP1_RATE_LEN                           = 4   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP2_RATE                               = 16  ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP2_RATE_LEN                           = 4   ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP3_RATE                               = 20  ;
static const uint8_t P9N2__SM2_CONFIG_TX_TEMP3_RATE_LEN                           = 4   ;
static const uint8_t P9N2__SM2_CONFIG_TX_SPARE2                                   = 24  ;
static const uint8_t P9N2__SM2_CONFIG_TX_SPARE2_LEN                               = 8   ;
static const uint8_t P9N2__SM2_CONFIG_TX_CRET_FREQ                                = 32  ;
static const uint8_t P9N2__SM2_CONFIG_TX_CRET_FREQ_LEN                            = 3   ;
static const uint8_t P9N2__SM2_CONFIG_TX_AGE_FREQ                                 = 35  ;
static const uint8_t P9N2__SM2_CONFIG_TX_AGE_FREQ_LEN                             = 5   ;
static const uint8_t P9N2__SM2_CONFIG_TX_RS2_HPWAIT                               = 40  ;
static const uint8_t P9N2__SM2_CONFIG_TX_RS2_HPWAIT_LEN                           = 6   ;
static const uint8_t P9N2__SM2_CONFIG_TX_RQ4_HPWAIT                               = 46  ;
static const uint8_t P9N2__SM2_CONFIG_TX_RQ4_HPWAIT_LEN                           = 6   ;
static const uint8_t P9N2__SM2_CONFIG_TX_RQ6_HPWAIT                               = 52  ;
static const uint8_t P9N2__SM2_CONFIG_TX_RQ6_HPWAIT_LEN                           = 6   ;
static const uint8_t P9N2__SM2_CONFIG_TX_CBUF_ECC_DIS                             = 58  ;
static const uint8_t P9N2__SM2_CONFIG_TX_STOP_LINK                                = 59  ;
static const uint8_t P9N2__SM2_CONFIG_TX_STOP_ON_UE                               = 60  ;
static const uint8_t P9N2__SM2_CONFIG_TX_T0_MASK_CRTN0                            = 61  ;
static const uint8_t P9N2__SM2_CONFIG_TX_T123_MASK_CRTN0                          = 62  ;
static const uint8_t P9N2__SM2_CONFIG_TX_SPARE3                                   = 63  ;

static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX2_TX_SEND_EN                        = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX2_TX_SPARE4                         = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX2_TX_SPARE4_LEN                     = 3   ;

static const uint8_t P9N2__CTL_CONFIG_TX2_TX_SEND_EN                              = 0   ;
static const uint8_t P9N2__CTL_CONFIG_TX2_TX_SPARE4                               = 1   ;
static const uint8_t P9N2__CTL_CONFIG_TX2_TX_SPARE4_LEN                           = 3   ;

static const uint8_t P9N2__SM3_CONFIG_TX2_TX_SEND_EN                              = 0   ;
static const uint8_t P9N2__SM3_CONFIG_TX2_TX_SPARE4                               = 1   ;
static const uint8_t P9N2__SM3_CONFIG_TX2_TX_SPARE4_LEN                           = 3   ;

static const uint8_t P9N2_PU_NPU_SM3_CONFIG_TX2_TX_SEND_EN                        = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_CONFIG_TX2_TX_SPARE4                         = 1   ;
static const uint8_t P9N2_PU_NPU_SM3_CONFIG_TX2_TX_SPARE4_LEN                     = 3   ;

static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DLC_DL_CREDITS                     = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DLC_DL_CREDITS_LEN                 = 10  ;

static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DLC_DL_CREDITS                     = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DLC_DL_CREDITS_LEN                 = 10  ;

static const uint8_t P9N2__CTL_CONFIG_TX_DLC_DL_CREDITS                           = 0   ;
static const uint8_t P9N2__CTL_CONFIG_TX_DLC_DL_CREDITS_LEN                       = 10  ;

static const uint8_t P9N2__SM2_CONFIG_TX_DLC_DL_CREDITS                           = 0   ;
static const uint8_t P9N2__SM2_CONFIG_TX_DLC_DL_CREDITS_LEN                       = 10  ;

static const uint8_t P9N2_PEC_CONTROL_REG_RESET_TRIP_HISTORY                      = 0   ;
static const uint8_t P9N2_PEC_CONTROL_REG_RESET_SAMPLE_PULSE_CNT                  = 1   ;
static const uint8_t P9N2_PEC_CONTROL_REG_F_RESET_CPM_RD                          = 2   ;
static const uint8_t P9N2_PEC_CONTROL_REG_F_RESET_CPM_WR                          = 3   ;
static const uint8_t P9N2_PEC_CONTROL_REG_RESET_SAMPLE_DTS                        = 4   ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_SAMPLE_DTS                        = 5   ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE          = 6   ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS             = 7   ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS             = 8   ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS             = 9   ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE        = 10  ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_MEASURE_VOLT                = 11  ;
static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_SHIFT_SENSOR                      = 12  ;

static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0      = 0   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHADDR_0       = 1   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_READCONT_0       = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTOP_0       = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0             = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0_LEN         = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0               = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0_LEN           = 7   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_RNW_0            = 15  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0              = 16  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0_LEN          = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0        = 18  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0_LEN    = 5   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0                    = 23  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0_LEN                = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_ENH_MODE_0                        = 26  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_ECC_ENABLE_0                      = 27  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_ECCCHK_DISABLE_0                  = 28  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_UNUSED_0                          = 29  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0 = 30  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0             = 32  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0             = 40  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0             = 48  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0             = 56  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0_LEN         = 8   ;

static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTART_1      = 0   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHADDR_1       = 1   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_READCONT_1       = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTOP_1       = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1             = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1_LEN         = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1               = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1_LEN           = 7   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_RNW_1            = 15  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1              = 16  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1_LEN          = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1        = 18  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1_LEN    = 5   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1                    = 23  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1_LEN                = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_ENH_MODE_1                        = 26  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_ECC_ENABLE_1                      = 27  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_ECCCHK_DISABLE_1                  = 28  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_UNUSED_1                          = 29  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1 = 30  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1             = 32  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1             = 40  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1             = 48  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1             = 56  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1_LEN         = 8   ;

static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTART_2      = 0   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHADDR_2       = 1   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_READCONT_2       = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTOP_2       = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2             = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2_LEN         = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2               = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2_LEN           = 7   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_RNW_2            = 15  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2              = 16  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2_LEN          = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2        = 18  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2_LEN    = 5   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2                    = 23  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2_LEN                = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_ENH_MODE_2                        = 26  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_ECC_ENABLE_2                      = 27  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_ECCCHK_DISABLE_2                  = 28  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_UNUSED_2                          = 29  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2 = 30  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2             = 32  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2             = 40  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2             = 48  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2             = 56  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2_LEN         = 8   ;

static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTART_3      = 0   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHADDR_3       = 1   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_READCONT_3       = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTOP_3       = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3             = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3_LEN         = 4   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3               = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3_LEN           = 7   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_RNW_3            = 15  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3              = 16  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3_LEN          = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3        = 18  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3_LEN    = 5   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3                    = 23  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3_LEN                = 3   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_ENH_MODE_3                        = 26  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_ECC_ENABLE_3                      = 27  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_ECCCHK_DISABLE_3                  = 28  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_UNUSED_3                          = 29  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3 = 30  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN = 2   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3             = 32  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3             = 40  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3             = 48  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3_LEN         = 8   ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3             = 56  ;
static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3_LEN         = 8   ;

static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC                  = 0   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN              = 6   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_6C                              = 6   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_7C                              = 7   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC                  = 8   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN              = 6   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_14C                             = 14  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_15C                             = 15  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC                  = 16  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN              = 6   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_22C                             = 22  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_23C                             = 23  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC                  = 24  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN              = 6   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_30C                             = 30  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_31C                             = 31  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC                 = 32  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC                  = 33  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_SDIS_DC_N                        = 34  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_SCAN_DIAG                        = 35  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_36C                = 36  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_37C                = 37  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_38C                = 38  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_39C                = 39  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC            = 40  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC       = 41  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_42C                             = 42  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_43C                             = 43  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_TC_PCB_DBG_GLB_BRCST_EN                  = 44  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_FREE_USAGE_45C                           = 45  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_FREE_USAGE_46C                           = 46  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_FREE_USAGE_47C                           = 47  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC                      = 48  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN                  = 4   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC                       = 52  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN                   = 3   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_55C                          = 55  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC                        = 56  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN                    = 5   ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_61C                          = 61  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_62C                          = 62  ;
static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_63C                          = 63  ;

static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_0D                                = 0   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_1D                                = 1   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_2D                                = 2   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_3D                                = 3   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_IOVALID                          = 4   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_5D                                = 5   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_6D                                = 6   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_7D                                = 7   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_8D                                = 8   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_9D                                = 9   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_10D                               = 10  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_11D                               = 11  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_SWAP_DC                          = 12  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC                      = 13  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC_LEN                  = 2   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_RATIO_OVERRIDE                   = 15  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_RATIO_DC                         = 16  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_RATIO_DC_LEN                     = 3   ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_19D                               = 19  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_20D                               = 20  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_21D                               = 21  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_22D                               = 22  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_23D                               = 23  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_24D                               = 24  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_25D                               = 25  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_26D                               = 26  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_27D                               = 27  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PCS                     = 28  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PMA                     = 29  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_TC_IOP_HSSPORWREN                        = 30  ;
static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_31D                               = 31  ;

static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC                = 0   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC                = 1   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC                 = 2   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC                   = 3   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC                  = 4   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_5A                                = 5   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_6A                                = 6   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_7A                                = 7   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC           = 8   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_9A                                = 9   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_10A                               = 10  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_11A                             = 11  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC                     = 12  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC     = 13  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC            = 14  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC              = 15  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_16A                               = 16  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_17A                               = 17  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_18A                             = 18  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_19A                             = 19  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_20A                               = 20  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_21A                               = 21  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_22A                               = 22  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_23A                               = 23  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_24A                               = 24  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_25A                               = 25  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_26A                               = 26  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_27A                               = 27  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_WRAPSEL_DC                        = 28  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_INTMODE_DC                        = 29  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_INV_DC                            = 30  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_EXTMODE_DC                        = 31  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC                     = 32  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_33A                             = 33  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_34A                             = 34  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_35A                             = 35  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_36A                               = 36  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_37A                               = 37  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_38A                             = 38  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_39A                             = 39  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC                  = 40  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN              = 2   ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_42A                             = 42  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_43A                             = 43  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_44A                               = 44  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_45A                               = 45  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_46A                               = 46  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC                     = 47  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_48A                           = 48  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_49A                           = 49  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_50A                           = 50  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_51A                           = 51  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_52A                           = 52  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_53A                           = 53  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_54A                           = 54  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_55A                           = 55  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_56A                           = 56  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_57A                           = 57  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_58A                           = 58  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_59A                           = 59  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_60A                           = 60  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_61A                           = 61  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_62A                           = 62  ;
static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_63A                           = 63  ;

static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_0B                                = 0   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_1B                                = 1   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_2B                                = 2   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_VITL_REGION_FENCE                     = 3   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_PERV_REGION_FENCE                     = 4   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_REGION1_FENCE                         = 5   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_REGION2_FENCE                         = 6   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_7B                                = 7   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_8B                                = 8   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_9B                                = 9   ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_10B                               = 10  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_11B                               = 11  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_12B                               = 12  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_13B                               = 13  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_14B                               = 14  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_RESERVED                                 = 15  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE            = 16  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_17B                               = 17  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_18B                               = 18  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_19B                               = 19  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_20B                               = 20  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_21B                               = 21  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_22B                               = 22  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_23B                               = 23  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_24B                               = 24  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_25B                               = 25  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_26B                               = 26  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_27B                               = 27  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_28B                               = 28  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_29B                               = 29  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_30B                               = 30  ;
static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_31B                               = 31  ;

static const uint8_t P9N2_PEC_CPLT_MASK0_CPLTMASK0                                = 0   ;
static const uint8_t P9N2_PEC_CPLT_MASK0_CPLTMASK0_LEN                            = 24  ;

static const uint8_t P9N2_PEC_CPLT_STAT0_ABIST_DONE_DC                            = 0   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_UNUSED                                   = 1   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_RESERVED_2E                              = 2   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_RESERVED_3E                              = 3   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_TC_DIAG_PORT0_OUT                        = 4   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_TC_DIAG_PORT1_OUT                        = 5   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_RESERVED_6E                              = 6   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_PLL_DESTOUT                              = 7   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC                     = 8   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC            = 9   ;
static const uint8_t P9N2_PEC_CPLT_STAT0_IOPCI_TC_HSSPRTREADYA                    = 10  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_IOPCI_TC_HSSPRTREADYB                    = 11  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_12E                           = 12  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_13E                           = 13  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_14E                           = 14  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_15E                           = 15  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_16E                           = 16  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_17E                           = 17  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_18E                           = 18  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_19E                           = 19  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_20E                           = 20  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_21E                           = 21  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_22E                           = 22  ;
static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_23E                           = 23  ;

static const uint8_t P9N2_PHB_CQSTAT_REG_PE_INBOUND_ACTIVE                        = 0   ;
static const uint8_t P9N2_PHB_CQSTAT_REG_PE_OUTBOUND_ACTIVE                       = 1   ;

static const uint8_t P9N2_PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE                 = 0   ;
static const uint8_t P9N2_PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE                = 1   ;

static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED1                       = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED1_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_START                           = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_START_LEN                       = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED2                       = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED2_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_END                             = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_END_LEN                         = 9   ;

static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED1_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_START                            = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_START_LEN                        = 9   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED2_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_END                              = 15  ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_END_LEN                          = 9   ;

static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED1                       = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED1_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_START                           = 3   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_START_LEN                       = 9   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED2                       = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED2_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_END                             = 15  ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_END_LEN                         = 9   ;

static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED1_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_START                            = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_START_LEN                        = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED2_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_END                              = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_END_LEN                          = 9   ;

static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED1                              = 0   ;
static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED1_LEN                          = 3   ;
static const uint8_t P9N2__SM2_CREQ_DA_PTR_START                                  = 3   ;
static const uint8_t P9N2__SM2_CREQ_DA_PTR_START_LEN                              = 9   ;
static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED2                              = 12  ;
static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED2_LEN                          = 3   ;
static const uint8_t P9N2__SM2_CREQ_DA_PTR_END                                    = 15  ;
static const uint8_t P9N2__SM2_CREQ_DA_PTR_END_LEN                                = 9   ;

static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED1                              = 0   ;
static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED1_LEN                          = 3   ;
static const uint8_t P9N2__SM1_CREQ_DA_PTR_START                                  = 3   ;
static const uint8_t P9N2__SM1_CREQ_DA_PTR_START_LEN                              = 9   ;
static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED2                              = 12  ;
static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED2_LEN                          = 3   ;
static const uint8_t P9N2__SM1_CREQ_DA_PTR_END                                    = 15  ;
static const uint8_t P9N2__SM1_CREQ_DA_PTR_END_LEN                                = 9   ;

static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED1                       = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_START                           = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_START_LEN                       = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED2                       = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_END                             = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_END_LEN                         = 7   ;

static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED1                       = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_START                           = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_START_LEN                       = 7   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED2                       = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_END                             = 17  ;
static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_END_LEN                         = 7   ;

static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED1                              = 0   ;
static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED1_LEN                          = 5   ;
static const uint8_t P9N2__SM2_CREQ_HA_PTR_START                                  = 5   ;
static const uint8_t P9N2__SM2_CREQ_HA_PTR_START_LEN                              = 7   ;
static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED2                              = 12  ;
static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED2_LEN                          = 5   ;
static const uint8_t P9N2__SM2_CREQ_HA_PTR_END                                    = 17  ;
static const uint8_t P9N2__SM2_CREQ_HA_PTR_END_LEN                                = 7   ;

static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED1                              = 0   ;
static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED1_LEN                          = 5   ;
static const uint8_t P9N2__SM1_CREQ_HA_PTR_START                                  = 5   ;
static const uint8_t P9N2__SM1_CREQ_HA_PTR_START_LEN                              = 7   ;
static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED2                              = 12  ;
static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED2_LEN                          = 5   ;
static const uint8_t P9N2__SM1_CREQ_HA_PTR_END                                    = 17  ;
static const uint8_t P9N2__SM1_CREQ_HA_PTR_END_LEN                                = 7   ;

static const uint8_t P9N2_PU_CSAR_SRAM_ADDRESS                                    = 16  ;
static const uint8_t P9N2_PU_CSAR_SRAM_ADDRESS_LEN                                = 13  ;

static const uint8_t P9N2_PU_CSCR_SRAM_ACCESS_MODE                                = 0   ;
static const uint8_t P9N2_PU_CSCR_SRAM_SCRUB_ENABLE                               = 1   ;
static const uint8_t P9N2_PU_CSCR_ECC_CORRECT_DIS                                 = 2   ;
static const uint8_t P9N2_PU_CSCR_ECC_DETECT_DIS                                  = 3   ;
static const uint8_t P9N2_PU_CSCR_ECC_INJECT_TYPE                                 = 4   ;
static const uint8_t P9N2_PU_CSCR_ECC_INJECT_ERR                                  = 5   ;
static const uint8_t P9N2_PU_CSCR_SPARE_6_7                                       = 6   ;
static const uint8_t P9N2_PU_CSCR_SPARE_6_7_LEN                                   = 2   ;
static const uint8_t P9N2_PU_CSCR_SRAM_SCRUB_INDEX                                = 47  ;
static const uint8_t P9N2_PU_CSCR_SRAM_SCRUB_INDEX_LEN                            = 13  ;

static const uint8_t P9N2_PU_CSDR_SRAM_DATA                                       = 0   ;
static const uint8_t P9N2_PU_CSDR_SRAM_DATA_LEN                                   = 64  ;

static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO0                        = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO1                        = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO2                        = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO3                        = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBGP                           = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBGP_LEN                       = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBSP                           = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBSP_LEN                       = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE0                          = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE0_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE1                          = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE1_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_LPCTH                           = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_LPCTH_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBM_STATE                       = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBM_STATE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_RLX                        = 28  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_RLX                        = 29  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_NVL                        = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_NVL                        = 31  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_ATS_SYNC                        = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NMMU                            = 33  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBLN                            = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBNNG                           = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBRNVG                          = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVREQ0                          = 37  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVDGD0                          = 38  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVREQ1                          = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVDGD1                          = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_ATSREQ                          = 41  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MMIO                            = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBRS                            = 43  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVRS0                           = 44  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVRS1                           = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_XARS                            = 46  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_ATRR                            = 47  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_AM_FENCED                  = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_AM_FENCED_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_AM_FENCED                  = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_AM_FENCED_LEN              = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_NTL_REQ_FENCE              = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_NTL_REQ_FENCE_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_NTL_REQ_FENCE              = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_NTL_REQ_FENCE_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBCP                           = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBCP_LEN                       = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_MISC_FENCE                 = 60  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_MISC_FENCE                 = 61  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_RESERVED                        = 62  ;
static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_RESERVED_LEN                    = 2   ;

static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO0                                  = 0   ;
static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO1                                  = 1   ;
static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO2                                  = 2   ;
static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO3                                  = 3   ;
static const uint8_t P9N2_NV_CTL_STATUS_MRBGP                                     = 4   ;
static const uint8_t P9N2_NV_CTL_STATUS_MRBGP_LEN                                 = 4   ;
static const uint8_t P9N2_NV_CTL_STATUS_MRBSP                                     = 8   ;
static const uint8_t P9N2_NV_CTL_STATUS_MRBSP_LEN                                 = 4   ;
static const uint8_t P9N2_NV_CTL_STATUS_FENCE0                                    = 12  ;
static const uint8_t P9N2_NV_CTL_STATUS_FENCE0_LEN                                = 4   ;
static const uint8_t P9N2_NV_CTL_STATUS_FENCE1                                    = 16  ;
static const uint8_t P9N2_NV_CTL_STATUS_FENCE1_LEN                                = 4   ;
static const uint8_t P9N2_NV_CTL_STATUS_LPCTH                                     = 20  ;
static const uint8_t P9N2_NV_CTL_STATUS_LPCTH_LEN                                 = 2   ;
static const uint8_t P9N2_NV_CTL_STATUS_PBM_STATE                                 = 22  ;
static const uint8_t P9N2_NV_CTL_STATUS_PBM_STATE_LEN                             = 6   ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK0_RLX                                  = 28  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK1_RLX                                  = 29  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK0_NVL                                  = 30  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK1_NVL                                  = 31  ;
static const uint8_t P9N2_NV_CTL_STATUS_ATS_SYNC                                  = 32  ;
static const uint8_t P9N2_NV_CTL_STATUS_NMMU                                      = 33  ;
static const uint8_t P9N2_NV_CTL_STATUS_PBLN                                      = 34  ;
static const uint8_t P9N2_NV_CTL_STATUS_PBNNG                                     = 35  ;
static const uint8_t P9N2_NV_CTL_STATUS_PBRNVG                                    = 36  ;
static const uint8_t P9N2_NV_CTL_STATUS_NVREQ0                                    = 37  ;
static const uint8_t P9N2_NV_CTL_STATUS_NVDGD0                                    = 38  ;
static const uint8_t P9N2_NV_CTL_STATUS_NVREQ1                                    = 39  ;
static const uint8_t P9N2_NV_CTL_STATUS_NVDGD1                                    = 40  ;
static const uint8_t P9N2_NV_CTL_STATUS_ATSREQ                                    = 41  ;
static const uint8_t P9N2_NV_CTL_STATUS_MMIO                                      = 42  ;
static const uint8_t P9N2_NV_CTL_STATUS_PBRS                                      = 43  ;
static const uint8_t P9N2_NV_CTL_STATUS_NVRS0                                     = 44  ;
static const uint8_t P9N2_NV_CTL_STATUS_NVRS1                                     = 45  ;
static const uint8_t P9N2_NV_CTL_STATUS_XARS                                      = 46  ;
static const uint8_t P9N2_NV_CTL_STATUS_ATRR                                      = 47  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK0_AM_FENCED                            = 48  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK0_AM_FENCED_LEN                        = 2   ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK1_AM_FENCED                            = 50  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK1_AM_FENCED_LEN                        = 2   ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK0_NTL_REQ_FENCE                        = 52  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK0_NTL_REQ_FENCE_LEN                    = 2   ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK1_NTL_REQ_FENCE                        = 54  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK1_NTL_REQ_FENCE_LEN                    = 2   ;
static const uint8_t P9N2_NV_CTL_STATUS_MRBCP                                     = 56  ;
static const uint8_t P9N2_NV_CTL_STATUS_MRBCP_LEN                                 = 4   ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK0_MISC_FENCE                           = 60  ;
static const uint8_t P9N2_NV_CTL_STATUS_BRK1_MISC_FENCE                           = 61  ;
static const uint8_t P9N2_NV_CTL_STATUS_RESERVED                                  = 62  ;
static const uint8_t P9N2_NV_CTL_STATUS_RESERVED_LEN                              = 2   ;

static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ENABLE                         = 0   ;
static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ID                             = 1   ;
static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ID_LEN                         = 4   ;
static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY                       = 8   ;
static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN                   = 8   ;

static const uint8_t P9N2_PEC_CTRL_PROTECT_MODE_REG_READ_ENABLE                   = 0   ;
static const uint8_t P9N2_PEC_CTRL_PROTECT_MODE_REG_WRITE_ENABLE                  = 1   ;

static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS                     = 1   ;
static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS_LEN                 = 15  ;

static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_READ_REG_DATA                        = 0   ;
static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_READ_REG_DATA_LEN                    = 64  ;

static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA                       = 0   ;
static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA_LEN                   = 64  ;

static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_ENABLE_TTYPE_DECODE           = 0   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE              = 2   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE_LEN          = 2   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_MCD_CHICKEN_SWITCH            = 6   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE                 = 7   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE_LEN             = 5   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE                      = 12  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE_LEN                  = 2   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR             = 32  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR_LEN         = 6   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR             = 40  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR_LEN         = 24  ;

static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_MODE                 = 0   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0                = 3   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0_LEN            = 9   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1                = 15  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1_LEN            = 9   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2                = 25  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2_LEN            = 11  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 45  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 3   ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE              = 48  ;
static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE_LEN          = 4   ;

static const uint8_t P9N2_CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA       = 0   ;
static const uint8_t P9N2_CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA_LEN   = 32  ;

static const uint8_t P9N2_CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER                 = 0   ;
static const uint8_t P9N2_CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER_LEN             = 48  ;

static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP                = 0   ;
static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP_LEN            = 4   ;
static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT           = 6   ;
static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT_LEN       = 6   ;
static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM             = 14  ;
static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM_LEN         = 6   ;

static const uint8_t P9N2_CAPP_CXA_TRIGCTL_PORTSEL                                = 0   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_PORTSEL_LEN                            = 4   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_APC0_ENABLE                            = 4   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_APC1_ENABLE                            = 5   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPFE_TRIGGER_ENABLE                   = 6   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPFE_DIR_TRIGGER_ENABLE               = 7   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPBE_TRIGGER_ENABLE                   = 8   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPBE_UOP_TRIGGER_ENABLE               = 9   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_TLBI_TRIGGER_SEL                       = 10  ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_XPT_TRIGGER_SEL                        = 11  ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL                       = 12  ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL_LEN                   = 4   ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL                       = 16  ;
static const uint8_t P9N2_CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL_LEN                   = 4   ;

static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF          = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX       = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV       = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD        = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS         = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL            = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS        = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00        = 7   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT = 9   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN       = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED = 13  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR           = 14  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR            = 15  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD       = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC       = 17  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE         = 18  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE         = 19  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE         = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE         = 21  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE    = 22  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE    = 23  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE    = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE    = 25  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE    = 26  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE    = 27  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE    = 28  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE    = 29  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE    = 30  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE    = 31  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE    = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE    = 33  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE       = 34  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE       = 35  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE        = 36  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE        = 37  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE        = 38  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE        = 39  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11           = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11            = 41  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12           = 42  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12            = 43  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2            = 44  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2             = 45  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR = 47  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR = 51  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW = 54  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR   = 55  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE      = 56  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE      = 57  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN   = 58  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN   = 59  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN  = 60  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN  = 61  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE       = 62  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63  ;

static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF          = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX       = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV       = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD        = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS         = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL            = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS        = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00        = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT = 9   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN       = 10  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED = 13  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR           = 14  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR            = 15  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD       = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC       = 17  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE         = 18  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE         = 19  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE         = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE         = 21  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE    = 22  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE    = 23  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE    = 24  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE    = 25  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE    = 26  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE    = 27  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE    = 28  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE    = 29  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE    = 30  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE    = 31  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE    = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE    = 33  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE       = 34  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE       = 35  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE        = 36  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE        = 37  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE        = 38  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE        = 39  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11           = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11            = 41  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12           = 42  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12            = 43  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2            = 44  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2             = 45  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR = 47  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR = 51  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW = 54  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR   = 55  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE      = 56  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE      = 57  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN   = 58  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN   = 59  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN  = 60  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN  = 61  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE       = 62  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63  ;

static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF                = 0   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX             = 1   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV             = 2   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD              = 3   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS               = 4   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL                  = 5   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS              = 6   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00              = 7   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN       = 8   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT  = 9   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN             = 10  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED  = 13  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR                 = 14  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR                  = 15  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD             = 16  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC             = 17  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE               = 18  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE               = 19  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE               = 20  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE               = 21  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE          = 22  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE          = 23  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE          = 24  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE          = 25  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE          = 26  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE          = 27  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE          = 28  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE          = 29  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE          = 30  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE          = 31  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE          = 32  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE          = 33  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE             = 34  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE             = 35  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE              = 36  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE              = 37  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE              = 38  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE              = 39  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11                 = 40  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11                  = 41  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12                 = 42  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12                  = 43  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2                  = 44  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2                   = 45  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR   = 47  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR    = 51  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW    = 54  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR         = 55  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE            = 56  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE            = 57  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN         = 58  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN         = 59  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN        = 60  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN        = 61  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE             = 62  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63  ;

static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF                = 0   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX             = 1   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV             = 2   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD              = 3   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS               = 4   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL                  = 5   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS              = 6   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00              = 7   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN       = 8   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT  = 9   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN             = 10  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED  = 13  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR                 = 14  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR                  = 15  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD             = 16  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC             = 17  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE               = 18  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE               = 19  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE               = 20  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE               = 21  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE          = 22  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE          = 23  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE          = 24  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE          = 25  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE          = 26  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE          = 27  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE          = 28  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE          = 29  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE          = 30  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE          = 31  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE          = 32  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE          = 33  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE             = 34  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE             = 35  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE              = 36  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE              = 37  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE              = 38  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE              = 39  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11                 = 40  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11                  = 41  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12                 = 42  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12                  = 43  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2                  = 44  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2                   = 45  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR   = 47  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR    = 51  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW    = 54  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR         = 55  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE            = 56  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE            = 57  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN         = 58  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN         = 59  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN        = 60  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN        = 61  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE             = 62  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63  ;

static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE00                  = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE01                  = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE02                  = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE03                  = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE04                  = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE05                  = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE06                  = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE07                  = 7   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE08                  = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE09                  = 9   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE10                  = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE11                  = 11  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE12                  = 12  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE13                  = 13  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE14                  = 14  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE15                  = 15  ;

static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE00                        = 0   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE01                        = 1   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE02                        = 2   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE03                        = 3   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE04                        = 4   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE05                        = 5   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE06                        = 6   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE07                        = 7   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE08                        = 8   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE09                        = 9   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE10                        = 10  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE11                        = 11  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE12                        = 12  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE13                        = 13  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE14                        = 14  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE15                        = 15  ;

static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE00                        = 0   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE01                        = 1   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE02                        = 2   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE03                        = 3   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE04                        = 4   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE05                        = 5   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE06                        = 6   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE07                        = 7   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE08                        = 8   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE09                        = 9   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE10                        = 10  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE11                        = 11  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE12                        = 12  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE13                        = 13  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE14                        = 14  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE15                        = 15  ;

static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE00                  = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE01                  = 1   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE02                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE03                  = 3   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE04                  = 4   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE05                  = 5   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE06                  = 6   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE07                  = 7   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE08                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE09                  = 9   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE10                  = 10  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE11                  = 11  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE12                  = 12  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE13                  = 13  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE14                  = 14  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE15                  = 15  ;

static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK000                  = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK001                  = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK002                  = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK003                  = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK004                  = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK005                  = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK006                  = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK007                  = 7   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK008                  = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK009                  = 9   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK010                  = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK011                  = 11  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK012                  = 12  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK013                  = 13  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK014                  = 14  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK015                  = 15  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK016                  = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK017                  = 17  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK018                  = 18  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK019                  = 19  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK020                  = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK021                  = 21  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK022                  = 22  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK023                  = 23  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK024                  = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK025                  = 25  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK026                  = 26  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK027                  = 27  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK028                  = 28  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK029                  = 29  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK030                  = 30  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK031                  = 31  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK032                  = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK033                  = 33  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK034                  = 34  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK035                  = 35  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK036                  = 36  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK037                  = 37  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK038                  = 38  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK039                  = 39  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK040                  = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK041                  = 41  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK042                  = 42  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK043                  = 43  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK044                  = 44  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK045                  = 45  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK046                  = 46  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK047                  = 47  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK048                  = 48  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK049                  = 49  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK050                  = 50  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK051                  = 51  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK052                  = 52  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK053                  = 53  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK054                  = 54  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK055                  = 55  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK056                  = 56  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK057                  = 57  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK058                  = 58  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK059                  = 59  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK060                  = 60  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK061                  = 61  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK062                  = 62  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK063                  = 63  ;

static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK000                  = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK001                  = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK002                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK003                  = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK004                  = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK005                  = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK006                  = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK007                  = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK008                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK009                  = 9   ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK010                  = 10  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK011                  = 11  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK012                  = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK013                  = 13  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK014                  = 14  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK015                  = 15  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK016                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK017                  = 17  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK018                  = 18  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK019                  = 19  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK020                  = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK021                  = 21  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK022                  = 22  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK023                  = 23  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK024                  = 24  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK025                  = 25  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK026                  = 26  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK027                  = 27  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK028                  = 28  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK029                  = 29  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK030                  = 30  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK031                  = 31  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK032                  = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK033                  = 33  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK034                  = 34  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK035                  = 35  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK036                  = 36  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK037                  = 37  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK038                  = 38  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK039                  = 39  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK040                  = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK041                  = 41  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK042                  = 42  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK043                  = 43  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK044                  = 44  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK045                  = 45  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK046                  = 46  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK047                  = 47  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK048                  = 48  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK049                  = 49  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK050                  = 50  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK051                  = 51  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK052                  = 52  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK053                  = 53  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK054                  = 54  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK055                  = 55  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK056                  = 56  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK057                  = 57  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK058                  = 58  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK059                  = 59  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK060                  = 60  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK061                  = 61  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK062                  = 62  ;
static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK063                  = 63  ;

static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK000                        = 0   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK001                        = 1   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK002                        = 2   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK003                        = 3   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK004                        = 4   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK005                        = 5   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK006                        = 6   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK007                        = 7   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK008                        = 8   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK009                        = 9   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK010                        = 10  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK011                        = 11  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK012                        = 12  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK013                        = 13  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK014                        = 14  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK015                        = 15  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK016                        = 16  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK017                        = 17  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK018                        = 18  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK019                        = 19  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK020                        = 20  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK021                        = 21  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK022                        = 22  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK023                        = 23  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK024                        = 24  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK025                        = 25  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK026                        = 26  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK027                        = 27  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK028                        = 28  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK029                        = 29  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK030                        = 30  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK031                        = 31  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK032                        = 32  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK033                        = 33  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK034                        = 34  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK035                        = 35  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK036                        = 36  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK037                        = 37  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK038                        = 38  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK039                        = 39  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK040                        = 40  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK041                        = 41  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK042                        = 42  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK043                        = 43  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK044                        = 44  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK045                        = 45  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK046                        = 46  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK047                        = 47  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK048                        = 48  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK049                        = 49  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK050                        = 50  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK051                        = 51  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK052                        = 52  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK053                        = 53  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK054                        = 54  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK055                        = 55  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK056                        = 56  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK057                        = 57  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK058                        = 58  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK059                        = 59  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK060                        = 60  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK061                        = 61  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK062                        = 62  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK063                        = 63  ;

static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK000                        = 0   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK001                        = 1   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK002                        = 2   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK003                        = 3   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK004                        = 4   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK005                        = 5   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK006                        = 6   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK007                        = 7   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK008                        = 8   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK009                        = 9   ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK010                        = 10  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK011                        = 11  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK012                        = 12  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK013                        = 13  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK014                        = 14  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK015                        = 15  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK016                        = 16  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK017                        = 17  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK018                        = 18  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK019                        = 19  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK020                        = 20  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK021                        = 21  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK022                        = 22  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK023                        = 23  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK024                        = 24  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK025                        = 25  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK026                        = 26  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK027                        = 27  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK028                        = 28  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK029                        = 29  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK030                        = 30  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK031                        = 31  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK032                        = 32  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK033                        = 33  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK034                        = 34  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK035                        = 35  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK036                        = 36  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK037                        = 37  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK038                        = 38  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK039                        = 39  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK040                        = 40  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK041                        = 41  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK042                        = 42  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK043                        = 43  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK044                        = 44  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK045                        = 45  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK046                        = 46  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK047                        = 47  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK048                        = 48  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK049                        = 49  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK050                        = 50  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK051                        = 51  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK052                        = 52  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK053                        = 53  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK054                        = 54  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK055                        = 55  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK056                        = 56  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK057                        = 57  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK058                        = 58  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK059                        = 59  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK060                        = 60  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK061                        = 61  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK062                        = 62  ;
static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK063                        = 63  ;

static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK100                  = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK101                  = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK102                  = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK103                  = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK104                  = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK105                  = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK106                  = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK107                  = 7   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK108                  = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK109                  = 9   ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK110                  = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK111                  = 11  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK112                  = 12  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK113                  = 13  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK114                  = 14  ;
static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK115                  = 15  ;

static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK100                        = 0   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK101                        = 1   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK102                        = 2   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK103                        = 3   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK104                        = 4   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK105                        = 5   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK106                        = 6   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK107                        = 7   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK108                        = 8   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK109                        = 9   ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK110                        = 10  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK111                        = 11  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK112                        = 12  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK113                        = 13  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK114                        = 14  ;
static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK115                        = 15  ;

static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK100                        = 0   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK101                        = 1   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK102                        = 2   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK103                        = 3   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK104                        = 4   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK105                        = 5   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK106                        = 6   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK107                        = 7   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK108                        = 8   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK109                        = 9   ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK110                        = 10  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK111                        = 11  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK112                        = 12  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK113                        = 13  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK114                        = 14  ;
static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK115                        = 15  ;

static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK100                  = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK101                  = 1   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK102                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK103                  = 3   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK104                  = 4   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK105                  = 5   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK106                  = 6   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK107                  = 7   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK108                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK109                  = 9   ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK110                  = 10  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK111                  = 11  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK112                  = 12  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK113                  = 13  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK114                  = 14  ;
static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK115                  = 15  ;

static const uint8_t P9N2_PU_DATA0TO7_REGISTER_B_PIB_0                            = 0   ;
static const uint8_t P9N2_PU_DATA0TO7_REGISTER_B_PIB_0_LEN                        = 64  ;

static const uint8_t P9N2_PU_DATA0TO7_REGISTER_C_PIB_1                            = 0   ;
static const uint8_t P9N2_PU_DATA0TO7_REGISTER_C_PIB_1_LEN                        = 64  ;

static const uint8_t P9N2_PU_DATA0TO7_REGISTER_D_PIB_2                            = 0   ;
static const uint8_t P9N2_PU_DATA0TO7_REGISTER_D_PIB_2_LEN                        = 64  ;

static const uint8_t P9N2_PU_DATA0TO7_REGISTER_E_PIB_3                            = 0   ;
static const uint8_t P9N2_PU_DATA0TO7_REGISTER_E_PIB_3_LEN                        = 64  ;

static const uint8_t P9N2_PU_DATA8TO15_REGISTER_B_PIB_0                           = 0   ;
static const uint8_t P9N2_PU_DATA8TO15_REGISTER_B_PIB_0_LEN                       = 64  ;

static const uint8_t P9N2_PU_DATA8TO15_REGISTER_C_PIB_1                           = 0   ;
static const uint8_t P9N2_PU_DATA8TO15_REGISTER_C_PIB_1_LEN                       = 64  ;

static const uint8_t P9N2_PU_DATA8TO15_REGISTER_D_PIB_2                           = 0   ;
static const uint8_t P9N2_PU_DATA8TO15_REGISTER_D_PIB_2_LEN                       = 64  ;

static const uint8_t P9N2_PU_DATA8TO15_REGISTER_E_PIB_3                           = 0   ;
static const uint8_t P9N2_PU_DATA8TO15_REGISTER_E_PIB_3_LEN                       = 64  ;

static const uint8_t P9N2_PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION                 = 0   ;
static const uint8_t P9N2_PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION_LEN             = 64  ;

static const uint8_t P9N2_PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION                 = 0   ;
static const uint8_t P9N2_PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION_LEN             = 64  ;

static const uint8_t P9N2_PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION                 = 0   ;
static const uint8_t P9N2_PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION_LEN             = 64  ;

static const uint8_t P9N2_PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION                 = 0   ;
static const uint8_t P9N2_PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION_LEN             = 64  ;

static const uint8_t P9N2_PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION                 = 0   ;
static const uint8_t P9N2_PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION_LEN             = 64  ;

static const uint8_t P9N2_PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION                 = 0   ;
static const uint8_t P9N2_PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION_LEN             = 64  ;

static const uint8_t P9N2_PU_DATA_REGISTER_OTP                                    = 0   ;
static const uint8_t P9N2_PU_DATA_REGISTER_OTP_LEN                                = 64  ;

static const uint8_t P9N2__CTL_DA_ADDR_MISC                                       = 0   ;
static const uint8_t P9N2__CTL_DA_ADDR_MISC_LEN                                   = 24  ;
static const uint8_t P9N2__CTL_DA_ADDR_MISC_LENGTH                                = 24  ;
static const uint8_t P9N2__CTL_DA_ADDR_MISC_LENGTH_LEN                            = 2   ;
static const uint8_t P9N2__CTL_DA_ADDR_MISC_RSVD                                  = 26  ;
static const uint8_t P9N2__CTL_DA_ADDR_MISC_RSVD_LEN                              = 38  ;

static const uint8_t P9N2_PEC_DBG_CBS_CC_RESET_EP                                 = 0   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_OPCG_IP                                  = 1   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_VITL_CLKOFF                              = 2   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_TEST_ENABLE                              = 3   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_REQ                                      = 4   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_CMD                                      = 5   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_CMD_LEN                                  = 3   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_STATE                                    = 8   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_STATE_LEN                                = 5   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_SECURITY_DEBUG_MODE                      = 13  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_PROTOCOL_ERROR                           = 14  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_PCB_IDLE                                 = 15  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_CURRENT_OPCG_MODE                        = 16  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_LAST_OPCG_MODE                           = 20  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_LAST_OPCG_MODE_LEN                       = 4   ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_PCB_ERROR                                = 24  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_PARITY_ERROR                             = 25  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_ERROR                                    = 26  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_CHIPLET_IS_ALIGNED                       = 27  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET                  = 28  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE              = 29  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE              = 30  ;
static const uint8_t P9N2_PEC_DBG_CBS_CC_TP_TPFSI_ACK                             = 31  ;

static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_A                    = 0   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_B                    = 8   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_A                    = 16  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_B                    = 24  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C1_INAROW_MODE                 = 32  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1              = 33  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1              = 34  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1             = 35  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED                         = 36  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED_LEN                     = 3   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C2_INAROW_MODE                 = 39  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2              = 40  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2              = 41  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2             = 42  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED_2                       = 43  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED_2_LEN                   = 3   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET             = 46  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EXACT_TO_MODE                  = 47  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1            = 48  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C3_ON_C0                 = 49  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_SLOW_TO_MODE                   = 50  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO           = 51  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT                    = 52  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN                = 4   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT                    = 56  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN                = 4   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT                = 60  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN            = 3   ;

static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A        = 0   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN    = 5   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B        = 5   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN    = 5   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A          = 10  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN      = 5   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B          = 15  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN      = 5   ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_TO_CMP_LT                      = 20  ;
static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                  = 24  ;

static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_A                    = 0   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_B                    = 8   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_A                    = 16  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_B                    = 24  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN                = 8   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C1_INAROW_MODE                 = 32  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1              = 33  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1              = 34  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1             = 35  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED                         = 36  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED_LEN                     = 3   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C2_INAROW_MODE                 = 39  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2              = 40  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2              = 41  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2             = 42  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED_2                       = 43  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED_2_LEN                   = 3   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET             = 46  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EXACT_TO_MODE                  = 47  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1            = 48  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C3_ON_C0                 = 49  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_SLOW_TO_MODE                   = 50  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO           = 51  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT                    = 52  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN                = 4   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT                    = 56  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN                = 4   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT                = 60  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN            = 3   ;

static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A                  = 0   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B                  = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A                  = 16  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B                  = 24  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C1_INAROW_MODE               = 32  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            = 33  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            = 34  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           = 35  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED                       = 36  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED_LEN                   = 3   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C2_INAROW_MODE               = 39  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            = 40  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            = 41  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           = 42  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED_2                     = 43  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 = 3   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           = 46  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EXACT_TO_MODE                = 47  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          = 48  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               = 49  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 = 50  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         = 51  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT                  = 52  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT                  = 56  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              = 4   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT              = 60  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          = 3   ;

static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A        = 0   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN    = 5   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B        = 5   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN    = 5   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A          = 10  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN      = 5   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B          = 15  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN      = 5   ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_TO_CMP_LT                      = 20  ;
static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                  = 24  ;

static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      = 0   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        = 10  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        = 15  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    = 5   ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT                    = 20  ;
static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                = 24  ;

static const uint8_t P9N2_PU_N3_DBG_MODE_REG_GLB_BRCST                            = 0   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_GLB_BRCST_LEN                        = 3   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRACE_SEL                            = 3   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRACE_SEL_LEN                        = 3   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRIG_SEL                             = 6   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRIG_SEL_LEN                         = 2   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              = 8   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          = 9   ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             = 10  ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_FREEZE_SEL                           = 11  ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_SYNC_BRCST                           = 12  ;
static const uint8_t P9N2_PU_N3_DBG_MODE_REG_SYNC_BRCST_LEN                       = 2   ;

static const uint8_t P9N2_PU_N1_DBG_MODE_REG_GLB_BRCST                            = 0   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_GLB_BRCST_LEN                        = 3   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRACE_SEL                            = 3   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRACE_SEL_LEN                        = 3   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRIG_SEL                             = 6   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRIG_SEL_LEN                         = 2   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              = 8   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          = 9   ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             = 10  ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_FREEZE_SEL                           = 11  ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_SYNC_BRCST                           = 12  ;
static const uint8_t P9N2_PU_N1_DBG_MODE_REG_SYNC_BRCST_LEN                       = 2   ;

static const uint8_t P9N2_PU_N2_DBG_MODE_REG_GLB_BRCST                            = 0   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_GLB_BRCST_LEN                        = 3   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRACE_SEL                            = 3   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRACE_SEL_LEN                        = 3   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRIG_SEL                             = 6   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRIG_SEL_LEN                         = 2   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              = 8   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          = 9   ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             = 10  ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_FREEZE_SEL                           = 11  ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_SYNC_BRCST                           = 12  ;
static const uint8_t P9N2_PU_N2_DBG_MODE_REG_SYNC_BRCST_LEN                       = 2   ;

static const uint8_t P9N2_PEC_DBG_MODE_REG_GLB_BRCST                              = 0   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_GLB_BRCST_LEN                          = 3   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_TRACE_SEL                              = 3   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_TRACE_SEL_LEN                          = 3   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_TRIG_SEL                               = 6   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_TRIG_SEL_LEN                           = 2   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION                = 8   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION            = 9   ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION               = 10  ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_FREEZE_SEL                             = 11  ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_SYNC_BRCST                             = 12  ;
static const uint8_t P9N2_PEC_DBG_MODE_REG_SYNC_BRCST_LEN                         = 2   ;

static const uint8_t P9N2_PU_N0_DBG_MODE_REG_GLB_BRCST                            = 0   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_GLB_BRCST_LEN                        = 3   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRACE_SEL                            = 3   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRACE_SEL_LEN                        = 3   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRIG_SEL                             = 6   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRIG_SEL_LEN                         = 2   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              = 8   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          = 9   ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             = 10  ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_FREEZE_SEL                           = 11  ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_SYNC_BRCST                           = 12  ;
static const uint8_t P9N2_PU_N0_DBG_MODE_REG_SYNC_BRCST_LEN                       = 2   ;

static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     = 0   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   = 16  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  = 17  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           = 18  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_FORCE_TEST                   = 19  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   = 20  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             = 21  ;

static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     = 0   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   = 16  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  = 17  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           = 18  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_FORCE_TEST                   = 19  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   = 20  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             = 21  ;

static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     = 0   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   = 16  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  = 17  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           = 18  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_FORCE_TEST                   = 19  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   = 20  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             = 21  ;

static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE       = 0   ;
static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN   = 16  ;
static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_IMM_FREEZE                     = 16  ;
static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                    = 17  ;
static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH             = 18  ;
static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_FORCE_TEST                     = 19  ;
static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_ACCUM_HIST                     = 20  ;
static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ               = 21  ;

static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     = 0   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   = 16  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  = 17  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           = 18  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_FORCE_TEST                   = 19  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   = 20  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             = 21  ;

static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_COND3_ENABLE                = 0   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_COND3_ENABLE                = 1   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST3_COND3_ENABLE                = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST4_COND3_ENABLE                = 3   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              = 4   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              = 5   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              = 6   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              = 7   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         = 8   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         = 10  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         = 12  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         = 14  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         = 16  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         = 18  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  = 32  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                = 33  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                = 34  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                = 39  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    = 44  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_ARM_SEL                           = 46  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_ARM_SEL_LEN                       = 4   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   = 50  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               = 4   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   = 54  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               = 4   ;

static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_COND3_ENABLE                = 0   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_COND3_ENABLE                = 1   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST3_COND3_ENABLE                = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST4_COND3_ENABLE                = 3   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              = 4   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              = 5   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              = 6   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              = 7   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         = 8   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         = 10  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         = 12  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         = 14  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         = 16  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         = 18  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  = 32  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                = 33  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                = 34  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                = 39  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    = 44  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_ARM_SEL                           = 46  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_ARM_SEL_LEN                       = 4   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   = 50  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               = 4   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   = 54  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               = 4   ;

static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_COND3_ENABLE                = 0   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_COND3_ENABLE                = 1   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST3_COND3_ENABLE                = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST4_COND3_ENABLE                = 3   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              = 4   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              = 5   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              = 6   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              = 7   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         = 8   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         = 10  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         = 12  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         = 14  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         = 16  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         = 18  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  = 32  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                = 33  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                = 34  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                = 39  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    = 44  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_ARM_SEL                           = 46  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_ARM_SEL_LEN                       = 4   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   = 50  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               = 4   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   = 54  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               = 4   ;

static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_COND3_ENABLE                  = 0   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_COND3_ENABLE                  = 1   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST3_COND3_ENABLE                  = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST4_COND3_ENABLE                  = 3   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE                = 4   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE                = 5   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE                = 6   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE                = 7   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL           = 8   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN       = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL           = 10  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN       = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL           = 12  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN       = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL           = 14  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN       = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL           = 16  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN       = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL           = 18  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN       = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                    = 32  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                  = 33  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                  = 34  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN              = 5   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                  = 39  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN              = 5   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                      = 44  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_ARM_SEL                             = 46  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_ARM_SEL_LEN                         = 4   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                     = 50  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN                 = 4   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                     = 54  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN                 = 4   ;

static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_COND3_ENABLE                = 0   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_COND3_ENABLE                = 1   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST3_COND3_ENABLE                = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST4_COND3_ENABLE                = 3   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              = 4   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              = 5   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              = 6   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              = 7   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         = 8   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         = 10  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         = 12  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         = 14  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         = 16  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         = 18  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  = 32  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                = 33  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                = 34  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                = 39  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            = 5   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    = 44  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_ARM_SEL                           = 46  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_ARM_SEL_LEN                       = 4   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   = 50  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               = 4   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   = 54  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               = 4   ;

static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        = 0   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        = 4   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        = 6   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        = 8   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        = 10  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     = 24  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     = 25  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     = 26  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     = 27  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     = 28  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     = 29  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      = 36  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      = 37  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      = 38  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      = 39  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      = 40  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      = 41  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           = 48  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     = 51  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           = 52  ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     = 55  ;

static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        = 0   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        = 4   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        = 6   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        = 8   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        = 10  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     = 24  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     = 25  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     = 26  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     = 27  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     = 28  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     = 29  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      = 36  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      = 37  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      = 38  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      = 39  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      = 40  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      = 41  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           = 48  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     = 51  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           = 52  ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     = 55  ;

static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        = 0   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        = 4   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        = 6   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        = 8   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        = 10  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     = 24  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     = 25  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     = 26  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     = 27  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     = 28  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     = 29  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      = 36  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      = 37  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      = 38  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      = 39  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      = 40  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      = 41  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           = 48  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     = 51  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           = 52  ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     = 55  ;

static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO          = 0   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN      = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO          = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN      = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO          = 4   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN      = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO          = 6   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN      = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO          = 8   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN      = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO          = 10  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN      = 2   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN       = 24  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN       = 25  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN       = 26  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN       = 27  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN       = 28  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN       = 29  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK        = 36  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK        = 37  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK        = 38  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK        = 39  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK        = 40  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK        = 41  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT             = 48  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN         = 3   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR       = 51  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT             = 52  ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN         = 3   ;
static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR       = 55  ;

static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        = 0   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        = 4   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        = 6   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        = 8   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        = 10  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    = 2   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     = 24  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     = 25  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     = 26  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     = 27  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     = 28  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     = 29  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      = 36  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      = 37  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      = 38  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      = 39  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      = 40  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      = 41  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           = 48  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     = 51  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           = 52  ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       = 3   ;
static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     = 55  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD0                                 = 0   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD0_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD1                                 = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD1_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD2                                 = 10  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD2_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD3                                 = 15  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD3_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD4                                 = 20  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD4_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD5                                 = 25  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD5_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD6                                 = 30  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD6_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD7                                 = 35  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD7_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD8                                 = 40  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD8_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD9                                 = 45  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD9_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD10                                = 50  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD10_LEN                            = 5   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_RESERVED1                            = 55  ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_RESERVED1_LEN                        = 8   ;
static const uint8_t P9N2__SM2_DEBUG0_CONFIG_ACT                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD0                                 = 0   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD0_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD1                                 = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD1_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD2                                 = 10  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD2_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD3                                 = 15  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD3_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD4                                 = 20  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD4_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD5                                 = 25  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD5_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD6                                 = 30  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD6_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD7                                 = 35  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD7_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD8                                 = 40  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD8_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD9                                 = 45  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD9_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD10                                = 50  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD10_LEN                            = 5   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_RESERVED1                            = 55  ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_RESERVED1_LEN                        = 8   ;
static const uint8_t P9N2__SM1_DEBUG0_CONFIG_ACT                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD0                         = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD0_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD1                         = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD2                         = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD3                         = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD3_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD4                         = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD4_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD5                         = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD5_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD6                         = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD6_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD7                         = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD7_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD8                         = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD8_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD9                         = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD9_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD10                        = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD10_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1                    = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_ACT                          = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD0                                 = 0   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD0_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD1                                 = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD1_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD2                                 = 10  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD2_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD3                                 = 15  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD3_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD4                                 = 20  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD4_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD5                                 = 25  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD5_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD6                                 = 30  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD6_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD7                                 = 35  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD7_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD8                                 = 40  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD8_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD9                                 = 45  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD9_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD10                                = 50  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD10_LEN                            = 5   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_RESERVED1                            = 55  ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_RESERVED1_LEN                        = 8   ;
static const uint8_t P9N2__SM0_DEBUG0_CONFIG_ACT                                  = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD0                           = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD0_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD1                           = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD1_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD2                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD2_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD3                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD3_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD4                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD4_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD5                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD5_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD6                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD6_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD7                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD7_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD8                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD8_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD9                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD9_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD10                          = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD10_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_RESERVED1                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_RESERVED1_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_ACT                            = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD0                           = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD0_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD1                           = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD1_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD2                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD2_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD3                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD3_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD4                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD4_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD5                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD5_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD6                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD6_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD7                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD7_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD8                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD8_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD9                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD9_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD10                          = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD10_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_RESERVED1                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_RESERVED1_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_ACT                            = 63  ;

static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD0                                   = 0   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD0_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD1                                   = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD1_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD2                                   = 10  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD2_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD3                                   = 15  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD3_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD4                                   = 20  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD4_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD5                                   = 25  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD5_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD6                                   = 30  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD6_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD7                                   = 35  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD7_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD8                                   = 40  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD8_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD9                                   = 45  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD9_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD10                                  = 50  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD10_LEN                              = 5   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_RESERVED1                              = 55  ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_RESERVED1_LEN                          = 8   ;
static const uint8_t P9N2_NV_DEBUG0_CONFIG_ACT                                    = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD0                                 = 0   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD0_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD1                                 = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD1_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD2                                 = 10  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD2_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD3                                 = 15  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD3_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD4                                 = 20  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD4_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD5                                 = 25  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD5_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD6                                 = 30  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD6_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD7                                 = 35  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD7_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD8                                 = 40  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD8_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD9                                 = 45  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD9_LEN                             = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD10                                = 50  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD10_LEN                            = 5   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_RESERVED1                            = 55  ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_RESERVED1_LEN                        = 8   ;
static const uint8_t P9N2__SM2_DEBUG1_CONFIG_ACT                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD0                                 = 0   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD0_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD1                                 = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD1_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD2                                 = 10  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD2_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD3                                 = 15  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD3_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD4                                 = 20  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD4_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD5                                 = 25  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD5_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD6                                 = 30  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD6_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD7                                 = 35  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD7_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD8                                 = 40  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD8_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD9                                 = 45  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD9_LEN                             = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD10                                = 50  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD10_LEN                            = 5   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_RESERVED1                            = 55  ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_RESERVED1_LEN                        = 8   ;
static const uint8_t P9N2__SM1_DEBUG1_CONFIG_ACT                                  = 63  ;

static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD0                         = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD0_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD1                         = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD2                         = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD3                         = 15  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD3_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD4                         = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD4_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD5                         = 25  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD5_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD6                         = 30  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD6_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD7                         = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD7_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD8                         = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD8_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD9                         = 45  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD9_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD10                        = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD10_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1                    = 55  ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_ACT                          = 63  ;

static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD0                                 = 0   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD0_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD1                                 = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD1_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD2                                 = 10  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD2_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD3                                 = 15  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD3_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD4                                 = 20  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD4_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD5                                 = 25  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD5_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD6                                 = 30  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD6_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD7                                 = 35  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD7_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD8                                 = 40  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD8_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD9                                 = 45  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD9_LEN                             = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD10                                = 50  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD10_LEN                            = 5   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_RESERVED1                            = 55  ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_RESERVED1_LEN                        = 8   ;
static const uint8_t P9N2__SM0_DEBUG1_CONFIG_ACT                                  = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD0                           = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD0_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD1                           = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD1_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD2                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD2_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD3                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD3_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD4                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD4_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD5                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD5_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD6                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD6_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD7                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD7_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD8                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD8_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD9                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD9_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD10                          = 50  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD10_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_RESERVED1                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_RESERVED1_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_ACT                            = 63  ;

static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD0                           = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD0_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD1                           = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD1_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD2                           = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD2_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD3                           = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD3_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD4                           = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD4_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD5                           = 25  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD5_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD6                           = 30  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD6_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD7                           = 35  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD7_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD8                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD8_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD9                           = 45  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD9_LEN                       = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD10                          = 50  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD10_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_RESERVED1                      = 55  ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_RESERVED1_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_ACT                            = 63  ;

static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD0                                   = 0   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD0_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD1                                   = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD1_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD2                                   = 10  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD2_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD3                                   = 15  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD3_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD4                                   = 20  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD4_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD5                                   = 25  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD5_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD6                                   = 30  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD6_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD7                                   = 35  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD7_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD8                                   = 40  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD8_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD9                                   = 45  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD9_LEN                               = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD10                                  = 50  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD10_LEN                              = 5   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_RESERVED1                              = 55  ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_RESERVED1_LEN                          = 8   ;
static const uint8_t P9N2_NV_DEBUG1_CONFIG_ACT                                    = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD0                          = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD0_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD1                          = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD1_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD2                          = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD2_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD3                          = 15  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD3_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD4                          = 20  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD4_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD5                          = 25  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD5_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD6                          = 30  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD6_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD7                          = 35  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD7_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD8                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD8_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD9                          = 45  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD9_LEN                      = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD10                         = 50  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD10_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1                     = 55  ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_ACT                           = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD0                       = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD0_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD1                       = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD1_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD2                       = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD2_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD3                       = 15  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD3_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD4                       = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD4_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD5                       = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD5_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD6                       = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD6_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD7                       = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD7_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD8                       = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD8_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD9                       = 45  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD9_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD10                      = 50  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD10_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_RESERVED1                  = 55  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_RESERVED1_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_ACT                        = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2           = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN       = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2           = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN       = 6   ;

static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2           = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN       = 6   ;

static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0           = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2           = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3           = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5           = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6           = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7           = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8           = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9           = 54  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN       = 6   ;

static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0              = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1              = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2              = 12  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3              = 18  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4              = 24  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5              = 30  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6              = 36  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7              = 42  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8              = 48  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9              = 54  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN          = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1       = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_ACT             = 43  ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1       = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_ACT             = 43  ;

static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1       = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_ACT             = 43  ;

static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13          = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14          = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1       = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_ACT             = 43  ;

static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10             = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11             = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12             = 12  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13             = 18  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14             = 24  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15             = 30  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16             = 36  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1          = 42  ;
static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_ACT                = 43  ;

static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE0                        = 0   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE0_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE1                        = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE1_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE2                        = 4   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE2_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE3                        = 6   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE3_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE4                        = 8   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE4_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE5                        = 10  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE5_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE6                        = 12  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE6_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE7                        = 14  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE7_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE8                        = 16  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE8_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE9                        = 18  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE9_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE10                       = 20  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE10_LEN                   = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE0                        = 22  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE0_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE1                        = 24  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE1_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE2                        = 26  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE2_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE3                        = 28  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE3_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE4                        = 30  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE4_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE5                        = 32  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE5_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE6                        = 34  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE6_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE7                        = 36  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE7_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE8                        = 38  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE8_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE9                        = 40  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE9_LEN                    = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE10                       = 42  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE10_LEN                   = 2   ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_RESERVED                              = 44  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_RESERVED_LEN                          = 19  ;
static const uint8_t P9N2__CTL_DEBUG_CONFIG_ACT                                   = 63  ;

static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL                   = 0   ;
static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL_LEN               = 4   ;
static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_SEL                            = 4   ;
static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN                        = 8   ;

static const uint8_t P9N2_PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_START                = 0   ;
static const uint8_t P9N2_PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP                 = 1   ;
static const uint8_t P9N2_PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET                = 2   ;

static const uint8_t P9N2_PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_START                 = 0   ;
static const uint8_t P9N2_PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP                  = 1   ;
static const uint8_t P9N2_PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET                 = 2   ;

static const uint8_t P9N2_CAPP_DFSUOP1_WORD                                       = 0   ;
static const uint8_t P9N2_CAPP_DFSUOP1_WORD_LEN                                   = 56  ;

static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_REG                           = 0   ;
static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_REG_LEN                       = 30  ;
static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_RESERVED                      = 30  ;
static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_RESERVED_LEN                  = 12  ;

static const uint8_t P9N2__SM1_DMA_SYNC_START_READ                                = 0   ;
static const uint8_t P9N2__SM1_DMA_SYNC_READ_COMPLETE                             = 1   ;
static const uint8_t P9N2__SM1_DMA_SYNC_START_WRITE                               = 2   ;
static const uint8_t P9N2__SM1_DMA_SYNC_WRITE_COMPLETE                            = 3   ;

static const uint8_t P9N2_PU_DMA_UP_ADDR_BASE_UPPER_BITS                          = 0   ;
static const uint8_t P9N2_PU_DMA_UP_ADDR_BASE_UPPER_BITS_LEN                      = 8   ;
static const uint8_t P9N2_PU_DMA_UP_ADDR_ESCAPE_ADDRESS                           = 16  ;
static const uint8_t P9N2_PU_DMA_UP_ADDR_ESCAPE_ADDRESS_LEN                       = 48  ;

static const uint8_t P9N2_PU_DMA_VAS_MMIO_BAR_BAR                                 = 8   ;
static const uint8_t P9N2_PU_DMA_VAS_MMIO_BAR_BAR_LEN                             = 31  ;

static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK                   = 0   ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK_LEN               = 6   ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_ENABLE_CTAG_DROP_PRIORITY          = 6   ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_ENABLE_IO_CMD_PACING               = 7   ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACECOUNT                      = 8   ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACECOUNT_LEN                  = 9   ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACEINC                        = 17  ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACEINC_LEN                    = 6   ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER                     = 23  ;
static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER_LEN                 = 3   ;

static const uint8_t P9N2_PEC_DTS_RESULT0_0_RESULT                                = 0   ;
static const uint8_t P9N2_PEC_DTS_RESULT0_0_RESULT_LEN                            = 16  ;
static const uint8_t P9N2_PEC_DTS_RESULT0_1_RESULT                                = 16  ;
static const uint8_t P9N2_PEC_DTS_RESULT0_1_RESULT_LEN                            = 16  ;

static const uint8_t P9N2_PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE              = 0   ;
static const uint8_t P9N2_PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN          = 44  ;
static const uint8_t P9N2_PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR       = 44  ;
static const uint8_t P9N2_PEC_DTS_TRC_RESULT_1                                    = 48  ;
static const uint8_t P9N2_PEC_DTS_TRC_RESULT_1_LEN                                = 16  ;

static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_PBTX_AMO_IGNORE_XUE             = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_BR_PERR                 = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_IR_PERR                 = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_OR_PERR                 = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_PT                     = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_PR                     = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_BR                     = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_IR                     = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_OR                     = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_PT                      = 9   ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_PR                      = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_BR                      = 11  ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_IR                      = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_OR                      = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_RESERVED                        = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_RESERVED_LEN                    = 18  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART0_REGISTER_PART_0                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART0_REGISTER_PART_0_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART0_REGISTER_PART_0                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART0_REGISTER_PART_0_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART10_REGISTER_PART_10                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART10_REGISTER_PART_10_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART10_REGISTER_PART_10                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART10_REGISTER_PART_10_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART11_REGISTER_PART_11                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART11_REGISTER_PART_11_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART11_REGISTER_PART_11                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART11_REGISTER_PART_11_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART12_REGISTER_PART_12                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART12_REGISTER_PART_12_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART12_REGISTER_PART_12                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART12_REGISTER_PART_12_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART13_REGISTER_PART_13                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART13_REGISTER_PART_13_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART13_REGISTER_PART_13                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART13_REGISTER_PART_13_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART14_REGISTER_PART_14                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART14_REGISTER_PART_14_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART14_REGISTER_PART_14                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART14_REGISTER_PART_14_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART15_REGISTER_PART_15                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART15_REGISTER_PART_15_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART15_REGISTER_PART_15                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART15_REGISTER_PART_15_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART16_REGISTER_PART_16                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART16_REGISTER_PART_16_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART16_REGISTER_PART_16                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART16_REGISTER_PART_16_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART17_REGISTER_PART_17                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART17_REGISTER_PART_17_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART17_REGISTER_PART_17                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART17_REGISTER_PART_17_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART18_REGISTER_PART_18                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART18_REGISTER_PART_18_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART18_REGISTER_PART_18                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART18_REGISTER_PART_18_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART19_REGISTER_PART_19                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART19_REGISTER_PART_19_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART19_REGISTER_PART_19                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART19_REGISTER_PART_19_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART1_REGISTER_PART_1                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART1_REGISTER_PART_1_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART1_REGISTER_PART_1                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART1_REGISTER_PART_1_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART20_REGISTER_PART_20                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART20_REGISTER_PART_20_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART20_REGISTER_PART_20                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART20_REGISTER_PART_20_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART21_REGISTER_PART_21                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART21_REGISTER_PART_21_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART21_REGISTER_PART_21                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART21_REGISTER_PART_21_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART22_REGISTER_PART_22                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART22_REGISTER_PART_22_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART22_REGISTER_PART_22                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART22_REGISTER_PART_22_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART23_REGISTER_PART_23                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART23_REGISTER_PART_23_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART23_REGISTER_PART_23                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART23_REGISTER_PART_23_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART24_REGISTER_PART_24                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART24_REGISTER_PART_24_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART24_REGISTER_PART_24                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART24_REGISTER_PART_24_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART25_REGISTER_PART_25                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART25_REGISTER_PART_25_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART25_REGISTER_PART_25                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART25_REGISTER_PART_25_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART26_REGISTER_PART_26                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART26_REGISTER_PART_26_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART26_REGISTER_PART_26                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART26_REGISTER_PART_26_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART27_REGISTER_PART_27                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART27_REGISTER_PART_27_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART27_REGISTER_PART_27                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART27_REGISTER_PART_27_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART28_REGISTER_PART_28                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART28_REGISTER_PART_28_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART28_REGISTER_PART_28                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART28_REGISTER_PART_28_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART29_REGISTER_PART_29                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART29_REGISTER_PART_29_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART29_REGISTER_PART_29                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART29_REGISTER_PART_29_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART2_REGISTER_PART_2                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART2_REGISTER_PART_2_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART2_REGISTER_PART_2                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART2_REGISTER_PART_2_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART30_REGISTER_PART_30                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART30_REGISTER_PART_30_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART30_REGISTER_PART_30                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART30_REGISTER_PART_30_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART31_REGISTER_PART_31                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART31_REGISTER_PART_31_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART31_REGISTER_PART_31                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART31_REGISTER_PART_31_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART32_REGISTER_PART_32                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART32_REGISTER_PART_32_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART32_REGISTER_PART_32                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART32_REGISTER_PART_32_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART33_REGISTER_PART_33                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART33_REGISTER_PART_33_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART33_REGISTER_PART_33                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART33_REGISTER_PART_33_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART34_REGISTER_PART_34                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART34_REGISTER_PART_34_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART34_REGISTER_PART_34                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART34_REGISTER_PART_34_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART35_REGISTER_PART_35                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART35_REGISTER_PART_35_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART35_REGISTER_PART_35                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART35_REGISTER_PART_35_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART36_REGISTER_PART_36                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART36_REGISTER_PART_36_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART36_REGISTER_PART_36                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART36_REGISTER_PART_36_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART37_REGISTER_PART_37                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART37_REGISTER_PART_37_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART37_REGISTER_PART_37                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART37_REGISTER_PART_37_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART38_REGISTER_PART_38                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART38_REGISTER_PART_38_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART38_REGISTER_PART_38                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART38_REGISTER_PART_38_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART39_REGISTER_PART_39                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART39_REGISTER_PART_39_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART39_REGISTER_PART_39                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART39_REGISTER_PART_39_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART3_REGISTER_PART_3                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART3_REGISTER_PART_3_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART3_REGISTER_PART_3                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART3_REGISTER_PART_3_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART40_REGISTER_PART_40                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART40_REGISTER_PART_40_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART40_REGISTER_PART_40                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART40_REGISTER_PART_40_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART41_REGISTER_PART_41                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART41_REGISTER_PART_41_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART41_REGISTER_PART_41                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART41_REGISTER_PART_41_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART42_REGISTER_PART_42                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART42_REGISTER_PART_42_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART42_REGISTER_PART_42                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART42_REGISTER_PART_42_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART43_REGISTER_PART_43                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART43_REGISTER_PART_43_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART43_REGISTER_PART_43                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART43_REGISTER_PART_43_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART44_REGISTER_PART_44                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART44_REGISTER_PART_44_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART44_REGISTER_PART_44                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART44_REGISTER_PART_44_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART45_REGISTER_PART_45                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART45_REGISTER_PART_45_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART45_REGISTER_PART_45                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART45_REGISTER_PART_45_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART46_REGISTER_PART_46                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART46_REGISTER_PART_46_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART46_REGISTER_PART_46                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART46_REGISTER_PART_46_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART47_REGISTER_PART_47                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART47_REGISTER_PART_47_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART47_REGISTER_PART_47                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART47_REGISTER_PART_47_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART48_REGISTER_PART_48                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART48_REGISTER_PART_48_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART48_REGISTER_PART_48                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART48_REGISTER_PART_48_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART49_REGISTER_PART_49                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART49_REGISTER_PART_49_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART49_REGISTER_PART_49                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART49_REGISTER_PART_49_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART4_REGISTER_PART_4                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART4_REGISTER_PART_4_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART4_REGISTER_PART_4                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART4_REGISTER_PART_4_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART50_REGISTER_PART_50                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART50_REGISTER_PART_50_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART50_REGISTER_PART_50                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART50_REGISTER_PART_50_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART51_REGISTER_PART_51                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART51_REGISTER_PART_51_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART51_REGISTER_PART_51                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART51_REGISTER_PART_51_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART52_REGISTER_PART_52                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART52_REGISTER_PART_52_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART52_REGISTER_PART_52                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART52_REGISTER_PART_52_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART53_REGISTER_PART_53                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART53_REGISTER_PART_53_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART53_REGISTER_PART_53                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART53_REGISTER_PART_53_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART54_REGISTER_PART_54                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART54_REGISTER_PART_54_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART54_REGISTER_PART_54                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART54_REGISTER_PART_54_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART55_REGISTER_PART_55                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART55_REGISTER_PART_55_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART55_REGISTER_PART_55                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART55_REGISTER_PART_55_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART56_REGISTER_PART_56                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART56_REGISTER_PART_56_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART56_REGISTER_PART_56                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART56_REGISTER_PART_56_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART57_REGISTER_PART_57                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART57_REGISTER_PART_57_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART57_REGISTER_PART_57                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART57_REGISTER_PART_57_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART58_REGISTER_PART_58                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART58_REGISTER_PART_58_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART58_REGISTER_PART_58                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART58_REGISTER_PART_58_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART59_REGISTER_PART_59                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART59_REGISTER_PART_59_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART59_REGISTER_PART_59                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART59_REGISTER_PART_59_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART5_REGISTER_PART_5                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART5_REGISTER_PART_5_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART5_REGISTER_PART_5                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART5_REGISTER_PART_5_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART60_REGISTER_PART_60                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART60_REGISTER_PART_60_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART60_REGISTER_PART_60                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART60_REGISTER_PART_60_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART61_REGISTER_PART_61                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART61_REGISTER_PART_61_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART61_REGISTER_PART_61                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART61_REGISTER_PART_61_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART62_REGISTER_PART_62                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART62_REGISTER_PART_62_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART62_REGISTER_PART_62                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART62_REGISTER_PART_62_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART63_REGISTER_PART_63                 = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART63_REGISTER_PART_63_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART63_REGISTER_PART_63                 = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART63_REGISTER_PART_63_LEN             = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART6_REGISTER_PART_6                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART6_REGISTER_PART_6_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART6_REGISTER_PART_6                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART6_REGISTER_PART_6_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART7_REGISTER_PART_7                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART7_REGISTER_PART_7_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART7_REGISTER_PART_7                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART7_REGISTER_PART_7_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART8_REGISTER_PART_8                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART8_REGISTER_PART_8_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART8_REGISTER_PART_8                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART8_REGISTER_PART_8_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM0_ECID_PART9_REGISTER_PART_9                   = 0   ;
static const uint8_t P9N2_PU_OTPROM0_ECID_PART9_REGISTER_PART_9_LEN               = 64  ;

static const uint8_t P9N2_PU_OTPROM1_ECID_PART9_REGISTER_PART_9                   = 0   ;
static const uint8_t P9N2_PU_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN               = 64  ;

static const uint8_t P9N2_PEC_EDRAM_STATUS_STAT                                   = 0   ;
static const uint8_t P9N2_PEC_EDRAM_STATUS_STAT_LEN                               = 4   ;

static const uint8_t P9N2_PU_EECNT_REG_EECNT                                      = 0   ;
static const uint8_t P9N2_PU_EECNT_REG_EECNT_LEN                                  = 6   ;

static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              = 4   ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          = 12  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               = 20  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           = 20  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               = 44  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           = 16  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            = 63  ;

static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                   = 8   ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               = 46  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              = 54  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          = 3   ;

static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      = 4   ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  = 8   ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           = 15  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       = 9   ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX           = 27  ;
static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN       = 9   ;

static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              = 4   ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          = 12  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               = 20  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           = 20  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               = 44  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           = 16  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            = 63  ;

static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                   = 8   ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               = 46  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              = 54  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          = 3   ;

static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      = 4   ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  = 8   ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           = 15  ;
static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       = 9   ;

static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LIMIT                               = 0   ;
static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LIMIT_LEN                           = 5   ;
static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_SRC_DDE                             = 5   ;
static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_SRC_DDE_LEN                         = 8   ;
static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_TARGET_DDE                          = 13  ;
static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_TARGET_DDE_LEN                      = 8   ;
static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LO_PRIOR_LIMIT                      = 21  ;
static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LO_PRIOR_LIMIT_LEN                  = 5   ;

static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_UE                    = 0   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_SUE                   = 1   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_CE                    = 2   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_CO_DROP_COUNTER_FULL           = 4   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DATA_HANG_DETECT               = 5   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_UNEXPECTED_DATA_OR_CRESP       = 6   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_INTERNAL_ERROR                 = 7   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_XSTOP_ERROR          = 8   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_XSTOP_ERROR         = 9   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_XSTOP_ERROR          = 10  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_XSTOP_ERROR          = 11  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_SND_XSTOP_ERROR            = 12  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_XSTOP_ERROR            = 13  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_RECOV_ERROR          = 14  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_RECOV_ERROR         = 15  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_RECOV_ERROR          = 16  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_RECOV_ERROR          = 17  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_SND_RECOV_ERROR            = 18  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_RRC                    = 19  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_NHTM_SCON_E                    = 20  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_SCOM_ERROR                     = 22  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_PARITY_ERROR                   = 23  ;

static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_UE                    = 0   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_SUE                   = 1   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_CE                    = 2   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_CO_DROP_COUNTER_FULL           = 4   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DATA_HANG_DETECT               = 5   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_UNEXPECTED_DATA_OR_CRESP       = 6   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_INTERNAL_ERROR                 = 7   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_XSTOP_ERROR          = 8   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_XSTOP_ERROR         = 9   ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_XSTOP_ERROR          = 10  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_XSTOP_ERROR          = 11  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_SND_XSTOP_ERROR            = 12  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_XSTOP_ERROR            = 13  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_RECOV_ERROR          = 14  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_RECOV_ERROR         = 15  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_RECOV_ERROR          = 16  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_RECOV_ERROR          = 17  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_SND_RECOV_ERROR            = 18  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_RRC                    = 19  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_NHTM_SCON_E                    = 20  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_SCOM_ERROR                     = 22  ;
static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_PARITY_ERROR                   = 23  ;

static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DPX0_DAT_UE                       = 0   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DPX0_DAT_SUE                      = 1   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DPX0_DAT_CE                       = 2   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_CO_DROP_COUNTER_FULL              = 4   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DATA_HANG_DETECT                  = 5   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_UNEXPECTED_DATA_OR_CRESP          = 6   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_INTERNAL_ERROR                    = 7   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_XSTOP_ERROR             = 8   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_XSTOP_ERROR            = 9   ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_XSTOP_ERROR             = 10  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBADR_XSTOP_ERROR             = 11  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_SND_XSTOP_ERROR               = 12  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_RCV_XSTOP_ERROR               = 13  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_RECOV_ERROR             = 14  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_RECOV_ERROR            = 15  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_RECOV_ERROR             = 16  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBADR_RECOV_ERROR             = 17  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_SND_RECOV_ERROR               = 18  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_RCV_RRC                       = 19  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_NHTM_SCON_E                       = 20  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_SPARE_ERROR_MASK                  = 21  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_SCOM_ERROR                        = 22  ;
static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_PARITY_ERROR                      = 23  ;

static const uint8_t P9N2_PU_ENHCA_FIR_REG_DPX0_DAT_UE                            = 0   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_DPX0_DAT_SUE                           = 1   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_DPX0_DAT_CE                            = 2   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_CO_DROP_COUNTER_FULL                   = 4   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_DATA_HANG_DETECT                       = 5   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_UNEXPECTED_DATA_OR_CRESP               = 6   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_INTERNAL_ERROR                         = 7   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBDAT_XSTOP_ERROR                  = 8   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_ALTDSM_XSTOP_ERROR                 = 9   ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_XCSMP_XSTOP_ERROR                  = 10  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBADR_XSTOP_ERROR                  = 11  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_SND_XSTOP_ERROR                    = 12  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_RCV_XSTOP_ERROR                    = 13  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBDAT_RECOV_ERROR                  = 14  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_ALTDSM_RECOV_ERROR                 = 15  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_XCSMP_RECOV_ERROR                  = 16  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBADR_RECOV_ERROR                  = 17  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_SND_RECOV_ERROR                    = 18  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_RCV_RRC                            = 19  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_NHTM_SCON_E                            = 20  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_SPARE_ERROR                            = 21  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_SCOM_ERROR                             = 22  ;
static const uint8_t P9N2_PU_ENHCA_FIR_REG_PARITY_ERROR                           = 23  ;

static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_RATE                      = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_RATE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W0_COUNT                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W1_COUNT                  = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R0_COUNT                  = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R1_COUNT                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R2_COUNT                  = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R2_COUNT_LEN              = 12  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_RATE                      = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_RATE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W0_COUNT                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W1_COUNT                  = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R0_COUNT                  = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R1_COUNT                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R2_COUNT                  = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R2_COUNT_LEN              = 12  ;

static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_RATE                         = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_RATE_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT                     = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT                     = 16  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT                     = 28  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT                     = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT                     = 52  ;
static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 = 12  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_RATE                      = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_RATE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W0_COUNT                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W1_COUNT                  = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R0_COUNT                  = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R1_COUNT                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R2_COUNT                  = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R2_COUNT_LEN              = 12  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_RATE                      = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_RATE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W0_COUNT                  = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W1_COUNT                  = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R0_COUNT                  = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R0_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R1_COUNT                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R1_COUNT_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R2_COUNT                  = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R2_COUNT_LEN              = 12  ;

static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_FORCE_BYPASS                     = 0   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_IDLE                             = 1   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_VALID_ENTRY                      = 2   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_HIT_UNDER_BARRIER        = 3   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_PROMOTE                  = 6   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_CHECKIN_HANG_TIMER       = 7   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_CHECKOUT_HANG_TIMER      = 8   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT        = 9   ;
static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT_LEN    = 3   ;

static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0                  = 0   ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0_LEN              = 6   ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1                  = 6   ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1_LEN              = 6   ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2                  = 12  ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2_LEN              = 6   ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3                  = 18  ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3_LEN              = 6   ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4                  = 24  ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4_LEN              = 6   ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5                  = 30  ;
static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5_LEN              = 6   ;

static const uint8_t P9N2_PEC_ERROR_REG_CE                                        = 0   ;
static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_ERRORS                            = 1   ;
static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_ERRORS_LEN                        = 3   ;
static const uint8_t P9N2_PEC_ERROR_REG_PARITY                                    = 4   ;
static const uint8_t P9N2_PEC_ERROR_REG_DATA_BUFFER                               = 5   ;
static const uint8_t P9N2_PEC_ERROR_REG_ADDR_BUFFER                               = 6   ;
static const uint8_t P9N2_PEC_ERROR_REG_PCB_FSM                                   = 7   ;
static const uint8_t P9N2_PEC_ERROR_REG_CL_FSM                                    = 8   ;
static const uint8_t P9N2_PEC_ERROR_REG_INT_RX_FSM                                = 9   ;
static const uint8_t P9N2_PEC_ERROR_REG_INT_TX_FSM                                = 10  ;
static const uint8_t P9N2_PEC_ERROR_REG_INT_TYPE                                  = 11  ;
static const uint8_t P9N2_PEC_ERROR_REG_CL_DATA                                   = 12  ;
static const uint8_t P9N2_PEC_ERROR_REG_INFO                                      = 13  ;
static const uint8_t P9N2_PEC_ERROR_REG_UNUSED_0                                  = 14  ;
static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_ATOMIC_LOCK                       = 15  ;
static const uint8_t P9N2_PEC_ERROR_REG_PCB_INTERFACE                             = 16  ;
static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_OFFLINE                           = 17  ;
static const uint8_t P9N2_PEC_ERROR_REG_EDRAM_SEQUENCE_ERR                        = 18  ;
static const uint8_t P9N2_PEC_ERROR_REG_CTRL_PARITY                               = 19  ;
static const uint8_t P9N2_PEC_ERROR_REG_ADDRESS_PARITY                            = 20  ;
static const uint8_t P9N2_PEC_ERROR_REG_TIMEOUT_PARITY                            = 21  ;
static const uint8_t P9N2_PEC_ERROR_REG_CONFIG_PARITY                             = 22  ;
static const uint8_t P9N2_PEC_ERROR_REG_UNUSED_1                                  = 23  ;
static const uint8_t P9N2_PEC_ERROR_REG_DIV_PARITY                                = 24  ;
static const uint8_t P9N2_PEC_ERROR_REG_PLL_UNLOCK                                = 25  ;
static const uint8_t P9N2_PEC_ERROR_REG_PLL_UNLOCK_LEN                            = 4   ;

static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED             = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE               = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN           = 7   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE            = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN        = 56  ;

static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED             = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE               = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN           = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE            = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN        = 56  ;

static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED                   = 0   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE                     = 1   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN                 = 7   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE                  = 8   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN              = 56  ;

static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED                   = 0   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE                     = 1   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN                 = 7   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE                  = 8   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN              = 56  ;

static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE                 = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_RSV3                           = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG               = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN           = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE               = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN           = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG                = 28  ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN            = 12  ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX               = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE            = 46  ;
static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN        = 16  ;

static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE                 = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_RSV3                           = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG               = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN           = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE               = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN           = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG                = 28  ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN            = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX               = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE            = 46  ;
static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN        = 16  ;

static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE                       = 0   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN                   = 3   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_RSV3                                 = 3   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG                     = 4   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN                 = 16  ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE                     = 20  ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN                 = 8   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG                      = 28  ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN                  = 12  ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX                     = 40  ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN                 = 6   ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE                  = 46  ;
static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN              = 16  ;

static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE                       = 0   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN                   = 3   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_RSV3                                 = 3   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG                     = 4   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN                 = 16  ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE                     = 20  ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN                 = 8   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG                      = 28  ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN                  = 12  ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX                     = 40  ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN                 = 6   ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE                  = 46  ;
static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN              = 16  ;

static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR              = 0   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR               = 1   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR                  = 2   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR              = 3   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR                 = 4   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR                 = 5   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR       = 6   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR                = 7   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR              = 8   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR              = 9   ;
static const uint8_t P9N2_PEC_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR                 = 10  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_SCAN_COLLISION_ERR                     = 11  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR           = 12  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_OPCG_TRIGGER_ERR                       = 13  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR               = 14  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR                = 15  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR                  = 16  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR            = 17  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR                 = 18  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR          = 19  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR                = 20  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR                 = 21  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_CLKCMD_REQUEST_ERR                     = 22  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_CBS_PROTOCOL_ERR                       = 23  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_VITL_ALIGN_ERR                         = 24  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_UNIT_SYNC_LVL_ERR                      = 25  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR       = 26  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_OPCG_STOPPED_BY_PCB_ERR                = 27  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_EDRAM_SCAN_PREVENTED_ERR               = 28  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_UNUSED_ERROR29                         = 29  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_UNUSED_ERROR30                         = 30  ;
static const uint8_t P9N2_PEC_ERROR_STATUS_UNUSED_ERROR31                         = 31  ;

static const uint8_t P9N2_CAPP_ERRRPT_APC_COLLISION                               = 0   ;
static const uint8_t P9N2_CAPP_ERRRPT_FSM_SM_ERROR                                = 1   ;
static const uint8_t P9N2_CAPP_ERRRPT_RBUFSM_ERROR                                = 2   ;
static const uint8_t P9N2_CAPP_ERRRPT_WBUF_SM_ERROR                               = 3   ;
static const uint8_t P9N2_CAPP_ERRRPT_PERR_BAR_REG                                = 4   ;
static const uint8_t P9N2_CAPP_ERRRPT_PERR_NONBAR_REG                             = 5   ;
static const uint8_t P9N2_CAPP_ERRRPT_RTAG_HANG_EPOCH                             = 6   ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_CE_ERR                           = 7   ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_CE_ERR                           = 8   ;
static const uint8_t P9N2_CAPP_ERRRPT_UOP_REGS_CE_ERR                             = 9   ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_UE_ERR                           = 10  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_UE_ERR                           = 11  ;
static const uint8_t P9N2_CAPP_ERRRPT_UOP_REGS_UE_ERR                             = 12  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_ATAG_PERR                        = 13  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_TTAG_PERR                        = 14  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_ATAG_PERR                        = 15  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_TTAG_PERR                        = 16  ;
static const uint8_t P9N2_CAPP_ERRRPT_FIR_ACTION1                                 = 17  ;
static const uint8_t P9N2_CAPP_ERRRPT_FIR_ACTION2                                 = 18  ;
static const uint8_t P9N2_CAPP_ERRRPT_FIR_ACTION3                                 = 19  ;
static const uint8_t P9N2_CAPP_ERRRPT_UNEXPECTED_CRESP                            = 20  ;
static const uint8_t P9N2_CAPP_ERRRPT_LD_CLASS_ARE_ERROR                          = 21  ;
static const uint8_t P9N2_CAPP_ERRRPT_ST_CLASS_ARE_ERROR                          = 22  ;
static const uint8_t P9N2_CAPP_ERRRPT_LD_CLASS_ACK_DEAD                           = 23  ;
static const uint8_t P9N2_CAPP_ERRRPT_FOREIGN_OP_HANG                             = 24  ;
static const uint8_t P9N2_CAPP_ERRRPT_DOMESTIC_OP_HANG                            = 25  ;
static const uint8_t P9N2_CAPP_ERRRPT_ST_CLASS_ACK_DEAD                           = 26  ;
static const uint8_t P9N2_CAPP_ERRRPT_ACTIVATE_FSMERR                             = 27  ;
static const uint8_t P9N2_CAPP_ERRRPT_SPARE1                                      = 28  ;
static const uint8_t P9N2_CAPP_ERRRPT_SPARE2                                      = 29  ;
static const uint8_t P9N2_CAPP_ERRRPT_CMDQ_CE_ERR                                 = 30  ;
static const uint8_t P9N2_CAPP_ERRRPT_CMDQ_UE_ERR                                 = 31  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_CE_ERR                           = 32  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_CE_ERR                           = 33  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_UE_ERR                           = 34  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_UE_ERR                           = 35  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_ATAG_PERR                        = 36  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_ATAG_PERR                        = 37  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_TTAG_PERR                        = 38  ;
static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_TTAG_PERR                        = 39  ;
static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR0                        = 40  ;
static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR1                        = 41  ;
static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR2                        = 42  ;
static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR0                        = 43  ;
static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR1                        = 44  ;
static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR2                        = 45  ;

static const uint8_t P9N2__SM2_ERR_FIRST_BITS                                     = 0   ;
static const uint8_t P9N2__SM2_ERR_FIRST_BITS_LEN                                 = 64  ;

static const uint8_t P9N2__SM2_ERR_HOLD_DEBUG0_CONFIG_P                           = 0   ;
static const uint8_t P9N2__SM2_ERR_HOLD_DEBUG1_CONFIG_P                           = 1   ;
static const uint8_t P9N2__SM2_ERR_HOLD_XTS_CONFIG_P                              = 2   ;
static const uint8_t P9N2__SM2_ERR_HOLD_XTS_CONFIG2_P                             = 3   ;
static const uint8_t P9N2__SM2_ERR_HOLD_XTS_CONFIG3_P                             = 4   ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED1                                   = 5   ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED1_LEN                               = 3   ;
static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR0                              = 8   ;
static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR1                              = 9   ;
static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR2                              = 10  ;
static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR3                              = 11  ;
static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR4                              = 12  ;
static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR5                              = 13  ;
static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR6                              = 14  ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATR_SM_STATE                              = 15  ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATSD_SM_STATE                             = 16  ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATR_TIMEOUT                               = 17  ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATSD_TIMEOUT                              = 18  ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATSD_BAD_TAG                              = 19  ;
static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR2                              = 20  ;
static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR3                              = 21  ;
static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR4                              = 22  ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATR_ARBSTATE                              = 23  ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATR_RADDR_BND                             = 24  ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED2                                   = 25  ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED2_LEN                               = 7   ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_CERR0                             = 32  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_CERR1                             = 33  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_CERR2                             = 34  ;
static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_CERR0                             = 35  ;
static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_CERR1                             = 36  ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED3                                   = 37  ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED3_LEN                               = 11  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR0                              = 48  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR1                              = 49  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR2                              = 50  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR3                              = 51  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR4                              = 52  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR5                              = 53  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR6                              = 54  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR7                              = 55  ;
static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR8                              = 56  ;
static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR0                              = 57  ;
static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR1                              = 58  ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED4                                   = 59  ;
static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED4_LEN                               = 4   ;
static const uint8_t P9N2__SM2_ERR_HOLD_ATR_MISS_IRQ                              = 63  ;

static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC                        = 0   ;
static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_LEN                    = 24  ;
static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR                   = 24  ;
static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR_LEN               = 2   ;
static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_RNW                    = 26  ;
static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_DA_OP                  = 27  ;

static const uint8_t P9N2__SM2_ERR_MASK_BITS                                      = 0   ;
static const uint8_t P9N2__SM2_ERR_MASK_BITS_LEN                                  = 64  ;

static const uint8_t P9N2__CTL_ERR_SCOPE_CTL_CONFIG_CTL                           = 0   ;
static const uint8_t P9N2__CTL_ERR_SCOPE_CTL_CONFIG_CTL_LEN                       = 16  ;

static const uint8_t P9N2_PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD = 0   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD        = 1   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD      = 2   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD     = 3   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD = 4   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD         = 5   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD    = 6   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD                 = 7   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_ERR_HOLD                   = 8   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD           = 9   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD        = 10  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD              = 11  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD               = 12  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_TIMEOUT_ERR_HOLD                     = 13  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_F_SKITTER_ERR_HOLD                   = 14  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_PCB_ERR_HOLD_OUT                     = 15  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK  = 16  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK            = 17  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK          = 18  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK         = 19  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK        = 20  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK             = 21  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_MASK                     = 23  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_MASK                       = 24  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_THRES_STATE_MASK                     = 25  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_OVERFLOW_MASK                        = 26  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_PARITY_MASK                  = 27  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_VALID_MASK                   = 28  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_TIMEOUT_MASK                         = 29  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_F_SKITTER_READ_MASK                  = 30  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_PCB_MASK                             = 31  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_LT                       = 40  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_LT_LEN                   = 4   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_LT                         = 44  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_LT_LEN                     = 3   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFT_DTS_LT                         = 47  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFT_VOLT_LT                        = 48  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_READ_STATE_LT                        = 49  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_READ_STATE_LT_LEN                    = 2   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_WRITE_STATE_LT                       = 51  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_WRITE_STATE_LT_LEN                   = 4   ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_SAMPLE_DTS_LT                        = 55  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_MEASURE_VOLT_LT                      = 56  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_READ_CPM_LT                          = 57  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_WRITE_CPM_LT                         = 58  ;
static const uint8_t P9N2_PEC_ERR_STATUS_REG_UNUSED                               = 59  ;

static const uint8_t P9N2_PU_ESB_CI_BASE_BASE                                     = 8   ;
static const uint8_t P9N2_PU_ESB_CI_BASE_BASE_LEN                                 = 40  ;
static const uint8_t P9N2_PU_ESB_CI_BASE_VALID                                    = 63  ;

static const uint8_t P9N2_PU_ESB_NOTIFY_ADDR                                      = 8   ;
static const uint8_t P9N2_PU_ESB_NOTIFY_ADDR_LEN                                  = 53  ;
static const uint8_t P9N2_PU_ESB_NOTIFY_VALID                                     = 63  ;

static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_NX_ALLOW_CRYPTO_DC               = 0   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC        = 1   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_EX_FUSE_FP_THROTTLE_EN_DC        = 2   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_2CHIP           = 3   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP           = 4   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP_LEN       = 2   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_NP_NVLINK_DISABLE                = 6   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_OTP_PCBMS_HW_MODE_SEL_DC            = 7   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_OTP_PCBMS_FUSED_CORE_MODE_SEL0_DC   = 8   ;
static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_OTP_PCBMS_FUSED_CORE_MODE_SEL1_DC   = 9   ;

static const uint8_t P9N2_PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0                   = 11  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0_LEN               = 5   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_B_SELF_BUSY_0                        = 25  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_B_PEEK_DATA1_0                       = 32  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_B_PEEK_DATA1_0_LEN                   = 8   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_B_LBUS_PARITY_ERR1_0                 = 40  ;

static const uint8_t P9N2_PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1                   = 11  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1_LEN               = 5   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_C_SELF_BUSY_1                        = 25  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_C_PEEK_DATA1_1                       = 32  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_C_PEEK_DATA1_1_LEN                   = 8   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_C_LBUS_PARITY_ERR1_1                 = 40  ;

static const uint8_t P9N2_PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2                   = 11  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2_LEN               = 5   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_D_SELF_BUSY_2                        = 25  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_D_PEEK_DATA1_2                       = 32  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_D_PEEK_DATA1_2_LEN                   = 8   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_D_LBUS_PARITY_ERR1_2                 = 40  ;

static const uint8_t P9N2_PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3                   = 11  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3_LEN               = 5   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_E_SELF_BUSY_3                        = 25  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_E_PEEK_DATA1_3                       = 32  ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_E_PEEK_DATA1_3_LEN                   = 8   ;
static const uint8_t P9N2_PU_EXTENDED_STATUS_E_LBUS_PARITY_ERR1_3                 = 40  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0               = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0_LEN           = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1               = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1_LEN           = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X0_FIR_ERR            = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X1_FIR_ERR            = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X2_FIR_ERR            = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X3_FIR_ERR            = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X4_FIR_ERR            = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X5_FIR_ERR            = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X6_FIR_ERR            = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_SCOM_ERROR               = 7   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X0_FIR_ERR                 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X1_FIR_ERR                 = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X2_FIR_ERR                 = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X3_FIR_ERR                 = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X4_FIR_ERR                 = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X5_FIR_ERR                 = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X6_FIR_ERR                 = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_SCOM_ERROR                    = 7   ;

static const uint8_t P9N2__CTL_FENCE_0_CONFIG_0                                   = 0   ;
static const uint8_t P9N2__CTL_FENCE_0_CONFIG_0_LEN                               = 64  ;

static const uint8_t P9N2__CTL_FENCE_1_CONFIG_1                                   = 0   ;
static const uint8_t P9N2__CTL_FENCE_1_CONFIG_1_LEN                               = 64  ;

static const uint8_t P9N2_PU_NPU_SM0_FENCE_2_CONFIG_2                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_FENCE_2_CONFIG_2_LEN                         = 64  ;

static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_FENCE0_REQUEST              = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_FENCE0_REQUEST_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_RESERVED                    = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_RESERVED_LEN                = 2   ;

static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_FENCE1_REQUEST              = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_FENCE1_REQUEST_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_RESERVED                    = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_RESERVED_LEN                = 2   ;

static const uint8_t P9N2__CTL_FENCE_STATE_BRK0                                   = 0   ;
static const uint8_t P9N2__CTL_FENCE_STATE_BRK1                                   = 1   ;
static const uint8_t P9N2__CTL_FENCE_STATE_BRK2                                   = 2   ;
static const uint8_t P9N2__CTL_FENCE_STATE_BRK3                                   = 3   ;
static const uint8_t P9N2__CTL_FENCE_STATE_BRK4                                   = 4   ;
static const uint8_t P9N2__CTL_FENCE_STATE_BRK5                                   = 5   ;

static const uint8_t P9N2_PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID                        = 0   ;
static const uint8_t P9N2_PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID_LEN                    = 16  ;
static const uint8_t P9N2_PU_FI2C_CFG_ECC_ENABLE                                  = 16  ;
static const uint8_t P9N2_PU_FI2C_CFG_DISABLE_ECC_CHK                             = 17  ;
static const uint8_t P9N2_PU_FI2C_CFG_I2C_SPEED_MUX                               = 18  ;
static const uint8_t P9N2_PU_FI2C_CFG_I2C_SPEED_MUX_LEN                           = 2   ;
static const uint8_t P9N2_PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE                      = 20  ;
static const uint8_t P9N2_PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE_LEN                  = 16  ;
static const uint8_t P9N2_PU_FI2C_CFG_I2C_BUS_HELD_MODE_ENABLE                    = 36  ;
static const uint8_t P9N2_PU_FI2C_CFG_PIPELINE_ENABLE                             = 37  ;
static const uint8_t P9N2_PU_FI2C_CFG_BACKUP_SEEPROM_SELECT                       = 38  ;
static const uint8_t P9N2_PU_FI2C_CFG_FORCE_RESET                                 = 39  ;
static const uint8_t P9N2_PU_FI2C_CFG_RESET_PIB                                   = 40  ;
static const uint8_t P9N2_PU_FI2C_CFG_DISABLE_TIMEOUT                             = 41  ;
static const uint8_t P9N2_PU_FI2C_CFG_RESERVED_FOR_CONFIGS                        = 42  ;
static const uint8_t P9N2_PU_FI2C_CFG_RESERVED_FOR_CONFIGS_LEN                    = 18  ;

static const uint8_t P9N2_PU_FI2C_SCFG0_REGISTER_VALID                            = 0   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_3                                = 1   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_4                                = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_4_LEN                            = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_5                                = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_5_LEN                            = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_DEVICE_ID                                 = 8   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_DEVICE_ID_LEN                             = 7   ;
static const uint8_t P9N2_PU_FI2C_SCFG0_ECC_ENABLE                                = 15  ;
static const uint8_t P9N2_PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP               = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG0_START_SEEPROM_ADDRESS                     = 32  ;
static const uint8_t P9N2_PU_FI2C_SCFG0_START_SEEPROM_ADDRESS_LEN                 = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG0_START_PPE_ADDR                            = 48  ;
static const uint8_t P9N2_PU_FI2C_SCFG0_START_PPE_ADDR_LEN                        = 16  ;

static const uint8_t P9N2_PU_FI2C_SCFG1_REGISTER_VALID                            = 0   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_6                                = 1   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_7                                = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_7_LEN                            = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_8                                = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_8_LEN                            = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_DEVICE_ID                                 = 8   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_DEVICE_ID_LEN                             = 7   ;
static const uint8_t P9N2_PU_FI2C_SCFG1_ECC_ENABLE                                = 15  ;
static const uint8_t P9N2_PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP               = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG1_START_SEEPROM_ADDRESS                     = 32  ;
static const uint8_t P9N2_PU_FI2C_SCFG1_START_SEEPROM_ADDRESS_LEN                 = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG1_START_PPE_ADDR                            = 48  ;
static const uint8_t P9N2_PU_FI2C_SCFG1_START_PPE_ADDR_LEN                        = 16  ;

static const uint8_t P9N2_PU_FI2C_SCFG2_REGISTER_VALID                            = 0   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_9                                = 1   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_10                               = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_10_LEN                           = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_11                               = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_11_LEN                           = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_DEVICE_ID                                 = 8   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_DEVICE_ID_LEN                             = 7   ;
static const uint8_t P9N2_PU_FI2C_SCFG2_ECC_ENABLE                                = 15  ;
static const uint8_t P9N2_PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP               = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG2_START_SEEPROM_ADDRESS                     = 32  ;
static const uint8_t P9N2_PU_FI2C_SCFG2_START_SEEPROM_ADDRESS_LEN                 = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG2_START_PPE_ADDR                            = 48  ;
static const uint8_t P9N2_PU_FI2C_SCFG2_START_PPE_ADDR_LEN                        = 16  ;

static const uint8_t P9N2_PU_FI2C_SCFG3_REGISTER_VALID                            = 0   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_12                               = 1   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_13                               = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_13_LEN                           = 2   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_14                               = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_14_LEN                           = 4   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_DEVICE_ID                                 = 8   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_DEVICE_ID_LEN                             = 7   ;
static const uint8_t P9N2_PU_FI2C_SCFG3_ECC_ENABLE                                = 15  ;
static const uint8_t P9N2_PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP               = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG3_START_SEEPROM_ADDRESS                     = 32  ;
static const uint8_t P9N2_PU_FI2C_SCFG3_START_SEEPROM_ADDRESS_LEN                 = 16  ;
static const uint8_t P9N2_PU_FI2C_SCFG3_START_PPE_ADDR                            = 48  ;
static const uint8_t P9N2_PU_FI2C_SCFG3_START_PPE_ADDR_LEN                        = 16  ;

static const uint8_t P9N2_PU_FI2C_STAT_PIB_RESPONSE_INFO                          = 0   ;
static const uint8_t P9N2_PU_FI2C_STAT_PIB_RESPONSE_INFO_LEN                      = 3   ;
static const uint8_t P9N2_PU_FI2C_STAT_I2CM_PIB_ERRORS                            = 3   ;
static const uint8_t P9N2_PU_FI2C_STAT_I2CM_PIB_ERRORS_LEN                        = 6   ;
static const uint8_t P9N2_PU_FI2C_STAT_I2CM_ECC_ERRORS                            = 9   ;
static const uint8_t P9N2_PU_FI2C_STAT_I2CM_ECC_ERRORS_LEN                        = 3   ;
static const uint8_t P9N2_PU_FI2C_STAT_I2CM_I2C_ERRORS                            = 12  ;
static const uint8_t P9N2_PU_FI2C_STAT_I2CM_I2C_ERRORS_LEN                        = 7   ;
static const uint8_t P9N2_PU_FI2C_STAT_ERR_ADDR_BEYOND_RANGE                      = 19  ;
static const uint8_t P9N2_PU_FI2C_STAT_ERR_ADDR_OVERLAP                           = 20  ;
static const uint8_t P9N2_PU_FI2C_STAT_PIB_ABORT                                  = 21  ;
static const uint8_t P9N2_PU_FI2C_STAT_TIMEOUT_ON_I2C_STATUS_RD                   = 22  ;
static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ERRS                          = 23  ;
static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ERRS_LEN                      = 9   ;
static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_PIBM_ADDR                           = 32  ;
static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_PIBM_ADDR_LEN                       = 8   ;
static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_FSM_RESET_ONGOING                   = 40  ;
static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ADDRESS                       = 41  ;
static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ADDRESS_LEN                   = 2   ;
static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_FSM_STATE                           = 43  ;
static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_FSM_STATE_LEN                       = 5   ;
static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS                     = 48  ;
static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS_LEN                 = 16  ;

static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0              = 0   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0                   = 32  ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_LBUS_PARITY_ERR1_0             = 40  ;

static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1              = 0   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1                   = 32  ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_LBUS_PARITY_ERR1_1             = 40  ;

static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2              = 0   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2                   = 32  ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_LBUS_PARITY_ERR1_2             = 40  ;

static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3              = 0   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3                   = 32  ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_LBUS_PARITY_ERR1_3             = 40  ;

static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0              = 0   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0              = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0              = 16  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0              = 24  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0                   = 32  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_LBUS_PARITY_ERR1_0             = 40  ;

static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1              = 0   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1              = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1              = 16  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1              = 24  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1                   = 32  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_LBUS_PARITY_ERR1_1             = 40  ;

static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2              = 0   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2              = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2              = 16  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2              = 24  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2                   = 32  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_LBUS_PARITY_ERR1_2             = 40  ;

static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3              = 0   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3              = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3              = 16  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3              = 24  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3_LEN          = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3                   = 32  ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN               = 8   ;
static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3             = 40  ;

static const uint8_t P9N2_CAPP_FIR_ACTION0_REG_ACTION0                            = 0   ;
static const uint8_t P9N2_CAPP_FIR_ACTION0_REG_ACTION0_LEN                        = 53  ;

static const uint8_t P9N2_PEC_FIR_ACTION0_REG_ACTION0                             = 0   ;
static const uint8_t P9N2_PEC_FIR_ACTION0_REG_ACTION0_LEN                         = 37  ;

static const uint8_t P9N2_PU_FIR_ACTION0_REG_ACTION0                              = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION0_REG_ACTION0_LEN                          = 7   ;

static const uint8_t P9N2_PU_FIR_ACTION0_REG_0_0                                  = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION0_REG_0_0_LEN                              = 64  ;

static const uint8_t P9N2_PU_FIR_ACTION0_REG_1_1                                  = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION0_REG_1_1_LEN                              = 64  ;

static const uint8_t P9N2_PU_FIR_ACTION0_REG_2_2                                  = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION0_REG_2_2_LEN                              = 64  ;

static const uint8_t P9N2_CAPP_FIR_ACTION1_REG_ACTION1                            = 0   ;
static const uint8_t P9N2_CAPP_FIR_ACTION1_REG_ACTION1_LEN                        = 53  ;

static const uint8_t P9N2_PEC_FIR_ACTION1_REG_ACTION1                             = 0   ;
static const uint8_t P9N2_PEC_FIR_ACTION1_REG_ACTION1_LEN                         = 37  ;

static const uint8_t P9N2_PU_FIR_ACTION1_REG_ACTION1                              = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION1_REG_ACTION1_LEN                          = 7   ;

static const uint8_t P9N2_PU_FIR_ACTION1_REG_0_0                                  = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION1_REG_0_0_LEN                              = 64  ;

static const uint8_t P9N2_PU_FIR_ACTION1_REG_1_1                                  = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION1_REG_1_1_LEN                              = 64  ;

static const uint8_t P9N2_PU_FIR_ACTION1_REG_2_2                                  = 0   ;
static const uint8_t P9N2_PU_FIR_ACTION1_REG_2_2_LEN                              = 64  ;

static const uint8_t P9N2_PEC_FIR_MASK_IN0                                        = 0   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN1                                        = 1   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN2                                        = 2   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN3                                        = 3   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN4                                        = 4   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN5                                        = 5   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN6                                        = 6   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN7                                        = 7   ;
static const uint8_t P9N2_PEC_FIR_MASK_IN7_LEN                                    = 19  ;
static const uint8_t P9N2_PEC_FIR_MASK_IN26                                       = 26  ;

static const uint8_t P9N2_CAPP_FIR_MASK_REG_BAR_PE                                = 0   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_REGISTER_PE                           = 1   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_ARRAY_CE                       = 2   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_ARRAY_UE                       = 3   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TIMER_EXPIRED_RECOV_ERROR             = 4   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TIMER_EXPIRED_XSTOP_ERROR             = 5   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_PSL_CMD_UE                            = 6   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_PSL_CMD_SUE                           = 7   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOP_ARRAY_CE                        = 8   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOP_ARRAY_UE                        = 9   ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_RECOVERY_FAILED                       = 10  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_ILLEGAL_LPC_BAR_ACCESS                = 11  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_RECOVERABLE_ERROR                 = 12  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_RECOVERABLE_ERROR              = 13  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOPER_RECOVERABLE_ERROR             = 14  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SECURE_SCOM_ERROR                     = 15  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_SYS_XSTOP_ERROR                = 16  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOPER_SYS_XSTOP_ERROR               = 17  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_SYS_XSTOP_ERROR                   = 18  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_MUOP_ERROR_1                          = 19  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_MUOP_ERROR_2                          = 20  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_MUOP_ERROR_3                          = 21  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SUOP_ERROR_1                          = 22  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SUOP_ERROR_2                          = 23  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SUOP_ERROR_3                          = 24  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_MISC_ERROR                   = 25  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_INTERFACE_PE                 = 26  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_DATA_HANG_ERROR              = 27  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_HANG_ERROR                   = 28  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_LD_CLASS_CMD_ADDR_ERR                 = 29  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_ST_CLASS_CMD_ADDR_ERR                 = 30  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_PHB_LINK_DOWN                         = 31  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL        = 32  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_FOREIGN_LINK_HANG_ERROR               = 33  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_POWERBUS_CE                       = 34  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_POWERBUS_UE                       = 35  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_POWERBUS_SUE                      = 36  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_TIMEOUT                          = 37  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_SOT_ERR                          = 38  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_BAD_OP_ERR                       = 39  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_SEQ_NUM_PARITY_ERR               = 40  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL        = 41  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TIME_BASE_ERR                         = 42  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_TRANSPORT_INFORMATIONAL_ERR           = 43  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_APC_ARRAY_CMD_CE_ERPT                 = 44  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_APC_ARRAY_CMD_UE_ERPT                 = 45  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_PSL_CREDIT_TIMEOUT_ERR                = 46  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SPARE_2                               = 47  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SPARE_3                               = 48  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_HYPERVISOR                            = 49  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SECURE_MEM_ACCESS                     = 50  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SCOM_ERR2                             = 51  ;
static const uint8_t P9N2_CAPP_FIR_MASK_REG_SCOM_ERR                              = 52  ;

static const uint8_t P9N2_PEC_FIR_MASK_REG_HSSCALERR                              = 0   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_HSSPLLAERR                             = 1   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_HSSPLLBERR                             = 2   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXAERR                                 = 3   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXBERR                                 = 4   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXCERR                                 = 5   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXDERR                                 = 6   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXEERR                                 = 7   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXFERR                                 = 8   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXGERR                                 = 9   ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXHERR                                 = 10  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXIERR                                 = 11  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXJERR                                 = 12  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXKERR                                 = 13  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXLERR                                 = 14  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXMERR                                 = 15  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXNERR                                 = 16  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXOERR                                 = 17  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_TXPERR                                 = 18  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXAERR                                 = 19  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXBERR                                 = 20  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXCERR                                 = 21  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXDERR                                 = 22  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXEERR                                 = 23  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXFERR                                 = 24  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXGERR                                 = 25  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXHERR                                 = 26  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXIERR                                 = 27  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXJERR                                 = 28  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXKERR                                 = 29  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXLERR                                 = 30  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXMERR                                 = 31  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXNERR                                 = 32  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXOERR                                 = 33  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_RXPERR                                 = 34  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_SCOM_PERR0                             = 35  ;
static const uint8_t P9N2_PEC_FIR_MASK_REG_SCOM_PERR1                             = 36  ;

static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED0                           = 0   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED2                           = 2   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED3                           = 3   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED4                           = 4   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR                     = 5   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE               = 6   ;

static const uint8_t P9N2_PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_PIB            = 3   ;
static const uint8_t P9N2_PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_PIB                 = 5   ;
static const uint8_t P9N2_PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_PIB                 = 6   ;
static const uint8_t P9N2_PU_FIR_MASK_REGISTER_RD_RST_INTRPT_PIB                  = 7   ;
static const uint8_t P9N2_PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_FACES          = 22  ;
static const uint8_t P9N2_PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_FACES               = 24  ;
static const uint8_t P9N2_PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_FACES               = 25  ;
static const uint8_t P9N2_PU_FIR_MASK_REGISTER_RD_RST_INTRPT_FACES                = 26  ;

static const uint8_t P9N2_PU_FIR_MASK_REG_0_0                                     = 0   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_0_0_LEN                                 = 64  ;

static const uint8_t P9N2_PU_FIR_MASK_REG_1_1                                     = 0   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_1_1_LEN                                 = 64  ;

static const uint8_t P9N2_PU_FIR_MASK_REG_2_2                                     = 0   ;
static const uint8_t P9N2_PU_FIR_MASK_REG_2_2_LEN                                 = 64  ;

static const uint8_t P9N2_CAPP_FIR_REG_BAR_PE                                     = 0   ;
static const uint8_t P9N2_CAPP_FIR_REG_REGISTER_PE                                = 1   ;
static const uint8_t P9N2_CAPP_FIR_REG_MASTER_ARRAY_CE                            = 2   ;
static const uint8_t P9N2_CAPP_FIR_REG_MASTER_ARRAY_UE                            = 3   ;
static const uint8_t P9N2_CAPP_FIR_REG_TIMER_EXPIRED_RECOV_ERROR                  = 4   ;
static const uint8_t P9N2_CAPP_FIR_REG_TIMER_EXPIRED_XSTOP_ERROR                  = 5   ;
static const uint8_t P9N2_CAPP_FIR_REG_PSL_CMD_UE                                 = 6   ;
static const uint8_t P9N2_CAPP_FIR_REG_PSL_CMD_SUE                                = 7   ;
static const uint8_t P9N2_CAPP_FIR_REG_SNOOP_ARRAY_CE                             = 8   ;
static const uint8_t P9N2_CAPP_FIR_REG_SNOOP_ARRAY_UE                             = 9   ;
static const uint8_t P9N2_CAPP_FIR_REG_RECOVERY_FAILED                            = 10  ;
static const uint8_t P9N2_CAPP_FIR_REG_ILLEGAL_LPC_BAR_ACCESS                     = 11  ;
static const uint8_t P9N2_CAPP_FIR_REG_XPT_RECOVERABLE_ERROR                      = 12  ;
static const uint8_t P9N2_CAPP_FIR_REG_MASTER_RECOVERABLE_ERROR                   = 13  ;
static const uint8_t P9N2_CAPP_FIR_REG_SNOOPER_RECOVERABLE_ERROR                  = 14  ;
static const uint8_t P9N2_CAPP_FIR_REG_SECURE_SCOM_ERROR                          = 15  ;
static const uint8_t P9N2_CAPP_FIR_REG_MASTER_SYS_XSTOP_ERROR                     = 16  ;
static const uint8_t P9N2_CAPP_FIR_REG_SNOOPER_SYS_XSTOP_ERROR                    = 17  ;
static const uint8_t P9N2_CAPP_FIR_REG_XPT_SYS_XSTOP_ERROR                        = 18  ;
static const uint8_t P9N2_CAPP_FIR_REG_MUOP_ERROR_1                               = 19  ;
static const uint8_t P9N2_CAPP_FIR_REG_MUOP_ERROR_2                               = 20  ;
static const uint8_t P9N2_CAPP_FIR_REG_MUOP_ERROR_3                               = 21  ;
static const uint8_t P9N2_CAPP_FIR_REG_SUOP_ERROR_1                               = 22  ;
static const uint8_t P9N2_CAPP_FIR_REG_SUOP_ERROR_2                               = 23  ;
static const uint8_t P9N2_CAPP_FIR_REG_SUOP_ERROR_3                               = 24  ;
static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_MISC_ERROR                        = 25  ;
static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_INTERFACE_PE                      = 26  ;
static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_DATA_HANG_ERROR                   = 27  ;
static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_HANG_ERROR                        = 28  ;
static const uint8_t P9N2_CAPP_FIR_REG_LD_CLASS_CMD_ADDR_ERR                      = 29  ;
static const uint8_t P9N2_CAPP_FIR_REG_ST_CLASS_CMD_ADDR_ERR                      = 30  ;
static const uint8_t P9N2_CAPP_FIR_REG_PHB_LINK_DOWN                              = 31  ;
static const uint8_t P9N2_CAPP_FIR_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL             = 32  ;
static const uint8_t P9N2_CAPP_FIR_REG_FOREIGN_LINK_HANG_ERROR                    = 33  ;
static const uint8_t P9N2_CAPP_FIR_REG_XPT_POWERBUS_CE                            = 34  ;
static const uint8_t P9N2_CAPP_FIR_REG_XPT_POWERBUS_UE                            = 35  ;
static const uint8_t P9N2_CAPP_FIR_REG_XPT_POWERBUS_SUE                           = 36  ;
static const uint8_t P9N2_CAPP_FIR_REG_TLBI_TIMEOUT                               = 37  ;
static const uint8_t P9N2_CAPP_FIR_REG_TLBI_SOT_ERR                               = 38  ;
static const uint8_t P9N2_CAPP_FIR_REG_TLBI_BAD_OP_ERR                            = 39  ;
static const uint8_t P9N2_CAPP_FIR_REG_TLBI_SEQ_NUM_PARITY_ERR                    = 40  ;
static const uint8_t P9N2_CAPP_FIR_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL             = 41  ;
static const uint8_t P9N2_CAPP_FIR_REG_TIME_BASE_ERR                              = 42  ;
static const uint8_t P9N2_CAPP_FIR_REG_TRANSPORT_INFORMATIONAL_ERR                = 43  ;
static const uint8_t P9N2_CAPP_FIR_REG_APC_ARRAY_CMD_CE_ERPT                      = 44  ;
static const uint8_t P9N2_CAPP_FIR_REG_APC_ARRAY_CMD_UE_ERPT                      = 45  ;
static const uint8_t P9N2_CAPP_FIR_REG_PSL_CREDIT_TIMEOUT_ERR                     = 46  ;
static const uint8_t P9N2_CAPP_FIR_REG_SPARE_2                                    = 47  ;
static const uint8_t P9N2_CAPP_FIR_REG_HYPERVISOR                                 = 48  ;
static const uint8_t P9N2_CAPP_FIR_REG_SPARE_3                                    = 49  ;
static const uint8_t P9N2_CAPP_FIR_REG_SECURE_MEM_ACCESS                          = 50  ;
static const uint8_t P9N2_CAPP_FIR_REG_SCOM_ERR2                                  = 51  ;
static const uint8_t P9N2_CAPP_FIR_REG_SCOM_ERR                                   = 52  ;

static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED0                                = 0   ;
static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED1                                = 1   ;
static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED2                                = 2   ;
static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED3                                = 3   ;
static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED4                                = 4   ;
static const uint8_t P9N2_PU_FIR_REG_INTERNAL_SCOM_ERROR                          = 5   ;
static const uint8_t P9N2_PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE                    = 6   ;

static const uint8_t P9N2_PHB_FIR_REG_AIB_COMMAND_INVALID                         = 0   ;
static const uint8_t P9N2_PHB_FIR_REG_AIB_ADDRESS_INVALID                         = 1   ;
static const uint8_t P9N2_PHB_FIR_REG_AIB_ACCESS_ERROR                            = 2   ;
static const uint8_t P9N2_PHB_FIR_REG_PAPR_OUTBOUND_INJECT_ERROR                  = 3   ;
static const uint8_t P9N2_PHB_FIR_REG_AIB_FATAL_CLASS_ERROR                       = 4   ;
static const uint8_t P9N2_PHB_FIR_REG_AIB_INF_CLASS_ERROR                         = 6   ;
static const uint8_t P9N2_PHB_FIR_REG_PE_STOP_STATE_SIGNALED                      = 7   ;
static const uint8_t P9N2_PHB_FIR_REG_OUT_COMMON_ARRAY_FATAL_ERROR                = 8   ;
static const uint8_t P9N2_PHB_FIR_REG_OUT_COMMON_LATCH_FATAL_ERROR                = 9   ;
static const uint8_t P9N2_PHB_FIR_REG_OUT_COMMON_LOGIC_FATAL_ERROR                = 10  ;
static const uint8_t P9N2_PHB_FIR_REG_BLIF_OUT_INTERFACE_PARITY_ERROR             = 11  ;
static const uint8_t P9N2_PHB_FIR_REG_CFG_WRITE_CA_OR_UR_RESPONSE                 = 12  ;
static const uint8_t P9N2_PHB_FIR_REG_MMIO_REQUEST_TIMEOUT                        = 13  ;
static const uint8_t P9N2_PHB_FIR_REG_OUT_RRB_SOURCED_ERROR                       = 14  ;
static const uint8_t P9N2_PHB_FIR_REG_CFG_LOGIC_SIGNALED_ERROR                    = 15  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_REQUEST_ADDRESS_ERROR                   = 16  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_FDA_FATAL_ERROR                         = 17  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_FDA_INF_ERROR                           = 18  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_FDB_FATAL_ERROR                         = 19  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_FDB_INF_ERROR                           = 20  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_ERR_FATAL_ERROR                         = 21  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_ERR_INF_ERROR                           = 22  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_DBG_FATAL_ERROR                         = 23  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_DBG_INF_ERROR                           = 24  ;
static const uint8_t P9N2_PHB_FIR_REG_PCIE_REQUEST_ACCESS_ERROR                   = 25  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_BUS_LOGIC_ERROR                         = 26  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_UVI_FATAL_ERROR                         = 27  ;
static const uint8_t P9N2_PHB_FIR_REG_RSB_UVI_INF_ERROR                           = 28  ;
static const uint8_t P9N2_PHB_FIR_REG_SCOM_FATAL_ERROR                            = 29  ;
static const uint8_t P9N2_PHB_FIR_REG_SCOM_INF_ERROR                              = 30  ;
static const uint8_t P9N2_PHB_FIR_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS              = 31  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_IODA_FATAL_ERROR                        = 32  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_MSI_PE_MATCH_ERROR                      = 33  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_MSI_ADDRESS_ERROR                       = 34  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_TVT_ERROR                               = 35  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_RCVD_FATAL_ERROR_MSG                    = 36  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_RCVD_NONFATAL_ERROR_MSG                 = 37  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG              = 38  ;
static const uint8_t P9N2_PHB_FIR_REG_PAPR_INBOUND_INJECT_ERROR                   = 39  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_COMMON_FATAL_ERROR                      = 40  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_TABLE_BAR_DISABLED_ERROR                = 41  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_BLIF_COMPLETION_ERROR                   = 42  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_PCT_TIMEOUT_ERROR                       = 43  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_ECC_CORRECTABLE_ERROR                   = 44  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_ECC_UNCORRECTABLE_ERROR                 = 45  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_TLP_POISON_SIGNALED                     = 46  ;
static const uint8_t P9N2_PHB_FIR_REG_ARB_RTT_PENUM_INVALID_ERROR                 = 47  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_COMMON_FATAL_ERROR                      = 48  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_TABLE_BAR_DISABLED_ERROR                = 49  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_ECC_CORRECTABLE_ERROR                   = 50  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_ECC_UNCORRECTABLE_ERROR                 = 51  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR                   = 52  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_MRT_ERROR                               = 53  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_RESERVED01                              = 54  ;
static const uint8_t P9N2_PHB_FIR_REG_MRG_RESERVED02                              = 55  ;
static const uint8_t P9N2_PHB_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR                  = 56  ;
static const uint8_t P9N2_PHB_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR                   = 57  ;
static const uint8_t P9N2_PHB_FIR_REG_TCE_UNEXPECTED_RESPONSE_ERROR               = 58  ;
static const uint8_t P9N2_PHB_FIR_REG_TCE_COMMON_FATAL_ERROR                      = 59  ;
static const uint8_t P9N2_PHB_FIR_REG_TCE_ECC_CORRECTABLE_ERROR                   = 60  ;
static const uint8_t P9N2_PHB_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR                 = 61  ;
static const uint8_t P9N2_PHB_FIR_REG_TCE_RESERVED01                              = 62  ;
static const uint8_t P9N2_PHB_FIR_REG_INTERNAL_PARITY_ERROR                       = 63  ;

static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_CE                               = 0   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_HDR_UE                           = 1   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_DATA_UE                          = 2   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_FLIT_PERR                          = 3   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_DATA_PERR                          = 4   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_PKT_MALFOR                         = 5   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_PKT_UNSUPPORTED                    = 6   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_CONFIG_ERR                         = 7   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_CRC_ERR                            = 8   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_PRI_ERR                                = 9   ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_LOGIC_ERR                              = 10  ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_LMD_POISON                             = 11  ;
static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_DATA_SUE                         = 12  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_ARRAY_CE                               = 13  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_RECOV_ERR                         = 14  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_RING_ERR                               = 15  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_MMIO_ST_DATA_UE                        = 16  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_PEF                                    = 17  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_NVL_CFG_ERR                            = 18  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_NVL_FATAL_ERR                          = 19  ;
static const uint8_t P9N2_PU_FIR_REG_0_RESERVED_1                                 = 20  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_ARRAY_UE                               = 21  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_PERR                              = 22  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_FATAL_ERR                         = 23  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_CONFIG_ERR                        = 24  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_FWD_PROGRESS_ERR                       = 25  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_LOGIC_ERR                              = 26  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_RSVD_14                                = 27  ;
static const uint8_t P9N2_PU_FIR_REG_0_CTL_RSVD_15                                = 28  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_UE                             = 29  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_CE                             = 30  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_PERR                           = 31  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_CREG_PERR                              = 32  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_RTAG_PERR                              = 33  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_STATE_PERR                             = 34  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_LOGIC_ERR                              = 35  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_SUE                            = 36  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_PBRX_SUE                               = 37  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_RSVD_9                                 = 38  ;
static const uint8_t P9N2_PU_FIR_REG_0_DAT_RSVD_10                                = 39  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_INT                                    = 40  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_SRAM_CE                                = 41  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_SRAM_UE                                = 42  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_PROTOCOL_CE                            = 43  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_PROTOCOL_UE                            = 44  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_PBUS_PROTOCOL                          = 45  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_6                                 = 46  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_7                                 = 47  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_8                                 = 48  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_9                                 = 49  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_10                                = 50  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_11                                = 51  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_12                                = 52  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_13                                = 53  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_14                                = 54  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_15                                = 55  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_16                                = 56  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_17                                = 57  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_18                                = 58  ;
static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_19                                = 59  ;
static const uint8_t P9N2_PU_FIR_REG_0_FIR0_RSVD_60                               = 60  ;
static const uint8_t P9N2_PU_FIR_REG_0_FIR0_RSVD_61                               = 61  ;
static const uint8_t P9N2_PU_FIR_REG_0_PARITY_ERR2                                = 62  ;
static const uint8_t P9N2_PU_FIR_REG_0_PARITY_ERR                                 = 63  ;

static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK0_STALL                             = 0   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK0_NOSTALL                           = 1   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK1_STALL                             = 2   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK1_NOSTALL                           = 3   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK2_STALL                             = 4   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK2_NOSTALL                           = 5   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK3_STALL                             = 6   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK3_NOSTALL                           = 7   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK4_STALL                             = 8   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK4_NOSTALL                           = 9   ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK5_STALL                             = 10  ;
static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK5_NOSTALL                           = 11  ;
static const uint8_t P9N2_PU_FIR_REG_1_MISC_RING_ERR                              = 12  ;
static const uint8_t P9N2_PU_FIR_REG_1_MISC_INT_RA_PERR                           = 13  ;
static const uint8_t P9N2_PU_FIR_REG_1_MISC_DA_ADDR_PERR                          = 14  ;
static const uint8_t P9N2_PU_FIR_REG_1_MISC_CTRL_PERR                             = 15  ;
static const uint8_t P9N2_PU_FIR_REG_1_MISC_NMMU_ERR                              = 16  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TVT_ENTRY_INVALID                      = 17  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR                     = 18  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR                 = 19  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR                 = 20  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR                 = 21  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_REQ_TO_ERR                         = 22  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCD_PERR                               = 23  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TDR_PERR                               = 24  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_EA_UE                               = 25  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_EA_CE                               = 26  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_TDRMEM_UE                           = 27  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_TDRMEM_CE                           = 28  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_RSPOUT_UE                           = 29  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_RSPOUT_CE                           = 30  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_TVT_PERR                               = 31  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_IODA_ADDR_PERR                         = 32  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_NPU_CTRL_PERR                          = 33  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_NPU_TOR_PERR                           = 34  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL                     = 35  ;
static const uint8_t P9N2_PU_FIR_REG_1_ATS_RSVD_19                                = 36  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_37                               = 37  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_38                               = 38  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_39                               = 39  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_40                               = 40  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_41                               = 41  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_42                               = 42  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_43                               = 43  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_44                               = 44  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_45                               = 45  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_46                               = 46  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_47                               = 47  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_48                               = 48  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_49                               = 49  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_50                               = 50  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_51                               = 51  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_52                               = 52  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_53                               = 53  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_54                               = 54  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_55                               = 55  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_56                               = 56  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_57                               = 57  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_58                               = 58  ;
static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_59                               = 59  ;
static const uint8_t P9N2_PU_FIR_REG_1_SCOMSAT00_ERR                              = 60  ;
static const uint8_t P9N2_PU_FIR_REG_1_SCOMSAT01_ERR                              = 61  ;
static const uint8_t P9N2_PU_FIR_REG_1_PARITY_ERR2                                = 62  ;
static const uint8_t P9N2_PU_FIR_REG_1_PARITY_ERR                                 = 63  ;

static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK2_XLAT_FAULT                        = 0   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK3_XLAT_FAULT                        = 1   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK4_XLAT_FAULT                        = 2   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK5_XLAT_FAULT                        = 3   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_TL_CRD_OVF                             = 4   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_ACTAG_IDX                          = 5   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_ACTAG_INV                          = 6   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_OPC_RSVD                           = 7   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_RTC_POS                            = 8   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_TMPL                               = 9   ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_TMPL_UNS                           = 10  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_TMPL_X00                           = 11  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_CTLFLIT_OVERRUN                    = 12  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_UNEXPECTED_DATA_FLIT               = 13  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_LINK_DOWN                          = 14  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_BAD_DATA_RECEIVED_CMD              = 15  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_BAD_DATA_RECEIVED_RESP_RXI_BAD_DATA_RECEIVED_RESP = 16  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_RESPONSE_NOT_ALLOWED               = 17  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_PERR                                   = 18  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_CE                                     = 19  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_UE                                     = 20  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXO_OP_ERRORS                          = 21  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXO_INTERNAL_ERRORS                    = 22  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_FIFO_OVERRUN                       = 23  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_CNTL_FLIT_DATA_RUN_LENGTH_INV      = 24  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_OPCODE_UTIL_DL_EQ_ZERO             = 25  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_22                                = 26  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_23                                = 27  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_24                                = 28  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_25                                = 29  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_26                                = 30  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_27                                = 31  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_28                                = 32  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_29                                = 33  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_30                                = 34  ;
static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_31                                = 35  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_MMIO_INVALIDATE_REQ_WHILE_1_INPROG     = 36  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_ITAG_PORT_0                 = 37  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_ITAG_PORT_1                 = 38  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_RD_PEE_COMPLETION           = 39  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_CO_RESP                     = 40  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_XLAT_REQ_WHILE_SPAP_INVALID            = 41  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_INVALID_PEE                            = 42  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_BLOOM_FILTER_PROTECT_ERR               = 43  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_8                                 = 44  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_9                                 = 45  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_CE                                     = 46  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_UE                                     = 47  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_SLBI_TLBI_BUFF_OVERFLOW                = 48  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_SBE_CORR_ERR_PB_CHKOUT_RSP_DATA        = 49  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_UE_PB_CHKOUT_RSP_DATA                  = 50  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_SUE_PB_CHKOUT_RSP_DATA                 = 51  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_16                                = 52  ;
static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_17                                = 53  ;
static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_54                               = 54  ;
static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_55                               = 55  ;
static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_56                               = 56  ;
static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_57                               = 57  ;
static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_58                               = 58  ;
static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_59                               = 59  ;
static const uint8_t P9N2_PU_FIR_REG_2_SCOMSAT10_ERR                              = 60  ;
static const uint8_t P9N2_PU_FIR_REG_2_SCOMSAT11_ERR                              = 61  ;
static const uint8_t P9N2_PU_FIR_REG_2_PARITY_ERR2                                = 62  ;
static const uint8_t P9N2_PU_FIR_REG_2_PARITY_ERR                                 = 63  ;

static const uint8_t P9N2_PEC_FIR_STATUS_REG_HSSCALERR                            = 0   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_HSSPLLAERR                           = 1   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_HSSPLLBERR                           = 2   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXAERR                               = 3   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXBERR                               = 4   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXCERR                               = 5   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXDERR                               = 6   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXEERR                               = 7   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXFERR                               = 8   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXGERR                               = 9   ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXHERR                               = 10  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXIERR                               = 11  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXJERR                               = 12  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXKERR                               = 13  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXLERR                               = 14  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXMERR                               = 15  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXNERR                               = 16  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXOERR                               = 17  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXPERR                               = 18  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXAERR                               = 19  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXBERR                               = 20  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXCERR                               = 21  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXDERR                               = 22  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXEERR                               = 23  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXFERR                               = 24  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXGERR                               = 25  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXHERR                               = 26  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXIERR                               = 27  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXJERR                               = 28  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXKERR                               = 29  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXLERR                               = 30  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXMERR                               = 31  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXNERR                               = 32  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXOERR                               = 33  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXPERR                               = 34  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_SCOM_PERR0                           = 35  ;
static const uint8_t P9N2_PEC_FIR_STATUS_REG_SCOM_PERR1                           = 36  ;

static const uint8_t P9N2_PEC_FIR_WOF_REG_WOF                                     = 0   ;
static const uint8_t P9N2_PEC_FIR_WOF_REG_WOF_LEN                                 = 37  ;

static const uint8_t P9N2_PU_FIR_WOF_REG_WOF                                      = 0   ;
static const uint8_t P9N2_PU_FIR_WOF_REG_WOF_LEN                                  = 7   ;

static const uint8_t P9N2_CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP                    = 0   ;
static const uint8_t P9N2_CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP_LEN                = 32  ;

static const uint8_t P9N2_CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP                      = 0   ;
static const uint8_t P9N2_CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP_LEN                  = 32  ;

static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_ITAG                         = 0   ;
static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_TX                           = 1   ;
static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_TX_LEN                       = 16  ;
static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_TX_OVERWRITE                 = 17  ;

static const uint8_t P9N2__CTL_FREEZE_0_CONFIG_0                                  = 0   ;
static const uint8_t P9N2__CTL_FREEZE_0_CONFIG_0_LEN                              = 64  ;

static const uint8_t P9N2__CTL_FREEZE_1_CONFIG_1                                  = 0   ;
static const uint8_t P9N2__CTL_FREEZE_1_CONFIG_1_LEN                              = 64  ;

static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_00                             = 0   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_01                             = 1   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_02                             = 2   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_10                             = 3   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_11                             = 4   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_12                             = 5   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_20                             = 6   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_21                             = 7   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_22                             = 8   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_30                             = 9   ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_31                             = 10  ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_32                             = 11  ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_40                             = 12  ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_41                             = 13  ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_42                             = 14  ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_50                             = 15  ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_51                             = 16  ;
static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_52                             = 17  ;

static const uint8_t P9N2_PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT             = 0   ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT_LEN         = 32  ;

static const uint8_t P9N2_PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT                          = 0   ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT_LEN                      = 32  ;

static const uint8_t P9N2_PU_FSB_DOWNFIFO_REQ_RESET_DNFIFO_REQ_RESET              = 0   ;

static const uint8_t P9N2_PU_FSB_DOWNFIFO_SIG_EOT_DNFIFO_SIGNAL                   = 0   ;

static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE          = 6   ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP           = 7   ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG         = 8   ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL                 = 10  ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY                = 11  ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT          = 12  ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN      = 4   ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS          = 16  ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN      = 8   ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS            = 24  ;
static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN        = 8   ;

static const uint8_t P9N2_PU_FSB_UPFIFO_ACK_EOT_UPFIFO_ACK                        = 0   ;

static const uint8_t P9N2_PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT             = 0   ;
static const uint8_t P9N2_PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT_LEN         = 32  ;

static const uint8_t P9N2_PU_FSB_UPFIFO_RESET_UPFIFO_RESET                        = 0   ;

static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP                    = 6   ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE                   = 7   ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG                  = 8   ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_FULL                          = 10  ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_EMPTY                         = 11  ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT                   = 12  ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN               = 4   ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS                   = 16  ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN               = 8   ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS                     = 24  ;
static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN                 = 8   ;

static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_ENABLE                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED1                      = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED1_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_GROUP                   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_GROUP_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_CHIP                    = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_CHIP_LEN                = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_ADDR                    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_ADDR_LEN                = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED2                      = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED2_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_POISON                  = 39  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_ENABLE                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED1                      = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED1_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_GROUP                   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_GROUP_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_CHIP                    = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_CHIP_LEN                = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_ADDR                    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_ADDR_LEN                = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED2                      = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED2_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_POISON                  = 39  ;

static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED1                         = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED1_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP                      = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP                       = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP_LEN                   = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR                       = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR_LEN                   = 26  ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED2                         = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_POISON                     = 39  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_ENABLE                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED1                      = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED1_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_GROUP                   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_GROUP_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_CHIP                    = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_CHIP_LEN                = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_ADDR                    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_ADDR_LEN                = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED2                      = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED2_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_POISON                  = 39  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_ENABLE                  = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED1                      = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED1_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_GROUP                   = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_GROUP_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_CHIP                    = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_CHIP_LEN                = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_ADDR                    = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_ADDR_LEN                = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED2                      = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED2_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_POISON                  = 39  ;

static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_RESERVED                       = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_RESERVED_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_COUNT                          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_COUNT_LEN                      = 62  ;

static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_RESERVED                       = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_RESERVED_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_COUNT                          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_COUNT_LEN                      = 62  ;

static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_RESERVED                       = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_RESERVED_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_COUNT                          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_COUNT_LEN                      = 62  ;

static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_RESERVED                       = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_RESERVED_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_COUNT                          = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_COUNT_LEN                      = 62  ;

static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_DBG                                   = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_HALT_ON_XSTOP                            = 1   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_HALT_ON_TRIG                             = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED3                                = 3   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_INTR_ADDR                             = 4   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_TRACE_EXTRA                           = 5   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_TRACE_STALL                           = 6   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_WAIT_CYCLES                           = 7   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_FULL_SPEED                            = 8   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED9                                = 9   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_MODE_SEL                           = 10  ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_MODE_SEL_LEN                       = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED12_15                            = 12  ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED12_15_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_FIR_TRIGGER                              = 16  ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_SPARE                                    = 17  ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_SPARE_LEN                                = 3   ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_DATA_SEL                           = 20  ;
static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_DATA_SEL_LEN                       = 4   ;

static const uint8_t P9N2_PU_GPE0_GPEIVPR_IVPR                                    = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEIVPR_IVPR_LEN                                = 23  ;

static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_LOW_PRIORITY                        = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_LOW_PRIORITY_LEN                    = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY                       = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY                      = 4   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY                     = 6   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY                       = 8   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY                      = 10  ;
static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  = 2   ;

static const uint8_t P9N2_PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR                         = 1   ;
static const uint8_t P9N2_PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR_LEN                     = 3   ;

static const uint8_t P9N2_PU_GPE0_GPESTR_PBASE                                    = 12  ;
static const uint8_t P9N2_PU_GPE0_GPESTR_PBASE_LEN                                = 10  ;
static const uint8_t P9N2_PU_GPE0_GPESTR_SIZE                                     = 29  ;
static const uint8_t P9N2_PU_GPE0_GPESTR_SIZE_LEN                                 = 3   ;

static const uint8_t P9N2_PU_GPE0_GPETSEL_WATCHDOG_SEL                            = 0   ;
static const uint8_t P9N2_PU_GPE0_GPETSEL_WATCHDOG_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE0_GPETSEL_FIT_SEL                                 = 4   ;
static const uint8_t P9N2_PU_GPE0_GPETSEL_FIT_SEL_LEN                             = 4   ;

static const uint8_t P9N2_PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR                       = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE0_GPEXIIAR_IAR                                    = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEXIIAR_IAR_LEN                                = 30  ;

static const uint8_t P9N2_PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR                          = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR_LEN                      = 32  ;

static const uint8_t P9N2_PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                = 32  ;

static const uint8_t P9N2_PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR                          = 1   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR_LEN                      = 3   ;

static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HS                                 = 0   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HC                                 = 1   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HC_LEN                             = 3   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HCP                                = 4   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_RIP                                = 5   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_SIP                                = 6   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_TRAP                               = 7   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_IAC                                = 8   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC                         = 9   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC_LEN                     = 3   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_DACR                               = 12  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_DACW                               = 13  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_WE                            = 14  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_TRH                                = 15  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_SMS                                = 16  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_SMS_LEN                            = 4   ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_LP                            = 20  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_EP                                 = 21  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_PTR                                = 24  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_ST                                 = 25  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_MFE                                = 28  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_MCS                                = 29  ;
static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_MCS_LEN                            = 3   ;

static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_POPULATE_PENDING              = 35  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_VALID_LEN                     = 2   ;

static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             = 34  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             = 35  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN                     = 4   ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID                   = 40  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID_LEN               = 4   ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE_PTR                      = 45  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE2_ERR                     = 46  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_PREFETCH_PENDING              = 47  ;

static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE                       = 35  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   = 8   ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_LINE_MODE                         = 43  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ERROR                             = 49  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ERROR_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE0_MIB_XISGB_STORE_ADDRESS                         = 0   ;
static const uint8_t P9N2_PU_GPE0_MIB_XISGB_STORE_ADDRESS_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     = 35  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISGB_SGB_BYTE_VALID                        = 36  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN                    = 4   ;
static const uint8_t P9N2_PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING                     = 63  ;

static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_RSP_INFO                          = 49  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_RSP_INFO_LEN                      = 3   ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_IAR                                = 32  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_IAR_LEN                            = 30  ;

static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0                      = 32  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  = 32  ;

static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR                         = 0   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_EDR                                = 32  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_EDR_LEN                            = 32  ;

static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_IR                                  = 0   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_IR_LEN                              = 32  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0                       = 32  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_XIXCR_XCR                           = 1   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_XIXCR_XCR_LEN                       = 3   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_SPRG0                               = 32  ;
static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_SPRG0_LEN                           = 32  ;

static const uint8_t P9N2_PU_GPE0_PPE_XIXCR_XCR                                   = 1   ;
static const uint8_t P9N2_PU_GPE0_PPE_XIXCR_XCR_LEN                               = 3   ;

static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_DBG                                   = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_HALT_ON_XSTOP                            = 1   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_HALT_ON_TRIG                             = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED3                                = 3   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_INTR_ADDR                             = 4   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_TRACE_EXTRA                           = 5   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_TRACE_STALL                           = 6   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_WAIT_CYCLES                           = 7   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_FULL_SPEED                            = 8   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED9                                = 9   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_MODE_SEL                           = 10  ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_MODE_SEL_LEN                       = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED12_15                            = 12  ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED12_15_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_FIR_TRIGGER                              = 16  ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_SPARE                                    = 17  ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_SPARE_LEN                                = 3   ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_DATA_SEL                           = 20  ;
static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_DATA_SEL_LEN                       = 4   ;

static const uint8_t P9N2_PU_GPE1_GPEIVPR_IVPR                                    = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEIVPR_IVPR_LEN                                = 23  ;

static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_LOW_PRIORITY                        = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_LOW_PRIORITY_LEN                    = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY                       = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY                      = 4   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY                     = 6   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY                       = 8   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY                      = 10  ;
static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  = 2   ;

static const uint8_t P9N2_PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR                         = 1   ;
static const uint8_t P9N2_PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR_LEN                     = 3   ;

static const uint8_t P9N2_PU_GPE1_GPESTR_PBASE                                    = 12  ;
static const uint8_t P9N2_PU_GPE1_GPESTR_PBASE_LEN                                = 10  ;
static const uint8_t P9N2_PU_GPE1_GPESTR_SIZE                                     = 29  ;
static const uint8_t P9N2_PU_GPE1_GPESTR_SIZE_LEN                                 = 3   ;

static const uint8_t P9N2_PU_GPE1_GPETSEL_WATCHDOG_SEL                            = 0   ;
static const uint8_t P9N2_PU_GPE1_GPETSEL_WATCHDOG_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE1_GPETSEL_FIT_SEL                                 = 4   ;
static const uint8_t P9N2_PU_GPE1_GPETSEL_FIT_SEL_LEN                             = 4   ;

static const uint8_t P9N2_PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR                       = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE1_GPEXIIAR_IAR                                    = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEXIIAR_IAR_LEN                                = 30  ;

static const uint8_t P9N2_PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR                          = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR_LEN                      = 32  ;

static const uint8_t P9N2_PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                = 32  ;

static const uint8_t P9N2_PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR                          = 1   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR_LEN                      = 3   ;

static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HS                                 = 0   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HC                                 = 1   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HC_LEN                             = 3   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HCP                                = 4   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_RIP                                = 5   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_SIP                                = 6   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_TRAP                               = 7   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_IAC                                = 8   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC                         = 9   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC_LEN                     = 3   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_DACR                               = 12  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_DACW                               = 13  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_WE                            = 14  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_TRH                                = 15  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_SMS                                = 16  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_SMS_LEN                            = 4   ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_LP                            = 20  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_EP                                 = 21  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_PTR                                = 24  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_ST                                 = 25  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_MFE                                = 28  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_MCS                                = 29  ;
static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_MCS_LEN                            = 3   ;

static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_POPULATE_PENDING              = 35  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_VALID_LEN                     = 2   ;

static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             = 34  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             = 35  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN                     = 4   ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID                   = 40  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID_LEN               = 4   ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE_PTR                      = 45  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE2_ERR                     = 46  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_PREFETCH_PENDING              = 47  ;

static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE                       = 35  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   = 8   ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_LINE_MODE                         = 43  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ERROR                             = 49  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ERROR_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE1_MIB_XISGB_STORE_ADDRESS                         = 0   ;
static const uint8_t P9N2_PU_GPE1_MIB_XISGB_STORE_ADDRESS_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     = 35  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISGB_SGB_BYTE_VALID                        = 36  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN                    = 4   ;
static const uint8_t P9N2_PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING                     = 63  ;

static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_RSP_INFO                          = 49  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_RSP_INFO_LEN                      = 3   ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_IAR                                = 32  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_IAR_LEN                            = 30  ;

static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0                      = 32  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  = 32  ;

static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR                         = 0   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_EDR                                = 32  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_EDR_LEN                            = 32  ;

static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_IR                                  = 0   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_IR_LEN                              = 32  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0                       = 32  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_XIXCR_XCR                           = 1   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_XIXCR_XCR_LEN                       = 3   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_SPRG0                               = 32  ;
static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_SPRG0_LEN                           = 32  ;

static const uint8_t P9N2_PU_GPE1_PPE_XIXCR_XCR                                   = 1   ;
static const uint8_t P9N2_PU_GPE1_PPE_XIXCR_XCR_LEN                               = 3   ;

static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_DBG                                   = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_HALT_ON_XSTOP                            = 1   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_HALT_ON_TRIG                             = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED3                                = 3   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_INTR_ADDR                             = 4   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_TRACE_EXTRA                           = 5   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_TRACE_STALL                           = 6   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_WAIT_CYCLES                           = 7   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_FULL_SPEED                            = 8   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED9                                = 9   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_MODE_SEL                           = 10  ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_MODE_SEL_LEN                       = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED12_15                            = 12  ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED12_15_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_FIR_TRIGGER                              = 16  ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_SPARE                                    = 17  ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_SPARE_LEN                                = 3   ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_DATA_SEL                           = 20  ;
static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_DATA_SEL_LEN                       = 4   ;

static const uint8_t P9N2_PU_GPE2_GPEIVPR_IVPR                                    = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEIVPR_IVPR_LEN                                = 23  ;

static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_LOW_PRIORITY                        = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_LOW_PRIORITY_LEN                    = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY                       = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY                      = 4   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY                     = 6   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY                       = 8   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY                      = 10  ;
static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  = 2   ;

static const uint8_t P9N2_PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR                         = 1   ;
static const uint8_t P9N2_PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR_LEN                     = 3   ;

static const uint8_t P9N2_PU_GPE2_GPESTR_PBASE                                    = 12  ;
static const uint8_t P9N2_PU_GPE2_GPESTR_PBASE_LEN                                = 10  ;
static const uint8_t P9N2_PU_GPE2_GPESTR_SIZE                                     = 29  ;
static const uint8_t P9N2_PU_GPE2_GPESTR_SIZE_LEN                                 = 3   ;

static const uint8_t P9N2_PU_GPE2_GPETSEL_WATCHDOG_SEL                            = 0   ;
static const uint8_t P9N2_PU_GPE2_GPETSEL_WATCHDOG_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE2_GPETSEL_FIT_SEL                                 = 4   ;
static const uint8_t P9N2_PU_GPE2_GPETSEL_FIT_SEL_LEN                             = 4   ;

static const uint8_t P9N2_PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR                       = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE2_GPEXIIAR_IAR                                    = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEXIIAR_IAR_LEN                                = 30  ;

static const uint8_t P9N2_PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR                          = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR_LEN                      = 32  ;

static const uint8_t P9N2_PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                = 32  ;

static const uint8_t P9N2_PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR                          = 1   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR_LEN                      = 3   ;

static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HS                                 = 0   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HC                                 = 1   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HC_LEN                             = 3   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HCP                                = 4   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_RIP                                = 5   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_SIP                                = 6   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_TRAP                               = 7   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_IAC                                = 8   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC                         = 9   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC_LEN                     = 3   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_DACR                               = 12  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_DACW                               = 13  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_WE                            = 14  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_TRH                                = 15  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_SMS                                = 16  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_SMS_LEN                            = 4   ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_LP                            = 20  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_EP                                 = 21  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_PTR                                = 24  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_ST                                 = 25  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_MFE                                = 28  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_MCS                                = 29  ;
static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_MCS_LEN                            = 3   ;

static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_POPULATE_PENDING              = 35  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_VALID_LEN                     = 2   ;

static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             = 34  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             = 35  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN                     = 4   ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID                   = 40  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID_LEN               = 4   ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE_PTR                      = 45  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE2_ERR                     = 46  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_PREFETCH_PENDING              = 47  ;

static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE                       = 35  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   = 8   ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_LINE_MODE                         = 43  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ERROR                             = 49  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ERROR_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE2_MIB_XISGB_STORE_ADDRESS                         = 0   ;
static const uint8_t P9N2_PU_GPE2_MIB_XISGB_STORE_ADDRESS_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     = 35  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISGB_SGB_BYTE_VALID                        = 36  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN                    = 4   ;
static const uint8_t P9N2_PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING                     = 63  ;

static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_RSP_INFO                          = 49  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_RSP_INFO_LEN                      = 3   ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_IAR                                = 32  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_IAR_LEN                            = 30  ;

static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0                      = 32  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  = 32  ;

static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR                         = 0   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_EDR                                = 32  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_EDR_LEN                            = 32  ;

static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_IR                                  = 0   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_IR_LEN                              = 32  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0                       = 32  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_XIXCR_XCR                           = 1   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_XIXCR_XCR_LEN                       = 3   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_SPRG0                               = 32  ;
static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_SPRG0_LEN                           = 32  ;

static const uint8_t P9N2_PU_GPE2_PPE_XIXCR_XCR                                   = 1   ;
static const uint8_t P9N2_PU_GPE2_PPE_XIXCR_XCR_LEN                               = 3   ;

static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_DBG                                   = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_HALT_ON_XSTOP                            = 1   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_HALT_ON_TRIG                             = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED3                                = 3   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_INTR_ADDR                             = 4   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_TRACE_EXTRA                           = 5   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_TRACE_STALL                           = 6   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_WAIT_CYCLES                           = 7   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_FULL_SPEED                            = 8   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED9                                = 9   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_MODE_SEL                           = 10  ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_MODE_SEL_LEN                       = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED12_15                            = 12  ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED12_15_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_FIR_TRIGGER                              = 16  ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_SPARE                                    = 17  ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_SPARE_LEN                                = 3   ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_DATA_SEL                           = 20  ;
static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_DATA_SEL_LEN                       = 4   ;

static const uint8_t P9N2_PU_GPE3_GPEIVPR_IVPR                                    = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEIVPR_IVPR_LEN                                = 23  ;

static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_LOW_PRIORITY                        = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_LOW_PRIORITY_LEN                    = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY                       = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY                      = 4   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY                     = 6   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY                       = 8   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY_LEN                   = 2   ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY                      = 10  ;
static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  = 2   ;

static const uint8_t P9N2_PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR                         = 1   ;
static const uint8_t P9N2_PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR_LEN                     = 3   ;

static const uint8_t P9N2_PU_GPE3_GPESTR_PBASE                                    = 12  ;
static const uint8_t P9N2_PU_GPE3_GPESTR_PBASE_LEN                                = 10  ;
static const uint8_t P9N2_PU_GPE3_GPESTR_SIZE                                     = 29  ;
static const uint8_t P9N2_PU_GPE3_GPESTR_SIZE_LEN                                 = 3   ;

static const uint8_t P9N2_PU_GPE3_GPETSEL_WATCHDOG_SEL                            = 0   ;
static const uint8_t P9N2_PU_GPE3_GPETSEL_WATCHDOG_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE3_GPETSEL_FIT_SEL                                 = 4   ;
static const uint8_t P9N2_PU_GPE3_GPETSEL_FIT_SEL_LEN                             = 4   ;

static const uint8_t P9N2_PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR                       = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE3_GPEXIIAR_IAR                                    = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEXIIAR_IAR_LEN                                = 30  ;

static const uint8_t P9N2_PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR                          = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR_LEN                      = 32  ;

static const uint8_t P9N2_PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                = 32  ;

static const uint8_t P9N2_PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR                          = 1   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR_LEN                      = 3   ;

static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HS                                 = 0   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HC                                 = 1   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HC_LEN                             = 3   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HCP                                = 4   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_RIP                                = 5   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_SIP                                = 6   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_TRAP                               = 7   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_IAC                                = 8   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC                         = 9   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC_LEN                     = 3   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_DACR                               = 12  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_DACW                               = 13  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_WE                            = 14  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_TRH                                = 15  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_SMS                                = 16  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_SMS_LEN                            = 4   ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_LP                            = 20  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_EP                                 = 21  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_PTR                                = 24  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_ST                                 = 25  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_MFE                                = 28  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_MCS                                = 29  ;
static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_MCS_LEN                            = 3   ;

static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_POPULATE_PENDING              = 35  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_VALID_LEN                     = 2   ;

static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR                      = 0   ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  = 27  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_ERR                           = 32  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING             = 34  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             = 35  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_VALID                         = 36  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN                     = 4   ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID                   = 40  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID_LEN               = 4   ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE_PTR                      = 45  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE2_ERR                     = 46  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_PREFETCH_PENDING              = 47  ;

static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE                       = 35  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   = 8   ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_LINE_MODE                         = 43  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ERROR                             = 49  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ERROR_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE3_MIB_XISGB_STORE_ADDRESS                         = 0   ;
static const uint8_t P9N2_PU_GPE3_MIB_XISGB_STORE_ADDRESS_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     = 35  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISGB_SGB_BYTE_VALID                        = 36  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN                    = 4   ;
static const uint8_t P9N2_PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING                     = 63  ;

static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_ADDR                              = 0   ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_R_NW                              = 32  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_BUSY                              = 33  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING           = 34  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_RSP_INFO                          = 49  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_RSP_INFO_LEN                      = 3   ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_IFETCH_PENDING                    = 62  ;
static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_DATAOP_PENDING                    = 63  ;

static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_IAR                                = 32  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_IAR_LEN                            = 30  ;

static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HS                             = 0   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HC                             = 1   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HC_LEN                         = 3   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HCP                            = 4   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_RIP                            = 5   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_SIP                            = 6   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_TRAP                           = 7   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_IAC                            = 8   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC                     = 9   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 = 3   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_DACR                           = 12  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_DACW                           = 13  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_WE                        = 14  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_TRH                            = 15  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_SMS                            = 16  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_SMS_LEN                        = 4   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_LP                        = 20  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_EP                             = 21  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_PTR                            = 24  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_ST                             = 25  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_MFE                            = 28  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_MCS                            = 29  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_MCS_LEN                        = 3   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0                      = 32  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  = 32  ;

static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR                         = 0   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     = 32  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_EDR                                = 32  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_EDR_LEN                            = 32  ;

static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_IR                                  = 0   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_IR_LEN                              = 32  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0                       = 32  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   = 32  ;

static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_XIXCR_XCR                           = 1   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_XIXCR_XCR_LEN                       = 3   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_SPRG0                               = 32  ;
static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_SPRG0_LEN                           = 32  ;

static const uint8_t P9N2_PU_GPE3_PPE_XIXCR_XCR                                   = 1   ;
static const uint8_t P9N2_PU_GPE3_PPE_XIXCR_XCR_LEN                               = 3   ;

static const uint8_t P9N2_PU_GPIO_INPUT_DIN_0                                     = 0   ;
static const uint8_t P9N2_PU_GPIO_INPUT_DIN_1                                     = 1   ;
static const uint8_t P9N2_PU_GPIO_INPUT_DIN_2                                     = 2   ;

static const uint8_t P9N2_PU_GPIO_INT_COND_INT_COND_0                             = 0   ;
static const uint8_t P9N2_PU_GPIO_INT_COND_INT_COND_1                             = 1   ;
static const uint8_t P9N2_PU_GPIO_INT_COND_INT_COND_2                             = 2   ;

static const uint8_t P9N2_PU_GPIO_INT_ENABLE_EN_0                                 = 0   ;
static const uint8_t P9N2_PU_GPIO_INT_ENABLE_EN_1                                 = 1   ;
static const uint8_t P9N2_PU_GPIO_INT_ENABLE_EN_2                                 = 2   ;

static const uint8_t P9N2_PU_GPIO_INT_POLARITY_POL_0                              = 0   ;
static const uint8_t P9N2_PU_GPIO_INT_POLARITY_POL_1                              = 1   ;
static const uint8_t P9N2_PU_GPIO_INT_POLARITY_POL_2                              = 2   ;

static const uint8_t P9N2_PU_GPIO_INT_STATUS_STAT_0                               = 0   ;
static const uint8_t P9N2_PU_GPIO_INT_STATUS_STAT_1                               = 1   ;
static const uint8_t P9N2_PU_GPIO_INT_STATUS_STAT_2                               = 2   ;

static const uint8_t P9N2_PU_GPIO_OUTPUT_DO_0                                     = 0   ;
static const uint8_t P9N2_PU_GPIO_OUTPUT_DO_1                                     = 1   ;
static const uint8_t P9N2_PU_GPIO_OUTPUT_DO_2                                     = 2   ;

static const uint8_t P9N2_PU_GPIO_OUTPUT_EN_DO_0                                  = 0   ;
static const uint8_t P9N2_PU_GPIO_OUTPUT_EN_DO_1                                  = 1   ;
static const uint8_t P9N2_PU_GPIO_OUTPUT_EN_DO_2                                  = 2   ;

static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMSELMATCH                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMSELMATCH_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR_LEN                    = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_POISON                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_GRANULE                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE                        = 28  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_RESERVED2                   = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MASK                        = 33  ;
static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MASK_LEN                    = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MEMSELMATCH              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MEMSELMATCH_LEN          = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_ADDR_LEN                 = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_POISON                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_GRANULE                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_SIZE                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_SIZE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MODE                     = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MODE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_RESERVED2                = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MASK                     = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MASK_LEN                 = 7   ;

static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0                    = 0   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1                    = 1   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2                    = 2   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3                    = 3   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4                    = 4   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5                    = 5   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6                    = 6   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7                    = 7   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8                    = 8   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9                    = 9   ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10                   = 10  ;
static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11                   = 11  ;

static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0                    = 0   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1                    = 1   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2                    = 2   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3                    = 3   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4                    = 4   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5                    = 5   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6                    = 6   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7                    = 7   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8                    = 8   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9                    = 9   ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10                   = 10  ;
static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11                   = 11  ;

static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0                    = 0   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1                    = 1   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2                    = 2   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3                    = 3   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4                    = 4   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5                    = 5   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6                    = 6   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7                    = 7   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8                    = 8   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9                    = 9   ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10                   = 10  ;
static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11                   = 11  ;

static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN0                           = 0   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN1                           = 1   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN2                           = 2   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN3                           = 3   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN4                           = 4   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN5                           = 5   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN6                           = 6   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN7                           = 7   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN8                           = 8   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN9                           = 9   ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN10                          = 10  ;
static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN11                          = 11  ;

static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_NEAR_HISTORY                = 0   ;
static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_FAR_HISTORY                 = 1   ;
static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_EXTRA_HASH_ACCESSES         = 2   ;
static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_EXTRA_FIFO_ACCESSES         = 3   ;
static const uint8_t P9N2_PU_GZIP_CONTROL_REG_HASH_SIZE_MASK                      = 8   ;
static const uint8_t P9N2_PU_GZIP_CONTROL_REG_HASH_SIZE_MASK_LEN                  = 8   ;

static const uint8_t P9N2_PU_GZIP_ERRRPT_HOLD_REG_HOLD                            = 0   ;
static const uint8_t P9N2_PU_GZIP_ERRRPT_HOLD_REG_HOLD_LEN                        = 12  ;

static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID             = 4   ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN         = 12  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID              = 20  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN          = 20  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID              = 44  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN          = 16  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE           = 63  ;

static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                  = 8   ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN              = 46  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE             = 54  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN         = 3   ;

static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET     = 4   ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8   ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED          = 15  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN      = 9   ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX          = 27  ;
static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN      = 9   ;

static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID             = 4   ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN         = 12  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID              = 20  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN          = 20  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID              = 44  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN          = 16  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE           = 63  ;

static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                  = 8   ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN              = 46  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE             = 54  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN         = 3   ;

static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET     = 4   ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8   ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED          = 15  ;
static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN      = 9   ;

static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_LOW                                = 0   ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_LOW_LEN                            = 5   ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_HIGH                               = 5   ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_HIGH_LEN                           = 5   ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_THRESHOLD                          = 10  ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_SRC_DDE                            = 11  ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_SRC_DDE_LEN                        = 8   ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_TARGET_DDE                         = 19  ;
static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_TARGET_DDE_LEN                     = 8   ;

static const uint8_t P9N2_PEC_HANG_PULSE_0_REG_0                                  = 0   ;
static const uint8_t P9N2_PEC_HANG_PULSE_0_REG_0_LEN                              = 6   ;
static const uint8_t P9N2_PEC_HANG_PULSE_0_REG_SUPPRESS                           = 6   ;

static const uint8_t P9N2_PEC_HANG_PULSE_1_REG_1                                  = 0   ;
static const uint8_t P9N2_PEC_HANG_PULSE_1_REG_1_LEN                              = 6   ;
static const uint8_t P9N2_PEC_HANG_PULSE_1_REG_SUPPRESS                           = 6   ;

static const uint8_t P9N2_PEC_HANG_PULSE_2_REG_2                                  = 0   ;
static const uint8_t P9N2_PEC_HANG_PULSE_2_REG_2_LEN                              = 6   ;
static const uint8_t P9N2_PEC_HANG_PULSE_2_REG_SUPPRESS                           = 6   ;

static const uint8_t P9N2_PEC_HANG_PULSE_3_REG_3                                  = 0   ;
static const uint8_t P9N2_PEC_HANG_PULSE_3_REG_3_LEN                              = 6   ;
static const uint8_t P9N2_PEC_HANG_PULSE_3_REG_SUPPRESS                           = 6   ;

static const uint8_t P9N2_PEC_HANG_PULSE_4_REG_4                                  = 0   ;
static const uint8_t P9N2_PEC_HANG_PULSE_4_REG_4_LEN                              = 6   ;
static const uint8_t P9N2_PEC_HANG_PULSE_4_REG_SUPPRESS                           = 6   ;

static const uint8_t P9N2_PEC_HANG_PULSE_5_REG_5                                  = 0   ;
static const uint8_t P9N2_PEC_HANG_PULSE_5_REG_5_LEN                              = 6   ;
static const uint8_t P9N2_PEC_HANG_PULSE_5_REG_SUPPRESS                           = 6   ;

static const uint8_t P9N2_PEC_HANG_PULSE_6_REG_6                                  = 0   ;
static const uint8_t P9N2_PEC_HANG_PULSE_6_REG_6_LEN                              = 6   ;
static const uint8_t P9N2_PEC_HANG_PULSE_6_REG_SUPPRESS                           = 6   ;

static const uint8_t P9N2_PU_HCA_BAR_ADDR                                         = 8   ;
static const uint8_t P9N2_PU_HCA_BAR_ADDR_LEN                                     = 24  ;
static const uint8_t P9N2_PU_HCA_BAR_RANGE                                        = 32  ;
static const uint8_t P9N2_PU_HCA_BAR_RANGE_LEN                                    = 11  ;
static const uint8_t P9N2_PU_HCA_BAR_PAGE_SIZE_64K                                = 62  ;
static const uint8_t P9N2_PU_HCA_BAR_VALID                                        = 63  ;

static const uint8_t P9N2_PU_HCA_COUNT_BAR_ADDR                                   = 21  ;
static const uint8_t P9N2_PU_HCA_COUNT_BAR_ADDR_LEN                               = 24  ;
static const uint8_t P9N2_PU_HCA_COUNT_BAR_VALID                                  = 63  ;

static const uint8_t P9N2_PU_HCA_DECAY1_DECAY_SCOM_VALID                          = 0   ;
static const uint8_t P9N2_PU_HCA_DECAY1_DECAY_SCOM_COUNT                          = 32  ;
static const uint8_t P9N2_PU_HCA_DECAY1_DECAY_SCOM_COUNT_LEN                      = 32  ;

static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_SCOM_DELAY                          = 0   ;
static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_SCOM_DELAY_LEN                      = 30  ;
static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR_COND                           = 30  ;
static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR_COND_LEN                       = 11  ;
static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR                                = 41  ;
static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR_LEN                            = 16  ;

static const uint8_t P9N2_PU_HCA_DROP_CASTOUT_COUNTER                             = 16  ;
static const uint8_t P9N2_PU_HCA_DROP_CASTOUT_COUNTER_LEN                         = 16  ;

static const uint8_t P9N2_PU_HCA_MIRROR_BAR_ADDR                                  = 8   ;
static const uint8_t P9N2_PU_HCA_MIRROR_BAR_ADDR_LEN                              = 25  ;
static const uint8_t P9N2_PU_HCA_MIRROR_BAR_VALID                                 = 63  ;

static const uint8_t P9N2_PU_HCA_MODES_PB_32_1                                    = 3   ;
static const uint8_t P9N2_PU_HCA_MODES_PB_16_1                                    = 4   ;
static const uint8_t P9N2_PU_HCA_MODES_TRACE_SELECT                               = 5   ;
static const uint8_t P9N2_PU_HCA_MODES_TRACE_SELECT_LEN                           = 8   ;
static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_CMD                           = 16  ;
static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_CMD_LEN                       = 5   ;
static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_DATA                          = 21  ;
static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_DATA_LEN                      = 5   ;
static const uint8_t P9N2_PU_HCA_MODES_EPSILON_COUNT                              = 33  ;
static const uint8_t P9N2_PU_HCA_MODES_EPSILON_COUNT_LEN                          = 12  ;
static const uint8_t P9N2_PU_HCA_MODES_EPSILON_DIVIDER                            = 45  ;
static const uint8_t P9N2_PU_HCA_MODES_EPSILON_DIVIDER_LEN                        = 4   ;

static const uint8_t P9N2_PU_HCA_REF_BAR_ADDR                                     = 21  ;
static const uint8_t P9N2_PU_HCA_REF_BAR_ADDR_LEN                                 = 25  ;
static const uint8_t P9N2_PU_HCA_REF_BAR_VALID                                    = 63  ;

static const uint8_t P9N2_PEC_HEARTBEAT_REG_DEAD                                  = 0   ;

static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_XATS                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_XATS_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR0                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR1                   = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ0                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB0                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ1                   = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB1                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_INTS                   = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_INTS_LEN               = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_XATS                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_XATS_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR0                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR1                   = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ0                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB0                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ1                   = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB1                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_INTS                   = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_INTS_LEN               = 6   ;

static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1                      = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0                      = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0                      = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1                      = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_INTS                      = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_INTS_LEN                  = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_XATS                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_XATS_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR0                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR1                   = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ0                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB0                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ1                   = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB1                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_INTS                   = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_INTS_LEN               = 6   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_XATS                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_XATS_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR0                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR1                   = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ0                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB0                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB0_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ1                   = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB1                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB1_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_INTS                   = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_INTS_LEN               = 6   ;

static const uint8_t P9N2_PEC_HOSTATTN_IN0                                        = 0   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN1                                        = 1   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN2                                        = 2   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN3                                        = 3   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN4                                        = 4   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN5                                        = 5   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN6                                        = 6   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN7                                        = 7   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN8                                        = 8   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN9                                        = 9   ;
static const uint8_t P9N2_PEC_HOSTATTN_IN10                                       = 10  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN11                                       = 11  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN12                                       = 12  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN13                                       = 13  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN14                                       = 14  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN15                                       = 15  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN16                                       = 16  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN17                                       = 17  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN18                                       = 18  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN19                                       = 19  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN20                                       = 20  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN21                                       = 21  ;
static const uint8_t P9N2_PEC_HOSTATTN_IN22                                       = 22  ;

static const uint8_t P9N2_PEC_HOSTATTN_MASK_IN                                    = 0   ;
static const uint8_t P9N2_PEC_HOSTATTN_MASK_IN_LEN                                = 22  ;

static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO               = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN           = 5   ;
static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT                     = 5   ;
static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN                 = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR             = 9   ;
static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF                 = 10  ;
static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_DIS_OPER_HANG                     = 11  ;

static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO               = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN           = 5   ;
static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT                     = 5   ;
static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN                 = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR             = 9   ;
static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF                 = 10  ;
static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_DIS_OPER_HANG                     = 11  ;

static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_TRIG                             = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_TRIG_LEN                         = 2   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_MARK                             = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_MARK_LEN                         = 2   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_DBG0_STOP                        = 6   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_DBG1_STOP                        = 7   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_RUN_STOP                         = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_OTHER_DBG0_STOP                  = 9   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1012                        = 10  ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1012_LEN                    = 3   ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_XSTOP_STOP                       = 13  ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1415                        = 14  ;
static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1415_LEN                    = 2   ;

static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_TRIG                             = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_TRIG_LEN                         = 2   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_MARK                             = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_MARK_LEN                         = 2   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_DBG0_STOP                        = 6   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_DBG1_STOP                        = 7   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_RUN_STOP                         = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_OTHER_DBG0_STOP                  = 9   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1012                        = 10  ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1012_LEN                    = 3   ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_XSTOP_STOP                       = 13  ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1415                        = 14  ;
static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1415_LEN                    = 2   ;

static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_PAT                              = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_PAT_LEN                          = 23  ;
static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT                        = 27  ;
static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT_LEN                    = 5   ;
static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_MASK                             = 32  ;
static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_MASK_LEN                         = 23  ;
static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK                       = 59  ;
static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK_LEN                   = 5   ;

static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_PAT                              = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_PAT_LEN                          = 23  ;
static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT                        = 27  ;
static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT_LEN                    = 5   ;
static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_MASK                             = 32  ;
static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_MASK_LEN                         = 23  ;
static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK                       = 59  ;
static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK_LEN                   = 5   ;

static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0                    = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1                    = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2                    = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3                    = 12  ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4                    = 16  ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5                    = 20  ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0                    = 24  ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1                    = 28  ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2                    = 32  ;
static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN                = 4   ;

static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0                    = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1                    = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2                    = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3                    = 12  ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4                    = 16  ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5                    = 20  ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0                    = 24  ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1                    = 28  ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN                = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2                    = 32  ;
static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN                = 4   ;

static const uint8_t P9N2_PU_HTM0_HTM_LAST_ADDRESS                                = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_LAST_ADDRESS_LEN                            = 49  ;

static const uint8_t P9N2_PU_HTM1_HTM_LAST_ADDRESS                                = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_LAST_ADDRESS_LEN                            = 49  ;

static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_ALLOC                             = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SCOPE                             = 1   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SCOPE_LEN                         = 3   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_PRIORITY                          = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SIZE_SMALL                        = 5   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SPARE67                           = 6   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SPARE67_LEN                       = 2   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_BASE                              = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_BASE_LEN                          = 32  ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SIZE                              = 40  ;
static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SIZE_LEN                          = 9   ;

static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_ALLOC                             = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SCOPE                             = 1   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SCOPE_LEN                         = 3   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_PRIORITY                          = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SIZE_SMALL                        = 5   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SPARE67                           = 6   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SPARE67_LEN                       = 2   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_BASE                              = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_BASE_LEN                          = 32  ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SIZE                              = 40  ;
static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SIZE_LEN                          = 9   ;

static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL                      = 1   ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE3                           = 3   ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CAPTURE                          = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CAPTURE_LEN                      = 9   ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_WRAP                             = 13  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_DIS_TSTAMP                       = 14  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SINGLE_TSTAMP                    = 15  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE16                          = 16  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_MARKERS_ONLY                     = 17  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE            = 18  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE                 = 19  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN             = 3   ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_WRITETOIO                        = 22  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE23                          = 23  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_VGTARGET                         = 24  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_VGTARGET_LEN                     = 16  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE4043                        = 40  ;
static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE4043_LEN                    = 4   ;

static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL                      = 1   ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE3                           = 3   ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CAPTURE                          = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CAPTURE_LEN                      = 9   ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_WRAP                             = 13  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_DIS_TSTAMP                       = 14  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SINGLE_TSTAMP                    = 15  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE16                          = 16  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_MARKERS_ONLY                     = 17  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE            = 18  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE                 = 19  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN             = 3   ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_WRITETOIO                        = 22  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE23                          = 23  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_VGTARGET                         = 24  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_VGTARGET_LEN                     = 16  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE4043                        = 40  ;
static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE4043_LEN                    = 4   ;

static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE                     = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE_LEN                 = 2   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_CRESP_OV                  = 2   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_REPAIR                    = 3   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_BUF_WAIT                  = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_TRIG_DROPPED_Q                  = 5   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                = 6   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_REC_DROPPED_Q                   = 7   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_INIT                      = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_PREREQ                    = 9   ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_READY                     = 10  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_TRACING                   = 11  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED                    = 12  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_FLUSH                     = 13  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE                  = 14  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_ENABLE                    = 15  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_STAMP                     = 16  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_SCOM_ERROR                      = 17  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_PARITY_ERROR                    = 18  ;
static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_INVALID_CRESP                   = 19  ;

static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE                     = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE_LEN                 = 2   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_CRESP_OV                  = 2   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_REPAIR                    = 3   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_BUF_WAIT                  = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_TRIG_DROPPED_Q                  = 5   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                = 6   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_REC_DROPPED_Q                   = 7   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_INIT                      = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_PREREQ                    = 9   ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_READY                     = 10  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_TRACING                   = 11  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_PAUSED                    = 12  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_FLUSH                     = 13  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_COMPLETE                  = 14  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_ENABLE                    = 15  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_STAMP                     = 16  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_SCOM_ERROR                      = 17  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_PARITY_ERROR                    = 18  ;
static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_INVALID_CRESP                   = 19  ;

static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_START                            = 0   ;
static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_STOP                             = 1   ;
static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_PAUSE                            = 2   ;
static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_STOP_ALT                         = 3   ;
static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_RESET                            = 4   ;
static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_MARK_VALID                       = 5   ;
static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE                        = 6   ;
static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE_LEN                    = 10  ;

static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_START                            = 0   ;
static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_STOP                             = 1   ;
static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_PAUSE                            = 2   ;
static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_STOP_ALT                         = 3   ;
static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_RESET                            = 4   ;
static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_MARK_VALID                       = 5   ;
static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE                        = 6   ;
static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE_LEN                    = 10  ;

static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT                         = 1   ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT_LEN                     = 7   ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT               = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN           = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK                        = 17  ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK_LEN                    = 7   ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK              = 24  ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN          = 8   ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_INVERT                      = 32  ;
static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT            = 33  ;

static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT                         = 1   ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT_LEN                     = 7   ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT               = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN           = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK                        = 17  ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK_LEN                    = 7   ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK              = 24  ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN          = 8   ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_INVERT                      = 32  ;
static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT            = 33  ;

static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0                     = 32  ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0_LEN                 = 8   ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_B_LBUS_PARITY_ERR1_0               = 40  ;

static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1                     = 32  ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1_LEN                 = 8   ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_C_LBUS_PARITY_ERR1_1               = 40  ;

static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2                     = 32  ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2_LEN                 = 8   ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_D_LBUS_PARITY_ERR1_2               = 40  ;

static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3                     = 32  ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3_LEN                 = 8   ;
static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_E_LBUS_PARITY_ERR1_3               = 40  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ0                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ0_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ0                    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ0_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_BLOCKY0                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_ONESHOT0                  = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST0                     = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST0_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ1                    = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ1_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ1                    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ1_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_BLOCKY1                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_ONESHOT1                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST1                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST1_LEN                 = 8   ;

static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0                       = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY0                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT0                     = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST0                        = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST0_LEN                    = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1                       = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1                       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY1                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT1                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST1                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST1_LEN                    = 8   ;

static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ0                      = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ0_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ0                      = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ0_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_BLOCKY0                     = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_ONESHOT0                    = 7   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST0                       = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST0_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ1                      = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ1_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ1                      = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ1_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_BLOCKY1                     = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_ONESHOT1                    = 23  ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST1                       = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST1_LEN                   = 8   ;

static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0                       = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY0                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT0                     = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST0                        = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST0_LEN                    = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1                       = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1                       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY1                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT1                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST1                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST1_LEN                    = 8   ;

static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0                       = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY0                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT0                     = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST0                        = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST0_LEN                    = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1                       = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1                       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY1                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT1                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST1                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST1_LEN                    = 8   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ0                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ0_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ0                    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ0_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_BLOCKY0                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_ONESHOT0                  = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST0                     = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST0_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ1                    = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ1_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ1                    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ1_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_BLOCKY1                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_ONESHOT1                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST1                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST1_LEN                 = 8   ;

static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ0                           = 0   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ0_LEN                       = 4   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ0                           = 4   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ0_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_BLOCKY0                          = 6   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_ONESHOT0                         = 7   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST0                            = 8   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST0_LEN                        = 8   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ1                           = 16  ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ1_LEN                       = 4   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ1                           = 20  ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_BLOCKY1                          = 22  ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_ONESHOT1                         = 23  ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST1                            = 24  ;
static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST1_LEN                        = 8   ;

static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0                       = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY0                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT0                     = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST0                        = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST0_LEN                    = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1                       = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1                       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY1                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT1                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST1                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST1_LEN                    = 8   ;

static const uint8_t P9N2__CTL_INHIBIT_CONFIG_LFREQ                               = 0   ;
static const uint8_t P9N2__CTL_INHIBIT_CONFIG_LFREQ_LEN                           = 4   ;
static const uint8_t P9N2__CTL_INHIBIT_CONFIG_IFREQ                               = 4   ;
static const uint8_t P9N2__CTL_INHIBIT_CONFIG_DEST                                = 5   ;
static const uint8_t P9N2__CTL_INHIBIT_CONFIG_DEST_LEN                            = 3   ;

static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ0                        = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ0_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ0                        = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ0_LEN                    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_BLOCKY0                       = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_ONESHOT0                      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST0                         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST0_LEN                     = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ1                        = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ1_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ1                        = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ1_LEN                    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_BLOCKY1                       = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_ONESHOT1                      = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST1                         = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST1_LEN                     = 8   ;

static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0                       = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY0                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT0                     = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST0                        = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST0_LEN                    = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1                       = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1                       = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY1                      = 22  ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT1                     = 23  ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST1                        = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST1_LEN                    = 8   ;

static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0                       = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY0                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT0                     = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST0                        = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST0_LEN                    = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1                       = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1                       = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY1                      = 22  ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT1                     = 23  ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST1                        = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST1_LEN                    = 8   ;

static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ0                                = 0   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ0_LEN                            = 4   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ0                                = 4   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ0_LEN                            = 2   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_BLOCKY0                               = 6   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_ONESHOT0                              = 7   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST0                                 = 8   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST0_LEN                             = 8   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ1                                = 16  ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ1_LEN                            = 4   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ1                                = 20  ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ1_LEN                            = 2   ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_BLOCKY1                               = 22  ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_ONESHOT1                              = 23  ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST1                                 = 24  ;
static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST1_LEN                             = 8   ;

static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ0                           = 0   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ0_LEN                       = 4   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ0                           = 4   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ0_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_BLOCKY0                          = 6   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_ONESHOT0                         = 7   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST0                            = 8   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST0_LEN                        = 8   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ1                           = 16  ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ1_LEN                       = 4   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ1                           = 20  ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_BLOCKY1                          = 22  ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_ONESHOT1                         = 23  ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST1                            = 24  ;
static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST1_LEN                        = 8   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ0                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ0_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ0                    = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ0_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_BLOCKY0                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_ONESHOT0                  = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST0                     = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST0_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ1                    = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ1_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ1                    = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ1_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_BLOCKY1                   = 22  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_ONESHOT1                  = 23  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST1                     = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST1_LEN                 = 8   ;

static const uint8_t P9N2_PEC_INJECT_REG_THERM_TRIP                               = 0   ;
static const uint8_t P9N2_PEC_INJECT_REG_THERM_TRIP_LEN                           = 2   ;
static const uint8_t P9N2_PEC_INJECT_REG_THERM_MODE                               = 2   ;
static const uint8_t P9N2_PEC_INJECT_REG_THERM_MODE_LEN                           = 2   ;

static const uint8_t P9N2_PHB_INTBAR_REG_PE_INT_BAR                               = 0   ;
static const uint8_t P9N2_PHB_INTBAR_REG_PE_INT_BAR_LEN                           = 28  ;

static const uint8_t P9N2_PEC_STACK0_INTBAR_REG_PE_INT_BAR                        = 0   ;
static const uint8_t P9N2_PEC_STACK0_INTBAR_REG_PE_INT_BAR_LEN                    = 28  ;

static const uint8_t P9N2_PU_INTERRUPTS_B_PEEK_DATA1_0                            = 32  ;
static const uint8_t P9N2_PU_INTERRUPTS_B_PEEK_DATA1_0_LEN                        = 8   ;
static const uint8_t P9N2_PU_INTERRUPTS_B_LBUS_PARITY_ERR1_0                      = 40  ;

static const uint8_t P9N2_PU_INTERRUPTS_C_PEEK_DATA1_1                            = 32  ;
static const uint8_t P9N2_PU_INTERRUPTS_C_PEEK_DATA1_1_LEN                        = 8   ;
static const uint8_t P9N2_PU_INTERRUPTS_C_LBUS_PARITY_ERR1_1                      = 40  ;

static const uint8_t P9N2_PU_INTERRUPTS_D_PEEK_DATA1_2                            = 32  ;
static const uint8_t P9N2_PU_INTERRUPTS_D_PEEK_DATA1_2_LEN                        = 8   ;
static const uint8_t P9N2_PU_INTERRUPTS_D_LBUS_PARITY_ERR1_2                      = 40  ;

static const uint8_t P9N2_PU_INTERRUPTS_E_PEEK_DATA1_3                            = 32  ;
static const uint8_t P9N2_PU_INTERRUPTS_E_PEEK_DATA1_3_LEN                        = 8   ;
static const uint8_t P9N2_PU_INTERRUPTS_E_LBUS_PARITY_ERR1_3                      = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_COND_B_INVALID_CMD_0                       = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_LBUS_PARITY_ERROR_0                 = 17  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_BE_OV_ERROR_0                       = 18  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_BE_ACC_ERROR_0                      = 19  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_ARBITRATION_LOST_ERROR_0            = 20  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_NACK_RECEIVED_ERROR_0               = 21  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_DATA_REQUEST_0                      = 22  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_STOP_ERROR_0                        = 24  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_PEEK_DATA1_0                        = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_PEEK_DATA1_0_LEN                    = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_COND_B_LBUS_PARITY_ERR1_0                  = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_COND_C_INVALID_CMD_1                       = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_LBUS_PARITY_ERROR_1                 = 17  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_BE_OV_ERROR_1                       = 18  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_BE_ACC_ERROR_1                      = 19  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_ARBITRATION_LOST_ERROR_1            = 20  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_NACK_RECEIVED_ERROR_1               = 21  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_DATA_REQUEST_1                      = 22  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_STOP_ERROR_1                        = 24  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_PEEK_DATA1_1                        = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_PEEK_DATA1_1_LEN                    = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_COND_C_LBUS_PARITY_ERR1_1                  = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_COND_D_INVALID_CMD_2                       = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_LBUS_PARITY_ERROR_2                 = 17  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_BE_OV_ERROR_2                       = 18  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_BE_ACC_ERROR_2                      = 19  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_ARBITRATION_LOST_ERROR_2            = 20  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_NACK_RECEIVED_ERROR_2               = 21  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_DATA_REQUEST_2                      = 22  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_STOP_ERROR_2                        = 24  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_PEEK_DATA1_2                        = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_PEEK_DATA1_2_LEN                    = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_COND_D_LBUS_PARITY_ERR1_2                  = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_COND_E_INVALID_CMD_3                       = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_LBUS_PARITY_ERROR_3                 = 17  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_BE_OV_ERROR_3                       = 18  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_BE_ACC_ERROR_3                      = 19  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_ARBITRATION_LOST_ERROR_3            = 20  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_NACK_RECEIVED_ERROR_3               = 21  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_DATA_REQUEST_3                      = 22  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_STOP_ERROR_3                        = 24  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_PEEK_DATA1_3                        = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_PEEK_DATA1_3_LEN                    = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_COND_E_LBUS_PARITY_ERR1_3                  = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_B_INT_0                      = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_B_INT_0_LEN                  = 16  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_C_INT_1                      = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_C_INT_1_LEN                  = 16  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_D_INT_2                      = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_D_INT_2_LEN                  = 16  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_E_INT_3                      = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_E_INT_3_LEN                  = 16  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0                 = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0_LEN             = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0          = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0_LEN      = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_LBUS_PARITY_ERR1_0    = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1                 = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1_LEN             = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1          = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1_LEN      = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_LBUS_PARITY_ERR1_1    = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2                 = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2_LEN             = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2          = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2_LEN      = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_LBUS_PARITY_ERR1_2    = 40  ;

static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3                 = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3_LEN             = 16  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3          = 32  ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3_LEN      = 8   ;
static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_LBUS_PARITY_ERR1_3    = 40  ;

static const uint8_t P9N2__CTL_INT_0_CONFIG_0                                     = 0   ;
static const uint8_t P9N2__CTL_INT_0_CONFIG_0_LEN                                 = 64  ;

static const uint8_t P9N2__CTL_INT_1_CONFIG_1                                     = 0   ;
static const uint8_t P9N2__CTL_INT_1_CONFIG_1_LEN                                 = 64  ;

static const uint8_t P9N2_PU_NPU_SM0_INT_2_CONFIG_2                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_INT_2_CONFIG_2_LEN                           = 64  ;

static const uint8_t P9N2__CTL_INT_BAR_CONFIG                                     = 0   ;
static const uint8_t P9N2__CTL_INT_BAR_CONFIG_LEN                                 = 39  ;

static const uint8_t P9N2_PU_INT_CQ_ACTION0_ACTION0                               = 0   ;
static const uint8_t P9N2_PU_INT_CQ_ACTION0_ACTION0_LEN                           = 64  ;

static const uint8_t P9N2_PU_INT_CQ_ACTION1_ACTION1                               = 0   ;
static const uint8_t P9N2_PU_INT_CQ_ACTION1_ACTION1_LEN                           = 64  ;

static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_DIS_ECCCHK_IN                         = 0   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2                 = 1   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2_LEN             = 3   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3                 = 4   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3                 = 8   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3                 = 12  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3                    = 16  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3_LEN                = 4   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_BLOCK_CMD_OVERLAP                     = 20  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_RESERVED_21_31                        = 21  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_RESERVED_21_31_LEN                    = 11  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5                   = 32  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5_LEN               = 6   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5                   = 38  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5_LEN               = 6   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5                   = 44  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5_LEN               = 6   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5                = 50  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5                = 56  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_RESERVED_62                           = 62  ;
static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_REINIT_CREDITS                        = 63  ;

static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4                       = 0   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4                       = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4                       = 10  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4                       = 15  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4                       = 20  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4                       = 25  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4                       = 30  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4                       = 35  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4                       = 40  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4                       = 45  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_ORDER_ALL                     = 50  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_RESERVED_51_63                        = 51  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_RESERVED_51_63_LEN                    = 13  ;

static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_BAR_MODE                      = 0   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_PUMP_MODE                          = 1   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_PHYP_SCOPE                         = 2   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_INIT                               = 3   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_MODE_128K_VP                       = 4   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_EXT_MASK_EN_15_21             = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_EXT_MASK_EN_15_21_LEN         = 7   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_SMF_CONFIG_0_1                     = 12  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_SMF_CONFIG_0_1_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_OPT                           = 14  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_OPT_LEN                       = 2   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_RESERVED_16                        = 16  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_GROUP_ID_0_3                       = 17  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_GROUP_ID_0_3_LEN                   = 4   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_CHIP_ID_0_2                        = 21  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_CHIP_ID_0_2_LEN                    = 3   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_UNIT_ID_0_7                        = 24  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_UNIT_ID_0_7_LEN                    = 8   ;

static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4                      = 0   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4                      = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4                       = 10  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4                       = 15  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4                       = 20  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4                       = 25  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4_LEN                   = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4                      = 30  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4                      = 35  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4                      = 40  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4                      = 45  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4                      = 50  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4                      = 55  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_RESERVED_60_63                       = 60  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_RESERVED_60_63_LEN                   = 4   ;

static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4                      = 0   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4                      = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4                      = 10  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4                      = 15  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4_LEN                  = 5   ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_RESERVED_20_31                       = 20  ;
static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_RESERVED_20_31_LEN                   = 12  ;

static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2                   = 0   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2                   = 3   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2                   = 6   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2                   = 9   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_RESERVED_12_23                       = 12  ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_RESERVED_12_23_LEN                   = 12  ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15                     = 24  ;
static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15_LEN                 = 16  ;

static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_INFO_CAPTURED                       = 0   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD0_ADDR_PERR                     = 1   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD1_ADDR_PERR                     = 2   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD2_ADDR_PERR                     = 3   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD3_ADDR_PERR                     = 4   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD0_TTAG_PERR                     = 5   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD1_TTAG_PERR                     = 6   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD2_TTAG_PERR                     = 7   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD3_TTAG_PERR                     = 8   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR0_TTAG_PERR                       = 9   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR1_TTAG_PERR                       = 10  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR2_TTAG_PERR                       = 11  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR3_TTAG_PERR                       = 12  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR0_ATAG_PERR                       = 13  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR1_ATAG_PERR                       = 14  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR2_ATAG_PERR                       = 15  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR3_ATAG_PERR                       = 16  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RTAG_PERR                           = 17  ;

static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_INFO_CAPTURED                       = 0   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_CI_WRITE                            = 1   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_CI_READ                             = 2   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_DMA_WRITE                           = 3   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TSIZE_4_6                           = 4   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TSIZE_4_6_LEN                       = 3   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3                         = 7   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3_LEN                     = 4   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TTAG_0_16                           = 11  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TTAG_0_16_LEN                       = 17  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_ADDRESS_28_63                       = 28  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_ADDRESS_28_63_LEN                   = 36  ;

static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_INFO_CAPTURED                       = 0   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RESERVED_1_5                        = 1   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RESERVED_1_5_LEN                    = 5   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_HI                                  = 6   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_LO                                  = 7   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7                         = 8   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_HI_0_7                          = 16  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_HI_0_7_LEN                      = 8   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_LO_0_7                          = 24  ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_LO_0_7_LEN                      = 8   ;

static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_INFO_CAPTURED                       = 0   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_STQ_FSM_PERR                        = 1   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_LDQ_FSM_PERR                        = 2   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_WRQ_FSM_PERR                        = 3   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_RDQ_FSM_PERR                        = 4   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_INTQ_FSM_PERR                       = 5   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_WRQ_OVERFLOW                        = 6   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_RDQ_OVERFLOW                        = 7   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_INTQ_OVERFLOW                       = 8   ;

static const uint8_t P9N2_PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48                        = 0   ;
static const uint8_t P9N2_PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48_LEN                    = 49  ;

static const uint8_t P9N2_PU_INT_CQ_FIR_PI_ECC_CE                                 = 0   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PI_ECC_UE                                 = 1   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PI_ECC_SUE                                = 2   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_ST_ECC_CE                                 = 3   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_ST_ECC_UE                                 = 4   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_LD_ECC_CE                                 = 5   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_LD_ECC_UE                                 = 6   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_CL_ECC_CE                                 = 7   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_CL_ECC_UE                                 = 8   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_WR_ECC_CE                                 = 9   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_WR_ECC_UE                                 = 10  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RD_ECC_CE                                 = 11  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RD_ECC_UE                                 = 12  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_AI_ECC_CE                                 = 13  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_AI_ECC_UE                                 = 14  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR                       = 15  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_AIB_IN_CMD_PERR                           = 16  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR                       = 17  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PB_PARITY_ERROR                           = 18  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1                          = 19  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2                          = 20  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3                          = 21  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA                   = 22  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_MRT_ERR_NOT_VALID                         = 23  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_MRT_ERR_PSIZE                             = 24  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_SCOM_S_ERR                                = 25  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_TCTXT_PRESP_ERROR                         = 26  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_WRQ_OP_HANG                               = 27  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_OP_HANG                               = 28  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_INTQ_OP_HANG                              = 29  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_DATA_HANG                             = 30  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_STQ_DATA_HANG                             = 31  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_LDQ_DATA_HANG                             = 32  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_WRQ_BAD_CRESP                             = 33  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_BAD_CRESP                             = 34  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_INTQ_BAD_CRESP                            = 35  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_BAD_128K_VP_OP                            = 36  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_ABORT_OP                              = 37  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_CRD_PERR                               = 38  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR                         = 39  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_CRD_PERR                               = 40  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR                         = 41  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR                         = 42  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_ABORT_TRM                             = 43  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_UNSOLICITED_CRESP                         = 44  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_UNSOLICITED_PBDATA                        = 45  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_FIR_PARITY_ERR                            = 46  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PGM_DBG_ACCESS                            = 47  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_RESERVED_48                               = 48  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2                        = 49  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN                    = 3   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2                        = 52  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN                    = 3   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_INFO_ERROR_0_2                         = 55  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN                     = 3   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1                        = 58  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN                    = 2   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1                        = 60  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN                    = 2   ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_INFO_ERROR_0_1                         = 62  ;
static const uint8_t P9N2_PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN                     = 2   ;

static const uint8_t P9N2_PU_INT_CQ_FIRMASK_FIR_MASK                              = 0   ;
static const uint8_t P9N2_PU_INT_CQ_FIRMASK_FIR_MASK_LEN                          = 64  ;

static const uint8_t P9N2_PU_INT_CQ_IC_BAR_VALID                                  = 0   ;
static const uint8_t P9N2_PU_INT_CQ_IC_BAR_PAGE_SIZE_64K                          = 1   ;
static const uint8_t P9N2_PU_INT_CQ_IC_BAR_ADDR_8_48                              = 8   ;
static const uint8_t P9N2_PU_INT_CQ_IC_BAR_ADDR_8_48_LEN                          = 41  ;

static const uint8_t P9N2_PU_INT_CQ_MSGSND_CORES_ENABLED_0_23                     = 0   ;
static const uint8_t P9N2_PU_INT_CQ_MSGSND_CORES_ENABLED_0_23_LEN                 = 24  ;

static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_LCL_POLL_BCST_RTY_MON               = 0   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_ALL_0_4                     = 1   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_ALL_0_4_LEN                 = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_0_4                     = 6   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_0_4_LEN                 = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_DROP_0_4                = 11  ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_DROP_0_4_LEN            = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_RMT_POLL_BCST_RTY_MON               = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_ALL_0_4                     = 17  ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_ALL_0_4_LEN                 = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_0_4                     = 22  ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_0_4_LEN                 = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_DROP_0_4                = 27  ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_DROP_0_4_LEN            = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_DROP_RESTORE_TIMER_0_2              = 32  ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_DROP_RESTORE_TIMER_0_2_LEN          = 3   ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_RESERVED_35_39                      = 35  ;
static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_RESERVED_35_39_LEN                  = 5   ;

static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_ECCCHK                            = 0   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_ECCCHK_STO                        = 1   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_2                            = 2   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_3                            = 3   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_4                            = 4   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_PC                      = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_VC                      = 6   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_LINUX_TRIG_MODE                       = 7   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1                     = 8   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1                         = 10  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_DMA_W                             = 12  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_STRICT_IPI_RULES                      = 13  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_ECC_CE                          = 14  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_ECC_UE                          = 15  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_ECC_SEL                         = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_SPEC_CILD_G                           = 17  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_IVE                      = 18  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_EQD                      = 19  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_HW                   = 20  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_SW                   = 21  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_TM_LOCAL                        = 22  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_VPC_ORDER                         = 23  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SYNC_ORDER                         = 24  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_25_31                        = 25  ;
static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_25_31_LEN                    = 7   ;

static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_ECCCHK_LDO                        = 0   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_ECCCHK_WRO                        = 1   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_ECCCHK_CLO                        = 2   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_7BIT_EQC_ORDER                     = 3   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_STRICT_ORDER                          = 4   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_MAX_SCOPE_INTRP                 = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_VG_SYS_INTRP                    = 6   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_INTRP                        = 7   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_HPC_READ                     = 8   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_DMA                          = 9   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_MASK_0_5                         = 10  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_MASK_0_5_LEN                     = 6   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_SLOW_CMD_RATE                         = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_RANDOM_BACKOFF                     = 17  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_POLL_BACKOFF                       = 18  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_CILD_BACKOFF                       = 19  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_CE                          = 20  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_UE                          = 21  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1                     = 22  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_INJECT                        = 24  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_CL_INJECT                       = 25  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_PR_INJECT                       = 26  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_HANG_ON_ADDR_ERROR                    = 27  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_HANG_ON_ACK_DEAD                      = 28  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_POLL_BCST_RTY_MON                     = 29  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4                  = 30  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4_LEN              = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4                  = 35  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4_LEN              = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4                  = 40  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4_LEN              = 5   ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_NN_RN                         = 45  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS                    = 46  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_G                             = 47  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_LN                            = 48  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_SKIP_G                                = 49  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_WRQ_CMD_REJ_DISABLE                   = 50  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_RDQ_CMD_REJ_DISABLE                   = 51  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_INTQ_CMD_REJ_DISABLE                  = 52  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_WRQ_INTRP_ORDER                   = 53  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_RDQ_INTRP_ORDER                   = 54  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_CI_WR                        = 55  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_CI_RD                        = 56  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_NGRP_INTRP_ORDER                  = 57  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_GRP_INTRP_ORDER                   = 58  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_RESERVED_59_63                        = 59  ;
static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_RESERVED_59_63_LEN                    = 5   ;

static const uint8_t P9N2_PU_INT_CQ_PC_BAR_VALID                                  = 0   ;
static const uint8_t P9N2_PU_INT_CQ_PC_BAR_ADDR_8_38                              = 8   ;
static const uint8_t P9N2_PU_INT_CQ_PC_BAR_ADDR_8_38_LEN                          = 31  ;

static const uint8_t P9N2_PU_INT_CQ_PC_BARM_ADDR_25_38                            = 25  ;
static const uint8_t P9N2_PU_INT_CQ_PC_BARM_ADDR_25_38_LEN                        = 14  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_0_COUNT_47                                = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_0_COUNT_47_LEN                            = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_1_COUNT_0_47                              = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_1_COUNT_0_47_LEN                          = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_2_COUNT_0_47                              = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_2_COUNT_0_47_LEN                          = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_3_COUNT_0_47                              = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_3_COUNT_0_47_LEN                          = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_4_COUNT_0_47                              = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_4_COUNT_0_47_LEN                          = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_5_COUNT_0_47                              = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_5_COUNT_0_47_LEN                          = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_6_COUNT_0_47                              = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_6_COUNT_0_47_LEN                          = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PMC_7_COUNT_0_47                              = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PMC_7_COUNT_0_47_LEN                          = 48  ;

static const uint8_t P9N2_PU_INT_CQ_PM_CTL_ENABLE_0_7                             = 0   ;
static const uint8_t P9N2_PU_INT_CQ_PM_CTL_ENABLE_0_7_LEN                         = 8   ;
static const uint8_t P9N2_PU_INT_CQ_PM_CTL_RESET_0_7                              = 8   ;
static const uint8_t P9N2_PU_INT_CQ_PM_CTL_RESET_0_7_LEN                          = 8   ;
static const uint8_t P9N2_PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1                     = 16  ;
static const uint8_t P9N2_PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_CQ_PM_CTL_GROUP_SEL_0_4                          = 18  ;
static const uint8_t P9N2_PU_INT_CQ_PM_CTL_GROUP_SEL_0_4_LEN                      = 5   ;

static const uint8_t P9N2_PU_INT_CQ_RST_CTL_SYNC_RESET                            = 0   ;
static const uint8_t P9N2_PU_INT_CQ_RST_CTL_QUIESCE_PB                            = 1   ;
static const uint8_t P9N2_PU_INT_CQ_RST_CTL_MASTER_IDLE                           = 2   ;
static const uint8_t P9N2_PU_INT_CQ_RST_CTL_SLAVE_IDLE                            = 3   ;
static const uint8_t P9N2_PU_INT_CQ_RST_CTL_PB_BAR_RESET                          = 4   ;
static const uint8_t P9N2_PU_INT_CQ_RST_CTL_RESERVED_5_7                          = 5   ;
static const uint8_t P9N2_PU_INT_CQ_RST_CTL_RESERVED_5_7_LEN                      = 3   ;

static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_HIST_DONE                             = 0   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_POLL_DONE                             = 1   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_BCAST_DONE                            = 2   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_ASSIGN_DONE                           = 3   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_BLK_UPDT_DONE                         = 4   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_Z                                     = 5   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_O                                     = 6   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_M                                     = 7   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_CRESP_0_4                             = 8   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_CRESP_0_4_LEN                         = 5   ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_RESERVED_13                           = 13  ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_COLLISON                              = 14  ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_PRECLUDE                              = 15  ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_ATAG_0_15                             = 16  ;
static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_ATAG_0_15_LEN                         = 16  ;

static const uint8_t P9N2_PU_INT_CQ_TAR_AUTO_INC                                  = 0   ;
static const uint8_t P9N2_PU_INT_CQ_TAR_TABLE_SEL_0_3                             = 12  ;
static const uint8_t P9N2_PU_INT_CQ_TAR_TABLE_SEL_0_3_LEN                         = 4   ;
static const uint8_t P9N2_PU_INT_CQ_TAR_ENTRY_SEL_0_5                             = 26  ;
static const uint8_t P9N2_PU_INT_CQ_TAR_ENTRY_SEL_0_5_LEN                         = 6   ;

static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_VALID                                 = 0   ;
static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_PAGE_SIZE_64K                         = 1   ;
static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_ADDR_8_49                             = 8   ;
static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_ADDR_8_49_LEN                         = 42  ;

static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_VALID                                 = 0   ;
static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_PAGE_SIZE_64K                         = 1   ;
static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_ADDR_8_49                             = 8   ;
static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_ADDR_8_49_LEN                         = 42  ;

static const uint8_t P9N2_PU_INT_CQ_VC_BAR_VALID                                  = 0   ;
static const uint8_t P9N2_PU_INT_CQ_VC_BAR_ADDR_8_37                              = 8   ;
static const uint8_t P9N2_PU_INT_CQ_VC_BAR_ADDR_8_37_LEN                          = 30  ;

static const uint8_t P9N2_PU_INT_CQ_VC_BARM_ADDR_22_37                            = 22  ;
static const uint8_t P9N2_PU_INT_CQ_VC_BARM_ADDR_22_37_LEN                        = 16  ;

static const uint8_t P9N2_PU_INT_CQ_WOF_WOF                                       = 0   ;
static const uint8_t P9N2_PU_INT_CQ_WOF_WOF_LEN                                   = 64  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_LVL                            = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_LVL_LEN                        = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_CQ                             = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_CQ_LEN                         = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_RSVD0                          = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_RSVD0_LEN                      = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_LVL                            = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_LVL_LEN                        = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_CQ                             = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_CQ_LEN                         = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_RSVD0                          = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_RSVD0_LEN                      = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_LVL                            = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_LVL_LEN                        = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_CQ                             = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_CQ_LEN                         = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_RSVD0                          = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_RSVD0_LEN                      = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_LVL                            = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_LVL_LEN                        = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_CQ                             = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_CQ_LEN                         = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_RSVD0                          = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_RSVD0_LEN                      = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_LVL                            = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_LVL_LEN                        = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_CQ                             = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_CQ_LEN                         = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_RSVD0                          = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_RSVD0_LEN                      = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_LVL                            = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_LVL_LEN                        = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_CQ                             = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_CQ_LEN                         = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_RSVD0                          = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_RSVD0_LEN                      = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_LVL                             = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_LVL_LEN                         = 35  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_CQ                              = 36  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_CQ_LEN                          = 12  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_RSVD0                           = 48  ;
static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_RSVD0_LEN                       = 16  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_DETAIL                         = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_DETAIL_LEN                     = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_RSVD0                          = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_RSVD0_LEN                      = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_DETAIL                         = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_DETAIL_LEN                     = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_RSVD0                          = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_RSVD0_LEN                      = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_DETAIL                         = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_DETAIL_LEN                     = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_RSVD0                          = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_RSVD0_LEN                      = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_DETAIL                         = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_DETAIL_LEN                     = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_RSVD0                          = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_RSVD0_LEN                      = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_DETAIL                         = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_DETAIL_LEN                     = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_RSVD0                          = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_RSVD0_LEN                      = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_VLD                            = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_DETAIL                         = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_DETAIL_LEN                     = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_RSVD0                          = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_RSVD0_LEN                      = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_VLD                             = 0   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_DETAIL                          = 1   ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_DETAIL_LEN                      = 32  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_RSVD0                           = 33  ;
static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_RSVD0_LEN                       = 31  ;

static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1                   = 0   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX                        = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX_LEN                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9                   = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX                        = 10  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX_LEN                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17                 = 16  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17_LEN             = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX                        = 18  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX_LEN                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25                 = 24  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25_LEN             = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX                        = 26  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX_LEN                    = 6   ;

static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1                   = 0   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX                        = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX_LEN                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9                   = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX                        = 10  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX_LEN                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17                 = 16  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17_LEN             = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX                        = 18  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX_LEN                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25                 = 24  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25_LEN             = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX                        = 26  ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX_LEN                    = 6   ;

static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_INIT_REQUEST                  = 0   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7                  = 1   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7_LEN              = 7   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER                    = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER_LEN                = 8   ;

static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_CRD_INIT_REQUEST                   = 24  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_25                        = 25  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ                       = 26  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ_LEN                   = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT                     = 28  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO                       = 30  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO_LEN                   = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_32_34                     = 32  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_32_34_LEN                 = 3   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_READ_POOL                          = 35  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_READ_POOL_LEN                      = 5   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_40_47                     = 40  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_40_47_LEN                 = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE                    = 48  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_50_51                     = 50  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_50_51_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE                      = 52  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT                     = 54  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC                  = 56  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC_LEN              = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_58                        = 58  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_WRITE_POOL                         = 59  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_WRITE_POOL_LEN                     = 5   ;

static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_TCTXT_RSP_WR_ORDERING            = 12  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_RELAXED_DMA_RD_WR_ORDERING       = 13  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_RELAXED_RMT_WR_ORDERING          = 14  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_RELAXED_RMT_VC_WR_ORDERING       = 15  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG                = 16  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG_LEN            = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG             = 24  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG_LEN         = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG          = 32  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG_LEN      = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG          = 40  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG_LEN      = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG          = 48  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG_LEN      = 8   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG       = 56  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG_LEN   = 8   ;

static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_LIMIT_AT_DEM_IN_PIPE          = 40  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43                    = 41  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS                      = 44  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR              = 46  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR_LEN          = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD                  = 48  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD_LEN              = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51                    = 50  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA                   = 52  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD                 = 54  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD_LEN             = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT                = 56  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT_LEN            = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC             = 58  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC_LEN         = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT                = 60  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_LEN            = 2   ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC             = 62  ;
static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC_LEN         = 2   ;

static const uint8_t P9N2_PU_INT_PC_AT_KILL_VALID                                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_24_26                        = 24  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_24_26_LEN                    = 3   ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_BLOCKID                               = 27  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_BLOCKID_LEN                           = 5   ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_OFFSET                                = 48  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_OFFSET_LEN                            = 13  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_61_63                        = 61  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_61_63_LEN                    = 3   ;

static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_24_26                   = 24  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_24_26_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_BLOCKID                          = 27  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_BLOCKID_LEN                      = 5   ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_OFFSET                           = 48  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_OFFSET_LEN                       = 13  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_61_63                   = 61  ;
static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_61_63_LEN               = 3   ;

static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_CRESP_CORR                        = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR                      = 1   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ARX_TAG_CORR                      = 3   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_MMIO_LDST_CORR                    = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_MMIO_RSP_CORR                     = 5   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_VRQ_QUEUE_CORR                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_AVX_CORR                          = 7   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ATX_CMD_CORR                      = 8   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ATX_BAR_CORR                      = 9   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ATX_AT_CORR                       = 10  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_11_15                        = 11  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_11_15_LEN                    = 5   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_FORCE_SINGLE_BIT_ERR                  = 16  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_FORCE_DOUBLE_BIT_ERR                  = 17  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_18_19                        = 18  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_18_19_LEN                    = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ARX_TAG_SRAM               = 20  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_CRESP_SRAM                 = 21  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_RSP_SRAM               = 22  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_VRQ_SRAM               = 23  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA                = 24  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA_LEN            = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA                = 26  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA_LEN            = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_BAR_SRAM               = 28  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AT_SSA                 = 29  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB                    = 30  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_32_37                        = 32  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_32_37_LEN                    = 6   ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ATX_AIB_REQ_IDLE                      = 38  ;
static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ATX_AIB_ARB_IDLE                      = 39  ;

static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_VLD                               = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_1_3                          = 1   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_1_3_LEN                      = 3   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_LEVEL                             = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_LEVEL_LEN                         = 3   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_7_8                          = 7   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_7_8_LEN                      = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID                            = 9   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID_LEN                        = 7   ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_16                           = 16  ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID_MASK                       = 17  ;
static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID_MASK_LEN                   = 7   ;

static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ARX_CMD                            = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ARX_VPC_REGS                       = 1   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CMD                          = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_RCMD                         = 3   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CRESP                        = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CAM_01                       = 5   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CAM_23                       = 6   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_LDST_UTIL                 = 7   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_LDST_CMD                  = 8   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_DONE_REQ                  = 9   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_PCMD_ARB                  = 10  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_ARB                            = 11  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_PROC_RCMD                      = 12  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_PROC_MMIO                      = 13  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_PROC_VPC                       = 14  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_PEND                       = 15  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_ARB                        = 16  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_ARB_DETAIL1                = 17  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_ARB_DETAIL2                = 18  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_BLCK                           = 19  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_CMD_LAT1                       = 20  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_CMD_LAT2                       = 21  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_CMD_LAT3                       = 22  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_ARB                            = 23  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_RESERVED_24_31                        = 24  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_RESERVED_24_31_LEN                    = 8   ;

static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R0                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R0_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1R                          = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1R_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1W                          = 8   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1W_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R2                           = 12  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R2_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R3                           = 16  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R3_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4R                          = 20  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4R_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4W                          = 24  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4W_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R5                           = 28  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R5_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R6                           = 32  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R6_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R7                           = 36  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R7_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R8                           = 40  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R8_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R9                           = 44  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R9_LEN                       = 4   ;

static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R0                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R0_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1R                          = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1R_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1W                          = 8   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1W_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R2                           = 12  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R2_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R3                           = 16  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R3_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4R                          = 20  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4R_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4W                          = 24  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4W_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R5                           = 28  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R5_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R6                           = 32  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R6_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R7                           = 36  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R7_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R8                           = 40  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R8_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R9                           = 44  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R9_LEN                       = 4   ;

static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R0                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R0_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1R                          = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1R_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1W                          = 8   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1W_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R2                           = 12  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R2_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R3                           = 16  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R3_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4R                          = 20  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4R_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4W                          = 24  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4W_LEN                      = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R5                           = 28  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R5_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R6                           = 32  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R6_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R7                           = 36  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R7_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R8                           = 40  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R8_LEN                       = 4   ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R9                           = 44  ;
static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R9_LEN                       = 4   ;

static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_0_1                         = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_0_1_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_ARX_TIMEOUT                          = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_ARX_TIMEOUT_LEN                      = 6   ;
static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_8_9                         = 8   ;
static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_8_9_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT                    = 10  ;
static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT_LEN                = 6   ;

static const uint8_t P9N2_PU_INT_PC_DBG_TRACE_RESERVED_0                          = 0   ;
static const uint8_t P9N2_PU_INT_PC_DBG_TRACE_RESERVED_1                          = 1   ;

static const uint8_t P9N2_PU_INT_PC_EQD_BLOCK_MODE_MODE                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_EQD_BLOCK_MODE_MODE_LEN                       = 32  ;

static const uint8_t P9N2_PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0                       = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0_LEN                   = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0                       = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0_LEN                   = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR0_FATAL_ERROR                              = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_FATAL_ERROR_LEN                          = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR0_INFO_ERROR                               = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_INFO_ERROR_LEN                           = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR0_RECOV_ERROR                              = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_RECOV_ERROR_LEN                          = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_CREDIT_ERROR                     = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_CMD_ERROR                        = 1   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_DAT_ERROR                        = 2   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_ROUTE_ERROR                      = 3   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_PARITY_ERROR                     = 4   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_AIB_ECC_CE                       = 5   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_AIB_ECC_UE                       = 6   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_TAG_ECC_CE                       = 7   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_TAG_ECC_UE                       = 8   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_TIMEOUT_ERROR                    = 9   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_10                          = 10  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ARX_OVERFLOW_ERROR               = 11  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ARX_DAT_ERROR                    = 12  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ARX_PARITY_ERROR                 = 13  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_OVERFLOW_ERROR               = 14  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_DAT_ERROR                    = 15  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_PARITY_ERROR                 = 16  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_ECC_CE                       = 17  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_ECC_UE                       = 18  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_TCTXT_OVERFLOW_ERROR             = 19  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_ADDR_ERROR                   = 20  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_21                          = 21  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_PRIO_ERROR                 = 22  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_USR_ERROR                  = 23  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_OS_ERROR                   = 24  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_HYP_ERROR                  = 25  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_ULT_ERROR                  = 26  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_INVALID_ERROR              = 27  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_USR_ERROR                  = 28  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_OS_ERROR                   = 29  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_HYP_ERROR                  = 30  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_ULT_ERROR                  = 31  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CMD_FIFO_ERROR                   = 32  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_VPC_FIFO_ERROR                   = 33  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_SLOT_OVERFLOW_ERROR              = 34  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_BAR_INVALID_ERROR                = 35  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_BAR_OFFSET_ERROR                 = 36  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_TAG_UNDERFLOW_ERROR              = 37  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_TAG_RELEASE_ERROR                = 38  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CREDIT_UNDERFLOW_ERROR           = 39  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CREDIT_OVERFLOW_ERROR            = 40  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_41                          = 41  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_PARITY_ERROR                     = 42  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_ECC_CE                           = 43  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CMD_ECC_UE                       = 44  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_VPC_ECC_UE                       = 45  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_BAR_ECC_UE                       = 46  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_CAM_STATE_ERROR               = 47  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_CAM_MULTIHIT_ERROR            = 48  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PARITY_ERROR                  = 49  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREF_REQ_ERROR                = 50  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREF_SLOTID_ERROR             = 51  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREFQ_OVERFLOW_ERROR          = 52  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREFQ_UNDERFLOW_ERROR         = 53  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_RD_REQ_CMD_ERROR              = 54  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_BAR_VALID_ERROR               = 55  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_BAR_PAGE_SIZE_ERROR           = 56  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_BAR_INDIR_ERROR               = 57  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_ECC_CE                        = 58  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_ECC_UE                        = 59  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_60                          = 60  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_REGS_PARITY_ERROR                    = 61  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_SCOM0_ERROR                          = 62  ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_SCOM1_ERROR                          = 63  ;

static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_DETAIL_DETAIL                        = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_DETAIL_DETAIL_LEN                    = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0                       = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0_LEN                   = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0                       = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0_LEN                   = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR1_FATAL_ERROR                              = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_FATAL_ERROR_LEN                          = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR1_INFO_ERROR                               = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_INFO_ERROR_LEN                           = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR1_RECOV_ERROR                              = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_RECOV_ERROR_LEN                          = 64  ;

static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_ARB_CONFIG_ERROR                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_ARB_PARITY_ERROR                 = 1   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_ARB_VPC_RSP_ERROR                = 2   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_3                           = 3   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_BLK_GRP_ERROR                  = 4   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_ALLOC_ERROR                = 5   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_STATE_ERROR                = 6   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_RCMD_MULTIHIT_ERROR        = 7   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_RCMD_ASSIGN_ERROR          = 8   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_CRESP_SEQ_ERROR            = 9   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_CRESP_REQ_ACK_ERROR        = 10  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_PARITY_ERROR                   = 11  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_ECC_CE                         = 12  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_ECC_UE                         = 13  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_PIPE_PARITY_ERROR                = 14  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_TCTXT_PARITY_ERROR                   = 15  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_16                          = 16  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_BLK_CNT_OVERFLOW_ERROR               = 17  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_BLK_CNT_UNDERFLOW_ERROR              = 18  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_BLK_PARITY_ERROR                     = 19  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_20                          = 20  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_THRD_MULTIHIT_ERROR        = 21  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_THRD_ASSIGN_ERROR          = 22  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_PRESP_MULTIHIT_ERROR       = 23  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_CRESP_SET_ERROR            = 24  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_CRESP_HIT_ERROR                 = 25  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_LSI_HIT_ERROR                   = 26  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_MMIO_DATA_CNFLT_ERROR           = 27  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_MMIO_DATA_RSP_ERROR             = 28  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_VRQ_CMD_ERROR                   = 29  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_VRQ_REQ_ERROR                   = 30  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_PARITY_ERROR                    = 31  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_VLD_ERROR            = 32  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_PEND_ERROR           = 33  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_WAIT_ERROR           = 34  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_TMOT_ERROR           = 35  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_LD_OVERFLOW_ERROR          = 36  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_ST_OVERFLOW_ERROR          = 37  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_PARITY_ERROR               = 38  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_ECC_CE                     = 39  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_ECC_UE                     = 40  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_DONE_CTRL_ERROR                 = 41  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_DONE_PARITY_ERROR               = 42  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_PCMD_CFG_ERROR                  = 43  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_PCMD_FIFO_ERROR                 = 44  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_PCMD_PARITY_ERROR               = 45  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_DATA_ERROR                  = 46  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_LVL_ERROR                   = 47  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_VPD_ERROR                   = 48  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_PARITY_ERROR                = 49  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_ECC_CE                      = 50  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_ECC_UE                      = 51  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_52                          = 52  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_53                          = 53  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_QSIZE_ERROR                  = 54  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_PEND_ARB_ERROR               = 55  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_VPC_ARB_ERROR                = 56  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_VPC_CRED_ERROR               = 57  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CTRL_ERROR                       = 58  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_PARITY_ERROR                     = 59  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_OVERFLOW_ERROR                   = 60  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_UNDERFLOW_ERROR                  = 61  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_ECC_CE                           = 62  ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_ECC_UE                           = 63  ;

static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_DETAIL_DETAIL                        = 0   ;
static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_DETAIL_DETAIL_LEN                    = 64  ;

static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_INDIRECT_MODE                      = 32  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_HOSTBOOT_MODE                      = 33  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_34_39                     = 34  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_34_39_LEN                 = 6   ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_CHIPID_OVERRIDE                = 40  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_41_43                     = 41  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_41_43_LEN                 = 3   ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_CHIPID                         = 44  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_CHIPID_LEN                     = 4   ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_END_PRIO_SEL               = 48  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_END_PRIO_SEL_LEN           = 2   ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_50_51                     = 50  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_50_51_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_BG_TABLE_COMPRESS          = 52  ;
static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_BG_TABLE_COMPRESS_LEN      = 4   ;

static const uint8_t P9N2_PU_INT_PC_IVE_BLOCK_MODE_MODE                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_IVE_BLOCK_MODE_MODE_LEN                       = 32  ;

static const uint8_t P9N2_PU_INT_PC_LSI_TRIG_EOI_LBS1_CMD_Q_BIT                   = 63  ;

static const uint8_t P9N2_PU_INT_PC_LSI_TRIG_LD_LBS1_CMD_P_BIT                    = 62  ;
static const uint8_t P9N2_PU_INT_PC_LSI_TRIG_LD_LBS1_CMD_Q_BIT                    = 63  ;

static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD_LEN             = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD_LEN             = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_4_5                         = 4   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_4_5_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL           = 6   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL_LEN       = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL           = 8   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL_LEN       = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP               = 10  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP_LEN           = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP               = 12  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP_LEN           = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK                   = 14  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_16                          = 16  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET               = 17  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET_LEN           = 3   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_20                          = 20  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP               = 21  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP_LEN           = 3   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_24                          = 24  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE                   = 25  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_28                          = 28  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR                     = 29  ;
static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR_LEN                 = 3   ;

static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_0                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI                         = 1   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI_LEN                     = 3   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_4                           = 4   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO                        = 5   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO_LEN                    = 3   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_8                           = 8   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ                     = 9   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ_LEN                 = 3   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_12                          = 12  ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP                     = 13  ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP_LEN                 = 3   ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_16                          = 16  ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_RR                          = 17  ;
static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_RR_LEN                      = 3   ;

static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_P0_IS_IDLE              = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_P1_IS_IDLE              = 1   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9            = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9_LEN        = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE         = 10  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN     = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27          = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27_LEN      = 12  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO      = 28  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33          = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33_LEN      = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB      = 34  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB_LEN  = 6   ;

static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1            = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH_LEN = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9            = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD = 10  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17          = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17_LEN      = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT  = 18  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_LEN = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25          = 24  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25_LEN      = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC_LEN = 6   ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_EN_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_EN_ENABLE_LEN                       = 32  ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_VP                      = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_SECURE                  = 7   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS             = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS_LEN         = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK               = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX               = 36  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX_LEN           = 28  ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB                     = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB_LEN                 = 8   ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL                      = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL_LEN                  = 48  ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_VG                      = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_SATURATE_VALUE          = 20  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_SATURATE_VALUE_LEN      = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS              = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS_LEN          = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK               = 36  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX               = 40  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX_LEN           = 23  ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG0                   = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG0_LEN               = 22  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG1                   = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG1_LEN               = 22  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG2_1                 = 50  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG2_1_LEN             = 14  ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2_2                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2_2_LEN             = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3                   = 10  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3_LEN               = 22  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG4                   = 34  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG4_LEN               = 22  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG5_1                 = 58  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG5_1_LEN             = 6   ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5_2                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5_2_LEN             = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6                   = 18  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6_LEN               = 22  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7                   = 42  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7_LEN               = 22  ;

static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_CONFLICT                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7             = 1   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN         = 7   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_FULL                     = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26            = 9   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26_LEN        = 18  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID                  = 27  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID_LEN              = 5   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44           = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44_LEN       = 13  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET                   = 45  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET_LEN               = 19  ;

static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_24_25                     = 24  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_24_25_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE                    = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE_LEN                = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_32                        = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_SYNC_DONE                          = 33  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_SYNC_DONE_LEN                      = 3   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_36_39                     = 36  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_36_39_LEN                 = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_ENA              = 40  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_RMT_ENA          = 41  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RMT_FIRST_GRPSCAN_ENA              = 42  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_LSMFB_SCAN_ALL_PRIO_ENA            = 43  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA              = 44  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA_LEN          = 3   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_47_50                     = 47  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_47_50_LEN                 = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_ENHANCED_HASH                      = 51  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE                       = 52  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE_LEN                   = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_56_57                     = 56  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_56_57_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_FORCE_INVALIDATE                   = 58  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED            = 59  ;
static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        = 5   ;

static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_RESERVED_0_29                       = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_RESERVED_0_29_LEN                   = 30  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_LD_ECC_CORRECTION               = 30  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION              = 31  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION            = 39  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION             = 41  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION_LEN         = 3   ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION             = 44  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            = 48  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            = 49  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL           = 50  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL_LEN       = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               = 52  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           = 5   ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_PMC_ENABLE                          = 57  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_TRACE_ENABLE                        = 58  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_RESERVED_59                         = 59  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY          = 60  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT               = 61  ;
static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           = 3   ;

static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG                     = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG_LEN                 = 64  ;

static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG                     = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG_LEN                 = 64  ;

static const uint8_t P9N2_PU_INT_PC_VPC_FATAL_ERR_ERROR                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_FATAL_ERR_ERROR_LEN                       = 64  ;

static const uint8_t P9N2_PU_INT_PC_VPC_INFO_ERR_ERROR                            = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_INFO_ERR_ERROR_LEN                        = 64  ;

static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25    = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25_LEN = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT     = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_LEN = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33   = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33_LEN = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC  = 34  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC_LEN = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41   = 40  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41_LEN = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD          = 42  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD_LEN      = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49   = 48  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49_LEN = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ     = 50  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ_LEN = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57   = 56  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57_LEN = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE    = 58  ;
static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE_LEN = 6   ;

static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL             = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL_LEN         = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL       = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL_LEN   = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE      = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD     = 12  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD     = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD        = 20  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN     = 24  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT        = 28  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT         = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT = 36  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        = 40  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE = 44  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY                = 48  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     = 52  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63           = 56  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN       = 8   ;

static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB               = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH            = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH_LEN        = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT        = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC           = 12  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC_LEN       = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT              = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_LEN          = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC           = 20  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC_LEN       = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD            = 24  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD_LEN        = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP       = 28  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP_LEN   = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP      = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP          = 36  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP_LEN      = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP         = 40  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF     = 44  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST           = 48  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST_LEN       = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH             = 52  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_LEN         = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC          = 56  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC_LEN      = 4   ;

static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY   = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY     = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY     = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY       = 12  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY_LEN   = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY        = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY        = 20  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY        = 24  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY     = 28  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY      = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY_LEN  = 4   ;

static const uint8_t P9N2_PU_INT_PC_VPC_RECOV_ERR_ERROR                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_RECOV_ERR_ERROR_LEN                       = 64  ;

static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_BLOCKID                        = 27  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_BLOCKID_LEN                    = 5   ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44                 = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44_LEN             = 13  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_OFFSET                         = 45  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_OFFSET_LEN                     = 19  ;

static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_VALID                          = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_WANT_CACHE_DISABLE             = 1   ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_WANT_INVALIDATE                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID                        = 27  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID_LEN                    = 5   ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44                 = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44_LEN             = 13  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_OFFSET                         = 45  ;
static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_OFFSET_LEN                     = 19  ;

static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_0                        = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_SCRUB_WB_CREDIT_ERROR             = 1   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_P0_PTAG_ERROR                  = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_PTAG_IN_USE_ERROR                 = 3   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_SYNC_OVERFLOW_ERROR               = 4   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_PARITY_ERROR                   = 5   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_TAG_SRAM_ECC_UE                = 6   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_STATE_SRAM_ECC_UE              = 7   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_8_9                      = 8   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_8_9_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_ATX_WB_CREDIT_OVERFLOW_ERROR      = 10  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_UNLOCK_FIFO_OVERFLOW_ERROR        = 11  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_12_13                    = 12  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_12_13_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_SRAM_ECC_CE                    = 14  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_15                       = 15  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_CL_INDEX_CAM_ERROR                = 16  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_AIB_CREDIT_ERROR                  = 17  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_18_19                    = 18  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_18_19_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_REPLAY_ERROR                      = 20  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PARITY_ERROR                   = 21  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_22_23                    = 22  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_22_23_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_DATA_SRAM_ECC_UE               = 24  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PTAG_SRAM_ECC_UE               = 25  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_ATX_CREDIT_OVERFLOW_ERROR         = 26  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_27_28                    = 27  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_27_28_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_SRAM_ECC_CE                    = 29  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PROC_SW_ERROR                  = 30  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PROC_HW_ERROR                  = 31  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_TAG_ERROR                      = 32  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_OVERFLOW                       = 33  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_SRAM_ECC_UE                    = 34  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_SRAM_ECC_CE                    = 35  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_36_52                    = 36  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_36_52_LEN                = 17  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_REGS_PARITY_ERROR                 = 53  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_WATCH_PARITY_ERROR                = 54  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_PARITY_ERROR                      = 55  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_56_62                    = 56  ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_56_62_LEN                = 7   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_WATCH_NOT_OWNED_BLOCKID           = 63  ;

static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR                      = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR_LEN                  = 64  ;

static const uint8_t P9N2_PU_INT_PC_VPD_BLOCK_MODE_MODE                           = 0   ;
static const uint8_t P9N2_PU_INT_PC_VPD_BLOCK_MODE_MODE_LEN                       = 64  ;

static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_CORE_PUSH_EN                      = 0   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_1_2                          = 1   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_1_2_LEN                      = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL                   = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL_LEN               = 5   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_8_10                         = 8   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_8_10_LEN                     = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL               = 11  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL_LEN           = 5   ;

static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_QUERY_RR_SEL           = 0   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_1                       = 1   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL            = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL            = 4   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7                     = 6   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP                = 8   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP_LEN            = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP                = 10  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP_LEN            = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16                   = 12  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16_LEN               = 5   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY                   = 17  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_20                      = 20  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH                    = 21  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_24                      = 24  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL                    = 25  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_28                      = 28  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR                      = 29  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR_LEN                  = 3   ;

static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_RESERVED_0                        = 0   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD                     = 1   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD_LEN                 = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PULL                    = 4   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL                     = 5   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL_LEN                 = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_LCL                = 8   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL                 = 9   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL_LEN             = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_ARX                = 12  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX                 = 13  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX_LEN             = 3   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_RESERVED_16                       = 16  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR                       = 17  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR_LEN                   = 3   ;

static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1                      = 0   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD                     = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD_LEN                 = 6   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9                      = 8   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT                     = 10  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT_LEN                 = 6   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17                    = 16  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD                 = 18  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD_LEN             = 6   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25                    = 24  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT                 = 26  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT_LEN             = 6   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33                    = 32  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD                 = 34  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD_LEN             = 6   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41                    = 40  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT                 = 42  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT_LEN             = 6   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49                    = 48  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49_LEN                = 2   ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_MAX                           = 50  ;
static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_MAX_LEN                       = 6   ;

static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_AUTO_INCREMENT                 = 0   ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3                   = 1   ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_12                    = 12  ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_SELECT                         = 13  ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_SELECT_LEN                     = 3   ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26                 = 24  ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26_LEN             = 3   ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_ADDRESS                        = 27  ;
static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_ADDRESS_LEN                    = 5   ;

static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_00                               = 0   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_01                               = 1   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_02                               = 2   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_03                               = 3   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_04                               = 4   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_05                               = 5   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_06                               = 6   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_07                               = 7   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_08                               = 8   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_09                               = 9   ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_10                               = 10  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_11                               = 11  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_12                               = 12  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_13                               = 13  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_14                               = 14  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_15                               = 15  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_16                               = 16  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_17                               = 17  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_18                               = 18  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_19                               = 19  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_20                               = 20  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_21                               = 21  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_22                               = 22  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_23                               = 23  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_24                               = 24  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_25                               = 25  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_26                               = 26  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_27                               = 27  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_28                               = 28  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_29                               = 29  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_30                               = 30  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_31                               = 31  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_32                               = 32  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_33                               = 33  ;
static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_34                               = 34  ;

static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_BLOCK_GROUP_EN                     = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_TARGET_EN                          = 1   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_LGS_EN                             = 2   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_STORE_ACK                          = 3   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_FUSE_CORE_EN                       = 4   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_5                             = 5   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_SMT_MODE                           = 6   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_SMT_MODE_LEN                       = 2   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_HARD_CHIPID_IN_BLOCK_EN            = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_CHIPID_OVERRIDE                    = 9   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_10_11                         = 10  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_10_11_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_CHIPID                             = 12  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_CHIPID_LEN                         = 4   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_EN                                 = 16  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_MSGSND                             = 17  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_18_19                         = 18  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_18_19_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH                        = 20  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH_LEN                    = 4   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_24                            = 24  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_COMPLEX_STORE_DIS                  = 25  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_COMPLEX_STORE_DIS_LEN              = 3   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_28_29                         = 28  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_28_29_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_LGS_AGE                            = 30  ;
static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_LGS_AGE_LEN                        = 2   ;

static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C0_EN                         = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C0_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C1_EN                         = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C1_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C2_EN                         = 16  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C2_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C3_EN                         = 24  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C3_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C4_EN                         = 32  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C4_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C5_EN                         = 40  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C5_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C6_EN                         = 48  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C6_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C7_EN                         = 56  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C7_EN_LEN                     = 8   ;

static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C8_EN                         = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C8_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C9_EN                         = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C9_EN_LEN                     = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C10_EN                        = 16  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C10_EN_LEN                    = 8   ;
static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C11_EN                        = 24  ;
static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C11_EN_LEN                    = 8   ;

static const uint8_t P9N2_PU_INT_TCTXT_INDIR0_INDIR_VLD                           = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR0_INDIR_THRDID                        = 9   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR0_INDIR_THRDID_LEN                    = 7   ;

static const uint8_t P9N2_PU_INT_TCTXT_INDIR1_INDIR_VLD                           = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR1_INDIR_THRDID                        = 9   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR1_INDIR_THRDID_LEN                    = 7   ;

static const uint8_t P9N2_PU_INT_TCTXT_INDIR2_INDIR_VLD                           = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR2_INDIR_THRDID                        = 9   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR2_INDIR_THRDID_LEN                    = 7   ;

static const uint8_t P9N2_PU_INT_TCTXT_INDIR3_INDIR_VLD                           = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR3_INDIR_THRDID                        = 9   ;
static const uint8_t P9N2_PU_INT_TCTXT_INDIR3_INDIR_THRDID_LEN                    = 7   ;

static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_EN                         = 0   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET                      = 1   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_2_3                         = 2   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_2_3_LEN                     = 2   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_EN                  = 4   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_VPC_EN              = 5   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_6_9                         = 6   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_6_9_LEN                     = 4   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY                = 10  ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_EN_VEC                     = 48  ;
static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_EN_VEC_LEN                 = 16  ;

static const uint8_t P9N2_PU_INT_VC_AIB_TIMEOUT_DELAY                             = 58  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TIMEOUT_DELAY_LEN                         = 6   ;

static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_PREVENT_MTP_AT_DEM_IN_PIPE = 32  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43            = 33  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43_LEN        = 11  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS         = 44  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS_LEN     = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ          = 46  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ_LEN      = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC          = 48  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC_LEN      = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51            = 50  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP = 52  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA      = 54  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA_LEN  = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD     = 56  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP  = 58  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD  = 60  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA      = 62  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA_LEN  = 2   ;

static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS                    = 24  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS_LEN                = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ                     = 32  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ_LEN                 = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC                     = 40  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC_LEN                 = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA                 = 48  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA_LEN             = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI                 = 56  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN             = 8   ;

static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_TRIG_FWD        = 20  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_EQP          = 21  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_DMA          = 22  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_IDX_IN_AIBTAG   = 23  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE            = 24  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE_LEN        = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE             = 32  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE_LEN         = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP             = 40  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP_LEN         = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD              = 48  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD_LEN          = 8   ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA                 = 56  ;
static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA_LEN             = 8   ;

static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_CRD_REQUEST             = 24  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_25             = 25  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ        = 26  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ_LEN    = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO        = 28  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO_LEN    = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD = 30  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33          = 32  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33_LEN      = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL           = 34  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL_LEN       = 6   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47          = 40  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47_LEN      = 8   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE       = 48  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE_LEN   = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST         = 50  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST_LEN     = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1      = 52  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1_LEN  = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2      = 54  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2_LEN  = 2   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58          = 56  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58_LEN      = 3   ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL          = 59  ;
static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL_LEN      = 5   ;

static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0                   = 0   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R                  = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W                  = 8   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2                   = 12  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3                   = 16  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4                   = 20  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R                  = 24  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W                  = 28  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP                = 36  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT                = 40  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP                = 44  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8                   = 48  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9                   = 52  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R                 = 56  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W                 = 60  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W_LEN             = 4   ;

static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0                   = 0   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R                  = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W                  = 8   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2                   = 12  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3                   = 16  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4                   = 20  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R                  = 24  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W                  = 28  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP                = 36  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT                = 40  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP                = 44  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8                   = 48  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9                   = 52  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R                 = 56  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W                 = 60  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W_LEN             = 4   ;

static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0                   = 0   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R                  = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W                  = 8   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2                   = 12  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3                   = 16  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4                   = 20  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R                  = 24  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W                  = 28  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP                = 36  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT                = 40  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP                = 44  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8                   = 48  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9                   = 52  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R                 = 56  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W                 = 60  ;
static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W_LEN             = 4   ;

static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_VALID                           = 0   ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_VST_TYPE                        = 14  ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_VST_TYPE_LEN                    = 2   ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_BLOCKID                         = 27  ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_BLOCKID_LEN                     = 5   ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_OFFSET                          = 48  ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_OFFSET_LEN                      = 13  ;

static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET                     = 48  ;
static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET_LEN                 = 13  ;

static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_P0_IS_IDLE              = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_P1_IS_IDLE              = 1   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE         = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN     = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI     = 16  ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO      = 24  ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN  = 8   ;

static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP     = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING         = 16  ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_LEN     = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD = 24  ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE = 40  ;
static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE_LEN = 8   ;

static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_EN_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_EN_ENABLE_LEN                       = 16  ;

static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA_LEN                = 64  ;

static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA_LEN                = 64  ;

static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA_LEN                = 64  ;

static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA_LEN                = 64  ;

static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_CONFLICT                 = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7             = 1   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN         = 7   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_FULL                     = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27            = 9   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27_LEN        = 19  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID                  = 28  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39           = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39_LEN       = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET_LEN               = 24  ;

static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG                    = 16  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG_LEN                = 16  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_SYNC_DONE                          = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_SYNC_DONE_LEN                      = 5   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_37                        = 37  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_EQP_ADD_INTERLEAVE          = 38  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_END_S_BIT                   = 39  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_END_U_BIT                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_END_C_BIT                   = 41  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_MORE_QSZ                    = 42  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_SKIP_ESCALATE                      = 43  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_44_45                     = 44  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_44_45_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE                    = 46  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE_LEN                = 6   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE                       = 52  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE_LEN                   = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_56_57                     = 56  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_56_57_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_FORCE_INVALIDATE                   = 58  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED            = 59  ;
static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        = 5   ;

static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_0_32                       = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_0_32_LEN                   = 33  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_ARX_ECC_CORRECTION              = 33  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION              = 34  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION            = 42  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_CTRLBUF_ECC_CORRECTION          = 44  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION             = 45  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            = 49  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            = 50  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               = 51  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           = 5   ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_TRACE_ENABLE                        = 56  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_57_58                      = 57  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_57_58_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_59                         = 59  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY          = 60  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT               = 61  ;
static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           = 3   ;

static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI  = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD  = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC = 12  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS = 16  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI         = 20  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE       = 24  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE_LEN   = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT    = 28  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT        = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT  = 36  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        = 40  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE = 44  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY                = 48  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     = 52  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63           = 56  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN       = 8   ;

static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH            = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH_LEN        = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP                  = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME               = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB                  = 12  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB_LEN              = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP                   = 16  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS                   = 20  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN               = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL         = 24  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD               = 28  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE             = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE_LEN         = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD        = 36  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD       = 40  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD_LEN   = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD        = 44  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD       = 48  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD_LEN   = 4   ;

static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY     = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY           = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY_LEN       = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY               = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY      = 12  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY     = 16  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY = 20  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY     = 24  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY     = 28  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY      = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED      = 36  ;
static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED_LEN  = 4   ;

static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_BLOCKID                        = 28  ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_BLOCKID_LEN                    = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39                 = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39_LEN             = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_OFFSET                         = 40  ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_OFFSET_LEN                     = 24  ;

static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_VALID                          = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_WANT_CACHE_DISABLE             = 1   ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_WANT_INVALIDATE                = 2   ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID                        = 28  ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID_LEN                    = 4   ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39                 = 32  ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39_LEN             = 8   ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_OFFSET                         = 40  ;
static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_OFFSET_LEN                     = 24  ;

static const uint8_t P9N2_PU_INT_VC_EQD_BLOCK_MODE_MODE                           = 0   ;
static const uint8_t P9N2_PU_INT_VC_EQD_BLOCK_MODE_MODE_LEN                       = 32  ;

static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG                     = 0   ;
static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG_LEN                 = 56  ;

static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG                     = 0   ;
static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG_LEN                 = 56  ;

static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG                     = 0   ;
static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG_LEN                 = 44  ;

static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG                     = 0   ;
static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG_LEN                 = 44  ;

static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G0_ERROR                            = 0   ;
static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G0_ERROR_LEN                        = 55  ;

static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G1_ERROR                            = 0   ;
static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G1_ERROR_LEN                        = 43  ;

static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_INDIRECT_MODE                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_EQD_4B_WRITE_MODE               = 33  ;
static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_RESERVED_34_63                  = 34  ;
static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_RESERVED_34_63_LEN              = 30  ;

static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G0_ERROR                             = 0   ;
static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G0_ERROR_LEN                         = 55  ;

static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G1_ERROR                             = 0   ;
static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G1_ERROR_LEN                         = 43  ;

static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_20                      = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_20_LEN                  = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC                    = 35  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISABLE                 = 42  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_QUEUE_DISABLE                    = 43  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_IVC_INTF_DISABLE                 = 44  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_ENABLE_MEMORY_BACKING            = 45  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE                         = 46  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE_LEN                     = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_52                      = 52  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT                    = 53  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_56                      = 56  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT                    = 57  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_FULL_WRITEBACK_ENABLE            = 60  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_QUEUE_NOT_EMPTY                  = 61  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_CREDIT_UPDATE_PENDING            = 62  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_FIFO_FULL                        = 63  ;

static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20_LEN                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC                    = 35  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISABLE                 = 42  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_QUEUE_DISABLE                    = 43  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_IVC_INTF_DISABLE                 = 44  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_ENABLE_MEMORY_BACKING            = 45  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE                         = 46  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE_LEN                     = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_52                      = 52  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT                    = 53  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_56                      = 56  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT                    = 57  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_FULL_WRITEBACK_ENABLE            = 60  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_QUEUE_NOT_EMPTY                  = 61  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_CREDIT_UPDATE_PENDING            = 62  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_FIFO_FULL                        = 63  ;

static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20_LEN                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC                    = 35  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISABLE                 = 42  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_QUEUE_DISABLE                    = 43  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_IVC_INTF_DISABLE                 = 44  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_ENABLE_MEMORY_BACKING            = 45  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE                         = 46  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE_LEN                     = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_52                      = 52  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT                    = 53  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_56                      = 56  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT                    = 57  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_FULL_WRITEBACK_ENABLE            = 60  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_QUEUE_NOT_EMPTY                  = 61  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_CREDIT_UPDATE_PENDING            = 62  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_FIFO_FULL                        = 63  ;

static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20_LEN                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC                    = 35  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISABLE                 = 42  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_QUEUE_DISABLE                    = 43  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_IVC_INTF_DISABLE                 = 44  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_ENABLE_MEMORY_BACKING            = 45  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE                         = 46  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE_LEN                     = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_52                      = 52  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT                    = 53  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_56                      = 56  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT                    = 57  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_FULL_WRITEBACK_ENABLE            = 60  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_QUEUE_NOT_EMPTY                  = 61  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_CREDIT_UPDATE_PENDING            = 62  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_FIFO_FULL                        = 63  ;

static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20_LEN                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC                    = 35  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISABLE                 = 42  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_QUEUE_DISABLE                    = 43  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_IVC_INTF_DISABLE                 = 44  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_ENABLE_MEMORY_BACKING            = 45  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE                         = 46  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE_LEN                     = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_52                      = 52  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT                    = 53  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_56                      = 56  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT                    = 57  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_FULL_WRITEBACK_ENABLE            = 60  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_QUEUE_NOT_EMPTY                  = 61  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_CREDIT_UPDATE_PENDING            = 62  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_FIFO_FULL                        = 63  ;

static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20                    = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20_LEN                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE                = 21  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE_LEN            = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34                   = 32  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34_LEN               = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC                    = 35  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41_LEN               = 2   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISABLE                 = 42  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_QUEUE_DISABLE                    = 43  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_IVC_INTF_DISABLE                 = 44  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_ENABLE_MEMORY_BACKING            = 45  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE                         = 46  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE_LEN                     = 6   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_52                      = 52  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT                    = 53  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_56                      = 56  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT                    = 57  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT_LEN                = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_FULL_WRITEBACK_ENABLE            = 60  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_QUEUE_NOT_EMPTY                  = 61  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_CREDIT_UPDATE_PENDING            = 62  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_FIFO_FULL                        = 63  ;

static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB        = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED         = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC      = 8   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR               = 12  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD               = 16  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL            = 20  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB        = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED         = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC      = 8   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR               = 12  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD               = 16  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL            = 20  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB        = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED         = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC      = 8   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR               = 12  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD               = 16  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL            = 20  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB        = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED         = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC      = 8   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR               = 12  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD               = 16  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL            = 20  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB        = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED         = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC      = 8   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR               = 12  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD               = 16  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL            = 20  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB        = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED         = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED_LEN     = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC      = 8   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR               = 12  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD               = 16  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD_LEN           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL            = 20  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY               = 0   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY_LEN           = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD                    = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY               = 8   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY_LEN           = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD                    = 11  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY              = 16  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY_LEN          = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD                   = 19  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD_LEN               = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY              = 24  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY_LEN          = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD                   = 27  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD_LEN               = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY             = 32  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY_LEN         = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD                  = 35  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD_LEN              = 5   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42             = 40  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42_LEN         = 3   ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL                       = 43  ;
static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL_LEN                   = 5   ;

static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_P0_IS_IDLE                = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_P1_IS_IDLE                = 1   ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE           = 8   ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN       = 8   ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO        = 24  ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN    = 8   ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH = 48  ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP = 56  ;
static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 8   ;

static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_EN_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_EN_ENABLE_LEN                       = 16  ;

static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX                = 54  ;
static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX_LEN            = 6   ;

static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA                     = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA_LEN                 = 64  ;

static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_32                         = 32  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE                     = 33  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE_LEN                 = 5   ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION              = 38  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_STATE_ECC_CORRECTION            = 42  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_43_44                      = 43  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_43_44_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION             = 45  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         = 2   ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_47_48                      = 47  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_47_48_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            = 49  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            = 50  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               = 51  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           = 5   ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_TRACE_ENABLE                        = 56  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_57_58                      = 57  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_57_58_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_FAST_SB_LOOKUP_DISABLE              = 59  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT               = 60  ;
static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           = 4   ;

static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_0                         = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_0                              = 1   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_0_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_8                         = 8   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD                                = 9   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_LEN                            = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_16                        = 16  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_2                              = 17  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_2_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_24                        = 24  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_3                              = 25  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_3_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_32                        = 32  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_4                              = 33  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_4_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_40                        = 40  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_5                              = 41  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_5_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_48                        = 48  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_6                              = 49  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_6_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_56                        = 56  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_7                              = 57  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_7_LEN                          = 7   ;

static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_0                         = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_8                              = 1   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_8_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_8                         = 8   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_9                              = 9   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_9_LEN                          = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_16                        = 16  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_10                             = 17  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_10_LEN                         = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_24                        = 24  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_11                             = 25  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_11_LEN                         = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_32                        = 32  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_12                             = 33  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_12_LEN                         = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_40                        = 40  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_13                             = 41  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_13_LEN                         = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_48                        = 48  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_14                             = 49  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_14_LEN                         = 7   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_56                        = 56  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_15                             = 57  ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_15_LEN                         = 7   ;

static const uint8_t P9N2_PU_INT_VC_IVC_HASH_3_RESERVED_0                         = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_3_IPI                                = 1   ;
static const uint8_t P9N2_PU_INT_VC_IVC_HASH_3_IPI_LEN                            = 7   ;

static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE     = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE     = 8   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE     = 12  ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC = 16  ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE     = 20  ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT        = 24  ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT        = 28  ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        = 32  ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE = 36  ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN = 4   ;

static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH            = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH_LEN        = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP           = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP_LEN       = 4   ;

static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY     = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY_LEN = 4   ;

static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_BLOCKID                        = 28  ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_BLOCKID_LEN                    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35                 = 32  ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_OFFSET                         = 36  ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_OFFSET_LEN                     = 28  ;

static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_VALID                          = 0   ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_WANT_CACHE_DISABLE             = 1   ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID                        = 28  ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID_LEN                    = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35                 = 32  ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35_LEN             = 4   ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_OFFSET                         = 36  ;
static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_OFFSET_LEN                     = 28  ;

static const uint8_t P9N2_PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE                       = 32  ;
static const uint8_t P9N2_PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE_LEN                   = 32  ;

static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_AIB_IN_ECC_CORRECTION          = 0   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_IRQ_ECC_CORRECTION             = 1   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_AT_SRAM_ECC_CORRECTION         = 2   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_BAR_SRAM_ECC_CORRECTION        = 3   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_TAG_SRAM_ECC_CORRECTION        = 4   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_IRQ_TRACE_ENABLE                   = 5   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_FORCE_SINGLE_BIT_ECC_ERR           = 6   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR           = 7   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_TRIG_TRACE_ENABLE                  = 8   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_RESERVED_9                         = 9   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION              = 10  ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION_LEN          = 6   ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ATX_CACHE_SLOTS_IDLE               = 16  ;
static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ATX_IS_IDLE                        = 17  ;

static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17    = 0   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17_LEN = 18  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE         = 18  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE_LEN     = 6   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25   = 24  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST          = 26  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST_LEN      = 6   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33   = 32  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST          = 34  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST_LEN      = 6   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41   = 40  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD          = 42  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD_LEN      = 6   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49   = 48  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ     = 50  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ_LEN = 6   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57   = 56  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57_LEN = 2   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE    = 58  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE_LEN = 6   ;

static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17         = 0   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17_LEN     = 18  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ              = 18  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ_LEN          = 6   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25        = 24  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25_LEN    = 2   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE             = 26  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE_LEN         = 6   ;

static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50        = 48  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50_LEN    = 3   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP            = 51  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP_LEN        = 5   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58        = 56  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58_LEN    = 3   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ              = 59  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ_LEN          = 5   ;

static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50        = 48  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50_LEN    = 3   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ              = 51  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ_LEN          = 5   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58        = 56  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58_LEN    = 3   ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE             = 59  ;
static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE_LEN         = 5   ;

static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G0_ERROR                            = 0   ;
static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G0_ERROR_LEN                        = 55  ;

static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G1_ERROR                            = 0   ;
static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G1_ERROR_LEN                        = 43  ;

static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_P0_IS_IDLE                = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_P1_IS_IDLE                = 1   ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE           = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN       = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI  = 16  ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO        = 24  ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN    = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH = 48  ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH_LEN = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE = 56  ;
static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE_LEN = 8   ;

static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_EN_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_EN_ENABLE_LEN                       = 16  ;

static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX                = 54  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX_LEN            = 6   ;

static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA                     = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA_LEN                 = 64  ;

static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_ENABLE_COMPLEX_CI_STORE            = 44  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_ENABLE_COMPLEX_CI_STORE_LEN        = 2   ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_RESERVED_46                        = 46  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE                    = 47  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE_LEN                = 5   ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE                       = 52  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE_LEN                   = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_RESERVED_56_57                     = 56  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_RESERVED_56_57_LEN                 = 2   ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_FORCE_INVALIDATE                   = 58  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_DONT_UPDATE_ON_PRF                 = 59  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED            = 60  ;
static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_32_33                      = 32  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_32_33_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION              = 34  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_38_41                      = 38  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_38_41_LEN                  = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_STATE_ECC_CORRECTION            = 42  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_43_44                      = 43  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_43_44_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION             = 45  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         = 2   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_47_48                      = 47  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_47_48_LEN                  = 2   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            = 49  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            = 50  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               = 51  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           = 5   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_TRACE_ENABLE                        = 56  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_57_59                      = 57  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_57_59_LEN                  = 3   ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT               = 60  ;
static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           = 4   ;

static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF              = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF_LEN          = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND           = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND_LEN       = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND          = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND_LEN      = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED   = 12  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED = 16  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI             = 20  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_LEN         = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT   = 24  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT        = 28  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT      = 32  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        = 36  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE = 40  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY                = 44  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     = 48  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN = 4   ;

static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH            = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH_LEN        = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP            = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP_LEN        = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11            = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11_LEN        = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE            = 12  ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE_LEN        = 4   ;

static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY     = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY_LEN = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY      = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY_LEN  = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY      = 8   ;
static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN  = 4   ;

static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_BLOCKID                        = 28  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_BLOCKID_LEN                    = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40                 = 32  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40_LEN             = 9   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_OFFSET                         = 41  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_OFFSET_LEN                     = 23  ;

static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_VALID                          = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_WANT_CACHE_DISABLE             = 1   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_WANT_INVALIDATE                = 2   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID                        = 28  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID_LEN                    = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40                 = 32  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40_LEN             = 9   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_OFFSET                         = 41  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_OFFSET_LEN                     = 23  ;

static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID                       = 28  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID_LEN                   = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35                = 32  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35_LEN            = 4   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET                        = 36  ;
static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET_LEN                    = 23  ;

static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE                      = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE_LEN                  = 64  ;

static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_MASK_MSK                           = 0   ;
static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_MASK_MSK_LEN                       = 32  ;

static const uint8_t P9N2_PU_INT_VC_VPS_BLOCK_MODE_MODE                           = 0   ;
static const uint8_t P9N2_PU_INT_VC_VPS_BLOCK_MODE_MODE_LEN                       = 64  ;

static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_AUTO_INCREMENT                 = 0   ;
static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_SELECT                         = 13  ;
static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_SELECT_LEN                     = 3   ;
static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26                 = 16  ;
static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26_LEN             = 11  ;
static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_ADDRESS                        = 27  ;
static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_ADDRESS_LEN                    = 5   ;

static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_INVALID_STATE             = 0   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_CRD_ERROR                 = 1   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OFFSET_ERROR              = 2   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DATA_ERROR                = 3   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ACCESS_ERROR              = 4   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OVERFLOW                  = 5   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_IDX_ERROR                 = 6   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_UNDERFLOW                 = 7   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_STATE_ERROR           = 8   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_WR_ERROR              = 9   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_RD_ERROR              = 10  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_UE                    = 11  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EQC_CREDIT_ERROR               = 12  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_TRIG_CRD_ERROR                 = 13  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EFIFO_DIN_ERROR                = 14  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_INPUT_BUF_ERROR                = 15  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EQ_ERROR                       = 16  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_PQ_ERROR                       = 17  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EQPQ_ERROR                     = 18  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_CE                    = 19  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_CTRL_PTY_ERROR                 = 20  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_CMD_PTY_ERROR                  = 21  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_SCOM_INTERNAL_ERROR           = 22  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_UE                = 23  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_UE                = 24  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_PARITY_ERROR                  = 25  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_CMD_CRD_ERROR                 = 26  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_DATA_CRD_ERROR                = 27  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_CMD_ERROR                  = 28  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_RESP_TIMEOUT               = 29  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_CE                = 30  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_CE                = 31  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_LACK_OF_TAG                    = 32  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_TAG_RELEASE_ERROR              = 33  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_BAD_CAM_STATE                   = 34  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_HIT                    = 35  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_PARITY_ERROR                    = 36  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_PRF_RQ                 = 37  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_TOO_LARGE_SLOTID                = 38  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_PRF_OVERFLOW                    = 39  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_PRF_UNDERFLOW                   = 40  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_CMD                     = 41  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_BAR                 = 42  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_PZ                  = 43  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_I                       = 44  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_CRD_PARITY_ERROR               = 45  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_AT_SRAM_ECC_UE                 = 46  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_BAR_SRAM_ECC_UE                = 47  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_WB_SRAM_ECC_UE                 = 48  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_SLOT_OVERFLOW                  = 49  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_CRD_OVERFLOW                   = 50  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_CRD_UNDERFLOW                  = 51  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_INVALID_BAR                    = 52  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_PAGE_OVERFLOW                  = 53  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_SRAM_ECC_CE                    = 54  ;

static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR                       = 0   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR_LEN                   = 64  ;

static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CL_INDEX_ERROR                 = 0   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CRD_OR_RESP_ERROR              = 1   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PTAG_ASSIGN_ERROR              = 2   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PTAG_RELEASE_ERROR             = 3   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_REPLAY_ERROR                   = 4   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PARITY_ERROR                   = 5   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_TAG_SRAM_ECC_UE                = 6   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_STATE_SRAM_ECC_UE              = 7   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_DATA_SRAM_ECC_UE               = 8   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CTRL_SRAM_ECC_UE               = 9   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_ARX_DATA_ECC_UE                = 10  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_UNLOCK_FIFO_OVERFLOW           = 11  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_EOI_OVERFLOW                   = 12  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_EOI_TAG_ERROR                  = 13  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_SRAM_ECC_CE                    = 14  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PROCESSING_ERROR               = 15  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_WATCH_ERROR                    = 16  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CFG_ERROR_OR_MULTISYNC         = 17  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_AIB_RESP_ERROR                 = 18  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PTAG_ASSIGN_ERROR              = 19  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PTAG_RELEASE_ERROR             = 20  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_REPLAY_ERROR                   = 21  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PARITY_ERROR                   = 22  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_TAG_SRAM_ECC_UE                = 23  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_STATE_SRAM_ECC_UE              = 24  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_DATA_SRAM_ECC_UE               = 25  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_UNLOCK_FIFO_OVERFLOW           = 26  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_SRAM_ECC_CE                    = 27  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PROCESSING_ERROR               = 28  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_CL_INDEX_ERROR                 = 29  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_CRD_OR_RESP_ERROR              = 30  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PTAG_ASSIGN_ERROR              = 31  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PTAG_RELEASE_ERROR             = 32  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_REPLAY_ERROR                   = 33  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PARITY_ERROR                   = 34  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_TAG_SRAM_ECC_UE                = 35  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_STATE_SRAM_ECC_UE              = 36  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_DATA_SRAM_ECC_UE               = 37  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_UNLOCK_FIFO_OVERFLOW           = 38  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_EOI_OVERFLOW                   = 39  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_EOI_TAG_ERROR                  = 40  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_SRAM_ECC_CE                    = 41  ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PROCESSING_ERROR               = 42  ;

static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR                       = 0   ;
static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR_LEN                   = 64  ;

static const uint8_t P9N2__SM1_IODA_ADDR_AUTO_INCREMENT                           = 0   ;
static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_SELECT                             = 11  ;
static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_SELECT_LEN                         = 5   ;
static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_ADDRESS                            = 54  ;
static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_ADDRESS_LEN                        = 10  ;

static const uint8_t P9N2__SM1_IODA_DAT0_TABLE_DATA                               = 0   ;
static const uint8_t P9N2__SM1_IODA_DAT0_TABLE_DATA_LEN                           = 64  ;

static const uint8_t P9N2_PU_IO_DATA_REG_PCB_TMP                                  = 0   ;
static const uint8_t P9N2_PU_IO_DATA_REG_PCB_TMP_LEN                              = 64  ;

static const uint8_t P9N2_PU_IVT_OFFSET_PAYLOAD                                   = 0   ;
static const uint8_t P9N2_PU_IVT_OFFSET_PAYLOAD_LEN                               = 28  ;

static const uint8_t P9N2_PU_JTG_PIB_OJCFG_JTAG_SRC_SEL                           = 0   ;
static const uint8_t P9N2_PU_JTG_PIB_OJCFG_RUN_TCK                                = 1   ;
static const uint8_t P9N2_PU_JTG_PIB_OJCFG_TCK_WIDTH                              = 2   ;
static const uint8_t P9N2_PU_JTG_PIB_OJCFG_TCK_WIDTH_LEN                          = 3   ;
static const uint8_t P9N2_PU_JTG_PIB_OJCFG_JTAG_TRST_B                            = 5   ;
static const uint8_t P9N2_PU_JTG_PIB_OJCFG_DBG_HALT                               = 6   ;

static const uint8_t P9N2_PU_JTG_PIB_OJIC_START_JTAG_CMD                          = 0   ;
static const uint8_t P9N2_PU_JTG_PIB_OJIC_DO_IR                                   = 1   ;
static const uint8_t P9N2_PU_JTG_PIB_OJIC_DO_DR                                   = 2   ;
static const uint8_t P9N2_PU_JTG_PIB_OJIC_DO_TAP_RESET                            = 3   ;
static const uint8_t P9N2_PU_JTG_PIB_OJIC_WR_VALID                                = 4   ;
static const uint8_t P9N2_PU_JTG_PIB_OJIC_JTAG_INSTR                              = 12  ;
static const uint8_t P9N2_PU_JTG_PIB_OJIC_JTAG_INSTR_LEN                          = 4   ;

static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_JTAG_INPROG                           = 0   ;
static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_SRC_SEL_EQ1_ERR                       = 1   ;
static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_RUN_TCK_EQ0_ERR                       = 2   ;
static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_TRST_B_EQ0_ERR                        = 3   ;
static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_IR_DR_EQ0_ERR                         = 4   ;
static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_INPROG_WR_ERR                         = 5   ;
static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_FSM_ERROR                             = 6   ;

static const uint8_t P9N2_PU_JTG_PIB_OJTDI_JTAG_TDI                               = 0   ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDI_JTAG_TDI_LEN                           = 32  ;

static const uint8_t P9N2_PU_JTG_PIB_OJTDO_JTAG_TDO                               = 0   ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_JTAG_TDO_LEN                           = 32  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_JTAG_SRC_SEL                     = 32  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_RUN_TCK                          = 33  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH                        = 34  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH_LEN                    = 3   ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_JTAG_TRST_B                      = 37  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_DBG_HALT                         = 38  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_JTAG_INPROG                     = 40  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_SRC_SEL_EQ1_ERR                 = 41  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_RUN_TCK_EQ0_ERR                 = 42  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_TRST_B_EQ0_ERR                  = 43  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_IR_DR_EQ0_ERR                   = 44  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_INPROG_WR_ERR                   = 45  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_FSM_ERROR                       = 46  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_DO_IR                             = 49  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_DO_DR                             = 50  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_DO_TAP_RESET                      = 51  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_WR_VALID                          = 52  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR                        = 60  ;
static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR_LEN                    = 4   ;

static const uint8_t P9N2__CTL_LCO_CONFIG_V_TARG                                  = 0   ;
static const uint8_t P9N2__CTL_LCO_CONFIG_V_TARG_LEN                              = 12  ;
static const uint8_t P9N2__CTL_LCO_CONFIG_E_TARG_MIN                              = 12  ;
static const uint8_t P9N2__CTL_LCO_CONFIG_E_TARG_MIN_LEN                          = 4   ;
static const uint8_t P9N2__CTL_LCO_CONFIG_RAND_EVENT                              = 16  ;
static const uint8_t P9N2__CTL_LCO_CONFIG_RAND_EVENT_LEN                          = 4   ;

static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_VALUE                             = 0   ;
static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_VALUE_LEN                         = 29  ;
static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_VALID                             = 32  ;
static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_RESP_PKT_RCV                      = 33  ;
static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_SECURE_ERR                        = 34  ;

static const uint8_t P9N2_PEC_LOCAL_FIR_IN0                                       = 0   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN1                                       = 1   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN2                                       = 2   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN3                                       = 3   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN4                                       = 4   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN5                                       = 5   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN6                                       = 6   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN7                                       = 7   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN8                                       = 8   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN9                                       = 9   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN10                                      = 10  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN11                                      = 11  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN12                                      = 12  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN13                                      = 13  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN14                                      = 14  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN15                                      = 15  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN16                                      = 16  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN17                                      = 17  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN18                                      = 18  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN19                                      = 19  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN20                                      = 20  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN21                                      = 21  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN22                                      = 22  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN23                                      = 23  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN24                                      = 24  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN25                                      = 25  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN26                                      = 26  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN27                                      = 27  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN28                                      = 28  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN29                                      = 29  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN30                                      = 30  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN31                                      = 31  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN32                                      = 32  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN33                                      = 33  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN34                                      = 34  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN35                                      = 35  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN36                                      = 36  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN37                                      = 37  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN38                                      = 38  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN39                                      = 39  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN40                                      = 40  ;
static const uint8_t P9N2_PEC_LOCAL_FIR_IN41                                      = 41  ;

static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION0_IN                                = 0   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION0_IN_LEN                            = 42  ;

static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION1_IN                                = 0   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION1_IN_LEN                            = 42  ;

static const uint8_t P9N2_PEC_LOCAL_FIR_MASK_LFIR_IN                              = 0   ;
static const uint8_t P9N2_PEC_LOCAL_FIR_MASK_LFIR_IN_LEN                          = 42  ;

static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN0                                 = 0   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN1                                 = 1   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN2                                 = 2   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN3                                 = 3   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN4                                 = 4   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN5                                 = 5   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN6                                 = 6   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN7                                 = 7   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN8                                 = 8   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN9                                 = 9   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN10                                = 10  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN11                                = 11  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN12                                = 12  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN13                                = 13  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN14                                = 14  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN15                                = 15  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN16                                = 16  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN17                                = 17  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN18                                = 18  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN19                                = 19  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN20                                = 20  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN21                                = 21  ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN22                                = 22  ;

static const uint8_t P9N2_PEC_LOCAL_XSTOP_MASK_IN                                 = 0   ;
static const uint8_t P9N2_PEC_LOCAL_XSTOP_MASK_IN_LEN                             = 22  ;

static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MODE_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_ONLY_MODE                        = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG                = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MIN_CRED_THRESH                  = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MIN_CRED_THRESH_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MAX_CRED_THRESH                  = 20  ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MAX_CRED_THRESH_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_CNT_THRESH                       = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_CNT_THRESH_LEN                   = 12  ;

static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MODE_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_ONLY_MODE                         = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG                 = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MIN_CRED_THRESH                   = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MIN_CRED_THRESH_LEN               = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MAX_CRED_THRESH                   = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MAX_CRED_THRESH_LEN               = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_CNT_THRESH                        = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_CNT_THRESH_LEN                    = 12  ;

static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MODE_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_ONLY_MODE                        = 1   ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG                = 2   ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MIN_CRED_THRESH                  = 8   ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MIN_CRED_THRESH_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MAX_CRED_THRESH                  = 20  ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MAX_CRED_THRESH_LEN              = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_CNT_THRESH                       = 32  ;
static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_CNT_THRESH_LEN                   = 12  ;

static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MODE_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_ONLY_MODE                         = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG                 = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MIN_CRED_THRESH                   = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MIN_CRED_THRESH_LEN               = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MAX_CRED_THRESH                   = 20  ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MAX_CRED_THRESH_LEN               = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_CNT_THRESH                        = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_CNT_THRESH_LEN                    = 12  ;

static const uint8_t P9N2__SM2_LOW_PWR_LP_MODE_ENABLE                             = 0   ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_ONLY_MODE                               = 1   ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_TIMER_TICK_CONFIG                       = 2   ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN                   = 6   ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_MIN_CRED_THRESH                         = 8   ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_MIN_CRED_THRESH_LEN                     = 12  ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_MAX_CRED_THRESH                         = 20  ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_MAX_CRED_THRESH_LEN                     = 12  ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_CNT_THRESH                              = 32  ;
static const uint8_t P9N2__SM2_LOW_PWR_LP_CNT_THRESH_LEN                          = 12  ;

static const uint8_t P9N2__SM1_LOW_PWR_LP_MODE_ENABLE                             = 0   ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_ONLY_MODE                               = 1   ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_TIMER_TICK_CONFIG                       = 2   ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN                   = 6   ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_MIN_CRED_THRESH                         = 8   ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_MIN_CRED_THRESH_LEN                     = 12  ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_MAX_CRED_THRESH                         = 20  ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_MAX_CRED_THRESH_LEN                     = 12  ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_CNT_THRESH                              = 32  ;
static const uint8_t P9N2__SM1_LOW_PWR_LP_CNT_THRESH_LEN                          = 12  ;

static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_XATS                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_XATS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR0                    = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR1                    = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ0                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB0                    = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ1                    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB1                    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_MAX_MACHINES            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED1                      = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED1_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC    = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_INTS                    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_INTS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED2                      = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED2_LEN                  = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_XATS                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_XATS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR0                    = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR1                    = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ0                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB0                    = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ1                    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB1                    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_MAX_MACHINES            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED1                      = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED1_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC    = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_INTS                    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_INTS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED2                      = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED2_LEN                  = 2   ;

static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_XATS                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_XATS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0                       = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1                       = 12  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0                       = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1                       = 30  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1                       = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES               = 42  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN           = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED1                         = 48  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       = 51  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_INTS                       = 52  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_INTS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED2                         = 58  ;
static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_XATS                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_XATS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR0                    = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR1                    = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ0                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB0                    = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ1                    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB1                    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_MAX_MACHINES            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_MAX_MACHINES_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED1                      = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED1_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC    = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_INTS                    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_INTS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED2                      = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED2_LEN                  = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_XATS                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_XATS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR0                    = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR1                    = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ0                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB0                    = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB0_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ1                    = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB1                    = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB1_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_MAX_MACHINES            = 42  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED1                      = 48  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED1_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC    = 51  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_INTS                    = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_INTS_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED2                      = 58  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED2_LEN                  = 2   ;

static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_BUSY_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_WINDOW_SELECT                 = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_WINDOW_SELECT_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_0                      = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_0_LEN                  = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_1                      = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_1_LEN                  = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_2                      = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_2_LEN                  = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_RESERVED1                     = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_RESERVED1_LEN                 = 2   ;

static const uint8_t P9N2_NV_LPCTH_CONFIG_BUSY_ENABLE                             = 0   ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_WINDOW_SELECT                           = 1   ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_WINDOW_SELECT_LEN                       = 3   ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_0                                = 4   ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_0_LEN                            = 10  ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_1                                = 14  ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_1_LEN                            = 10  ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_2                                = 24  ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_2_LEN                            = 10  ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_RESERVED1                               = 34  ;
static const uint8_t P9N2_NV_LPCTH_CONFIG_RESERVED1_LEN                           = 2   ;

static const uint8_t P9N2_PU_LPC_BASE_REG_BASE                                    = 8   ;
static const uint8_t P9N2_PU_LPC_BASE_REG_BASE_LEN                                = 24  ;
static const uint8_t P9N2_PU_LPC_BASE_REG_DISABLE                                 = 63  ;

static const uint8_t P9N2_PU_LPC_CMD_REG_RNW                                      = 0   ;
static const uint8_t P9N2_PU_LPC_CMD_REG_SIZE                                     = 5   ;
static const uint8_t P9N2_PU_LPC_CMD_REG_SIZE_LEN                                 = 7   ;
static const uint8_t P9N2_PU_LPC_CMD_REG_ADR                                      = 32  ;
static const uint8_t P9N2_PU_LPC_CMD_REG_ADR_LEN                                  = 32  ;

static const uint8_t P9N2_PU_LPC_DATA_REG_DATA                                    = 0   ;
static const uint8_t P9N2_PU_LPC_DATA_REG_DATA_LEN                                = 64  ;

static const uint8_t P9N2_PU_LPC_STATUS_REG_DONE                                  = 0   ;
static const uint8_t P9N2_PU_LPC_STATUS_REG_VALID                                 = 10  ;
static const uint8_t P9N2_PU_LPC_STATUS_REG_ACK                                   = 11  ;

static const uint8_t P9N2_PHB_MASK_REG_AIB_COMMAND_INVALID                        = 0   ;
static const uint8_t P9N2_PHB_MASK_REG_AIB_ADDRESSING_ERROR                       = 1   ;
static const uint8_t P9N2_PHB_MASK_REG_AIB_ACCESS_ERROR                           = 2   ;
static const uint8_t P9N2_PHB_MASK_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED    = 3   ;
static const uint8_t P9N2_PHB_MASK_REG_AIB_FATAL_CLASS_ERROR                      = 4   ;
static const uint8_t P9N2_PHB_MASK_REG_AIB_INF_CLASS_ERROR                        = 5   ;
static const uint8_t P9N2_PHB_MASK_REG_PE_STOP_STATE_ERROR                        = 6   ;
static const uint8_t P9N2_PHB_MASK_REG_AIB_DAT_ERR_SIGNALED                       = 7   ;
static const uint8_t P9N2_PHB_MASK_REG_OUT_COMMON_ARRAY_FATAL_ERROR               = 8   ;
static const uint8_t P9N2_PHB_MASK_REG_OUT_COMMON_LATCH_FATAL_ERROR               = 9   ;
static const uint8_t P9N2_PHB_MASK_REG_OUT_COMMON_LOGIC_FATAL_ERROR               = 10  ;
static const uint8_t P9N2_PHB_MASK_REG_BLIF_OUT_INTERFACE_PARITY_ERROR            = 11  ;
static const uint8_t P9N2_PHB_MASK_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE           = 12  ;
static const uint8_t P9N2_PHB_MASK_REG_MMIO_REQUEST_TIMEOUT                       = 13  ;
static const uint8_t P9N2_PHB_MASK_REG_OUT_RRB_SOURCED_ERROR                      = 14  ;
static const uint8_t P9N2_PHB_MASK_REG_CFG_LOGIC_SIGNALED_ERROR                   = 15  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_REG_REQUEST_ADDRESS_ERROR              = 16  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_FDA_FATAL_ERROR                        = 17  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_FDA_INF_ERROR                          = 18  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_FDB_FATAL_ERROR                        = 19  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_FDB_INF_ERROR                          = 20  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_ERR_FATAL_ERROR                        = 21  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_ERR_INF_ERROR                          = 22  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_DBG_FATAL_ERROR                        = 23  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_DBG_INF_ERROR                          = 24  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_PCIE_REQUEST_ACCESS_ERROR              = 25  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_BUS_LOGIC_ERROR                        = 26  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_UVI_FATAL_ERROR                        = 27  ;
static const uint8_t P9N2_PHB_MASK_REG_RSB_UVI_INF_ERROR                          = 28  ;
static const uint8_t P9N2_PHB_MASK_REG_SCOM_FATAL_ERROR                           = 29  ;
static const uint8_t P9N2_PHB_MASK_REG_SCOM_INF_ERROR                             = 30  ;
static const uint8_t P9N2_PHB_MASK_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS             = 31  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_IODA_FATAL_ERROR                       = 32  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_MSI_PE_MATCH_ERROR                     = 33  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_MSI_ADDRESS_ERROR                      = 34  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_TVT_ERROR                              = 35  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_RCVD_FATAL_ERROR_MSG                   = 36  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_RCVD_NONFATAL_ERROR_MSG                = 37  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG             = 38  ;
static const uint8_t P9N2_PHB_MASK_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED     = 39  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_COMMON_FATAL_ERROR                     = 40  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_TABLE_BAR_DISABLED_ERROR               = 41  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_BLIF_COMPLETION_ERROR                  = 42  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_PCT_TIMEOUT_ERROR                      = 43  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_ECC_CORRECTABLE_ERROR                  = 44  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_ECC_UNCORRECTABLE_ERROR                = 45  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_TLP_POISON_SIGNALED                    = 46  ;
static const uint8_t P9N2_PHB_MASK_REG_ARB_RTT_PENUM_INVALID_ERROR                = 47  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_COMMON_FATAL_ERROR                     = 48  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_TABLE_BAR_DISABLED_ERROR               = 49  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_ECC_CORRECTABLE_ERROR                  = 50  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_ECC_UNCORRECTABLE_ERROR                = 51  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_AIB2_TX_TIMEOUT_ERROR                  = 52  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_MRT_ERROR                              = 53  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_RESERVED01                             = 54  ;
static const uint8_t P9N2_PHB_MASK_REG_MRG_RESERVED02                             = 55  ;
static const uint8_t P9N2_PHB_MASK_REG_TCE_IODA_PAGE_ACCESS_ERROR                 = 56  ;
static const uint8_t P9N2_PHB_MASK_REG_TCE_REQUEST_TIMEOUT_ERROR                  = 57  ;
static const uint8_t P9N2_PHB_MASK_REG_TCE_UNEXPECTED_RESPONSE_ERROR              = 58  ;
static const uint8_t P9N2_PHB_MASK_REG_TCE_COMMON_FATAL_ERRORS                    = 59  ;
static const uint8_t P9N2_PHB_MASK_REG_TCE_ECC_CORRECTABLE_ERROR                  = 60  ;
static const uint8_t P9N2_PHB_MASK_REG_TCE_ECC_UNCORRECTABLE_ERROR                = 61  ;
static const uint8_t P9N2_PHB_MASK_REG_TCE_RESERVED01                             = 62  ;
static const uint8_t P9N2_PHB_MASK_REG_LEM_FIR_INTERNAL_PARITY_ERROR              = 63  ;

static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR                     = 0   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR                     = 1   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR                   = 2   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_SM_OR_CASE_ERR                       = 3   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR                 = 4   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_CRESP_ADDR_ERR                       = 5   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR                = 6   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_TTAG_PARITY_ERR                      = 7   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_UPDATE_ERR                           = 8   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR                   = 9   ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_SCOM_ERR                             = 10  ;
static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_SCOM_ERR_DUP                         = 11  ;

static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR                = 0   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR                = 1   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR              = 2   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_SM_OR_CASE_ERR                  = 3   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR            = 4   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_CRESP_ADDR_ERR                  = 5   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR           = 6   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_TTAG_PARITY_ERR                 = 7   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_UPDATE_ERR                      = 8   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR              = 9   ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR                        = 10  ;
static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR_DUP                    = 11  ;

static const uint8_t P9N2_PU_MCD_DBG_TRACE_ENABLE                                 = 3   ;
static const uint8_t P9N2_PU_MCD_DBG_TRACE_SELECT                                 = 4   ;
static const uint8_t P9N2_PU_MCD_DBG_TRACE_SELECT_LEN                             = 4   ;
static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ENABLE                               = 8   ;
static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_TYPE                                 = 9   ;
static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ACTION                               = 10  ;
static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ARRAY_SEL                            = 11  ;
static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN                        = 4   ;
static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_STATUS                               = 15  ;
static const uint8_t P9N2_PU_MCD_DBG_PMU_ENABLE                                   = 19  ;
static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_LOW                               = 20  ;
static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_LOW_LEN                           = 3   ;
static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_HIGH                              = 23  ;
static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_HIGH_LEN                          = 3   ;
static const uint8_t P9N2_PU_MCD_DBG_PMU_BUS_ENABLE                               = 32  ;
static const uint8_t P9N2_PU_MCD_DBG_PMU_BUS_ENABLE_LEN                           = 16  ;
static const uint8_t P9N2_PU_MCD_DBG_RECOVER_ADDR                                 = 48  ;
static const uint8_t P9N2_PU_MCD_DBG_RECOVER_ADDR_LEN                             = 15  ;

static const uint8_t P9N2_PU_MCD1_MCD_DBG_TRACE_ENABLE                            = 3   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_TRACE_SELECT                            = 4   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_TRACE_SELECT_LEN                        = 4   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ENABLE                          = 8   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_TYPE                            = 9   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ACTION                          = 10  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL                       = 11  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN                   = 4   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_STATUS                          = 15  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_ENABLE                              = 19  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_LOW                          = 20  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_LOW_LEN                      = 3   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_HIGH                         = 23  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_HIGH_LEN                     = 3   ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_BUS_ENABLE                          = 32  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_BUS_ENABLE_LEN                      = 16  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_RECOVER_ADDR                            = 48  ;
static const uint8_t P9N2_PU_MCD1_MCD_DBG_RECOVER_ADDR_LEN                        = 15  ;

static const uint8_t P9N2_PU_MCD_ECAP_ECC_CLEAR                                   = 0   ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_UE                                      = 2   ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_CE                                      = 3   ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_COUNT                             = 4   ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_COUNT_LEN                         = 4   ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_ADDR                              = 10  ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_ADDR_LEN                          = 14  ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_SYNDROME                                = 24  ;
static const uint8_t P9N2_PU_MCD_ECAP_ECC_SYNDROME_LEN                            = 8   ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR                       = 33  ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR                       = 34  ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR                       = 35  ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR                       = 36  ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR                       = 37  ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR                       = 38  ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR                       = 39  ;
static const uint8_t P9N2_PU_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR                       = 40  ;
static const uint8_t P9N2_PU_MCD_ECAP_PRESP_RTY_OTHER                             = 41  ;
static const uint8_t P9N2_PU_MCD_ECAP_REC_SM_ERROR_ERR                            = 42  ;
static const uint8_t P9N2_PU_MCD_ECAP_REC_PB_SM_ERROR_ERR                         = 43  ;
static const uint8_t P9N2_PU_MCD_ECAP_ADDR_ERROR_PULSE                            = 44  ;
static const uint8_t P9N2_PU_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR                     = 45  ;
static const uint8_t P9N2_PU_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR                     = 46  ;
static const uint8_t P9N2_PU_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR                     = 47  ;
static const uint8_t P9N2_PU_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR                     = 48  ;
static const uint8_t P9N2_PU_MCD_ECAP_WARB_INVALID_CASE_ERROR                     = 49  ;
static const uint8_t P9N2_PU_MCD_ECAP_INVALID_CRESP_ERROR                         = 50  ;
static const uint8_t P9N2_PU_MCD_ECAP_TTAG_PARITY_ERROR                           = 51  ;
static const uint8_t P9N2_PU_MCD_ECAP_RDADDR_ARB_BAD_HAND                         = 52  ;
static const uint8_t P9N2_PU_MCD_ECAP_RDWR_UPDATE_ERROR                           = 53  ;
static const uint8_t P9N2_PU_MCD_ECAP_REC_UPDATE_ERROR                            = 54  ;
static const uint8_t P9N2_PU_MCD_ECAP_REC_ACK_DEAD_ERROR                          = 55  ;

static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_CLEAR                              = 0   ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_UE                                 = 2   ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_CE                                 = 3   ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT                        = 4   ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT_LEN                    = 4   ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR                         = 10  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR_LEN                     = 14  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_SYNDROME                           = 24  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_SYNDROME_LEN                       = 8   ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR                  = 33  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR                  = 34  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR                  = 35  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR                  = 36  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR                  = 37  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR                  = 38  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR                  = 39  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR                  = 40  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_PRESP_RTY_OTHER                        = 41  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_SM_ERROR_ERR                       = 42  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_PB_SM_ERROR_ERR                    = 43  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ADDR_ERROR_PULSE                       = 44  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR                = 45  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR                = 46  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR                = 47  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR                = 48  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_WARB_INVALID_CASE_ERROR                = 49  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_INVALID_CRESP_ERROR                    = 50  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_TTAG_PARITY_ERROR                      = 51  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RDADDR_ARB_BAD_HAND                    = 52  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RDWR_UPDATE_ERROR                      = 53  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_UPDATE_ERROR                       = 54  ;
static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_ACK_DEAD_ERROR                     = 55  ;

static const uint8_t P9N2_PU_MCD_FIR_ACTION0_REG_ACTION0                          = 0   ;
static const uint8_t P9N2_PU_MCD_FIR_ACTION0_REG_ACTION0_LEN                      = 12  ;

static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0                     = 0   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0_LEN                 = 12  ;

static const uint8_t P9N2_PU_MCD_FIR_ACTION1_REG_ACTION1                          = 0   ;
static const uint8_t P9N2_PU_MCD_FIR_ACTION1_REG_ACTION1_LEN                      = 12  ;

static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1                     = 0   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1_LEN                 = 12  ;

static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_ARRAY_ECC_UE                        = 0   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_ARRAY_ECC_CE                        = 1   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_PB_ADDR_PARITY                      = 2   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_SM_OR_CASE                          = 3   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG                    = 4   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_CRESP_ADDR                          = 5   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_UNSOLICITED_CRESP                   = 6   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_TTAG_PARITY                         = 7   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_UPDATE_ERR                          = 8   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_ACK_DEAD_CRESP                      = 9   ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_SCOM_ERR                            = 10  ;
static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_SCOM_ERR_DUP                        = 11  ;

static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE                   = 0   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_CE                   = 1   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_PB_ADDR_PARITY                 = 2   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_SM_OR_CASE                     = 3   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG               = 4   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_CRESP_ADDR                     = 5   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_UNSOLICITED_CRESP              = 6   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_TTAG_PARITY                    = 7   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_UPDATE_ERR                     = 8   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_ACK_DEAD_CRESP                 = 9   ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR                       = 10  ;
static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP                   = 11  ;

static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_TAG_ADDR                           = 0   ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                       = 27  ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_ERR                                = 32  ;
static const uint8_t P9N2_PU_MIB_XIICAC_PIB_IFETCH_PENDING                        = 34  ;
static const uint8_t P9N2_PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING                  = 35  ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_VALID                              = 36  ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_VALID_LEN                          = 4   ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE2_VALID                        = 40  ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE2_VALID_LEN                    = 4   ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE_PTR                           = 45  ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE2_ERR                          = 46  ;
static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_PREFETCH_PENDING                   = 47  ;

static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ADDR                                   = 0   ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ADDR_LEN                               = 32  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_R_NW                                   = 32  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_BUSY                                   = 33  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING                = 34  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_BYTE_ENABLE                            = 35  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                        = 8   ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_LINE_MODE                              = 43  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ERROR                                  = 49  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ERROR_LEN                              = 3   ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_IFETCH_PENDING                         = 62  ;
static const uint8_t P9N2_PU_MIB_XIMEM_MEM_DATAOP_PENDING                         = 63  ;

static const uint8_t P9N2_PU_MIB_XISGB_STORE_ADDRESS                              = 0   ;
static const uint8_t P9N2_PU_MIB_XISGB_STORE_ADDRESS_LEN                          = 32  ;
static const uint8_t P9N2_PU_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING          = 35  ;
static const uint8_t P9N2_PU_MIB_XISGB_SGB_BYTE_VALID                             = 36  ;
static const uint8_t P9N2_PU_MIB_XISGB_SGB_BYTE_VALID_LEN                         = 4   ;
static const uint8_t P9N2_PU_MIB_XISGB_SGB_FLUSH_PENDING                          = 63  ;

static const uint8_t P9N2_PU_MIB_XISIB_PIB_ADDR                                   = 0   ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_ADDR_LEN                               = 32  ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_R_NW                                   = 32  ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_BUSY                                   = 33  ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING                = 34  ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_RSP_INFO                               = 49  ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_RSP_INFO_LEN                           = 3   ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_IFETCH_PENDING                         = 62  ;
static const uint8_t P9N2_PU_MIB_XISIB_PIB_DATAOP_PENDING                         = 63  ;

static const uint8_t P9N2__CTL_MISC_CONFIG_SYNC_WAIT                              = 0   ;
static const uint8_t P9N2__CTL_MISC_CONFIG_SYNC_WAIT_LEN                          = 5   ;
static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_ENABLE                            = 5   ;
static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_PE_MASK                           = 6   ;
static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_PE_MATCH                          = 7   ;
static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_PE_MATCH_LEN                      = 4   ;
static const uint8_t P9N2__CTL_MISC_CONFIG_IPI_PS                                 = 11  ;
static const uint8_t P9N2__CTL_MISC_CONFIG_IPI_OS                                 = 12  ;
static const uint8_t P9N2__CTL_MISC_CONFIG_OC_ATS_SYNC_START                      = 13  ;
static const uint8_t P9N2__CTL_MISC_CONFIG_CQ_RESP_VALID_ENABLE                   = 14  ;
static const uint8_t P9N2__CTL_MISC_CONFIG_RSVD                                   = 15  ;
static const uint8_t P9N2__CTL_MISC_CONFIG_RSVD_LEN                               = 49  ;

static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL0_STALL                         = 0   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL0_NOSTALL                       = 1   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL1_STALL                         = 2   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL1_NOSTALL                       = 3   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL2_STALL                         = 4   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL2_NOSTALL                       = 5   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL3_STALL                         = 6   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL3_NOSTALL                       = 7   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL4_STALL                         = 8   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL4_NOSTALL                       = 9   ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL5_STALL                         = 10  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL5_NOSTALL                       = 11  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RING_ERRP                          = 12  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_IBAR_ERRP                          = 13  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_SCOMDAA_ERRP                       = 14  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_CNTL_ERRP                          = 15  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_MM_LOCAL_XSTOP                     = 16  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX10_FAULT                         = 17  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX11_FAULT                         = 18  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX20_FAULT                         = 19  ;
static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX21_FAULT                         = 20  ;

static const uint8_t P9N2__CTL_MISC_MASK_IDIAL                                    = 0   ;
static const uint8_t P9N2__CTL_MISC_MASK_IDIAL_LEN                                = 21  ;

static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_LN              = 0   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP           = 1   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS      = 2   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN           = 3   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_LN              = 4   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP           = 5   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS      = 6   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN           = 7   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK                  = 8   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK_LEN              = 3   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN                   = 11  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN_LEN               = 4   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG                = 15  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG_LEN            = 12  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_UNUSED                         = 27  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_UNUSED_LEN                     = 4   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES                = 31  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN            = 2   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_BAR                       = 33  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_SKIP_G                         = 34  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_RESERVED                       = 35  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_RESERVED_LEN                   = 2   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_ARE            = 37  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_LINK_FAIL      = 38  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_CFG_PUMP                       = 39  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK     = 40  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN = 8   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK     = 48  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN = 8   ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK                  = 56  ;
static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK_LEN              = 7   ;

static const uint8_t P9N2_PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0                     = 0   ;
static const uint8_t P9N2_PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN                 = 40  ;

static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0              = 0   ;
static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN          = 40  ;

static const uint8_t P9N2_PHB_MMIOBAR0_REG_PE_MMIO_BAR0                           = 0   ;
static const uint8_t P9N2_PHB_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                       = 40  ;

static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0                    = 0   ;
static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                = 40  ;

static const uint8_t P9N2_PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1                     = 0   ;
static const uint8_t P9N2_PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN                 = 40  ;

static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1              = 0   ;
static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN          = 40  ;

static const uint8_t P9N2_PHB_MMIOBAR1_REG_PE_MMIO_BAR1                           = 0   ;
static const uint8_t P9N2_PHB_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                       = 40  ;

static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1                    = 0   ;
static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                = 40  ;

static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_RESERVED1                   = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_ADDR                        = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_ADDR_LEN                    = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_RESERVED2                   = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_RESERVED2_LEN               = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_NV_MMIOPA0_CONFIG_RESERVED1                             = 0   ;
static const uint8_t P9N2_NV_MMIOPA0_CONFIG_ADDR                                  = 1   ;
static const uint8_t P9N2_NV_MMIOPA0_CONFIG_ADDR_LEN                              = 35  ;
static const uint8_t P9N2_NV_MMIOPA0_CONFIG_RESERVED2                             = 36  ;
static const uint8_t P9N2_NV_MMIOPA0_CONFIG_RESERVED2_LEN                         = 3   ;
static const uint8_t P9N2_NV_MMIOPA0_CONFIG_SIZE                                  = 39  ;
static const uint8_t P9N2_NV_MMIOPA0_CONFIG_SIZE_LEN                              = 5   ;

static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_RESERVED1                   = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_ADDR                        = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_ADDR_LEN                    = 35  ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_RESERVED2                   = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_RESERVED2_LEN               = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_NV_MMIOPA1_CONFIG_RESERVED1                             = 0   ;
static const uint8_t P9N2_NV_MMIOPA1_CONFIG_ADDR                                  = 1   ;
static const uint8_t P9N2_NV_MMIOPA1_CONFIG_ADDR_LEN                              = 35  ;
static const uint8_t P9N2_NV_MMIOPA1_CONFIG_RESERVED2                             = 36  ;
static const uint8_t P9N2_NV_MMIOPA1_CONFIG_RESERVED2_LEN                         = 3   ;
static const uint8_t P9N2_NV_MMIOPA1_CONFIG_SIZE                                  = 39  ;
static const uint8_t P9N2_NV_MMIOPA1_CONFIG_SIZE_LEN                              = 5   ;

static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_0                 = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS        = 1   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_EN             = 2   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_HANGP_EN       = 3   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS                   = 8   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS               = 9   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_INV_AMORT_DIS          = 10  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_10_11             = 11  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_DIN_ECC_CHK_DIS        = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_ECC_CHK_DIS       = 13  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_PROT_ERR_CHK_DIS  = 14  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_TIMEOUT_CHK_DIS   = 15  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_PROT_ERR_CHK_DIS        = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_TIMEOUT_CHK_DIS         = 17  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_PROT_ERR_CHK_DIS      = 18  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_TIMEOUT_CHK_DIS       = 19  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_PROT_ERR_CHK_DIS       = 20  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_TIMEOUT_CHK_DIS        = 21  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_PROT_ERR_CHK_DIS        = 22  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_TIMEOUT_CHK_DIS         = 23  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_PROT_ERR_CHK_DIS   = 24  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS    = 25  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS   = 26  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_27                = 27  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD      = 28  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD_LEN  = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT              = 32  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT_LEN          = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE     = 48  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE_LEN = 8   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE     = 56  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE_LEN = 8   ;

static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS                     = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS_LEN                 = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_SNGL_THD_EN                 = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_ALLOC_DIS               = 17  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DMAP_MODE_EN                = 18  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ALT_SEGSZ_DIS               = 19  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DIR_PERR_CHK_DIS            = 20  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_PERR_CHK_DIS            = 21  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_LRU_PERR_CHK_DIS            = 22  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_MULTIHIT_CHK_DIS            = 23  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS505_FIX_DIS              = 24  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS510_FIX_DIS              = 25  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS511_FIX_DIS              = 26  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS544_FIX_DIS              = 27  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS554_FIX_DIS              = 28  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS560_FIX_DIS              = 29  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DD2_ISS584_FIX_DIS          = 30  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_31                 = 31  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL           = 32  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL_LEN       = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL           = 36  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL_LEN       = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51              = 40  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51_LEN          = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS542_FIX_DIS              = 52  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_53_56              = 53  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_53_56_LEN          = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_TWSM_11_1_MODE_ENA          = 57  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_SNGL_SHOT_ENA               = 58  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_FBC_SNGL_SHOT_HOLDOFF_ENA   = 59  ;

static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS                     = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS_LEN                 = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS                   = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS_LEN               = 8   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN         = 20  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS               = 21  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23               = 22  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23_LEN           = 2   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS487_EN                    = 24  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_25                  = 25  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS526_EN                    = 26  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29               = 27  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29_LEN           = 3   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_MPSS_DIS                  = 31  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH     = 32  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH_LEN = 8   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_HPT_SAO_FOLD_DIS      = 40  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_SAO_FOLD_DIS      = 41  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_NIO_FOLD_DIS      = 42  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_TIO_FOLD_DIS      = 43  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_EN                = 44  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_ABRT_IF_UPRC          = 45  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_ABRT_IF_PF            = 46  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_47                  = 47  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_48                  = 48  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_49                  = 49  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_50                  = 50  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PDE_EN            = 51  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_DIS               = 52  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_PWC_DIS           = 53  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_TLB_DIS           = 54  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_SPLIT_EN          = 55  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_VA_HASH           = 56  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_57                  = 57  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN           = 58  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN  = 59  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT             = 60  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT_LEN         = 4   ;

static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS                     = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS_LEN                 = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_SNGL_THD_EN                 = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_ALLOC_DIS               = 17  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DMAP_MODE_EN                = 18  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MPSS_DIS                    = 19  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_LPID_DIS               = 20  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS                = 21  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DIR_PERR_CHK_DIS            = 22  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_PERR_CHK_DIS            = 23  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_LRU_PERR_CHK_DIS            = 24  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MULTIHIT_CHK_DIS            = 25  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_EA_RANGE_CHK_DIS            = 26  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS426_FIX_DIS              = 27  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS486_FIX_DIS              = 28  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS505_FIX_DIS              = 29  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS510_FIX_DIS              = 30  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS512_FIX_DIS              = 31  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL           = 32  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN       = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL           = 36  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN       = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS534_FIX_DIS              = 40  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS537_FIX_DIS              = 41  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS540_FIX_DIS              = 42  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543_FIX_DIS              = 43  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ             = 44  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ_LEN         = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ              = 48  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ_LEN          = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS542_FIX_DIS              = 52  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543B_FIX_EN              = 53  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS567_FIX_DIS              = 54  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS586_FIX_DIS              = 55  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MPSS_PREF_PGSZ_ENA          = 56  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_TWSM_11_1_MODE_ENA          = 57  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_SNGL_SHOT_ENA               = 58  ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_SLB_SNGL_SHOT_HOLDOFF_ENA   = 59  ;

static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR                 = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR_LEN             = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR                  = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR_LEN              = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_URMOR                 = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_URMOR_LEN             = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL      = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL_LEN  = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL      = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL_LEN  = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL      = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL_LEN  = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL      = 28  ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL_LEN  = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_DISABLE                = 32  ;

static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0                     = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0_LEN                 = 48  ;

static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1                     = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1_LEN                 = 48  ;

static const uint8_t P9N2_PU_NMMU_MM_FIR1_MASK_REG_MASK                           = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_MASK_REG_MASK_LEN                       = 48  ;

static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_CE_DET             = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_UE_DET             = 1   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_SUE_DET            = 2   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_CE_DET             = 3   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_UE_DET             = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_SUE_DET            = 5   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_PROT_ERR_DET               = 6   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_TIMEOUT_DET                = 7   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_DIR_PERR_DET                    = 8   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_CAC_PERR_DET                    = 9   ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_LRU_PERR_DET                    = 10  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_MULTIHIT_DET                    = 11  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_DIR_PERR_DET                    = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_CAC_PERR_DET                    = 13  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_LRU_PERR_DET                    = 14  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_MULTIHIT_DET                    = 15  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_SEG_FAULT_DET                    = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_NOPTE_DET               = 17  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_BPCHK_DET               = 18  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_VPCHK_DET               = 19  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_SEID_DET                = 20  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_RD_DET                = 21  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PTE_UPD_FAIL_DET                 = 22  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_WR_DET                = 23  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_GUEST_DET                = 24  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_HOST_DET                 = 25  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_INVALID_WIMG_DET                 = 26  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_INV_RDX_QUAD_DET                 = 27  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_FOREIGN_ADDR_DET                 = 28  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PREFETCH_ABT_DET                 = 29  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_CXT_CAC_PERR_DET                 = 30  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_RDX_PWC_PERR_DET                 = 31  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_SM_CTL_ERR_DET                   = 32  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CO_SM_CTL_ERR_DET                   = 33  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CI_SM_CTL_ERR_DET                   = 34  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_INV_SM_CTL_ERR_DET                  = 35  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_TIMEOUT_ERR_DET                  = 36  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CO_TIMEOUT_ERR_DET                  = 37  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CI_TIMEOUT_ERR_DET                  = 38  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_INV_TIMEOUT_ERR_DET                 = 39  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_NX0_LXSTOP_ERR_DET                  = 40  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CP0_LXSTOP_ERR_DET                  = 41  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CP1_LXSTOP_ERR_DET                  = 42  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_NPU_LXSTOP_ERR_DET                  = 43  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_LXSTOP_ERR_DET                  = 44  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SPARE                               = 45  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SCOM_PE_FIR                         = 46  ;
static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SCOM_PE_DUP_FIR                     = 47  ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_EN                             = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS0_STG2_SEL              = 1   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS1_STG2_SEL              = 2   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG2_SEL              = 3   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG2_SEL              = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG2_SEL              = 5   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG2_SEL              = 6   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG2_SEL              = 7   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG2_SEL              = 8   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG2_SEL               = 9   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG2_SEL               = 10  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG2_SEL              = 11  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG2_SEL              = 12  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG2_SEL              = 13  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG2_SEL              = 14  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG1_SEL              = 15  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG1_SEL              = 16  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG1_SEL              = 17  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG1_SEL              = 18  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG1_SEL              = 19  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG1_SEL              = 20  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG1_SEL               = 21  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG1_SEL               = 22  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG1_SEL              = 23  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG1_SEL              = 24  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG1_SEL              = 25  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG1_SEL              = 26  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31                 = 27  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31_LEN             = 5   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL              = 32  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL_LEN          = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL              = 36  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL_LEN          = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL              = 40  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL_LEN          = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL              = 44  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL_LEN          = 4   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL               = 48  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL_LEN           = 6   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL               = 54  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL_LEN           = 6   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL              = 60  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL_LEN          = 2   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL              = 62  ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL_LEN          = 2   ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_INJ_INJ                             = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_INJ_INJ_LEN                         = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_LOG_LOG                             = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_LOG_LOG_LEN                         = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_FLT_STAT_REG_STAT                       = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_FLT_STAT_REG_STAT_LEN                   = 16  ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CNT_REG_CNT                        = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CNT_REG_CNT_LEN                    = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CTL_REG_CTL                        = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CTL_REG_CTL_LEN                    = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CNT_REG_CNT                        = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CNT_REG_CNT_LEN                    = 64  ;

static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CTL_REG_CTL                        = 0   ;
static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CTL_REG_CTL_LEN                    = 64  ;

static const uint8_t P9N2_PEC_MODE_REG_IN0                                        = 0   ;
static const uint8_t P9N2_PEC_MODE_REG_IN1                                        = 1   ;
static const uint8_t P9N2_PEC_MODE_REG_IN2                                        = 2   ;
static const uint8_t P9N2_PEC_MODE_REG_IN3                                        = 3   ;
static const uint8_t P9N2_PEC_MODE_REG_IN4                                        = 4   ;
static const uint8_t P9N2_PEC_MODE_REG_IN5                                        = 5   ;
static const uint8_t P9N2_PEC_MODE_REG_IN6                                        = 6   ;
static const uint8_t P9N2_PEC_MODE_REG_IN7                                        = 7   ;
static const uint8_t P9N2_PEC_MODE_REG_IN8                                        = 8   ;
static const uint8_t P9N2_PEC_MODE_REG_IN9                                        = 9   ;
static const uint8_t P9N2_PEC_MODE_REG_IN10                                       = 10  ;
static const uint8_t P9N2_PEC_MODE_REG_IN11                                       = 11  ;
static const uint8_t P9N2_PEC_MODE_REG_IN                                         = 12  ;
static const uint8_t P9N2_PEC_MODE_REG_IN_LEN                                     = 4   ;

static const uint8_t P9N2_PU_MODE_REGISTER_DCOMP_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_MODE_REGISTER_ECC_ENABLE                             = 1   ;
static const uint8_t P9N2_PU_MODE_REGISTER_PROGRAM_ENABLE                         = 2   ;
static const uint8_t P9N2_PU_MODE_REGISTER_ECC_CHK_DISABLE                        = 3   ;
static const uint8_t P9N2_PU_MODE_REGISTER_UNUSED_4_15                            = 4   ;
static const uint8_t P9N2_PU_MODE_REGISTER_UNUSED_4_15_LEN                        = 12  ;
static const uint8_t P9N2_PU_MODE_REGISTER_CLK_RATE_SEL                           = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_CLK_RATE_SEL_LEN                       = 16  ;

static const uint8_t P9N2_PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0                   = 0   ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0_LEN               = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_PORT_NUMBER_0                        = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_PORT_NUMBER_0_LEN                    = 6   ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_FGAT_0                               = 28  ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_DIAG_0                               = 29  ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_PACING_ALLOW_0                       = 30  ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_WRAP_0                               = 31  ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_PEEK_DATA1_0                         = 32  ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_PEEK_DATA1_0_LEN                     = 8   ;
static const uint8_t P9N2_PU_MODE_REGISTER_B_LBUS_PARITY_ERR1_0                   = 40  ;

static const uint8_t P9N2_PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1                   = 0   ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1_LEN               = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_PORT_NUMBER_1                        = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_PORT_NUMBER_1_LEN                    = 6   ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_FGAT_1                               = 28  ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_DIAG_1                               = 29  ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_PACING_ALLOW_1                       = 30  ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_WRAP_1                               = 31  ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_PEEK_DATA1_1                         = 32  ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_PEEK_DATA1_1_LEN                     = 8   ;
static const uint8_t P9N2_PU_MODE_REGISTER_C_LBUS_PARITY_ERR1_1                   = 40  ;

static const uint8_t P9N2_PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2                   = 0   ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2_LEN               = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_PORT_NUMBER_2                        = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_PORT_NUMBER_2_LEN                    = 6   ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_FGAT_2                               = 28  ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_DIAG_2                               = 29  ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_PACING_ALLOW_2                       = 30  ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_WRAP_2                               = 31  ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_PEEK_DATA1_2                         = 32  ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_PEEK_DATA1_2_LEN                     = 8   ;
static const uint8_t P9N2_PU_MODE_REGISTER_D_LBUS_PARITY_ERR1_2                   = 40  ;

static const uint8_t P9N2_PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3                   = 0   ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3_LEN               = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_PORT_NUMBER_3                        = 16  ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_PORT_NUMBER_3_LEN                    = 6   ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_FGAT_3                               = 28  ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_DIAG_3                               = 29  ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_PACING_ALLOW_3                       = 30  ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_WRAP_3                               = 31  ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_PEEK_DATA1_3                         = 32  ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_PEEK_DATA1_3_LEN                     = 8   ;
static const uint8_t P9N2_PU_MODE_REGISTER_E_LBUS_PARITY_ERR1_3                   = 40  ;

static const uint8_t P9N2_PEC_MULTICAST_GROUP_1_MULTICAST1                        = 3   ;
static const uint8_t P9N2_PEC_MULTICAST_GROUP_1_MULTICAST1_LEN                    = 3   ;

static const uint8_t P9N2_PEC_MULTICAST_GROUP_2_MULTICAST2                        = 3   ;
static const uint8_t P9N2_PEC_MULTICAST_GROUP_2_MULTICAST2_LEN                    = 3   ;

static const uint8_t P9N2_PEC_MULTICAST_GROUP_3_MULTICAST3                        = 3   ;
static const uint8_t P9N2_PEC_MULTICAST_GROUP_3_MULTICAST3_LEN                    = 3   ;

static const uint8_t P9N2_PEC_MULTICAST_GROUP_4_MULTICAST4                        = 3   ;
static const uint8_t P9N2_PEC_MULTICAST_GROUP_4_MULTICAST4_LEN                    = 3   ;

static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_ENABLE                      = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED1                          = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED1_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP                       = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP                        = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR                        = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    = 26  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_POISON                      = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED2                          = 37  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED2_LEN                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_SIZE                        = 39  ;
static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_SIZE_LEN                    = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED1                       = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED1_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_GROUP                    = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_GROUP_LEN                = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_CHIP                     = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_CHIP_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_ADDR                     = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_ADDR_LEN                 = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_POISON                   = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED2                       = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_SIZE                     = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_SIZE_LEN                 = 5   ;

static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_A                         = 0   ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_A_LEN                     = 4   ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_B                         = 4   ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_B_LEN                     = 4   ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_C                         = 8   ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_C_LEN                     = 4   ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_D                         = 12  ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_D_LEN                     = 4   ;
static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_ENABLE                            = 16  ;

static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE                     = 0   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PCB_EP_RESET                       = 1   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CLK_ASYNC_RESET                    = 2   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLL_TEST_EN                        = 3   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLL_RESET                          = 4   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLL_BYPASS                         = 5   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_SCAN                         = 6   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_SCAN_IN                      = 7   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_PHASE                        = 8   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_FLUSH_ALIGN_OVR                    = 9   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_AL                           = 10  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_ACT_DIS                            = 11  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_MPW1                               = 12  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_MPW2                               = 13  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_MPW3                               = 14  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_DELAY_LCLKR                        = 15  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_THOLD                        = 16  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_FLUSH_SCAN_N                       = 17  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_FENCE_EN                           = 18  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CPLT_RCTRL                         = 19  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CPLT_DCTRL                         = 20  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_ADJ_FUNC_CLKSEL                    = 22  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_TP_FENCE_PCB                       = 25  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_LVLTRANS_FENCE                     = 26  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_ARRAY_WRITE_ASSIST_EN              = 27  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_HTB_INTEST                         = 28  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_HTB_EXTEST                         = 29  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PM_ACCESS                          = 30  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLLFORCE_OUT_EN                    = 31  ;

static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PLL_CLKIN_SEL                      = 0   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_DCC_BYPASS_EN                  = 1   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PDLY_BYPASS_EN                 = 2   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_DIV_BYPASS_EN                  = 3   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX0_SEL                 = 4   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX1_SEL                 = 5   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PLL_BNDY_BYPASS_EN                 = 6   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL                      = 8   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL_LEN                  = 8   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SB_STRENGTH                        = 16  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SB_STRENGTH_LEN                    = 4   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_ASYNC_TYPE                         = 20  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_ASYNC_OBS                          = 21  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CPM_CAL_SET                        = 22  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SENSEADJ_RESET0                    = 23  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SENSEADJ_RESET1                    = 24  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PULSE_EN                       = 25  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE                     = 26  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE_LEN                 = 2   ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PCB_ACCESS                         = 28  ;
static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PCB_ACCESS_LEN                     = 4   ;

static const uint8_t P9N2_PHB_NFIRACTION0_REG_NFIRACTION0                         = 0   ;
static const uint8_t P9N2_PHB_NFIRACTION0_REG_NFIRACTION0_LEN                     = 30  ;

static const uint8_t P9N2_PEC_STACK0_NFIRACTION0_REG_NFIRACTION0                  = 0   ;
static const uint8_t P9N2_PEC_STACK0_NFIRACTION0_REG_NFIRACTION0_LEN              = 30  ;

static const uint8_t P9N2_PHB_NFIRACTION1_REG_NFIRACTION1                         = 0   ;
static const uint8_t P9N2_PHB_NFIRACTION1_REG_NFIRACTION1_LEN                     = 30  ;

static const uint8_t P9N2_PEC_STACK0_NFIRACTION1_REG_NFIRACTION1                  = 0   ;
static const uint8_t P9N2_PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN              = 30  ;

static const uint8_t P9N2_PHB_NFIRMASK_REG_NFIRMASK                               = 0   ;
static const uint8_t P9N2_PHB_NFIRMASK_REG_NFIRMASK_LEN                           = 30  ;

static const uint8_t P9N2_PEC_STACK0_NFIRMASK_REG_NFIRMASK                        = 0   ;
static const uint8_t P9N2_PEC_STACK0_NFIRMASK_REG_NFIRMASK_LEN                    = 30  ;

static const uint8_t P9N2_PHB_NFIR_REG_NFIRNFIR                                   = 0   ;
static const uint8_t P9N2_PHB_NFIR_REG_NFIRNFIR_LEN                               = 30  ;

static const uint8_t P9N2_PEC_STACK0_NFIR_REG_NFIRNFIR                            = 0   ;
static const uint8_t P9N2_PEC_STACK0_NFIR_REG_NFIRNFIR_LEN                        = 30  ;

static const uint8_t P9N2_PU_NOTRUST_BAR0_UNTRUSTED                               = 14  ;
static const uint8_t P9N2_PU_NOTRUST_BAR0_UNTRUSTED_LEN                           = 30  ;

static const uint8_t P9N2_PU_NOTRUST_BAR0MASK_UNTRUSTED                           = 14  ;
static const uint8_t P9N2_PU_NOTRUST_BAR0MASK_UNTRUSTED_LEN                       = 30  ;

static const uint8_t P9N2_PU_NOTRUST_BAR1_UNTRUSTED                               = 14  ;
static const uint8_t P9N2_PU_NOTRUST_BAR1_UNTRUSTED_LEN                           = 30  ;

static const uint8_t P9N2_PU_NOTRUST_BAR1MASK_UNTRUSTED                           = 14  ;
static const uint8_t P9N2_PU_NOTRUST_BAR1MASK_UNTRUSTED_LEN                       = 30  ;

static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_ENABLE                               = 0   ;
static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_0_SELECT                             = 1   ;
static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_0_SELECT_LEN                         = 3   ;
static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_1_SELECT                             = 4   ;
static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_1_SELECT_LEN                         = 3   ;

static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_MODE                             = 0   ;
static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_MODE_LEN                         = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_TYPE                             = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_TYPE_LEN                         = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_ENABLE                           = 4   ;
static const uint8_t P9N2__SM0_NPU_AT_ECC_ARRAY_SELECT                            = 5   ;
static const uint8_t P9N2__SM0_NPU_AT_ECC_ARRAY_SELECT_LEN                        = 4   ;

static const uint8_t P9N2__SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK                      = 0   ;
static const uint8_t P9N2__SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK_LEN                  = 20  ;

static const uint8_t P9N2__SM1_NPU_AT_ESR_IDIAL_ATS                               = 0   ;
static const uint8_t P9N2__SM1_NPU_AT_ESR_IDIAL_ATS_LEN                           = 20  ;

static const uint8_t P9N2__SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK                     = 0   ;
static const uint8_t P9N2__SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK_LEN                 = 20  ;

static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_CAPTURED                   = 0   ;
static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_SPARE                      = 1   ;
static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_SPARE_LEN                  = 2   ;
static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_DECODE                     = 3   ;
static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_DECODE_LEN                 = 5   ;
static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_INFO                       = 8   ;
static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_INFO_LEN                   = 56  ;

static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT0                                = 0   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT0_LEN                            = 16  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT1                                = 16  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT1_LEN                            = 16  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT2                                = 32  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT2_LEN                            = 16  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT3                                = 48  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT3_LEN                            = 16  ;

static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_ENABLE                 = 0   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_RESETMODE              = 1   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_FREEZEMODE             = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_DISABLE_PMISC          = 3   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PMISC_MODE             = 4   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE                = 5   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE_LEN            = 3   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0            = 8   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0_LEN        = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1            = 10  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1_LEN        = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2            = 12  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2_LEN        = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3            = 14  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3_LEN        = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0           = 16  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0_LEN       = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1           = 18  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1_LEN       = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2           = 20  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2_LEN       = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3           = 22  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3_LEN       = 2   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS                 = 24  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS_LEN             = 3   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0                      = 27  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0_LEN                  = 5   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1                      = 32  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1_LEN                  = 5   ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE                  = 37  ;
static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE_LEN              = 5   ;

static const uint8_t P9N2__SM1_NPU_Q_DMA_R_QUIESCE                                = 0   ;
static const uint8_t P9N2__SM1_NPU_Q_DMA_R_QUIESCE_AUTO_RESET                     = 1   ;
static const uint8_t P9N2__SM1_NPU_Q_DMA_R_RESPONSE                               = 4   ;
static const uint8_t P9N2__SM1_NPU_Q_DMA_R_TCE_RESPONSE                           = 6   ;

static const uint8_t P9N2__CTL_NPU_VERSION_RSVD0                                  = 0   ;
static const uint8_t P9N2__CTL_NPU_VERSION_RSVD0_LEN                              = 24  ;
static const uint8_t P9N2__CTL_NPU_VERSION_MAJOR                                  = 24  ;
static const uint8_t P9N2__CTL_NPU_VERSION_MAJOR_LEN                              = 8   ;
static const uint8_t P9N2__CTL_NPU_VERSION_RSVD1                                  = 32  ;
static const uint8_t P9N2__CTL_NPU_VERSION_RSVD1_LEN                              = 16  ;
static const uint8_t P9N2__CTL_NPU_VERSION_MINOR                                  = 48  ;
static const uint8_t P9N2__CTL_NPU_VERSION_MINOR_LEN                              = 16  ;

static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK0                                  = 0   ;
static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK0_LEN                              = 32  ;
static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK1                                  = 32  ;
static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK1_LEN                              = 16  ;
static const uint8_t P9N2_PEC_NRDSTKOVR_REG_ENABLE                                = 48  ;

static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK0                                 = 0   ;
static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK0_LEN                             = 8   ;
static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK1                                 = 8   ;
static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK1_LEN                             = 4   ;
static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_ENABLE                               = 12  ;

static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK0                                  = 0   ;
static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK0_LEN                              = 16  ;
static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK1                                  = 16  ;
static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK1_LEN                              = 8   ;
static const uint8_t P9N2_PEC_NWRSTKOVR_REG_ENABLE                                = 24  ;

static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN                   = 0   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP                = 1   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS           = 2   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN                = 3   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_LN                   = 4   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP                = 5   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS           = 6   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN                = 7   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_LN                  = 8   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_GROUP               = 9   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_VG_NOT_SYS          = 10  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_NN_RN               = 11  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_LN                  = 12  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_GROUP               = 13  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_VG_NOT_SYS          = 14  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_NN_RN               = 15  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES                     = 16  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN                 = 2   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_RESERVED                            = 18  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_RESERVED_LEN                        = 2   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_NOT_INJECT                   = 20  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_PARTIAL_WRT_NOT_INJECT          = 21  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_RD_GO_M_QOS                         = 22  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ADDR_BAR                            = 23  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_SKIP_G                              = 24  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG                = 25  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG_LEN            = 2   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_HANG_SM_ON_ARE                      = 27  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_HANG_SM_ON_LINK_FAIL                = 28  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_CFG_PUMP                            = 29  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DISABLE_FLOW_SCOPE                  = 30  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DISABLE_PMU_SNOOPING                = 31  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ENDABLE_PMU_CNT_RESET               = 32  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DISABLE_WRP                         = 33  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_SMF_CONFIG                          = 34  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_SMF_CONFIG_LEN                      = 2   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UNUSED                              = 36  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UNUSED_LEN                          = 4   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK          = 40  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN      = 8   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK          = 48  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN      = 8   ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ADDR_EXT_MASK                       = 56  ;
static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ADDR_EXT_MASK_LEN                   = 7   ;

static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0                   = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN               = 22  ;

static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION0_REG_ACTION0                        = 0   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN                    = 44  ;

static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1                   = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN               = 21  ;

static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION1_REG_ACTION1                        = 0   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN                    = 44  ;

static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_MASK_REG_MASK                         = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_MASK_REG_MASK_LEN                     = 22  ;

static const uint8_t P9N2_PU_NX_CQ_FIR_MASK_REG_MASK                              = 0   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_MASK_REG_MASK_LEN                          = 44  ;

static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBI_PE                            = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_CMD_HANG                     = 1   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_READ_ARE                     = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_WRITE_ARE                    = 3   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_MISC_HW                      = 4   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_RSVD                              = 5   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_UE                  = 6   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_SUE                 = 7   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_CE                       = 8   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_UE                       = 9   ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_SUE                      = 10  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_CE             = 11  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_UE             = 12  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_SUE            = 13  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE                 = 14  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE                 = 15  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INT_STATE_ERR                     = 16  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR                = 17  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR               = 18  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_LINK_ABORT                   = 19  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_SCOM_PE                           = 20  ;
static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_SCOM_PE_DUP                       = 21  ;

static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBI_PE                                 = 0   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_ECC_CE                            = 1   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_ECC_UE                            = 2   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_ECC_SUE                           = 3   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE                      = 4   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE                      = 5   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PASTE_REJECT                           = 6   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_CMD_HANG                          = 7   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_READ_ARE                          = 8   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_WRITE_ARE                         = 9   ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_MISC_HW                           = 10  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_MMIO_BAR_PE                            = 11  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_WC_INT_ADDR_UE                    = 12  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR                     = 13  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR                    = 14  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_LINK_ABORT                        = 15  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBI_INTERNAL_HANG                      = 16  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_PE                          = 17  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_CE                          = 18  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_UE                          = 19  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_SUE                         = 20  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_CICO_HANG                         = 21  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_CNTRL_ERR                         = 22  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PB_XLAT_DATA_UE                        = 23  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PB_XLAT_DATA_SUE                       = 24  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_LD_LINK_ERR                       = 25  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_LINK_ABORT                        = 26  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_CRB_UE                            = 27  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_CRB_SUE                           = 28  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_LOCAL_CSTOP                       = 29  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_OTHER_SCOM_PE                          = 30  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_SCOM_WRITE                         = 31  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_FIRST_FAIL                         = 32  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_SECOND_FAIL                        = 33  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_CNTRL_LOGIC_ERR                    = 34  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_NMMU_LOCAL_XSTOP                       = 35  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_VAS_LOCAL_XSTOP                        = 36  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBCQ_CNTRL_LOGIC_ERR                   = 37  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_FAILED_LINK_ON_INTERRUPT               = 38  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_WC_INT_ADDR_SUE                   = 39  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SPARE_40                               = 40  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SPARE_41                               = 41  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SCOM_PE                                = 42  ;
static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SCOM_PE_DUP                            = 43  ;

static const uint8_t P9N2_PU_NX_DEBUGMUX_CTRL_BITS                                = 47  ;
static const uint8_t P9N2_PU_NX_DEBUGMUX_CTRL_BITS_LEN                            = 14  ;

static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63                       = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN                   = 64  ;

static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_0_B0_63                            = 0   ;
static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN                        = 64  ;

static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87                      = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN                  = 24  ;

static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_1_B64_87                           = 0   ;
static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN                       = 24  ;

static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_HANG_TIMER                            = 0   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_SHM_INVALID_STATE                     = 1   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_02                           = 2   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_03                           = 3   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_ECC_CE                        = 4   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_ECC_UE                        = 5   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_ECC_CE                        = 6   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_ECC_UE                        = 7   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_NONZERO_CSB_CC                        = 8   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ECC_CE                                = 9   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_CE                     = 10  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_ECC_CE                       = 11  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_ECC_UE                       = 12  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_PE                           = 13  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OTHER_SCOM_SAT                        = 14  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_INVALID_STATE_UNRECOV                 = 15  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_INVALID_STATE_RECOV                   = 16  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ECC_UE                                = 17  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_UE                     = 18  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_INRD_DONE_ERR                         = 19  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_INVALID_STATE                 = 20  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_INVALID_STATE                 = 21  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH2_SYM_INVALID_STATE                 = 22  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH3_SYM_INVALID_STATE                 = 23  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_INVALID_STATE                = 24  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_25                           = 25  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_26                           = 26  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_27                           = 27  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_28                           = 28  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_29                           = 29  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_30                           = 30  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CRB_ECC_UE                            = 31  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CRB_ECC_SUE                           = 32  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_SUE                    = 33  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_WATCHDOG                      = 34  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_WATCHDOG                      = 35  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH2_SYM_WATCHDOG                      = 36  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH3_SYM_WATCHDOG                      = 37  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_38                           = 38  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_WATCHDOG                     = 39  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_40                           = 40  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_41                           = 41  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_42                           = 42  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_43                           = 43  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_44                           = 44  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_45                           = 45  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_46                           = 46  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_47                           = 47  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_SCOM_PE                               = 48  ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_SCOM_PE_DUP                           = 49  ;

static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION0_BITS                          = 0   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION0_BITS_LEN                      = 50  ;

static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION1_BITS                          = 0   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION1_BITS_LEN                      = 50  ;

static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_MASK_BITS                             = 0   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_MASK_BITS_LEN                         = 50  ;

static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_WOF_BITS                              = 0   ;
static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_WOF_BITS_LEN                          = 50  ;

static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_ENA                          = 2   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_TYPE                         = 3   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_ACTION                       = 4   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT                       = 5   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT_LEN                   = 4   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_ENA                          = 9   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_TYPE                         = 10  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_ACTION                       = 11  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT                       = 12  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT_LEN                   = 4   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INWR_ENA                        = 23  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INWR_TYPE                       = 24  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INWR_ACTION                     = 25  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ENA                       = 26  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_TYPE                      = 27  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ACTION                    = 28  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ENA                    = 29  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_TYPE                   = 30  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ACTION                 = 31  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT                 = 32  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT_LEN             = 4   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ENA                    = 36  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_TYPE                   = 37  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ACTION                 = 38  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT                 = 39  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT_LEN             = 4   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ENA                    = 43  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_TYPE                   = 44  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ACTION                 = 45  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_SELECT                 = 46  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_ENA                         = 48  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_TYPE                        = 49  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_ACTION                      = 50  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT                      = 51  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT_LEN                  = 8   ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW0_UEINJ_ENA             = 59  ;
static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW4_UEINJ_ENA             = 60  ;

static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE             = 4   ;
static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN         = 4   ;
static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE             = 8   ;
static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN         = 4   ;
static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE              = 12  ;
static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN          = 4   ;

static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE                  = 4   ;
static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN              = 4   ;
static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE                  = 8   ;
static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN              = 4   ;
static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE                   = 12  ;
static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN               = 4   ;
static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE             = 16  ;
static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE_LEN         = 4   ;

static const uint8_t P9N2_PU_NX_MMIO_BAR_BAR                                      = 8   ;
static const uint8_t P9N2_PU_NX_MMIO_BAR_BAR_LEN                                  = 44  ;
static const uint8_t P9N2_PU_NX_MMIO_BAR_ENABLE                                   = 52  ;

static const uint8_t P9N2_PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL                 = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN             = 8   ;

static const uint8_t P9N2_PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL                      = 0   ;
static const uint8_t P9N2_PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN                  = 8   ;

static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE                  = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN              = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE                  = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN              = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE           = 4   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY                   = 5   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN               = 4   ;

static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE                       = 0   ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE                       = 2   ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE                = 4   ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY                        = 5   ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN                    = 4   ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ENABLE                 = 16  ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ACTION                 = 17  ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ENABLE                 = 24  ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_TYPE                   = 25  ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ACTION                 = 26  ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT                 = 27  ;
static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT_LEN             = 4   ;

static const uint8_t P9N2_PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT              = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN          = 52  ;
static const uint8_t P9N2_PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE                  = 52  ;

static const uint8_t P9N2_PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT                   = 0   ;
static const uint8_t P9N2_PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN               = 63  ;
static const uint8_t P9N2_PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE                       = 63  ;

static const uint8_t P9N2_PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT                   = 0   ;
static const uint8_t P9N2_PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT_LEN               = 11  ;

static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_FREEZE                           = 1   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_RESET                            = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_DIS_GLOB_SCOM                    = 3   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0                   = 4   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1                   = 6   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2                   = 8   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3                   = 10  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP                     = 12  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP                     = 14  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP                     = 16  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP                     = 18  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL                     = 20  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL                     = 23  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL                     = 26  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL                     = 29  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_FREEZE_ON_OVERFLOW               = 32  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CASCADE                          = 33  ;
static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CASCADE_LEN                      = 3   ;

static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_0                                = 0   ;
static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_0_LEN                            = 16  ;
static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_1                                = 16  ;
static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_1_LEN                            = 16  ;
static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_2                                = 32  ;
static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_2_LEN                            = 16  ;
static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_3                                = 48  ;
static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_3_LEN                            = 16  ;

static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_FREEZE                           = 1   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_RESET                            = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_DIS_GLOB_SCOM                    = 3   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0                   = 4   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1                   = 6   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2                   = 8   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3                   = 10  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3_LEN               = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP                     = 12  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP                     = 14  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP                     = 16  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP                     = 18  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL                     = 20  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL                     = 23  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL                     = 26  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL                     = 29  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL_LEN                 = 3   ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_FREEZE_ON_OVERFLOW               = 32  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CASCADE                          = 33  ;
static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CASCADE_LEN                      = 3   ;

static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_0                                = 0   ;
static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_0_LEN                            = 16  ;
static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_1                                = 16  ;
static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_1_LEN                            = 16  ;
static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_2                                = 32  ;
static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_2_LEN                            = 16  ;
static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_3                                = 48  ;
static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_3_LEN                            = 16  ;

static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_ENABLE                  = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_ENABLE                  = 1   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_ENABLE                  = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_ENABLE                  = 3   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL                = 4   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL_LEN            = 3   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_POSEDGE_SEL             = 7   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_POSEDGE_SEL             = 8   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_POSEDGE_SEL             = 9   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_POSEDGE_SEL             = 10  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_RESET                        = 11  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL               = 12  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL_LEN           = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL            = 14  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL_LEN        = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL               = 16  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL_LEN           = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL            = 18  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL_LEN        = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL               = 20  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL_LEN           = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL            = 22  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL_LEN        = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL               = 24  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL_LEN           = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL            = 26  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL_LEN        = 2   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL                     = 28  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL_LEN                 = 2   ;

static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_0                            = 0   ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_0_LEN                        = 16  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_1                            = 16  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_1_LEN                        = 16  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_2                            = 32  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_2_LEN                        = 16  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_3                            = 48  ;
static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_3_LEN                        = 16  ;

static const uint8_t P9N2_PU_NX_RNG_BYPASS_RRN_DATA                               = 0   ;
static const uint8_t P9N2_PU_NX_RNG_BYPASS_RRN_DATA_LEN                           = 64  ;

static const uint8_t P9N2_PU_NX_RNG_CFG_FAIL_REG                                  = 0   ;
static const uint8_t P9N2_PU_NX_RNG_CFG_FAIL_REG_LEN                              = 10  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_RNG0_FAIL                                 = 10  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_RNG1_FAIL                                 = 11  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_INTERRUPT_SENT                            = 12  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_ENABLE                               = 16  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_COMPLETE                             = 17  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_RNG0_BIST_FAIL                            = 18  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_RNG1_BIST_FAIL                            = 19  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_BIT_FAIL_TH                          = 20  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_BIT_FAIL_TH_LEN                      = 3   ;
static const uint8_t P9N2_PU_NX_RNG_CFG_RNG0_INJ_CONTINOUS_ERROR                  = 23  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_RNG1_INJ_CONTINOUS_ERROR                  = 24  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_ST2_RESET_PERIOD                          = 30  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_ST2_RESET_PERIOD_LEN                      = 8   ;
static const uint8_t P9N2_PU_NX_RNG_CFG_RRN_BYPASS_ENABLE                         = 38  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_MASK_TOGGLE_ENABLE                        = 39  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_SAMPTEST_ENABLE                           = 40  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_REPTEST_ENABLE                            = 41  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_ADAPTEST_1BIT_ENABLE                      = 42  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_ADAPTEST_ENABLE                           = 43  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_COND_STARTUP_TEST_FAIL                    = 44  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_PACE_RATE                                 = 46  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_PACE_RATE_LEN                             = 16  ;
static const uint8_t P9N2_PU_NX_RNG_CFG_ENABLE                                    = 63  ;

static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD                      = 0   ;
static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD_LEN                  = 2   ;
static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD                     = 2   ;
static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD_LEN                 = 2   ;
static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_LFSR_RESEED_EN                      = 6   ;
static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO                      = 7   ;
static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN                  = 5   ;

static const uint8_t P9N2_PU_NX_RNG_RESET_RESET                                   = 0   ;

static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_MATCH_TH                          = 0   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN                      = 2   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH                      = 2   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH_LEN                  = 5   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE                      = 7   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN                  = 2   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE                      = 9   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH                = 12  ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN            = 12  ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH                = 24  ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN            = 12  ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH                = 36  ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN            = 12  ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH                = 48  ;
static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN            = 12  ;

static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH                     = 0   ;
static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN                 = 7   ;
static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN                = 7   ;
static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN            = 16  ;
static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX                = 23  ;
static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN            = 16  ;

static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0         = 0   ;
static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN     = 8   ;
static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1         = 8   ;
static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN     = 8   ;
static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0         = 16  ;
static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN     = 8   ;
static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1         = 24  ;
static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN     = 8   ;
static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0              = 32  ;
static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN          = 6   ;
static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1              = 38  ;
static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN          = 6   ;

static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_RRN_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE                      = 1   ;
static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN                     = 4   ;
static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN                 = 16  ;
static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX                     = 20  ;
static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN                 = 16  ;

static const uint8_t P9N2_PU_NX_TRIGGER_CTRL_BITS                                 = 50  ;
static const uint8_t P9N2_PU_NX_TRIGGER_CTRL_BITS_LEN                             = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_CCSR_CORE_CONFIG                             = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_CCSR_CORE_CONFIG_LEN                         = 24  ;
static const uint8_t P9N2_PU_OCB_OCI_CCSR_RESERVED_24                             = 24  ;
static const uint8_t P9N2_PU_OCB_OCI_CCSR_RESERVED_24_LEN                         = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_CCSR_CHANGE_IN_PROGRESS                      = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVIDEND                                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVIDEND_LEN                            = 32  ;
static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVISOR                                 = 32  ;
static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVISOR_LEN                             = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_DORP_QUOTIENT                                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_DORP_QUOTIENT_LEN                            = 32  ;
static const uint8_t P9N2_PU_OCB_OCI_DORP_REMAINDER                               = 32  ;
static const uint8_t P9N2_PU_OCB_OCI_DORP_REMAINDER_LEN                           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N           = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0B_O2SCMD_A_N_RESERVED_0               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0B_O2S_CLEAR_STICKY_BITS_A_N           = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1A_O2SCMD_A_N_RESERVED_0               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1A_O2S_CLEAR_STICKY_BITS_A_N           = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1B_O2SCMD_A_N_RESERVED_0               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1B_O2S_CLEAR_STICKY_BITS_A_N           = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_BRIDGE_ENABLE_A_N             = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CPOL_A_N                      = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CPHA_A_N                      = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N             = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N_LEN         = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16       = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16_LEN   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_NR_OF_FRAMES_A_N              = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_BRIDGE_ENABLE_A_N             = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CPOL_A_N                      = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CPHA_A_N                      = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N             = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N_LEN         = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16       = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16_LEN   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_NR_OF_FRAMES_A_N              = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_BRIDGE_ENABLE_A_N             = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CPOL_A_N                      = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CPHA_A_N                      = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N             = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N_LEN         = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16       = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16_LEN   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_NR_OF_FRAMES_A_N              = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_BRIDGE_ENABLE_A_N             = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CPOL_A_N                      = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CPHA_A_N                      = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N             = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N_LEN         = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16       = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16_LEN   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_NR_OF_FRAMES_A_N              = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N_LEN     = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N_LEN     = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N_LEN     = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N_LEN     = 17  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N                = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N                 = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N                = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N                 = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N                = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N                 = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N                = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N                 = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N_LEN            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N_LEN             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N                 = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N_LEN             = 6   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2S_ONGOING_A_N                      = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4               = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4_LEN           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_6                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2S_FSM_ERR_A_N                      = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2S_ONGOING_A_N                      = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4               = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4_LEN           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_6                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2S_FSM_ERR_A_N                      = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2S_ONGOING_A_N                      = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4               = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4_LEN           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_6                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2S_FSM_ERR_A_N                      = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2S_ONGOING_A_N                      = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4               = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4_LEN           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_6                 = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2S_FSM_ERR_A_N                      = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_ENABLE                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_SPARE_0                             = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_SPARE_0_LEN                         = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR                   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR_LEN               = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK                  = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK_LEN              = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_ENABLE                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_SPARE_0                             = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_SPARE_0_LEN                         = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR                   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR_LEN               = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK                  = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK_LEN              = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_ENABLE                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_SPARE_0                             = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_SPARE_0_LEN                         = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR                   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR_LEN               = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK                  = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK_LEN              = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_ENABLE                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_SPARE_0                             = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_SPARE_0_LEN                         = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR                   = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR_LEN               = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK                  = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK_LEN              = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION_LEN           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE                 = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE_LEN             = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION_LEN           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE                 = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE_LEN             = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION_LEN           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE                 = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE_LEN             = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION_LEN           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE                 = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE_LEN             = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP_LEN            = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_SPARE0                              = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_SPARE0_LEN                          = 5   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP_LEN            = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_SPARE0                              = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_SPARE0_LEN                          = 5   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP_LEN            = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_SPARE0                              = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_SPARE0_LEN                          = 5   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP_LEN            = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_SPARE0                              = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_SPARE0_LEN                          = 5   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSES0_PUSH_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSES0_PULL_WRITE_OVERFLOW                  = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSES1_PUSH_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSES1_PULL_WRITE_OVERFLOW                  = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSES2_PUSH_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSES2_PULL_WRITE_OVERFLOW                  = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSES3_PUSH_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSES3_PULL_WRITE_OVERFLOW                  = 1   ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_REGION                         = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_REGION_LEN                     = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_START                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_START_LEN                      = 26  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_FULL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_EMPTY                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_SPARE                               = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_SPARE_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1                = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1_LEN            = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_LENGTH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_LENGTH_LEN                     = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR                      = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR_LEN                  = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR_LEN                   = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_ENABLE                         = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OCCFLG_OCC_FLAGS                             = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCFLG_OCC_FLAGS_LEN                         = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OCCFLG2_OCC_FLAGS                            = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCFLG2_OCC_FLAGS_LEN                        = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT                   = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT_LEN               = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN                      = 16  ;

static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_CORE_EXT_INTR                        = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE_1_3                            = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE_1_3_LEN                        = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN                       = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN_LEN                   = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_GROSS                    = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_FINE                     = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_FIRMWARE_FAULT                       = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_FIRMWARE_NOTIFY                      = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE                                = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE_LEN                            = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS                     = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS_LEN                 = 3   ;

static const uint8_t P9N2_PU_OCB_OCI_OCCS0_OCC_SCRATCH_N                          = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCS0_OCC_SCRATCH_N_LEN                      = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OCCS1_OCC_SCRATCH_N                          = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCS1_OCC_SCRATCH_N_LEN                      = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OCCS2_OCC_SCRATCH_N                          = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCCS2_OCC_SCRATCH_N_LEN                      = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M0_PRIORITY                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M0_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M1_PRIORITY                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M1_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M2_PRIORITY                           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M2_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M3_PRIORITY                           = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M3_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M4_PRIORITY                           = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M4_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M5_PRIORITY                           = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M5_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M6_PRIORITY                           = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M6_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M7_PRIORITY                           = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M7_PRIORITY_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M0_PRIORITY_SEL                       = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M1_PRIORITY_SEL                       = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M2_PRIORITY_SEL                       = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M3_PRIORITY_SEL                       = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_OCICFG_RESERVED_20                    = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M5_PRIORITY_SEL                       = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_OCICFG_RESERVED_23                    = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M7_PRIORITY_SEL                       = 23  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_PLBARB_LOCKERR                        = 24  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_SPARE_24_31                           = 25  ;
static const uint8_t P9N2_PU_OCB_OCI_OCICFG_SPARE_24_31_LEN                       = 7   ;

static const uint8_t P9N2_PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N_LEN           = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N              = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N_LEN          = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N              = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N_LEN          = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY                       = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN                   = 20  ;

static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_SRC_SEL                           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_SRC_SEL_LEN                       = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_STOP                              = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS                 = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS_LEN             = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE                       = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE_LEN                   = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_EN                         = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_EN_LEN                     = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL                       = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL_LEN                   = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_OCC                        = 23  ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE0                       = 24  ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE1                       = 25  ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE2                       = 26  ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE3                       = 27  ;
static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_HALT_STATE                 = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N                  = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N_LEN              = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N                  = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N_LEN              = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N                       = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N_LEN                   = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N                       = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N_LEN                   = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N                   = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N_LEN               = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N                   = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N_LEN               = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N                   = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N_LEN               = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N                   = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N_LEN               = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N                   = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N_LEN               = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N                   = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N_LEN               = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OISR0_DEBUGGER                               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_TRACE_TRIGGER                          = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_ERROR                              = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_PBA_ERROR                              = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_SRT_ERROR                              = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE0_ERROR                             = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE1_ERROR                             = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE2_ERROR                             = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE3_ERROR                             = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_PPC405_HALT                            = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_ERROR                                  = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_SPARE_11                               = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_PPC405                      = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE0                        = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE1                        = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE2                        = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE3                        = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_MALF_ALERT                         = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_ADU_MALF_ALERT                         = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_EXTERNAL_TRAP                          = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_IVRM_PVREF_ERROR                       = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_TIMER0                             = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_TIMER1                             = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_AVS_SLAVE0                             = 23  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_AVS_SLAVE1                             = 24  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI0_HI_PRIORITY                       = 25  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI1_HI_PRIORITY                       = 26  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI2_HI_PRIORITY                       = 27  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI3_HI_PRIORITY                       = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI4_HI_PRIORITY                       = 29  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_ADCFSM_ONGOING                         = 30  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR0_I2CM_INTER                             = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBAX_OCC_SEND_ATTN                     = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBAX_OCC_PUSH0                         = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBAX_OCC_PUSH1                         = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBA_BCDE_ATTN                          = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBA_BCUE_ATTN                          = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM0_PULL                         = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM0_PUSH                         = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM1_PULL                         = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM1_PUSH                         = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM2_PULL                         = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM2_PUSH                         = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM3_PULL                         = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM3_PUSH                         = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE0_PENDING             = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE1_PENDING             = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE2_PENDING             = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE3_PENDING             = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE4_PENDING             = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE5_PENDING             = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE6_PENDING             = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE7_PENDING             = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_0A_ONGOING                     = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_0B_ONGOING                     = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_1A_ONGOING                     = 23  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_1B_ONGOING                     = 24  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_PSSBRIDGE_ONGOING                      = 25  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI0_LO_PRIORITY                       = 26  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI1_LO_PRIORITY                       = 27  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI2_LO_PRIORITY                       = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI3_LO_PRIORITY                       = 29  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI4_LO_PRIORITY                       = 30  ;
static const uint8_t P9N2_PU_OCB_OCI_OISR1_SPARE_31                               = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N                       = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N_LEN                   = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N                       = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN                   = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N            = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N_LEN        = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N            = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N_LEN        = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_5           = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_6           = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_7           = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_8           = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_9           = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_10          = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_11          = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_12          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_13          = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_14          = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_15          = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_16          = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_17          = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_18          = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_19          = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_20          = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_21          = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_22          = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_23          = 23  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_5           = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_6           = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_7           = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_8           = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_9           = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_10          = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_11          = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_12          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_13          = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_14          = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_15          = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_16          = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_17          = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_18          = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_19          = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_20          = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_21          = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_22          = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_23          = 23  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_5           = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_6           = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_7           = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_8           = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_9           = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_10          = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_11          = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_12          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_13          = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_14          = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_15          = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_16          = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_17          = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_18          = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_19          = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_20          = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_21          = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_22          = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_23          = 23  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_5           = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_6           = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_7           = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_8           = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_9           = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_10          = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_11          = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_12          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_13          = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_14          = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_15          = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_16          = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_17          = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_18          = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_19          = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_20          = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_21          = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_22          = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_23          = 23  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_5           = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_6           = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_7           = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_8           = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_9           = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_10          = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_11          = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_12          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_13          = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_14          = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_15          = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_16          = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_17          = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_18          = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_19          = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_20          = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_21          = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_22          = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_23          = 23  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N              = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N_LEN          = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N               = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N_LEN           = 12  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_5           = 5   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_6           = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_7           = 7   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_8           = 8   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_9           = 9   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_10          = 10  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_11          = 11  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_12          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_13          = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_14          = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_15          = 15  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_16          = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_17          = 17  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_18          = 18  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_19          = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_20          = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_21          = 21  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_22          = 22  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_23          = 23  ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_5           = 5   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_0           = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_1           = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_2           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_3           = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_4           = 4   ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_5           = 5   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N               = 28  ;
static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N_LEN           = 4   ;

static const uint8_t P9N2_PU_OCB_OCI_OTBR_TIMEBASE                                = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OTBR_TIMEBASE_LEN                            = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OTR0_TIMEOUT_N                               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR0_CONTROL_N                               = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR0_AUTO_RELOAD_N                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR0_SPARE_N                                 = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR0_SPARE_N_LEN                             = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OTR0_TIMER_N                                 = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OTR0_TIMER_N_LEN                             = 16  ;

static const uint8_t P9N2_PU_OCB_OCI_OTR1_TIMEOUT_N                               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR1_CONTROL_N                               = 1   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR1_AUTO_RELOAD_N                           = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR1_SPARE_N                                 = 3   ;
static const uint8_t P9N2_PU_OCB_OCI_OTR1_SPARE_N_LEN                             = 13  ;
static const uint8_t P9N2_PU_OCB_OCI_OTR1_TIMER_N                                 = 16  ;
static const uint8_t P9N2_PU_OCB_OCI_OTR1_TIMER_N_LEN                             = 16  ;

static const uint8_t P9N2_PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N              = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N_LEN          = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N              = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N_LEN          = 32  ;

static const uint8_t P9N2_PU_OCB_OCI_QCSR_EX_CONFIG                               = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_QCSR_EX_CONFIG_LEN                           = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_QCSR_RESERVED_12_30                          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_QCSR_RESERVED_12_30_LEN                      = 19  ;
static const uint8_t P9N2_PU_OCB_OCI_QCSR_CHANGE_IN_PROGRESS                      = 31  ;

static const uint8_t P9N2_PU_OCB_OCI_QSSR_L2_STOPPED                              = 0   ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_L2_STOPPED_LEN                          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_RESERVED_12_13                          = 12  ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_RESERVED_12_13_LEN                      = 2   ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_QUAD_STOPPED                            = 14  ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_QUAD_STOPPED_LEN                        = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_ENTRY_ONGOING                      = 20  ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_ENTRY_ONGOING_LEN                  = 6   ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_EXIT_ONGOING                       = 26  ;
static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_EXIT_ONGOING_LEN                   = 6   ;

static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_PRIORITY_MODE                       = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER                      = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER_LEN                  = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_HI_BUS_MODE                         = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL               = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL_LEN           = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_WRITE_PIPELINE_CONTROL              = 7   ;

static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_OCI_REGION                            = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_OCI_REGION_LEN                        = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_ADDRESS                               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_ADDRESS_LEN                           = 26  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_OCI_REGION                            = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_OCI_REGION_LEN                        = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_ADDRESS                               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_ADDRESS_LEN                           = 26  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_OCI_REGION                            = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_OCI_REGION_LEN                        = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_ADDRESS                               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_ADDRESS_LEN                           = 26  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_OCI_REGION                            = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_OCI_REGION_LEN                        = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_ADDRESS                               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_ADDRESS_LEN                           = 26  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW                  = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW_EN               = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW_EN               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_STREAM_MODE                          = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_STREAM_TYPE                          = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE0                               = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE0_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_OCI_TIMEOUT                          = 8   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_OCI_READ_DATA_PARITY                 = 9   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_OCI_SLAVE_ERROR                      = 10  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_ADDR_PARITY_ERR                      = 11  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_DATA_PARITY_ERR                      = 12  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE1                               = 13  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_FSM_ERR                              = 14  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE2                               = 15  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW                  = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW_EN               = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW_EN               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_STREAM_MODE                          = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_STREAM_TYPE                          = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE0                               = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE0_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_OCI_TIMEOUT                          = 8   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_OCI_READ_DATA_PARITY                 = 9   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_OCI_SLAVE_ERROR                      = 10  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_ADDR_PARITY_ERR                      = 11  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_DATA_PARITY_ERR                      = 12  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE1                               = 13  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_FSM_ERR                              = 14  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE2                               = 15  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW                  = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW_EN               = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW_EN               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_STREAM_MODE                          = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_STREAM_TYPE                          = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE0                               = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE0_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_OCI_TIMEOUT                          = 8   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_OCI_READ_DATA_PARITY                 = 9   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_OCI_SLAVE_ERROR                      = 10  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_ADDR_PARITY_ERR                      = 11  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_DATA_PARITY_ERR                      = 12  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE1                               = 13  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_FSM_ERR                              = 14  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE2                               = 15  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW                  = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW_EN               = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW_EN               = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_STREAM_MODE                          = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_STREAM_TYPE                          = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE0                               = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE0_LEN                           = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_OCI_TIMEOUT                          = 8   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_OCI_READ_DATA_PARITY                 = 9   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_OCI_SLAVE_ERROR                      = 10  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_ADDR_PARITY_ERR                      = 11  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_DATA_PARITY_ERR                      = 12  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE1                               = 13  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_FSM_ERR                              = 14  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE2                               = 15  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBDR0_DATA                                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBDR0_DATA_LEN                              = 64  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBDR1_DATA                                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBDR1_DATA_LEN                              = 64  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBDR2_DATA                                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBDR2_DATA_LEN                              = 64  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBDR3_DATA                                  = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBDR3_DATA_LEN                              = 64  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_ERROR_ADDRESS                         = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_ERROR_ADDRESS_LEN                     = 32  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_RESERVED_32_34                        = 32  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_RESERVED_32_34_LEN                    = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_DIRECT_BRIDGE_SOURCE                  = 35  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_0_SOURCE              = 36  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_1_SOURCE              = 37  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_2_SOURCE              = 38  ;
static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_3_SOURCE              = 39  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBESR0_ERROR_ADDR                           = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBESR0_ERROR_ADDR_LEN                       = 32  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBESR1_ERROR_ADDR                           = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBESR1_ERROR_ADDR_LEN                       = 32  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBESR2_ERROR_ADDR                           = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBESR2_ERROR_ADDR_LEN                       = 32  ;

static const uint8_t P9N2_PU_OCB_PIB_OCBESR3_ERROR_ADDR                           = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCBESR3_ERROR_ADDR_LEN                       = 32  ;

static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_ABUSPAREN                      = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_BEPAREN                        = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_WRDBUSPAREN                    = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_RDDBUSPAR                      = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_SPARE                              = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_SACK                           = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_ABUSPAR                        = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_BEPAR                          = 7   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_BE                             = 8   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_WRDBUSPAR                      = 9   ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_RDDBUSPAREN                    = 10  ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_SPARE                              = 11  ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SPARE                                  = 12  ;
static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SPARE_LEN                              = 4   ;

static const uint8_t P9N2_PU_OCB_PIB_OCR_CORE_RESET                               = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_CHIP_RESET                               = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_SYSTEM_RESET                             = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_OCI_ARB_RESET                            = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_TRACE_DISABLE                            = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_TRACE_EVENT                              = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_DBG_UNCONDITIONAL_EVENT                  = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_EXT_INTERRUPT                            = 7   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_CRITICAL_INTERRUPT                       = 8   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_SLAVE_RESET_TO_405_ENABLE                = 9   ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_OCC_DBG_HALT                             = 10  ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_SPARE                                    = 11  ;
static const uint8_t P9N2_PU_OCB_PIB_OCR_SPARE_LEN                                = 5   ;

static const uint8_t P9N2_PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR                        = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR_LEN                    = 32  ;

static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_TIMEOUT_ERROR                    = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_RW_STATUS                        = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_FLCK                             = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_OEAR_LOCK                        = 3   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_TIMEOUT_ERROR                    = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_RW_STATUS                        = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_FLCK                             = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_OEAR_LOCK                        = 7   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_TIMEOUT_ERROR                    = 8   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_RW_STATUS                        = 9   ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_FLCK                             = 10  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_OEAR_LOCK                        = 11  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_TIMEOUT_ERROR                    = 12  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_RW_STATUS                        = 13  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_FLCK                             = 14  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_OEAR_LOCK                        = 15  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_TIMEOUT_ERROR                    = 16  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_RW_STATUS                        = 17  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_FLCK                             = 18  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_OEAR_LOCK                        = 19  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_TIMEOUT_ERROR                    = 20  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_RW_STATUS                        = 21  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_FLCK                             = 22  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_OEAR_LOCK                        = 23  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_TIMEOUT_ERROR                    = 24  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_RW_STATUS                        = 25  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_FLCK                             = 26  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_OEAR_LOCK                        = 27  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_TIMEOUT_ERROR                    = 28  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_RW_STATUS                        = 29  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_FLCK                             = 30  ;
static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_OEAR_LOCK                        = 31  ;

static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_DCU                      = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_ICU                      = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_CE_UE                    = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_SINGL_CONT               = 3   ;

static const uint8_t P9N2_PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR                = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR_LEN            = 32  ;

static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_ICU_TIMEOUT_ERROR                    = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_ICU_RNW                              = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_2_3                         = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_2_3_LEN                     = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_DCU_TIMEOUT_ERROR                    = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_DCU_RNW                              = 5   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_6_7                         = 6   ;
static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_6_7_LEN                     = 2   ;

static const uint8_t P9N2_PU_OCB_PIB_OTDCR_TRACE_BUS_EN                           = 0   ;
static const uint8_t P9N2_PU_OCB_PIB_OTDCR_TRACE_MUX_SEL                          = 1   ;
static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL                      = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL_LEN                  = 2   ;
static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL                      = 4   ;
static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL_LEN                  = 4   ;

static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP                                     = 0   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_LEN                                 = 4   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP                                     = 4   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_LEN                                 = 4   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP                                     = 8   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_LEN                                 = 4   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_WAIT                                = 12  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_WAIT_LEN                            = 8   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_WAIT                                = 20  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_WAIT_LEN                            = 12  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_WAIT                                = 32  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_WAIT_LEN                            = 8   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_FORCE_SG                            = 40  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_FORCE_SG                            = 41  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_FORCE_SG                            = 42  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD                       = 43  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SOURCE_SELECT                            = 44  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SOURCE_SELECT_LEN                        = 2   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_UNUSED46                                 = 46  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SCAN_RATIO                               = 47  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_SCAN_RATIO_LEN                           = 5   ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_WAIT_CYCLES                              = 52  ;
static const uint8_t P9N2_PEC_OPCG_ALIGN_WAIT_CYCLES_LEN                          = 12  ;

static const uint8_t P9N2_PEC_OPCG_CAPT1_COUNT                                    = 0   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_COUNT_LEN                                = 4   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_01                                   = 4   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_01_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_02                                   = 9   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_02_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_03                                   = 14  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_03_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_04                                   = 19  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_04_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_05                                   = 24  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_05_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_06                                   = 29  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_06_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_07                                   = 34  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_07_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_08                                   = 39  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_08_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_09                                   = 44  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_09_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_10                                   = 49  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_10_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_11                                   = 54  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_11_LEN                               = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_12                                   = 59  ;
static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_12_LEN                               = 5   ;

static const uint8_t P9N2_PEC_OPCG_CAPT2_UNUSED                                   = 0   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_UNUSED_LEN                               = 4   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_13_01EVEN                            = 4   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_13_01EVEN_LEN                        = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_14_01ODD                             = 9   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_14_01ODD_LEN                         = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_15_02EVEN                            = 14  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_15_02EVEN_LEN                        = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_16_02ODD                             = 19  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_16_02ODD_LEN                         = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_17_03EVEN                            = 24  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_17_03EVEN_LEN                        = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_18_03ODD                             = 29  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_18_03ODD_LEN                         = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_19_04EVEN                            = 34  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_19_04EVEN_LEN                        = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_20_04ODD                             = 39  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_20_04ODD_LEN                         = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_21_05EVEN                            = 44  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_21_05EVEN_LEN                        = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_22_05ODD                             = 49  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_22_05ODD_LEN                         = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_23_06EVEN                            = 54  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_23_06EVEN_LEN                        = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_24_06ODD                             = 59  ;
static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_24_06ODD_LEN                         = 5   ;

static const uint8_t P9N2_PEC_OPCG_CAPT3_UNUSED                                   = 0   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_UNUSED_LEN                               = 4   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07EVEN                               = 4   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07EVEN_LEN                           = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07ODD                                = 9   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07ODD_LEN                            = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08EVEN                               = 14  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08EVEN_LEN                           = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08ODD                                = 19  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08ODD_LEN                            = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09EVEN                               = 24  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09EVEN_LEN                           = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09ODD                                = 29  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09ODD_LEN                            = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10EVEN                               = 34  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10EVEN_LEN                           = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10ODD                                = 39  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10ODD_LEN                            = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11EVEN                               = 44  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11EVEN_LEN                           = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11ODD                                = 49  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11ODD_LEN                            = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12EVEN                               = 54  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12EVEN_LEN                           = 5   ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12ODD                                = 59  ;
static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12ODD_LEN                            = 5   ;

static const uint8_t P9N2_PEC_OPCG_REG0_RUNN_MODE                                 = 0   ;
static const uint8_t P9N2_PEC_OPCG_REG0_GO                                        = 1   ;
static const uint8_t P9N2_PEC_OPCG_REG0_RUN_SCAN0                                 = 2   ;
static const uint8_t P9N2_PEC_OPCG_REG0_SCAN0_MODE                                = 3   ;
static const uint8_t P9N2_PEC_OPCG_REG0_IN_SLAVE_MODE                             = 4   ;
static const uint8_t P9N2_PEC_OPCG_REG0_IN_MASTER_MODE                            = 5   ;
static const uint8_t P9N2_PEC_OPCG_REG0_KEEP_MS_MODE                              = 6   ;
static const uint8_t P9N2_PEC_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL                 = 7   ;
static const uint8_t P9N2_PEC_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL                 = 8   ;
static const uint8_t P9N2_PEC_OPCG_REG0_RUN_CHIPLET_SCAN0                         = 9   ;
static const uint8_t P9N2_PEC_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL                  = 10  ;
static const uint8_t P9N2_PEC_OPCG_REG0_RUN_ON_UPDATE_DR                          = 11  ;
static const uint8_t P9N2_PEC_OPCG_REG0_RUN_ON_CAPTURE_DR                         = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG0_STOP_RUNN_ON_XSTOP                        = 13  ;
static const uint8_t P9N2_PEC_OPCG_REG0_STARTS_BIST                               = 14  ;
static const uint8_t P9N2_PEC_OPCG_REG0_UNUSED1520                                = 15  ;
static const uint8_t P9N2_PEC_OPCG_REG0_UNUSED1520_LEN                            = 6   ;
static const uint8_t P9N2_PEC_OPCG_REG0_LOOP_COUNT                                = 21  ;
static const uint8_t P9N2_PEC_OPCG_REG0_LOOP_COUNT_LEN                            = 43  ;

static const uint8_t P9N2_PEC_OPCG_REG1_SCAN_COUNT                                = 0   ;
static const uint8_t P9N2_PEC_OPCG_REG1_SCAN_COUNT_LEN                            = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG1_MISR_A_VAL                                = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG1_MISR_A_VAL_LEN                            = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG1_MISR_B_VAL                                = 24  ;
static const uint8_t P9N2_PEC_OPCG_REG1_MISR_B_VAL_LEN                            = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG1_MISR_INIT_WAIT                            = 36  ;
static const uint8_t P9N2_PEC_OPCG_REG1_MISR_INIT_WAIT_LEN                        = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK                    = 48  ;
static const uint8_t P9N2_PEC_OPCG_REG1_SCAN_CLK_USE_EVEN                         = 49  ;
static const uint8_t P9N2_PEC_OPCG_REG1_UNUSED2                                   = 50  ;
static const uint8_t P9N2_PEC_OPCG_REG1_UNUSED2_LEN                               = 2   ;
static const uint8_t P9N2_PEC_OPCG_REG1_RTIM_THOLD_FORCE                          = 52  ;
static const uint8_t P9N2_PEC_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL               = 53  ;
static const uint8_t P9N2_PEC_OPCG_REG1_SG_HIGH_DURING_FILL                       = 54  ;
static const uint8_t P9N2_PEC_OPCG_REG1_LBIST_SKITTER_CTL                         = 55  ;
static const uint8_t P9N2_PEC_OPCG_REG1_LBIST_SKITTER_CTL_LEN                     = 2   ;
static const uint8_t P9N2_PEC_OPCG_REG1_MISR_MODE                                 = 57  ;
static const uint8_t P9N2_PEC_OPCG_REG1_INFINITE_MODE                             = 58  ;
static const uint8_t P9N2_PEC_OPCG_REG1_NSL_FILL_COUNT                            = 59  ;
static const uint8_t P9N2_PEC_OPCG_REG1_NSL_FILL_COUNT_LEN                        = 5   ;

static const uint8_t P9N2_PEC_OPCG_REG2_GO2                                       = 0   ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_WEIGHTING                            = 1   ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_WEIGHTING_LEN                        = 3   ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_VALUE                                = 4   ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_VALUE_LEN                            = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_A_VAL                                = 16  ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_A_VAL_LEN                            = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_B_VAL                                = 28  ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_B_VAL_LEN                            = 12  ;
static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_MODE                                 = 40  ;
static const uint8_t P9N2_PEC_OPCG_REG2_UNUSED41_63                               = 41  ;
static const uint8_t P9N2_PEC_OPCG_REG2_UNUSED41_63_LEN                           = 23  ;

static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2                   = 0   ;
static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2_LEN               = 3   ;
static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK0TO1                    = 3   ;
static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK0TO1_LEN                = 2   ;
static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK4TO5                    = 5   ;
static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK4TO5_LEN                = 2   ;

static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_VC0                      = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_VC1                      = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_VC2                      = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_RSVD3                    = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_DCP0                     = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_DCP1                     = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_RSVD6                    = 6   ;
static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_RSVD7                    = 7   ;

static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_VC0                      = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_VC1                      = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_VC2                      = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_RSVD3                    = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_DCP0                     = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_DCP1                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_RSVD6                    = 6   ;
static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_RSVD7                    = 7   ;

static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_VC0                            = 0   ;
static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_VC1                            = 1   ;
static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_VC2                            = 2   ;
static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_RSVD3                          = 3   ;
static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_DCP0                           = 4   ;
static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_DCP1                           = 5   ;
static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_RSVD6                          = 6   ;
static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_RSVD7                          = 7   ;

static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_VC0                            = 0   ;
static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_VC1                            = 1   ;
static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_VC2                            = 2   ;
static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_RSVD3                          = 3   ;
static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_DCP0                           = 4   ;
static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_DCP1                           = 5   ;
static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_RSVD6                          = 6   ;
static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_RSVD7                          = 7   ;

static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MEMSELMATCH                     = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MEMSELMATCH_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_GRANULE                         = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_SIZE                            = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_SIZE_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MODE                            = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MODE_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_RESERVED                        = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MASK                            = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MASK_LEN                        = 7   ;

static const uint8_t P9N2_NV_PA0_CONFIG_MEMSELMATCH                               = 0   ;
static const uint8_t P9N2_NV_PA0_CONFIG_MEMSELMATCH_LEN                           = 3   ;
static const uint8_t P9N2_NV_PA0_CONFIG_GRANULE                                   = 3   ;
static const uint8_t P9N2_NV_PA0_CONFIG_SIZE                                      = 4   ;
static const uint8_t P9N2_NV_PA0_CONFIG_SIZE_LEN                                  = 4   ;
static const uint8_t P9N2_NV_PA0_CONFIG_MODE                                      = 8   ;
static const uint8_t P9N2_NV_PA0_CONFIG_MODE_LEN                                  = 4   ;
static const uint8_t P9N2_NV_PA0_CONFIG_RESERVED                                  = 12  ;
static const uint8_t P9N2_NV_PA0_CONFIG_MASK                                      = 13  ;
static const uint8_t P9N2_NV_PA0_CONFIG_MASK_LEN                                  = 7   ;

static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MEMSELMATCH                     = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MEMSELMATCH_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_GRANULE                         = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_SIZE                            = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_SIZE_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MODE                            = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MODE_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_RESERVED                        = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MASK                            = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MASK_LEN                        = 7   ;

static const uint8_t P9N2_NV_PA1_CONFIG_MEMSELMATCH                               = 0   ;
static const uint8_t P9N2_NV_PA1_CONFIG_MEMSELMATCH_LEN                           = 3   ;
static const uint8_t P9N2_NV_PA1_CONFIG_GRANULE                                   = 3   ;
static const uint8_t P9N2_NV_PA1_CONFIG_SIZE                                      = 4   ;
static const uint8_t P9N2_NV_PA1_CONFIG_SIZE_LEN                                  = 4   ;
static const uint8_t P9N2_NV_PA1_CONFIG_MODE                                      = 8   ;
static const uint8_t P9N2_NV_PA1_CONFIG_MODE_LEN                                  = 4   ;
static const uint8_t P9N2_NV_PA1_CONFIG_RESERVED                                  = 12  ;
static const uint8_t P9N2_NV_PA1_CONFIG_MASK                                      = 13  ;
static const uint8_t P9N2_NV_PA1_CONFIG_MASK_LEN                                  = 7   ;

static const uint8_t P9N2_PU_PBABAR0_CMD_SCOPE                                    = 0   ;
static const uint8_t P9N2_PU_PBABAR0_CMD_SCOPE_LEN                                = 3   ;
static const uint8_t P9N2_PU_PBABAR0_RESERVED_3                                   = 3   ;
static const uint8_t P9N2_PU_PBABAR0_ADDR                                         = 8   ;
static const uint8_t P9N2_PU_PBABAR0_ADDR_LEN                                     = 36  ;
static const uint8_t P9N2_PU_PBABAR0_VTARGET                                      = 48  ;
static const uint8_t P9N2_PU_PBABAR0_VTARGET_LEN                                  = 16  ;

static const uint8_t P9N2_PU_PBABAR1_CMD_SCOPE                                    = 0   ;
static const uint8_t P9N2_PU_PBABAR1_CMD_SCOPE_LEN                                = 3   ;
static const uint8_t P9N2_PU_PBABAR1_RESERVED_3                                   = 3   ;
static const uint8_t P9N2_PU_PBABAR1_ADDR                                         = 8   ;
static const uint8_t P9N2_PU_PBABAR1_ADDR_LEN                                     = 36  ;
static const uint8_t P9N2_PU_PBABAR1_VTARGET                                      = 48  ;
static const uint8_t P9N2_PU_PBABAR1_VTARGET_LEN                                  = 16  ;

static const uint8_t P9N2_PU_PBABAR2_CMD_SCOPE                                    = 0   ;
static const uint8_t P9N2_PU_PBABAR2_CMD_SCOPE_LEN                                = 3   ;
static const uint8_t P9N2_PU_PBABAR2_RESERVED_3                                   = 3   ;
static const uint8_t P9N2_PU_PBABAR2_ADDR                                         = 8   ;
static const uint8_t P9N2_PU_PBABAR2_ADDR_LEN                                     = 36  ;
static const uint8_t P9N2_PU_PBABAR2_VTARGET                                      = 48  ;
static const uint8_t P9N2_PU_PBABAR2_VTARGET_LEN                                  = 16  ;

static const uint8_t P9N2_PU_PBABAR3_CMD_SCOPE                                    = 0   ;
static const uint8_t P9N2_PU_PBABAR3_CMD_SCOPE_LEN                                = 3   ;
static const uint8_t P9N2_PU_PBABAR3_RESERVED_3                                   = 3   ;
static const uint8_t P9N2_PU_PBABAR3_ADDR                                         = 8   ;
static const uint8_t P9N2_PU_PBABAR3_ADDR_LEN                                     = 36  ;
static const uint8_t P9N2_PU_PBABAR3_VTARGET                                      = 48  ;
static const uint8_t P9N2_PU_PBABAR3_VTARGET_LEN                                  = 16  ;

static const uint8_t P9N2_PU_PBABARMSK0_MSK                                       = 23  ;
static const uint8_t P9N2_PU_PBABARMSK0_MSK_LEN                                   = 21  ;

static const uint8_t P9N2_PU_PBABARMSK1_MSK                                       = 23  ;
static const uint8_t P9N2_PU_PBABARMSK1_MSK_LEN                                   = 21  ;

static const uint8_t P9N2_PU_PBABARMSK2_MSK                                       = 23  ;
static const uint8_t P9N2_PU_PBABARMSK2_MSK_LEN                                   = 21  ;

static const uint8_t P9N2_PU_PBABARMSK3_MSK                                       = 23  ;
static const uint8_t P9N2_PU_PBABARMSK3_MSK_LEN                                   = 21  ;

static const uint8_t P9N2_PU_PBACFG_PBREQ_SLVFW_MAX_PRIORITY                      = 0   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_ON_HANG                            = 1   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_BCE_MAX_PRIORITY                        = 2   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_ON_HANG_PBAX                       = 3   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_DATA_HANG_DIV                           = 4   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_DATA_HANG_DIV_LEN                       = 5   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_OPER_HANG_DIV                           = 9   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_OPER_HANG_DIV_LEN                       = 5   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_DROP_PRIORITY_MASK                      = 14  ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_DROP_PRIORITY_MASK_LEN                  = 6   ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_HANG_DIV                           = 20  ;
static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_HANG_DIV_LEN                       = 4   ;
static const uint8_t P9N2_PU_PBACFG_CHSW_HANG_ON_ADRERROR                         = 24  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIABUSPAR_CHECK                     = 25  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIBEPAR_CHECK                       = 26  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_HANG_ON_DERROR                           = 27  ;
static const uint8_t P9N2_PU_PBACFG_RESERVED_28                                   = 28  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_WRITE_MATCH_REARB                    = 29  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIDATAPAR_GEN                       = 30  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIDATAPAR_CHECK                     = 31  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OPER_HANG                            = 32  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_DATA_HANG                            = 33  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_ECC_CHECK                            = 34  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_RETRY_BACKOFF                        = 35  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_EXIT_ON_INVALID_CRESP                    = 36  ;
static const uint8_t P9N2_PU_PBACFG_RESERVED_37                                   = 37  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_GROUP_SCOPE                          = 38  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_RTAG_PARITY_CHK                      = 39  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_PB_PARITY_CHK                        = 40  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_SKIP_GROUP_SCOPE                         = 41  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_USE_PR_DMA_INJ                           = 42  ;
static const uint8_t P9N2_PU_PBACFG_CHSW_USE_CL_DMA_INJ                           = 43  ;
static const uint8_t P9N2_PU_PBACFG_RESERVED_44_47                                = 44  ;
static const uint8_t P9N2_PU_PBACFG_RESERVED_44_47_LEN                            = 4   ;

static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDDATATO_FW                       = 0   ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDDATATO_FW_LEN                   = 6   ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDADRERR_FW                       = 6   ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDADRERR_FW_LEN                   = 6   ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_WRADRERR_FW                       = 12  ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_WRADRERR_FW_LEN                   = 4   ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD                     = 16  ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD_LEN                 = 6   ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR                     = 22  ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR_LEN                 = 2   ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPCRESP                        = 24  ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPCRESP_LEN                    = 11  ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPDATA                         = 35  ;
static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPDATA_LEN                     = 6   ;

static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_BADCRESP                          = 0   ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_BADCRESP_LEN                      = 12  ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_OPERTO                            = 12  ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_OPERTO_LEN                        = 12  ;
static const uint8_t P9N2_PU_PBAERRRPT1_RESERVED_24_29                            = 24  ;
static const uint8_t P9N2_PU_PBAERRRPT1_RESERVED_24_29_LEN                        = 6   ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR                       = 30  ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR_LEN                   = 2   ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR                       = 32  ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR_LEN                   = 2   ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR                     = 34  ;
static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR_LEN                 = 2   ;

static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR                     = 0   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR_LEN                 = 8   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR                    = 8   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR_LEN                = 4   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR                    = 12  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR_LEN                = 4   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BAR_PARITY_ERR                       = 16  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SCOMTB_ERR                           = 17  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SPARE                                = 18  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SPARE_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_PBDOUT_PARITY_ERR                    = 20  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_PB_PARITY_ERR                        = 21  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_PB_PARITY_ERR_LEN                    = 3   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXFLOW_ERR                           = 24  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXFLOW_ERR_LEN                       = 5   ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXPUSH_WRERR                         = 29  ;
static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXPUSH_WRERR_LEN                     = 2   ;

static const uint8_t P9N2_PU_PBAFIR_OCI_APAR_ERR                                  = 0   ;
static const uint8_t P9N2_PU_PBAFIR_PB_RDADRERR_FW                                = 1   ;
static const uint8_t P9N2_PU_PBAFIR_PB_RDDATATO_FW                                = 2   ;
static const uint8_t P9N2_PU_PBAFIR_PB_SUE_FW                                     = 3   ;
static const uint8_t P9N2_PU_PBAFIR_PB_UE_FW                                      = 4   ;
static const uint8_t P9N2_PU_PBAFIR_PB_CE_FW                                      = 5   ;
static const uint8_t P9N2_PU_PBAFIR_OCI_SLAVE_INIT                                = 6   ;
static const uint8_t P9N2_PU_PBAFIR_OCI_WRPAR_ERR                                 = 7   ;
static const uint8_t P9N2_PU_PBAFIR_RESERVED_8                                    = 8   ;
static const uint8_t P9N2_PU_PBAFIR_PB_UNEXPCRESP                                 = 9   ;
static const uint8_t P9N2_PU_PBAFIR_PB_UNEXPDATA                                  = 10  ;
static const uint8_t P9N2_PU_PBAFIR_PB_PARITY_ERR                                 = 11  ;
static const uint8_t P9N2_PU_PBAFIR_PB_WRADRERR_FW                                = 12  ;
static const uint8_t P9N2_PU_PBAFIR_PB_BADCRESP                                   = 13  ;
static const uint8_t P9N2_PU_PBAFIR_PB_ACKDEAD_FW_RD                              = 14  ;
static const uint8_t P9N2_PU_PBAFIR_PB_OPERTO                                     = 15  ;
static const uint8_t P9N2_PU_PBAFIR_BCUE_SETUP_ERR                                = 16  ;
static const uint8_t P9N2_PU_PBAFIR_BCUE_PB_ACK_DEAD                              = 17  ;
static const uint8_t P9N2_PU_PBAFIR_BCUE_PB_ADRERR                                = 18  ;
static const uint8_t P9N2_PU_PBAFIR_BCUE_OCI_DATERR                               = 19  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_SETUP_ERR                                = 20  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_PB_ACK_DEAD                              = 21  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_PB_ADRERR                                = 22  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_RDDATATO_ERR                             = 23  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_SUE_ERR                                  = 24  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_UE_ERR                                   = 25  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_CE                                       = 26  ;
static const uint8_t P9N2_PU_PBAFIR_BCDE_OCI_DATERR                               = 27  ;
static const uint8_t P9N2_PU_PBAFIR_INTERNAL_ERR                                  = 28  ;
static const uint8_t P9N2_PU_PBAFIR_ILLEGAL_CACHE_OP                              = 29  ;
static const uint8_t P9N2_PU_PBAFIR_OCI_BAD_REG_ADDR                              = 30  ;
static const uint8_t P9N2_PU_PBAFIR_AXPUSH_WRERR                                  = 31  ;
static const uint8_t P9N2_PU_PBAFIR_AXRCV_DLO_ERR                                 = 32  ;
static const uint8_t P9N2_PU_PBAFIR_AXRCV_DLO_TO                                  = 33  ;
static const uint8_t P9N2_PU_PBAFIR_AXRCV_RSVDATA_TO                              = 34  ;
static const uint8_t P9N2_PU_PBAFIR_AXFLOW_ERR                                    = 35  ;
static const uint8_t P9N2_PU_PBAFIR_AXSND_DHI_RTYTO                               = 36  ;
static const uint8_t P9N2_PU_PBAFIR_AXSND_DLO_RTYTO                               = 37  ;
static const uint8_t P9N2_PU_PBAFIR_AXSND_RSVTO                                   = 38  ;
static const uint8_t P9N2_PU_PBAFIR_AXSND_RSVERR                                  = 39  ;
static const uint8_t P9N2_PU_PBAFIR_PB_ACKDEAD_FW_WR                              = 40  ;
static const uint8_t P9N2_PU_PBAFIR_RESERVED_41                                   = 41  ;
static const uint8_t P9N2_PU_PBAFIR_RESERVED_42                                   = 42  ;
static const uint8_t P9N2_PU_PBAFIR_RESERVED_43                                   = 43  ;
static const uint8_t P9N2_PU_PBAFIR_FIR_PARITY_ERR2                               = 44  ;
static const uint8_t P9N2_PU_PBAFIR_FIR_PARITY_ERR                                = 45  ;

static const uint8_t P9N2_PU_PBAFIRACT0_FIR_ACTION0                               = 0   ;
static const uint8_t P9N2_PU_PBAFIRACT0_FIR_ACTION0_LEN                           = 46  ;

static const uint8_t P9N2_PU_PBAFIRACT1_FIR_ACTION1                               = 0   ;
static const uint8_t P9N2_PU_PBAFIRACT1_FIR_ACTION1_LEN                           = 46  ;

static const uint8_t P9N2_PU_PBAFIRMASK_OCI_APAR_ERR_MASK                         = 0   ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_RDADRERR_FW_MASK                       = 1   ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_RDDATATO_FW_MASK                       = 2   ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_SUE_FW_MASK                            = 3   ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_UE_FW_MASK                             = 4   ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_CE_FW_MASK                             = 5   ;
static const uint8_t P9N2_PU_PBAFIRMASK_OCI_SLAVE_INIT_MASK                       = 6   ;
static const uint8_t P9N2_PU_PBAFIRMASK_OCI_WRPAR_ERR_MASK                        = 7   ;
static const uint8_t P9N2_PU_PBAFIRMASK_RESERVED_8                                = 8   ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_UNEXPCRESP_MASK                        = 9   ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_UNEXPDATA_MASK                         = 10  ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_PARITY_ERR_MASK                        = 11  ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_WRADRERR_FW_MASK                       = 12  ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_BADCRESP_MASK                          = 13  ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_ACKDEAD_FW_RD_MASK                     = 14  ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_OPERTO_MASK                            = 15  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_SETUP_ERR_MASK                       = 16  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_PB_ACK_DEAD_MASK                     = 17  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_PB_ADRERR_MASK                       = 18  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_OCI_DATERR_MASK                      = 19  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_SETUP_ERR_MASK                       = 20  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_PB_ACK_DEAD_MASK                     = 21  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_PB_ADRERR_MASK                       = 22  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_RDDATATO_ERR_MASK                    = 23  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_SUE_ERR_MASK                         = 24  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_UE_ERR_MASK                          = 25  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_CE_MASK                              = 26  ;
static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_OCI_DATERR_MASK                      = 27  ;
static const uint8_t P9N2_PU_PBAFIRMASK_INTERNAL_ERR_MASK                         = 28  ;
static const uint8_t P9N2_PU_PBAFIRMASK_ILLEGAL_CACHE_OP_MASK                     = 29  ;
static const uint8_t P9N2_PU_PBAFIRMASK_OCI_BAD_REG_ADDR_MASK                     = 30  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXPUSH_WRERR_MASK                         = 31  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXRCV_DLO_ERR_MASK                        = 32  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXRCV_DLO_TO_MASK                         = 33  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXRCV_RSVDATA_TO_MASK                     = 34  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXFLOW_ERR_MASK                           = 35  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_DHI_RTYTO_MASK                      = 36  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_DLO_RTYTO_MASK                      = 37  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_RSVTO_MASK                          = 38  ;
static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_RSVERR_MASK                         = 39  ;
static const uint8_t P9N2_PU_PBAFIRMASK_PB_ACKDEAD_FW_WR_MASK                     = 40  ;
static const uint8_t P9N2_PU_PBAFIRMASK_RESERVED_41_43                            = 41  ;
static const uint8_t P9N2_PU_PBAFIRMASK_RESERVED_41_43_LEN                        = 3   ;
static const uint8_t P9N2_PU_PBAFIRMASK_FIR_PARITY_ERR2_MASK                      = 44  ;
static const uint8_t P9N2_PU_PBAFIRMASK_FIR_PARITY_ERR_MASK                       = 45  ;

static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED0                            = 0   ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED0_LEN                        = 16  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE               = 16  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN           = 3   ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED1                            = 19  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM                       = 20  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN                   = 4   ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM                       = 24  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM_LEN                   = 4   ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE              = 28  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE_LEN          = 2   ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN                 = 30  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_SELECT_ETU_TRACE                  = 31  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL                 = 32  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL_LEN             = 4   ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT                 = 36  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN             = 3   ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED2                            = 39  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT                  = 40  ;
static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN              = 3   ;

static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCA                     = 0   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCA_LEN                 = 3   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCR                     = 10  ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCR_LEN                 = 6   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCA                     = 16  ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCA_LEN                 = 3   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCR                     = 26  ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCR_LEN                 = 6   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCA                     = 32  ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCA_LEN                 = 3   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCR                     = 41  ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCR_LEN                 = 7   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCA                     = 48  ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCA_LEN                 = 3   ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCR                     = 58  ;
static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCR_LEN                 = 6   ;

static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH0_DCR                     = 9   ;
static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH0_DCR_LEN                 = 7   ;
static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH1_DCR                     = 26  ;
static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH1_DCR_LEN                 = 6   ;
static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH3_DCR                     = 58  ;
static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH3_DCR_LEN                 = 6   ;

static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE                    = 0   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PHBRESET_PE                      = 1   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE                   = 2   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE                    = 3   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE                    = 4   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN                    = 5   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR                   = 6   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR                 = 7   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE                     = 8   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE                     = 9   ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE           = 10  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE           = 11  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE                 = 12  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE                 = 13  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR                = 14  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_ASYNC_ERROR                      = 15  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR               = 16  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR                 = 17  ;
static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE                 = 18  ;

static const uint8_t P9N2_PU_PBAMODE_RESERVED_0_3                                 = 0   ;
static const uint8_t P9N2_PU_PBAMODE_RESERVED_0_3_LEN                             = 4   ;
static const uint8_t P9N2_PU_PBAMODE_DIS_REARB                                    = 4   ;
static const uint8_t P9N2_PU_PBAMODE_DIS_MSTID_MATCH_PREF_INV                     = 5   ;
static const uint8_t P9N2_PU_PBAMODE_DIS_SLAVE_RDPIPE                             = 6   ;
static const uint8_t P9N2_PU_PBAMODE_DIS_SLAVE_WRPIPE                             = 7   ;
static const uint8_t P9N2_PU_PBAMODE_EN_MARKER_ACK                                = 8   ;
static const uint8_t P9N2_PU_PBAMODE_RESERVED_9                                   = 9   ;
static const uint8_t P9N2_PU_PBAMODE_EN_SECOND_WRBUF                              = 10  ;
static const uint8_t P9N2_PU_PBAMODE_DIS_REREQUEST_TO                             = 11  ;
static const uint8_t P9N2_PU_PBAMODE_INJECT_TYPE                                  = 12  ;
static const uint8_t P9N2_PU_PBAMODE_INJECT_TYPE_LEN                              = 2   ;
static const uint8_t P9N2_PU_PBAMODE_INJECT_MODE                                  = 14  ;
static const uint8_t P9N2_PU_PBAMODE_INJECT_MODE_LEN                              = 2   ;
static const uint8_t P9N2_PU_PBAMODE_PBA_REGION                                   = 16  ;
static const uint8_t P9N2_PU_PBAMODE_PBA_REGION_LEN                               = 2   ;
static const uint8_t P9N2_PU_PBAMODE_OCI_MARKER_SPACE                             = 18  ;
static const uint8_t P9N2_PU_PBAMODE_OCI_MARKER_SPACE_LEN                         = 3   ;
static const uint8_t P9N2_PU_PBAMODE_BCDE_OCITRANS                                = 21  ;
static const uint8_t P9N2_PU_PBAMODE_BCDE_OCITRANS_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBAMODE_BCUE_OCITRANS                                = 23  ;
static const uint8_t P9N2_PU_PBAMODE_BCUE_OCITRANS_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBAMODE_DIS_MASTER_RD_PIPE                           = 25  ;
static const uint8_t P9N2_PU_PBAMODE_DIS_MASTER_WR_PIPE                           = 26  ;
static const uint8_t P9N2_PU_PBAMODE_EN_SLV_FAIRNESS                              = 27  ;
static const uint8_t P9N2_PU_PBAMODE_EN_EVENT_COUNT                               = 28  ;
static const uint8_t P9N2_PU_PBAMODE_PB_NOCI_EVENT_SEL                            = 29  ;
static const uint8_t P9N2_PU_PBAMODE_SLV_EVENT_MUX                                = 30  ;
static const uint8_t P9N2_PU_PBAMODE_SLV_EVENT_MUX_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBAMODE_ENABLE_DEBUG_BUS                             = 32  ;
static const uint8_t P9N2_PU_PBAMODE_DEBUG_PB_NOT_OCI                             = 33  ;
static const uint8_t P9N2_PU_PBAMODE_DEBUG_OCI_MODE                               = 34  ;
static const uint8_t P9N2_PU_PBAMODE_DEBUG_OCI_MODE_LEN                           = 5   ;
static const uint8_t P9N2_PU_PBAMODE_RESERVED_39                                  = 39  ;
static const uint8_t P9N2_PU_PBAMODE_OCISLV_FAIRNESS_MASK                         = 40  ;
static const uint8_t P9N2_PU_PBAMODE_OCISLV_FAIRNESS_MASK_LEN                     = 5   ;
static const uint8_t P9N2_PU_PBAMODE_OCISLV_REREQ_HANG_DIV                        = 45  ;
static const uint8_t P9N2_PU_PBAMODE_OCISLV_REREQ_HANG_DIV_LEN                    = 5   ;
static const uint8_t P9N2_PU_PBAMODE_DIS_CHGRATE_COUNT                            = 50  ;
static const uint8_t P9N2_PU_PBAMODE_PBREQ_EVENT_MUX                              = 51  ;
static const uint8_t P9N2_PU_PBAMODE_PBREQ_EVENT_MUX_LEN                          = 2   ;
static const uint8_t P9N2_PU_PBAMODE_RESERVED_53_63                               = 53  ;
static const uint8_t P9N2_PU_PBAMODE_RESERVED_53_63_LEN                           = 11  ;

static const uint8_t P9N2_PU_PBAOCCACT_OCC_ACTION_SET                             = 0   ;
static const uint8_t P9N2_PU_PBAOCCACT_OCC_ACTION_SET_LEN                         = 44  ;

static const uint8_t P9N2_PU_PBAPBOCR0_EVENT                                      = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR0_EVENT_LEN                                  = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR0_ACCUM                                      = 44  ;
static const uint8_t P9N2_PU_PBAPBOCR0_ACCUM_LEN                                  = 20  ;

static const uint8_t P9N2_PU_PBAPBOCR1_EVENT                                      = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR1_EVENT_LEN                                  = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR1_ACCUM                                      = 44  ;
static const uint8_t P9N2_PU_PBAPBOCR1_ACCUM_LEN                                  = 20  ;

static const uint8_t P9N2_PU_PBAPBOCR2_EVENT                                      = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR2_EVENT_LEN                                  = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR2_ACCUM                                      = 44  ;
static const uint8_t P9N2_PU_PBAPBOCR2_ACCUM_LEN                                  = 20  ;

static const uint8_t P9N2_PU_PBAPBOCR3_EVENT                                      = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR3_EVENT_LEN                                  = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR3_ACCUM                                      = 44  ;
static const uint8_t P9N2_PU_PBAPBOCR3_ACCUM_LEN                                  = 20  ;

static const uint8_t P9N2_PU_PBAPBOCR4_EVENT                                      = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR4_EVENT_LEN                                  = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR4_ACCUM                                      = 44  ;
static const uint8_t P9N2_PU_PBAPBOCR4_ACCUM_LEN                                  = 20  ;

static const uint8_t P9N2_PU_PBAPBOCR5_EVENT                                      = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR5_EVENT_LEN                                  = 16  ;
static const uint8_t P9N2_PU_PBAPBOCR5_ACCUM                                      = 44  ;
static const uint8_t P9N2_PU_PBAPBOCR5_ACCUM_LEN                                  = 20  ;

static const uint8_t P9N2_PU_PBARBUFVAL0_RD_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBARBUFVAL0_RD_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL0_CUR_RD_ADDR                              = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL0_CUR_RD_ADDR_LEN                          = 23  ;
static const uint8_t P9N2_PU_PBARBUFVAL0_PREFETCH                                 = 28  ;
static const uint8_t P9N2_PU_PBARBUFVAL0_ABORT                                    = 31  ;
static const uint8_t P9N2_PU_PBARBUFVAL0_BUFFER_STATUS                            = 33  ;
static const uint8_t P9N2_PU_PBARBUFVAL0_BUFFER_STATUS_LEN                        = 7   ;
static const uint8_t P9N2_PU_PBARBUFVAL0_MASTERID                                 = 41  ;
static const uint8_t P9N2_PU_PBARBUFVAL0_MASTERID_LEN                             = 3   ;

static const uint8_t P9N2_PU_PBARBUFVAL1_RD_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBARBUFVAL1_RD_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL1_CUR_RD_ADDR                              = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL1_CUR_RD_ADDR_LEN                          = 23  ;
static const uint8_t P9N2_PU_PBARBUFVAL1_PREFETCH                                 = 28  ;
static const uint8_t P9N2_PU_PBARBUFVAL1_ABORT                                    = 31  ;
static const uint8_t P9N2_PU_PBARBUFVAL1_BUFFER_STATUS                            = 33  ;
static const uint8_t P9N2_PU_PBARBUFVAL1_BUFFER_STATUS_LEN                        = 7   ;
static const uint8_t P9N2_PU_PBARBUFVAL1_MASTERID                                 = 41  ;
static const uint8_t P9N2_PU_PBARBUFVAL1_MASTERID_LEN                             = 3   ;

static const uint8_t P9N2_PU_PBARBUFVAL2_RD_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBARBUFVAL2_RD_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL2_CUR_RD_ADDR                              = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL2_CUR_RD_ADDR_LEN                          = 23  ;
static const uint8_t P9N2_PU_PBARBUFVAL2_PREFETCH                                 = 28  ;
static const uint8_t P9N2_PU_PBARBUFVAL2_ABORT                                    = 31  ;
static const uint8_t P9N2_PU_PBARBUFVAL2_BUFFER_STATUS                            = 33  ;
static const uint8_t P9N2_PU_PBARBUFVAL2_BUFFER_STATUS_LEN                        = 7   ;
static const uint8_t P9N2_PU_PBARBUFVAL2_MASTERID                                 = 41  ;
static const uint8_t P9N2_PU_PBARBUFVAL2_MASTERID_LEN                             = 3   ;

static const uint8_t P9N2_PU_PBARBUFVAL3_RD_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBARBUFVAL3_RD_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL3_CUR_RD_ADDR                              = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL3_CUR_RD_ADDR_LEN                          = 23  ;
static const uint8_t P9N2_PU_PBARBUFVAL3_PREFETCH                                 = 28  ;
static const uint8_t P9N2_PU_PBARBUFVAL3_ABORT                                    = 31  ;
static const uint8_t P9N2_PU_PBARBUFVAL3_BUFFER_STATUS                            = 33  ;
static const uint8_t P9N2_PU_PBARBUFVAL3_BUFFER_STATUS_LEN                        = 7   ;
static const uint8_t P9N2_PU_PBARBUFVAL3_MASTERID                                 = 41  ;
static const uint8_t P9N2_PU_PBARBUFVAL3_MASTERID_LEN                             = 3   ;

static const uint8_t P9N2_PU_PBARBUFVAL4_RD_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBARBUFVAL4_RD_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL4_CUR_RD_ADDR                              = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL4_CUR_RD_ADDR_LEN                          = 23  ;
static const uint8_t P9N2_PU_PBARBUFVAL4_PREFETCH                                 = 28  ;
static const uint8_t P9N2_PU_PBARBUFVAL4_ABORT                                    = 31  ;
static const uint8_t P9N2_PU_PBARBUFVAL4_BUFFER_STATUS                            = 33  ;
static const uint8_t P9N2_PU_PBARBUFVAL4_BUFFER_STATUS_LEN                        = 7   ;
static const uint8_t P9N2_PU_PBARBUFVAL4_MASTERID                                 = 41  ;
static const uint8_t P9N2_PU_PBARBUFVAL4_MASTERID_LEN                             = 3   ;

static const uint8_t P9N2_PU_PBARBUFVAL5_RD_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBARBUFVAL5_RD_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL5_CUR_RD_ADDR                              = 2   ;
static const uint8_t P9N2_PU_PBARBUFVAL5_CUR_RD_ADDR_LEN                          = 23  ;
static const uint8_t P9N2_PU_PBARBUFVAL5_PREFETCH                                 = 28  ;
static const uint8_t P9N2_PU_PBARBUFVAL5_ABORT                                    = 31  ;
static const uint8_t P9N2_PU_PBARBUFVAL5_BUFFER_STATUS                            = 33  ;
static const uint8_t P9N2_PU_PBARBUFVAL5_BUFFER_STATUS_LEN                        = 7   ;
static const uint8_t P9N2_PU_PBARBUFVAL5_MASTERID                                 = 41  ;
static const uint8_t P9N2_PU_PBARBUFVAL5_MASTERID_LEN                             = 3   ;

static const uint8_t P9N2_PU_PBASLVCTL0_ENABLE                                    = 0   ;
static const uint8_t P9N2_PU_PBASLVCTL0_MID_MATCH_VALUE                           = 1   ;
static const uint8_t P9N2_PU_PBASLVCTL0_MID_MATCH_VALUE_LEN                       = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_4                                = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL0_MID_CARE_MASK                             = 5   ;
static const uint8_t P9N2_PU_PBASLVCTL0_MID_CARE_MASK_LEN                         = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TTYPE                               = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TTYPE_LEN                           = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_11_14                            = 11  ;
static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_11_14_LEN                        = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL0_READ_TTYPE                                = 15  ;
static const uint8_t P9N2_PU_PBASLVCTL0_READ_PREFETCH_CTL                         = 16  ;
static const uint8_t P9N2_PU_PBASLVCTL0_READ_PREFETCH_CTL_LEN                     = 2   ;
static const uint8_t P9N2_PU_PBASLVCTL0_BUF_INVALIDATE_CTL                        = 18  ;
static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_W                               = 19  ;
static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_A                               = 20  ;
static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_B                               = 21  ;
static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_C                               = 22  ;
static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_23                               = 23  ;
static const uint8_t P9N2_PU_PBASLVCTL0_DIS_WRITE_GATHER                          = 24  ;
static const uint8_t P9N2_PU_PBASLVCTL0_WR_GATHER_TIMEOUT                         = 25  ;
static const uint8_t P9N2_PU_PBASLVCTL0_WR_GATHER_TIMEOUT_LEN                     = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TSIZE                               = 28  ;
static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TSIZE_LEN                           = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL0_EXTADDR                                   = 36  ;
static const uint8_t P9N2_PU_PBASLVCTL0_EXTADDR_LEN                               = 14  ;
static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_50                               = 50  ;

static const uint8_t P9N2_PU_PBASLVCTL1_ENABLE                                    = 0   ;
static const uint8_t P9N2_PU_PBASLVCTL1_MID_MATCH_VALUE                           = 1   ;
static const uint8_t P9N2_PU_PBASLVCTL1_MID_MATCH_VALUE_LEN                       = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_4                                = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL1_MID_CARE_MASK                             = 5   ;
static const uint8_t P9N2_PU_PBASLVCTL1_MID_CARE_MASK_LEN                         = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TTYPE                               = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TTYPE_LEN                           = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_11_14                            = 11  ;
static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_11_14_LEN                        = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL1_READ_TTYPE                                = 15  ;
static const uint8_t P9N2_PU_PBASLVCTL1_READ_PREFETCH_CTL                         = 16  ;
static const uint8_t P9N2_PU_PBASLVCTL1_READ_PREFETCH_CTL_LEN                     = 2   ;
static const uint8_t P9N2_PU_PBASLVCTL1_BUF_INVALIDATE_CTL                        = 18  ;
static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_W                               = 19  ;
static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_A                               = 20  ;
static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_B                               = 21  ;
static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_C                               = 22  ;
static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_23                               = 23  ;
static const uint8_t P9N2_PU_PBASLVCTL1_DIS_WRITE_GATHER                          = 24  ;
static const uint8_t P9N2_PU_PBASLVCTL1_WR_GATHER_TIMEOUT                         = 25  ;
static const uint8_t P9N2_PU_PBASLVCTL1_WR_GATHER_TIMEOUT_LEN                     = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TSIZE                               = 28  ;
static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TSIZE_LEN                           = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL1_EXTADDR                                   = 36  ;
static const uint8_t P9N2_PU_PBASLVCTL1_EXTADDR_LEN                               = 14  ;
static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_50                               = 50  ;

static const uint8_t P9N2_PU_PBASLVCTL2_ENABLE                                    = 0   ;
static const uint8_t P9N2_PU_PBASLVCTL2_MID_MATCH_VALUE                           = 1   ;
static const uint8_t P9N2_PU_PBASLVCTL2_MID_MATCH_VALUE_LEN                       = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_4                                = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL2_MID_CARE_MASK                             = 5   ;
static const uint8_t P9N2_PU_PBASLVCTL2_MID_CARE_MASK_LEN                         = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TTYPE                               = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TTYPE_LEN                           = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_11_14                            = 11  ;
static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_11_14_LEN                        = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL2_READ_TTYPE                                = 15  ;
static const uint8_t P9N2_PU_PBASLVCTL2_READ_PREFETCH_CTL                         = 16  ;
static const uint8_t P9N2_PU_PBASLVCTL2_READ_PREFETCH_CTL_LEN                     = 2   ;
static const uint8_t P9N2_PU_PBASLVCTL2_BUF_INVALIDATE_CTL                        = 18  ;
static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_W                               = 19  ;
static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_A                               = 20  ;
static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_B                               = 21  ;
static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_C                               = 22  ;
static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_23                               = 23  ;
static const uint8_t P9N2_PU_PBASLVCTL2_DIS_WRITE_GATHER                          = 24  ;
static const uint8_t P9N2_PU_PBASLVCTL2_WR_GATHER_TIMEOUT                         = 25  ;
static const uint8_t P9N2_PU_PBASLVCTL2_WR_GATHER_TIMEOUT_LEN                     = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TSIZE                               = 28  ;
static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TSIZE_LEN                           = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL2_EXTADDR                                   = 36  ;
static const uint8_t P9N2_PU_PBASLVCTL2_EXTADDR_LEN                               = 14  ;
static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_50                               = 50  ;

static const uint8_t P9N2_PU_PBASLVCTL3_ENABLE                                    = 0   ;
static const uint8_t P9N2_PU_PBASLVCTL3_MID_MATCH_VALUE                           = 1   ;
static const uint8_t P9N2_PU_PBASLVCTL3_MID_MATCH_VALUE_LEN                       = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_4                                = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL3_MID_CARE_MASK                             = 5   ;
static const uint8_t P9N2_PU_PBASLVCTL3_MID_CARE_MASK_LEN                         = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TTYPE                               = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TTYPE_LEN                           = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_11_14                            = 11  ;
static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_11_14_LEN                        = 4   ;
static const uint8_t P9N2_PU_PBASLVCTL3_READ_TTYPE                                = 15  ;
static const uint8_t P9N2_PU_PBASLVCTL3_READ_PREFETCH_CTL                         = 16  ;
static const uint8_t P9N2_PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN                     = 2   ;
static const uint8_t P9N2_PU_PBASLVCTL3_BUF_INVALIDATE_CTL                        = 18  ;
static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_W                               = 19  ;
static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_A                               = 20  ;
static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_B                               = 21  ;
static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_C                               = 22  ;
static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_23                               = 23  ;
static const uint8_t P9N2_PU_PBASLVCTL3_DIS_WRITE_GATHER                          = 24  ;
static const uint8_t P9N2_PU_PBASLVCTL3_WR_GATHER_TIMEOUT                         = 25  ;
static const uint8_t P9N2_PU_PBASLVCTL3_WR_GATHER_TIMEOUT_LEN                     = 3   ;
static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TSIZE                               = 28  ;
static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TSIZE_LEN                           = 8   ;
static const uint8_t P9N2_PU_PBASLVCTL3_EXTADDR                                   = 36  ;
static const uint8_t P9N2_PU_PBASLVCTL3_EXTADDR_LEN                               = 14  ;
static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_50                               = 50  ;

static const uint8_t P9N2_PU_PBASLVRST_SET                                        = 0   ;
static const uint8_t P9N2_PU_PBASLVRST_SET_LEN                                    = 3   ;
static const uint8_t P9N2_PU_PBASLVRST_IN_PROG                                    = 4   ;
static const uint8_t P9N2_PU_PBASLVRST_IN_PROG_LEN                                = 4   ;
static const uint8_t P9N2_PU_PBASLVRST_BUSY_STATUS                                = 8   ;
static const uint8_t P9N2_PU_PBASLVRST_BUSY_STATUS_LEN                            = 4   ;
static const uint8_t P9N2_PU_PBASLVRST_SCOPE_ATTN_BAR                             = 12  ;
static const uint8_t P9N2_PU_PBASLVRST_SCOPE_ATTN_BAR_LEN                         = 2   ;

static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBAWBUFVAL0_START_WR_ADDR                            = 2   ;
static const uint8_t P9N2_PU_PBAWBUFVAL0_START_WR_ADDR_LEN                        = 30  ;
static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BUFFER_STATUS                         = 35  ;
static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BUFFER_STATUS_LEN                     = 5   ;
static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BYTE_COUNT                            = 41  ;
static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BYTE_COUNT_LEN                        = 7   ;

static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_SLVNUM                                = 0   ;
static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_SLVNUM_LEN                            = 2   ;
static const uint8_t P9N2_PU_PBAWBUFVAL1_START_WR_ADDR                            = 2   ;
static const uint8_t P9N2_PU_PBAWBUFVAL1_START_WR_ADDR_LEN                        = 30  ;
static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BUFFER_STATUS                         = 35  ;
static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BUFFER_STATUS_LEN                     = 5   ;
static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BYTE_COUNT                            = 41  ;
static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BYTE_COUNT_LEN                        = 7   ;

static const uint8_t P9N2_PU_PBAXCFG_PBAX_EN                                      = 0   ;
static const uint8_t P9N2_PU_PBAXCFG_RESERVATION_EN                               = 1   ;
static const uint8_t P9N2_PU_PBAXCFG_SND_RESET                                    = 2   ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_RESET                                    = 3   ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_GROUPID                                  = 4   ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_GROUPID_LEN                              = 4   ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_CHIPID                                   = 8   ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_CHIPID_LEN                               = 3   ;
static const uint8_t P9N2_PU_PBAXCFG_RESERVED_11                                  = 11  ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_BRDCST_GROUP                             = 12  ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_BRDCST_GROUP_LEN                         = 8   ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_DATATO_DIV                               = 20  ;
static const uint8_t P9N2_PU_PBAXCFG_RCV_DATATO_DIV_LEN                           = 5   ;
static const uint8_t P9N2_PU_PBAXCFG_RESERVED_25_26                               = 25  ;
static const uint8_t P9N2_PU_PBAXCFG_RESERVED_25_26_LEN                           = 2   ;
static const uint8_t P9N2_PU_PBAXCFG_SND_RETRY_COUNT_OVERCOM                      = 27  ;
static const uint8_t P9N2_PU_PBAXCFG_SND_RETRY_THRESH                             = 28  ;
static const uint8_t P9N2_PU_PBAXCFG_SND_RETRY_THRESH_LEN                         = 8   ;
static const uint8_t P9N2_PU_PBAXCFG_SND_RSVTO_DIV                                = 36  ;
static const uint8_t P9N2_PU_PBAXCFG_SND_RSVTO_DIV_LEN                            = 5   ;

static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_IN_PROGRESS                          = 0   ;
static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_ERROR                                = 1   ;
static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS                    = 2   ;
static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_RESERVATION_SET                      = 3   ;
static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_CAPTURE                              = 4   ;
static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_CAPTURE_LEN                          = 16  ;

static const uint8_t P9N2_PU_PBAXSHBR0_PUSH_START                                 = 0   ;
static const uint8_t P9N2_PU_PBAXSHBR0_PUSH_START_LEN                             = 29  ;

static const uint8_t P9N2_PU_PBAXSHBR1_PUSH_START                                 = 0   ;
static const uint8_t P9N2_PU_PBAXSHBR1_PUSH_START_LEN                             = 29  ;

static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_FULL                                  = 0   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_EMPTY                                 = 1   ;
static const uint8_t P9N2_PU_PBAXSHCS0_RESERVED_2_3                               = 2   ;
static const uint8_t P9N2_PU_PBAXSHCS0_RESERVED_2_3_LEN                           = 2   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1                       = 4   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1_LEN                   = 2   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_LENGTH                                = 6   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_LENGTH_LEN                            = 5   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_WRITE_PTR                             = 13  ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_WRITE_PTR_LEN                         = 5   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_READ_PTR                              = 21  ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_READ_PTR_LEN                          = 5   ;
static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_ENABLE                                = 31  ;

static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_FULL                                  = 0   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_EMPTY                                 = 1   ;
static const uint8_t P9N2_PU_PBAXSHCS1_RESERVED_2_3                               = 2   ;
static const uint8_t P9N2_PU_PBAXSHCS1_RESERVED_2_3_LEN                           = 2   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1                       = 4   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1_LEN                   = 2   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_LENGTH                                = 6   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_LENGTH_LEN                            = 5   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_WRITE_PTR                             = 13  ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_WRITE_PTR_LEN                         = 5   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_READ_PTR                              = 21  ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_READ_PTR_LEN                          = 5   ;
static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_ENABLE                                = 31  ;

static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_IN_PROGRESS                          = 0   ;
static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_ERROR                                = 1   ;
static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_PHASE_STATUS                         = 2   ;
static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_PHASE_STATUS_LEN                     = 2   ;
static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_CNT_STATUS                           = 4   ;
static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_CNT_STATUS_LEN                       = 4   ;
static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_RETRY_COUNT                          = 8   ;
static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_RETRY_COUNT_LEN                      = 8   ;

static const uint8_t P9N2_PU_PBAXSNDTX_SND_SCOPE                                  = 0   ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_SCOPE_LEN                              = 3   ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_QID                                    = 3   ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_TYPE                                   = 4   ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_RESERVATION                            = 5   ;
static const uint8_t P9N2_PU_PBAXSNDTX_RESERVED_6_7                               = 6   ;
static const uint8_t P9N2_PU_PBAXSNDTX_RESERVED_6_7_LEN                           = 2   ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_GROUPID                                = 8   ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_GROUPID_LEN                            = 4   ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_CHIPID                                 = 12  ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_CHIPID_LEN                             = 3   ;
static const uint8_t P9N2_PU_PBAXSNDTX_RESERVED_15                                = 15  ;
static const uint8_t P9N2_PU_PBAXSNDTX_VG_TARGE                                   = 16  ;
static const uint8_t P9N2_PU_PBAXSNDTX_VG_TARGE_LEN                               = 16  ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_STOP                                   = 59  ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_CNT                                    = 60  ;
static const uint8_t P9N2_PU_PBAXSNDTX_SND_CNT_LEN                                = 4   ;

static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_INJECT_TYPE                         = 0   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_INJECT_TYPE_LEN                     = 2   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_ECC_INJECT_ENABLE                = 2   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY                       = 3   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY_LEN                   = 4   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_PAR_INJECT_ENABLE                = 7   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY                   = 8   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY_LEN               = 3   ;
static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CONSTANT_EINJ                       = 11  ;

static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_POLL_SCALE                       = 0   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_POLL_SCALE_LEN                   = 4   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_DATA_SCALE                       = 4   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_DATA_SCALE_LEN                   = 4   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_PE_SCALE                         = 8   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_PE_SCALE_LEN                     = 4   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_BLOCK_CQPB_PB_INIT                 = 12  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_DISABLE_RCMD_CLKGATE                  = 13  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_HANG_SM_ON_ARE                     = 14  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_PCI_CLK_CHECK              = 15  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_LFSR_ARB_MODE                         = 16  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_DMAR_IOPACING               = 17  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_DMAW_IOPACING               = 18  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ADR_BAR_MODE                       = 19  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_STQ_ALLOCATION                     = 20  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_DISABLE_LPC_CMDS                      = 21  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_OOO_MODE                   = 22  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START                   = 23  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START_LEN               = 4   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE                    = 27  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE_LEN                = 2   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED1                             = 29  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED1_LEN                         = 3   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_WR_STRICT_ORDER_MODE               = 32  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN               = 33  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE               = 34  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE_LEN           = 2   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_NEW_FLOW_CACHE_INJECT       = 36  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INJ_ON_RESEND              = 37  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 38  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_ENH_FLOW                    = 39  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED2                             = 40  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG                      = 41  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP             = 42  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_VG                   = 43  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_GROUP          = 44  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_NODE           = 45  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED3                             = 46  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED3_LEN                         = 2   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING                  = 48  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING_LEN              = 2   ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_NODAL             = 50  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_GROUP             = 51  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_RNNN              = 52  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_RD_SKIP_GROUP               = 53  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_VG                      = 54  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_NODAL            = 55  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_GROUP            = 56  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_RNNN             = 57  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_TCE_SKIP_GROUP              = 58  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_VG                     = 59  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_ARBITRATION            = 60  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_CQ_TCE_ARBITRATION         = 61  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_MC_PREFETCH                = 62  ;
static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_IGNORE_SFSTAT                      = 63  ;

static const uint8_t P9N2_PHB_PBCQMODE_REG_PE_PEER2PEER_MODDE                     = 0   ;
static const uint8_t P9N2_PHB_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE            = 1   ;

static const uint8_t P9N2_PEC_STACK0_PBCQMODE_REG_PE_PEER2PEER_MODDE              = 0   ;
static const uint8_t P9N2_PEC_STACK0_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE     = 1   ;

static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_VALID                         = 0   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_WR_NOT_RD                     = 1   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_BAD_ADDR                      = 2   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_LINK_DOWN                     = 3   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_CORRUPT                       = 4   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_SENT                          = 5   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_BAD_WRITE                     = 6   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_RESET                         = 7   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_ID                               = 8   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID                       = 9   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID_LEN                   = 3   ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_SPARE                         = 12  ;
static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_SPARE_LEN                     = 4   ;

static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_VALID                     = 0   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_WR_NOT_RD                 = 1   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_ADDR                  = 2   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_DOWN                 = 3   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_CORRUPT                   = 4   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_SENT                      = 5   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_WRITE                 = 6   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_RESET                     = 7   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_ID                           = 8   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID                   = 9   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID_LEN               = 3   ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE                     = 12  ;
static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN                 = 4   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EN                     = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_RESET_MODE             = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_COUNTER_MODE           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_DIS       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_MODE      = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EXTERNAL_FREEZE        = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP                 = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP                 = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP                 = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP                 = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP                 = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP               = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP               = 18  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP               = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP               = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP               = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP               = 26  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP               = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP               = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP               = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP               = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP               = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0           = 38  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1           = 41  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2           = 44  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3           = 47  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MASK                   = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS0_MASK          = 51  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS1_MASK          = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS0_MASK          = 53  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS1_MASK          = 54  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_PB_CFG_CNPME_MASK          = 55  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MCD_MASK               = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE0_MASK               = 57  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE1_MASK               = 58  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE2_MASK               = 59  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_VAS_MASK               = 60  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EN                     = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_RESET_MODE             = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_COUNTER_MODE           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_DIS       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_MODE      = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EXTERNAL_FREEZE        = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP                 = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP                 = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP                 = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP                 = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP                 = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP               = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP               = 18  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP               = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP               = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP               = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP               = 26  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP               = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP               = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP               = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP               = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP               = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP_LEN           = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0           = 38  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1           = 41  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2           = 44  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3           = 47  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MASK                   = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS0_MASK          = 51  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS1_MASK          = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS0_MASK          = 53  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS1_MASK          = 54  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_INT_MASK               = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE0_MASK               = 57  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE1_MASK               = 58  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE2_MASK               = 59  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_PB_CFG_CNPMW_MASK          = 60  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ERROR          = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ADDR_ERROR     = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_ERROR_OTHER = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE      = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE_LEN  = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE      = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG       = 18  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG_LEN   = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE      = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE_LEN  = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP            = 43  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_LEN        = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP            = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP_LEN        = 14  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE            = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_LEN        = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK       = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK_LEN   = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE            = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_LEN        = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK       = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK_LEN   = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG             = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_LEN         = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK        = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK_LEN    = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP            = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_LEN        = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK       = 55  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK_LEN   = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_POLARITY   = 60  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE            = 61  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE_LEN        = 3   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE            = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_LEN        = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK       = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK_LEN   = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE            = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_LEN        = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK       = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK_LEN   = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG             = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_LEN         = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK        = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK_LEN    = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP            = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_LEN        = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK       = 55  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK_LEN   = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_POLARITY   = 60  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE            = 61  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE_LEN        = 3   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP      = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_LEN  = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK = 17  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK_LEN = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP      = 35  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_LEN  = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK = 49  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK_LEN = 14  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0           = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1           = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2           = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3           = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4           = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5           = 15  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6           = 18  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7           = 21  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT           = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT_SEL2      = 57  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_CHSW_HW405366  = 58  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT_LEN = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT_LEN = 32  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0          = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN      = 18  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1          = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1_LEN      = 18  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_PROTOCOL_ERROR      = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_OVERFLOW_ERROR      = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HW_PARITY_ERROR     = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_3             = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_COHERENCY_ERROR     = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ADDR_ERROR    = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ERROR         = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_LIMIT_ERROR = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_DATA_ROUTE_ERROR    = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_GTE_LEVEL1 = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_FORCE_MP_IPL        = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SBE_IPL             = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_12            = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13            = 13  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_14            = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_15            = 15  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR            = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR_DUP        = 17  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_PROTOCOL_ERROR           = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_OVERFLOW_ERROR           = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_HW_PARITY_ERROR          = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_3                  = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_COHERENCY_ERROR          = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ADDR_ERROR         = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ERROR              = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_LIMIT_ERROR = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_DATA_ROUTE_ERROR         = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_GTE_LEVEL1 = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_FORCE_MP_IPL             = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SBE_IPL                  = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_12                 = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_13                 = 13  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_14                 = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_15                 = 15  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR                 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP             = 17  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0         = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1         = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2         = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3         = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4         = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5         = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6         = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7         = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7_LEN     = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0         = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1         = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2         = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3         = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4         = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5         = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6         = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6_LEN     = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7         = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7_LEN     = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_EN = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_EN = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_EN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_EN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_EN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_EN = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_EN = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_EN = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_EN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_EN = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_EN = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_EN = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID = 44  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID = 60  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN = 4   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_EN = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_EN = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_EN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_EN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_EN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_EN = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_EN = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_EN = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_EN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_EN = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_EN = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_EN = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID = 44  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID = 60  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN = 4   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_EN     = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_EN     = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_EN     = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_EN     = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_EN     = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_EN     = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_EN     = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS = 13  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID = 19  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID = 25  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID = 31  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_AGGREGATE    = 37  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_FP_DISABLED  = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_INDIRECT_EN  = 49  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE     = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_EN     = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_EN     = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_EN     = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_EN     = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_EN     = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_EN     = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_EN     = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS = 13  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID = 19  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID = 25  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID = 31  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_AGGREGATE    = 37  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_FP_DISABLED  = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_INDIRECT_EN  = 49  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE     = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_MASTER_CHIP     = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_TM_MASTER       = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_EN      = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_EN      = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_EN      = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_EN      = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_AGGREGATE     = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_HOP             = 29  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_SMP_OPTICS      = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_CAPI_MODE = 31  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0            = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1            = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2            = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3            = 38  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_SPARE01 = 47  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_SPARE01_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_A_INDIRECT_EN = 49  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_SPARE2  = 51  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP   = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_ADDR_BAR        = 53  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP            = 54  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_DCACHE_CAPP     = 55  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE      = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE_LEN  = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_MASTER_CHIP     = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_TM_MASTER       = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_EN      = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_EN      = 5   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_EN      = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_EN      = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_AGGREGATE     = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_HOP             = 29  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_SMP_OPTICS      = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CAPI            = 31  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0            = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1            = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2            = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3            = 38  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_SPARE01 = 47  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_SPARE01_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_A_INDIRECT_EN = 49  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_SPARE2  = 51  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PHYP_IS_GROUP   = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_ADDR_BAR        = 53  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PUMP            = 54  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_DCACHE_CAPP     = 55  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE      = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN  = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_DD1_MODE    = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL         = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_PMU_FREEZE_MODE = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP  = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT    = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT_LEN = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT    = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT_LEN = 24  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_PBIXXX_INIT         = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED_LEN = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_IS_SYSTEM          = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_HNG_CHK_DISABLE         = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_DBG_CLR_MAX_HANG_STAGE      = 9   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT              = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT_LEN          = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK              = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK_LEN          = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK              = 23  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK_LEN          = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK             = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK_LEN         = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE      = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE_LEN  = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK = 42  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN = 7   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_PPE_SERIAL_CONTROL      = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_REQ_GATHER_ENABLE       = 57  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_CD_PULSE         = 58  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_OPTION_AB        = 59  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SERIAL_READ_ENABLE      = 60  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SERIAL_READ_SEL         = 61  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SERIAL_READ_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_RESET_ERROR_CAPTURE     = 63  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_ENABLE      = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL  = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_EN       = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL      = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL_LEN  = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP  = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP_LEN = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT    = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT_LEN = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT    = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT_LEN = 24  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1 = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2 = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3 = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3_LEN = 16  ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0  = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1  = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2  = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3  = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1  = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2  = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3  = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0  = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1  = 18  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2  = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3  = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0  = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1  = 26  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2  = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3  = 30  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C0  = 33  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1  = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2  = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3  = 38  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0  = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1  = 42  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2  = 44  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3  = 46  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0  = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1  = 50  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2  = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3  = 54  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0  = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1  = 58  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2  = 60  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3  = 62  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3_LEN = 2   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT_LEN = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT_LEN = 32  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0    = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1    = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2    = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3    = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4    = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5    = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6    = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7    = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7_LEN = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0    = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1    = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2    = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3    = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4    = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5    = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6    = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6_LEN = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7    = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7_LEN = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG                 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SLOW            = 1   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT     = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT          = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT_LEN      = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA      = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN  = 52  ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0      = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1      = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2      = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3      = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4      = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5      = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6      = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7      = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7_LEN  = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0      = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1      = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2      = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3      = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4      = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5      = 40  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6      = 48  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7      = 56  ;
static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7_LEN  = 8   ;

static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0                 = 0   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1                 = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2                 = 4   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3                 = 6   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0                 = 8   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1                 = 10  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2                 = 12  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3                 = 14  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3_LEN             = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL        = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL        = 18  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL        = 20  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL        = 22  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL        = 24  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL        = 26  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_SEL              = 28  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT                  = 29  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT_LEN              = 3   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_EN           = 32  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_TRIG         = 33  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL  = 34  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL_LEN = 2   ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH = 36  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH_LEN = 16  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_PRESCALE = 52  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_FIXED_WIN = 53  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP1_SEL     = 54  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP2_SEL     = 55  ;
static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_DATA_ACT               = 63  ;

static const uint8_t P9N2_PU_PB_CHGRATE_CFG_ENABLE                                = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_SERIAL_SWITCH_CD                      = 1   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_GP_DP0_HIST                     = 2   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_GP_DP1_HIST                     = 3   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_VG_DP0_HIST                     = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_VG_DP1_HIST                     = 5   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_RNS_DP0_HIST                    = 6   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_RNS_DP1_HIST                    = 7   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_SPARE1                                = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_SPARE1_LEN                            = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_GP_DP0_OVERFLOW                       = 32  ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_GP_DP1_OVERFLOW                       = 33  ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_VG_DP0_OVERFLOW                       = 34  ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_VG_DP1_OVERFLOW                       = 35  ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RNS_DP0_OVERFLOW                      = 36  ;
static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RNS_DP1_OVERFLOW                      = 37  ;

static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_00                  = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_00_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_01                  = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_01_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_02                  = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_02_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_03                  = 12  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_03_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_04                  = 16  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_04_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_05                  = 20  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_05_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_06                  = 24  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_06_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_07                  = 28  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_07_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_08                  = 32  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_08_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_09                  = 36  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_09_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_10                  = 40  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_10_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_11                  = 44  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_11_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_12                  = 48  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_12_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_13                  = 52  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_13_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_14                  = 56  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_14_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_15                  = 60  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_15_LEN              = 4   ;

static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_00                  = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_00_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_01                  = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_01_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_02                  = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_02_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_03                  = 12  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_03_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_04                  = 16  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_04_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_05                  = 20  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_05_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_06                  = 24  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_06_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_07                  = 28  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_07_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_08                  = 32  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_08_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_09                  = 36  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_09_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_10                  = 40  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_10_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_11                  = 44  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_11_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_12                  = 48  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_12_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_13                  = 52  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_13_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_14                  = 56  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_14_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_15                  = 60  ;
static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_15_LEN              = 4   ;

static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_00                 = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_00_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_01                 = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_01_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_02                 = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_02_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_03                 = 12  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_03_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_04                 = 16  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_04_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_05                 = 20  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_05_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_06                 = 24  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_06_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_07                 = 28  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_07_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_08                 = 32  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_08_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_09                 = 36  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_09_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_10                 = 40  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_10_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_11                 = 44  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_11_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_12                 = 48  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_12_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_13                 = 52  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_13_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_14                 = 56  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_14_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_15                 = 60  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_15_LEN             = 4   ;

static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_00                 = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_00_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_01                 = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_01_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_02                 = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_02_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_03                 = 12  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_03_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_04                 = 16  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_04_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_05                 = 20  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_05_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_06                 = 24  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_06_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_07                 = 28  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_07_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_08                 = 32  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_08_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_09                 = 36  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_09_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_10                 = 40  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_10_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_11                 = 44  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_11_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_12                 = 48  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_12_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_13                 = 52  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_13_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_14                 = 56  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_14_LEN             = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_15                 = 60  ;
static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_15_LEN             = 4   ;

static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_LOAD          = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SLOW          = 1   ;
static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_COUNT   = 2   ;
static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_COUNT_LEN = 6   ;
static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SELECT        = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SELECT_LEN    = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_DATA    = 12  ;
static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_DATA_LEN = 52  ;

static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_00                  = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_00_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_01                  = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_01_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_02                  = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_02_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_03                  = 12  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_03_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_04                  = 16  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_04_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_05                  = 20  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_05_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_06                  = 24  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_06_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_07                  = 28  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_07_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_08                  = 32  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_08_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_09                  = 36  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_09_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_10                  = 40  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_10_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_11                  = 44  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_11_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_12                  = 48  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_12_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_13                  = 52  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_13_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_14                  = 56  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_14_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_15                  = 60  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_15_LEN              = 4   ;

static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_00                  = 0   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_00_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_01                  = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_01_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_02                  = 8   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_02_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_03                  = 12  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_03_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_04                  = 16  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_04_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_05                  = 20  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_05_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_06                  = 24  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_06_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_07                  = 28  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_07_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_08                  = 32  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_08_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_09                  = 36  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_09_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_10                  = 40  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_10_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_11                  = 44  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_11_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_12                  = 48  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_12_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_13                  = 52  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_13_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_14                  = 56  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_14_LEN              = 4   ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_15                  = 60  ;
static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_15_LEN              = 4   ;

static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION0_REG_ACTION0                      = 0   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION0_REG_ACTION0_LEN                  = 34  ;

static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION1_REG_ACTION1                      = 0   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION1_REG_ACTION1_LEN                  = 34  ;

static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW1_ERROR           = 0   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW2_ERROR           = 1   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_PROTOCOL_ERROR      = 2   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_OVERFLOW_ERROR      = 3   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW1_ERROR           = 4   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW2_ERROR           = 5   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_PROTOCOL_ERROR      = 6   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_OVERFLOW_ERROR      = 7   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_8                         = 8   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_9                         = 9   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_10                        = 10  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_11                        = 11  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_12                        = 12  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_13                        = 13  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_14                        = 14  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_15                        = 15  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_OVERFLOW_CHECKSTOP              = 16  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PROTOCOL_CHECKSTOP              = 17  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_ROUTE_CHECKSTOP                 = 18  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_19                        = 19  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_20                        = 20  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_21                        = 21  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_22                        = 22  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_23                        = 23  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_24                        = 24  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_25                        = 25  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_26                        = 26  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_27                        = 27  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_28                        = 28  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_29                        = 29  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_30                        = 30  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_31                        = 31  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SCOM_ERR                        = 32  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SCOM_ERR_DUP                    = 33  ;

static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW1_ERROR                = 0   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW2_ERROR                = 1   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_PROTOCOL_ERROR           = 2   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_OVERFLOW_ERROR           = 3   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW1_ERROR                = 4   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW2_ERROR                = 5   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_PROTOCOL_ERROR           = 6   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_OVERFLOW_ERROR           = 7   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_8                              = 8   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_9                              = 9   ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_10                             = 10  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_11                             = 11  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_12                             = 12  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_13                             = 13  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_14                             = 14  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_15                             = 15  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_OVERFLOW_CHECKSTOP                   = 16  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PROTOCOL_CHECKSTOP                   = 17  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_ROUTE_CHECKSTOP                      = 18  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_19                             = 19  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_20                             = 20  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_21                             = 21  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_22                             = 22  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_23                             = 23  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_24                             = 24  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_25                             = 25  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_26                             = 26  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_27                             = 27  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_28                             = 28  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_29                             = 29  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_30                             = 30  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_31                             = 31  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SCOM_ERR                             = 32  ;
static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SCOM_ERR_DUP                         = 33  ;

static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0              = 0   ;
static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0_LEN          = 64  ;

static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1              = 0   ;
static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1_LEN          = 64  ;

static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_EN     = 0   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_EN     = 1   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_EN     = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_EN     = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_EN     = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_EN     = 5   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_EN     = 6   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_EN     = 7   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_EN     = 8   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_EN     = 9   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_EN     = 10  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_EN     = 11  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID = 28  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID = 32  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID = 36  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID = 40  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID = 44  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID = 48  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID = 52  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID = 56  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID = 60  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN = 4   ;

static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_EN     = 0   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_EN     = 1   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_EN     = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_EN     = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_EN     = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_EN     = 5   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_EN     = 6   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_EN     = 7   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_EN     = 8   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_EN     = 9   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_EN     = 10  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_EN     = 11  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID = 28  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID = 32  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID = 36  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID = 40  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID = 44  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID = 48  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID = 52  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID = 56  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID = 60  ;
static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN = 4   ;

static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_EN                 = 0   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_EN                 = 1   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_EN                 = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_EN                 = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_EN                 = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_EN                 = 5   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_EN                 = 6   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS          = 8   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS          = 9   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS          = 10  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS          = 11  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS          = 12  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS          = 13  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS          = 14  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID             = 16  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID             = 19  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID             = 22  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID             = 25  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID             = 28  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID             = 31  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID             = 34  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_AGGREGATE                = 37  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_FP_DISABLED              = 48  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_INDIRECT_EN              = 49  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE            = 50  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE                 = 56  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN             = 8   ;

static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_EN                 = 0   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_EN                 = 1   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_EN                 = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_EN                 = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_EN                 = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_EN                 = 5   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_EN                 = 6   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS          = 8   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS          = 9   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS          = 10  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS          = 11  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS          = 12  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS          = 13  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS          = 14  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID             = 16  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID             = 19  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID             = 22  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID             = 25  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID             = 28  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID             = 31  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID             = 34  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN         = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_AGGREGATE                = 37  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_FP_DISABLED              = 48  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN              = 49  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE            = 50  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE                 = 56  ;
static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN             = 8   ;

static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_MASTER_CHIP                 = 0   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_TM_MASTER                   = 1   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER          = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER          = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_EN                  = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_EN                  = 5   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_EN                  = 6   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_EN                  = 7   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS           = 8   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS           = 9   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS           = 10  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS           = 11  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID             = 12  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID             = 16  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID             = 20  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID             = 24  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_AGGREGATE                 = 28  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_HOP                         = 29  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_SMP_OPTICS                  = 30  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_CAPI_MODE           = 31  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT0                        = 32  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT0_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT1                        = 34  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT1_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT2                        = 36  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT2_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT3                        = 38  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT3_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID            = 40  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN        = 7   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_SPARE01             = 47  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_SPARE01_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_A_INDIRECT_EN       = 49  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_GATHER_ENABLE             = 50  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_SPARE2              = 51  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_PHYP_IS_GROUP               = 52  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_ADDR_BAR                    = 53  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_PUMP                        = 54  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_DCACHE_CAPP                 = 55  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE                  = 56  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN              = 8   ;

static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_MASTER_CHIP                 = 0   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_TM_MASTER                   = 1   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER          = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER          = 3   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_EN                  = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_EN                  = 5   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_EN                  = 6   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_EN                  = 7   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS           = 8   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS           = 9   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS           = 10  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS           = 11  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID             = 12  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID             = 16  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID             = 20  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID             = 24  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN         = 4   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_AGGREGATE                 = 28  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_HOP                         = 29  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_SMP_OPTICS                  = 30  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_CAPI                        = 31  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0                        = 32  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1                        = 34  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2                        = 36  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3                        = 38  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3_LEN                    = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID            = 40  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN        = 7   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_SPARE01             = 47  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_SPARE01_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_A_INDIRECT_EN       = 49  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE             = 50  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_SPARE2              = 51  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP               = 52  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_ADDR_BAR                    = 53  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_PUMP                        = 54  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_DCACHE_CAPP                 = 55  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE                  = 56  ;
static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN              = 8   ;

static const uint8_t P9N2_PU_PB_EAST_MODE_PB_EAST_PBIXXX_INIT                     = 0   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_CHIP_IS_SYSTEM                      = 4   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_HNG_CHK_DISABLE                     = 8   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_DBG_CLR_MAX_HANG_STAGE                  = 9   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SW_AB_WAIT                          = 12  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SW_AB_WAIT_LEN                      = 4   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SP_HW_MARK                          = 16  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SP_HW_MARK_LEN                      = 7   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_GP_HW_MARK                          = 23  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_GP_HW_MARK_LEN                      = 7   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_LCL_HW_MARK                         = 30  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_LCL_HW_MARK_LEN                     = 6   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE          = 36  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE_LEN      = 6   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK            = 42  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN        = 7   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_PPE_SERIAL_CONTROL                  = 56  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_REQ_GATHER_ENABLE                   = 57  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SWITCH_CD_PULSE                     = 58  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SWITCH_OPTION_AB                    = 59  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SERIAL_READ_ENABLE                  = 60  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SERIAL_READ_SEL                     = 61  ;
static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SERIAL_READ_SEL_LEN                 = 2   ;
static const uint8_t P9N2_PU_PB_EAST_MODE_PB_CFG_EAST_RESET_ERROR_CAPTURE         = 63  ;

static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG                             = 0   ;
static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SLOW                        = 1   ;
static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT                 = 2   ;
static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN             = 6   ;
static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT                      = 8   ;
static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT_LEN                  = 4   ;
static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA                  = 12  ;
static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN              = 52  ;

static const uint8_t P9N2_PU_PB_EAST_SPARE_SPARE                                  = 0   ;
static const uint8_t P9N2_PU_PB_EAST_SPARE_SPARE_LEN                              = 64  ;

static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT             = 1   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN         = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT         = 9   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT         = 17  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT         = 24  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN     = 5   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT             = 33  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT_LEN         = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT         = 41  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT         = 49  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN     = 7   ;

static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT             = 1   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN         = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT         = 9   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT         = 17  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT         = 24  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN     = 5   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT             = 33  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN         = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT         = 41  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT         = 49  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN     = 7   ;

static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT             = 1   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN         = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT         = 9   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT         = 17  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT         = 24  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN     = 5   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT             = 33  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN         = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT         = 41  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT         = 49  ;
static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN     = 7   ;

static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY                = 4   ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN            = 12  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY                = 20  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN            = 12  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY                = 36  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN            = 12  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY                = 52  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN            = 12  ;

static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY                  = 4   ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY_LEN              = 12  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY                  = 20  ;
static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY_LEN              = 12  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER0                               = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER0_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER1                               = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER1_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER2                               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER2_LEN                           = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER3                               = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER3_LEN                           = 16  ;

static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0_ENABLE                     = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU1_ENABLE                     = 1   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2_ENABLE                     = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU3_ENABLE                     = 3   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU4_ENABLE                     = 4   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU5_ENABLE                     = 5   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU6_ENABLE                     = 6   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU7_ENABLE                     = 7   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMULET_FREEZE_MODE              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_COMMON_FREEZE_MODE              = 9   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMULET_RESET_MODE               = 10  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT0_SEL                      = 11  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL                      = 12  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL                      = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL                      = 20  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL_LEN                  = 4   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE                       = 24  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE_LEN                   = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE                       = 26  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE_LEN                   = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE                       = 28  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE_LEN                   = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE                       = 30  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE_LEN                   = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU01_LINK_SELECT               = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU23_LINK_SELECT               = 33  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU45_LINK_SELECT               = 34  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU67_LINK_SELECT               = 35  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE             = 36  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE             = 38  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE             = 40  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE             = 42  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE             = 44  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE             = 46  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE             = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE             = 50  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN         = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN               = 52  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_GLOBAL_RUN_MODE                 = 53  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_SPARE                           = 54  ;
static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_SPARE_LEN                       = 10  ;

static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_SET                        = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN                    = 6   ;
static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0                  = 6   ;
static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0_LEN              = 2   ;
static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_STAT                       = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN                   = 6   ;

static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0                  = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1                  = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2                  = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3                  = 24  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0                  = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1                  = 40  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2                  = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3                  = 56  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN              = 8   ;

static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0                  = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1                  = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2                  = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3                  = 24  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0                  = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1                  = 40  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2                  = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3                  = 56  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN              = 8   ;

static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0                  = 0   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1                  = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2                  = 16  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3                  = 24  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0                  = 32  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1                  = 40  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2                  = 48  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN              = 8   ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3                  = 56  ;
static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN              = 8   ;

static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE                       = 0   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN                   = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE                       = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN                   = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE                      = 8   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN                  = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE                       = 12  ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN                   = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE                       = 16  ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN                   = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE                      = 20  ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN                  = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE                       = 24  ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN                   = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE                       = 28  ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN                   = 4   ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE                      = 32  ;
static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN                  = 4   ;

static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE                   = 0   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE                   = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE                  = 8   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN              = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE                   = 12  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE                   = 16  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE                  = 20  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN              = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE                   = 24  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE                   = 28  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE                  = 32  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN              = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE                   = 36  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE                   = 40  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE                  = 44  ;
static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE_LEN              = 4   ;

static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CONTROL_ERROR                     = 0   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_ADDR_PERR                         = 1   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC0_CREDITERR                     = 2   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC1_CREDITERR                     = 3   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC2_CREDITERR                     = 4   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC3_CREDITERR                     = 5   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_DAT_HI_PERR                       = 6   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_DAT_LO_PERR                       = 7   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_FRAME_CREDITERR                   = 8   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_PC0_CREDITERR                     = 9   ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_PC1_CREDITERR                     = 10  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_PRSP_PTYERR                       = 11  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_TTAG_PERR                         = 12  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_VC0_CREDITERR                     = 13  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_VC1_CREDITERR                     = 14  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_RTAG_PTYERR                       = 15  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CONTROL_ERROR                     = 16  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_ADDR_PERR                         = 17  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC0_CREDITERR                     = 18  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC1_CREDITERR                     = 19  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC2_CREDITERR                     = 20  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC3_CREDITERR                     = 21  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_DAT_HI_PERR                       = 22  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_DAT_LO_PERR                       = 23  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_FRAME_CREDITERR                   = 24  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_PC0_CREDITERR                     = 25  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_PC1_CREDITERR                     = 26  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_PRSP_PTYERR                       = 27  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_TTAG_PERR                         = 28  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_VC0_CREDITERR                     = 29  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_VC1_CREDITERR                     = 30  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_RTAG_PTYERR                       = 31  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CONTROL_ERROR                     = 32  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_ADDR_PERR                         = 33  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC0_CREDITERR                     = 34  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC1_CREDITERR                     = 35  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC2_CREDITERR                     = 36  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC3_CREDITERR                     = 37  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_DAT_HI_PERR                       = 38  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_DAT_LO_PERR                       = 39  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_FRAME_CREDITERR                   = 40  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_PC0_CREDITERR                     = 41  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_PC1_CREDITERR                     = 42  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_PRSP_PTYERR                       = 43  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_TTAG_PERR                         = 44  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_VC0_CREDITERR                     = 45  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_VC1_CREDITERR                     = 46  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_RTAG_PTYERR                       = 47  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CONTROL_ERROR                     = 48  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_ADDR_PERR                         = 49  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC0_CREDITERR                     = 50  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC1_CREDITERR                     = 51  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC2_CREDITERR                     = 52  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC3_CREDITERR                     = 53  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_DAT_HI_PERR                       = 54  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_DAT_LO_PERR                       = 55  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_FRAME_CREDITERR                   = 56  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_PC0_CREDITERR                     = 57  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_PC1_CREDITERR                     = 58  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_PRSP_PTYERR                       = 59  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_TTAG_PERR                         = 60  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_VC0_CREDITERR                     = 61  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_VC1_CREDITERR                     = 62  ;
static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_RTAG_PTYERR                       = 63  ;

static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CONTROL_ERROR                 = 0   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_ADDR_PERR                     = 1   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC0_CREDITERR                 = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC1_CREDITERR                 = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC2_CREDITERR                 = 4   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC3_CREDITERR                 = 5   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_DAT_HI_PERR                   = 6   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_DAT_LO_PERR                   = 7   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_FRAME_CREDITERR               = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_PC0_CREDITERR                 = 9   ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_PC1_CREDITERR                 = 10  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_PRSP_PTYERR                   = 11  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_TTAG_PERR                     = 12  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_VC0_CREDITERR                 = 13  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_VC1_CREDITERR                 = 14  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_RTAG_PTYERR                   = 15  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CONTROL_ERROR                 = 16  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_ADDR_PERR                     = 17  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC0_CREDITERR                 = 18  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC1_CREDITERR                 = 19  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC2_CREDITERR                 = 20  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC3_CREDITERR                 = 21  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_DAT_HI_PERR                   = 22  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_DAT_LO_PERR                   = 23  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_FRAME_CREDITERR               = 24  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_PC0_CREDITERR                 = 25  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_PC1_CREDITERR                 = 26  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_PRSP_PTYERR                   = 27  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_TTAG_PERR                     = 28  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_VC0_CREDITERR                 = 29  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_VC1_CREDITERR                 = 30  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_RTAG_PTYERR                   = 31  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CONTROL_ERROR                 = 32  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_ADDR_PERR                     = 33  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC0_CREDITERR                 = 34  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC1_CREDITERR                 = 35  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC2_CREDITERR                 = 36  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC3_CREDITERR                 = 37  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_DAT_HI_PERR                   = 38  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_DAT_LO_PERR                   = 39  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_FRAME_CREDITERR               = 40  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_PC0_CREDITERR                 = 41  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_PC1_CREDITERR                 = 42  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_PRSP_PTYERR                   = 43  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_TTAG_PERR                     = 44  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_VC0_CREDITERR                 = 45  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_VC1_CREDITERR                 = 46  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_RTAG_PTYERR                   = 47  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CONTROL_ERROR                 = 48  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_ADDR_PERR                     = 49  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC0_CREDITERR                 = 50  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC1_CREDITERR                 = 51  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC2_CREDITERR                 = 52  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC3_CREDITERR                 = 53  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_DAT_HI_PERR                   = 54  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_DAT_LO_PERR                   = 55  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_FRAME_CREDITERR               = 56  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_PC0_CREDITERR                 = 57  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_PC1_CREDITERR                 = 58  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_PRSP_PTYERR                   = 59  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_TTAG_PERR                     = 60  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_VC0_CREDITERR                 = 61  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_VC1_CREDITERR                 = 62  ;
static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_RTAG_PTYERR                   = 63  ;

static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CONTROL_ERROR                 = 0   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_ADDR_PERR                     = 1   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC0_CREDITERR                 = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC1_CREDITERR                 = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC2_CREDITERR                 = 4   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC3_CREDITERR                 = 5   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_DAT_HI_PERR                   = 6   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_DAT_LO_PERR                   = 7   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_FRAME_CREDITERR               = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_PC0_CREDITERR                 = 9   ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_PC1_CREDITERR                 = 10  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_PRSP_PTYERR                   = 11  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_TTAG_PERR                     = 12  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_VC0_CREDITERR                 = 13  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_VC1_CREDITERR                 = 14  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_RTAG_PTYERR                   = 15  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CONTROL_ERROR                 = 16  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_ADDR_PERR                     = 17  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC0_CREDITERR                 = 18  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC1_CREDITERR                 = 19  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC2_CREDITERR                 = 20  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC3_CREDITERR                 = 21  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_DAT_HI_PERR                   = 22  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_DAT_LO_PERR                   = 23  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_FRAME_CREDITERR               = 24  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_PC0_CREDITERR                 = 25  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_PC1_CREDITERR                 = 26  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_PRSP_PTYERR                   = 27  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_TTAG_PERR                     = 28  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_VC0_CREDITERR                 = 29  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_VC1_CREDITERR                 = 30  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_RTAG_PTYERR                   = 31  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CONTROL_ERROR                 = 32  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_ADDR_PERR                     = 33  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC0_CREDITERR                 = 34  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC1_CREDITERR                 = 35  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC2_CREDITERR                 = 36  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC3_CREDITERR                 = 37  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_DAT_HI_PERR                   = 38  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_DAT_LO_PERR                   = 39  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_FRAME_CREDITERR               = 40  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_PC0_CREDITERR                 = 41  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_PC1_CREDITERR                 = 42  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_PRSP_PTYERR                   = 43  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_TTAG_PERR                     = 44  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_VC0_CREDITERR                 = 45  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_VC1_CREDITERR                 = 46  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_RTAG_PTYERR                   = 47  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CONTROL_ERROR                 = 48  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_ADDR_PERR                     = 49  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC0_CREDITERR                 = 50  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC1_CREDITERR                 = 51  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC2_CREDITERR                 = 52  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC3_CREDITERR                 = 53  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_DAT_HI_PERR                   = 54  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_DAT_LO_PERR                   = 55  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_FRAME_CREDITERR               = 56  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_PC0_CREDITERR                 = 57  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_PC1_CREDITERR                 = 58  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_PRSP_PTYERR                   = 59  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_TTAG_PERR                     = 60  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_VC0_CREDITERR                 = 61  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_VC1_CREDITERR                 = 62  ;
static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_RTAG_PTYERR                   = 63  ;

static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CONTROL_ERROR                       = 0   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_ADDR_PERR                           = 1   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC0_CREDITERR                       = 2   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC1_CREDITERR                       = 3   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC2_CREDITERR                       = 4   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC3_CREDITERR                       = 5   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_DAT_HI_PERR                         = 6   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_DAT_LO_PERR                         = 7   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_FRAME_CREDITERR                     = 8   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_PC0_CREDITERR                       = 9   ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_PC1_CREDITERR                       = 10  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_PRSP_PTYERR                         = 11  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_TTAG_PERR                           = 12  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_VC0_CREDITERR                       = 13  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_VC1_CREDITERR                       = 14  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_RTAG_PTYERR                         = 15  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CONTROL_ERROR                       = 16  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_ADDR_PERR                           = 17  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC0_CREDITERR                       = 18  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC1_CREDITERR                       = 19  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC2_CREDITERR                       = 20  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC3_CREDITERR                       = 21  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_DAT_HI_PERR                         = 22  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_DAT_LO_PERR                         = 23  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_FRAME_CREDITERR                     = 24  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_PC0_CREDITERR                       = 25  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_PC1_CREDITERR                       = 26  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_PRSP_PTYERR                         = 27  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_TTAG_PERR                           = 28  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_VC0_CREDITERR                       = 29  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_VC1_CREDITERR                       = 30  ;
static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_RTAG_PTYERR                         = 31  ;

static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8              = 0   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_DISABLE_GATHERING                    = 1   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION              = 2   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION             = 3   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT                   = 4   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT                   = 12  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_FMR_DISABLE                          = 20  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_FMR_SPARE                            = 21  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_CMD_EXP_TIME                             = 22  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_CMD_EXP_TIME_LEN                         = 2   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR                = 24  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_PRS_DISABLE                          = 25  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_PRS_SPARE                            = 26  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_PRS_SPARE_LEN                        = 6   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8              = 32  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_DISABLE_GATHERING                    = 33  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION              = 34  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION             = 35  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT                   = 36  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT                   = 44  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_FMR_DISABLE                          = 52  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_FMR_SPARE                            = 53  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_FMR_SPARE_LEN                        = 3   ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR                = 56  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_PRS_DISABLE                          = 57  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_PRS_SPARE                            = 58  ;
static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_PRS_SPARE_LEN                        = 6   ;

static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8          = 0   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_DISABLE_GATHERING                = 1   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION          = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION         = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT               = 12  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_FMR_DISABLE                      = 20  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_FMR_SPARE                        = 21  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_CMD_EXP_TIME                         = 22  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_CMD_EXP_TIME_LEN                     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR            = 24  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_PRS_DISABLE                      = 25  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE                        = 26  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE_LEN                    = 6   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8          = 32  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_DISABLE_GATHERING                = 33  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION          = 34  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION         = 35  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT               = 36  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT               = 44  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_FMR_DISABLE                      = 52  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE                        = 53  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE_LEN                    = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR            = 56  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_PRS_DISABLE                      = 57  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE                        = 58  ;
static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE_LEN                    = 6   ;

static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8              = 0   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_DISABLE_GATHERING                    = 1   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION              = 2   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION             = 3   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT                   = 4   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT                   = 12  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_FMR_DISABLE                          = 20  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_FMR_SPARE                            = 21  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_CMD_EXP_TIME                             = 22  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_CMD_EXP_TIME_LEN                         = 2   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR                = 24  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_PRS_DISABLE                          = 25  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_PRS_SPARE                            = 26  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_PRS_SPARE_LEN                        = 6   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8              = 32  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_DISABLE_GATHERING                    = 33  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION              = 34  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION             = 35  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT                   = 36  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT                   = 44  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_FMR_DISABLE                          = 52  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_FMR_SPARE                            = 53  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_FMR_SPARE_LEN                        = 3   ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR                = 56  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_PRS_DISABLE                          = 57  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_PRS_SPARE                            = 58  ;
static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_PRS_SPARE_LEN                        = 6   ;

static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8          = 0   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_DISABLE_GATHERING                = 1   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION          = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION         = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT               = 12  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_FMR_DISABLE                      = 20  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_FMR_SPARE                        = 21  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_CMD_EXP_TIME                         = 22  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_CMD_EXP_TIME_LEN                     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR            = 24  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_PRS_DISABLE                      = 25  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE                        = 26  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE_LEN                    = 6   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8          = 32  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_DISABLE_GATHERING                = 33  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION          = 34  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION         = 35  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT               = 36  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT               = 44  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_FMR_DISABLE                      = 52  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE                        = 53  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE_LEN                    = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR            = 56  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_PRS_DISABLE                      = 57  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE                        = 58  ;
static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE_LEN                    = 6   ;

static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8              = 0   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_DISABLE_GATHERING                    = 1   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION              = 2   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION             = 3   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT                   = 4   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT                   = 12  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_FMR_DISABLE                          = 20  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_FMR_SPARE                            = 21  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_CMD_EXP_TIME                             = 22  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_CMD_EXP_TIME_LEN                         = 2   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR                = 24  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_PRS_DISABLE                          = 25  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_PRS_SPARE                            = 26  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_PRS_SPARE_LEN                        = 6   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8              = 32  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_DISABLE_GATHERING                    = 33  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION              = 34  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION             = 35  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT                   = 36  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT                   = 44  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN               = 8   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_FMR_DISABLE                          = 52  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_FMR_SPARE                            = 53  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_FMR_SPARE_LEN                        = 3   ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR                = 56  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_PRS_DISABLE                          = 57  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_PRS_SPARE                            = 58  ;
static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_PRS_SPARE_LEN                        = 6   ;

static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8          = 0   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_DISABLE_GATHERING                = 1   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION          = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION         = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT               = 12  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_FMR_DISABLE                      = 20  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_FMR_SPARE                        = 21  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_CMD_EXP_TIME                         = 22  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_CMD_EXP_TIME_LEN                     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR            = 24  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_PRS_DISABLE                      = 25  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE                        = 26  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE_LEN                    = 6   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8          = 32  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_DISABLE_GATHERING                = 33  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION          = 34  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION         = 35  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT               = 36  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT               = 44  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_FMR_DISABLE                      = 52  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE                        = 53  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE_LEN                    = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR            = 56  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_PRS_DISABLE                      = 57  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE                        = 58  ;
static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE_LEN                    = 6   ;

static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_CREDIT_PRIORITY_4_NOT_8          = 0   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_DISABLE_GATHERING                = 1   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_DISABLE_CMD_COMPRESSION          = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_DISABLE_PRSP_COMPRESSION         = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT               = 12  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_FMR_DISABLE                      = 20  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_FMR_SPARE                        = 21  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_CMD_EXP_TIME                         = 22  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_CMD_EXP_TIME_LEN                     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_RUN_AFTER_FRAME_ERROR            = 24  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_PRS_DISABLE                      = 25  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE                        = 26  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE_LEN                    = 6   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_CREDIT_PRIORITY_4_NOT_8          = 32  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_DISABLE_GATHERING                = 33  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_DISABLE_CMD_COMPRESSION          = 34  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_DISABLE_PRSP_COMPRESSION         = 35  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT               = 36  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT               = 44  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT_LEN           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_FMR_DISABLE                      = 52  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE                        = 53  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE_LEN                    = 3   ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_RUN_AFTER_FRAME_ERROR            = 56  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_PRS_DISABLE                      = 57  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE                        = 58  ;
static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE_LEN                    = 6   ;

static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION0_REG_ACTION0                       = 0   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION0_REG_ACTION0_LEN                   = 64  ;

static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION1_REG_ACTION1                       = 0   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION1_REG_ACTION1_LEN                   = 64  ;

static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR00_TRAINED                    = 0   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR01_TRAINED                    = 1   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR02_TRAINED                    = 2   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR03_TRAINED                    = 3   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR04_TRAINED                    = 4   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR05_TRAINED                    = 5   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV6                             = 6   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV7                             = 7   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_UE                         = 8   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_CE                         = 9   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_SUE                        = 10  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_UE                         = 11  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_CE                         = 12  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_SUE                        = 13  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_UE                         = 14  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_CE                         = 15  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_SUE                        = 16  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV17                            = 17  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV18                            = 18  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV19                            = 19  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER00_ATTN                    = 20  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER01_ATTN                    = 21  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER02_ATTN                    = 22  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER03_ATTN                    = 23  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER04_ATTN                    = 24  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER05_ATTN                    = 25  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV26                            = 26  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV27                            = 27  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER00_ATTN                    = 28  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER01_ATTN                    = 29  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER02_ATTN                    = 30  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER03_ATTN                    = 31  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER04_ATTN                    = 32  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER05_ATTN                    = 33  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV34                            = 34  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV35                            = 35  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB00_SPATTN                      = 36  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB01_SPATTN                      = 37  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB10_SPATTN                      = 38  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB11_SPATTN                      = 39  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB20_SPATTN                      = 40  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB21_SPATTN                      = 41  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB30_SPATTN                      = 42  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB31_SPATTN                      = 43  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB40_SPATTN                      = 44  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB41_SPATTN                      = 45  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB50_SPATTN                      = 46  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB51_SPATTN                      = 47  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_ERR                        = 52  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_ERR                        = 53  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_ERR                        = 54  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DIB01_ERR                        = 56  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DIB23_ERR                        = 57  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DIB45_ERR                        = 58  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_SCOM_ERR_DUP                     = 62  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_SCOM_ERR                         = 63  ;

static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR00_TRAINED                         = 0   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR01_TRAINED                         = 1   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR02_TRAINED                         = 2   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR03_TRAINED                         = 3   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR04_TRAINED                         = 4   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR05_TRAINED                         = 5   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV6                                  = 6   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV7                                  = 7   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_UE                              = 8   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_CE                              = 9   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_SUE                             = 10  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_UE                              = 11  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_CE                              = 12  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_SUE                             = 13  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_UE                              = 14  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_CE                              = 15  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_SUE                             = 16  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV17                                 = 17  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV18                                 = 18  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV19                                 = 19  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER00_ATTN                         = 20  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER01_ATTN                         = 21  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER02_ATTN                         = 22  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER03_ATTN                         = 23  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER04_ATTN                         = 24  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER05_ATTN                         = 25  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV26                                 = 26  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV27                                 = 27  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER00_ATTN                         = 28  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER01_ATTN                         = 29  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER02_ATTN                         = 30  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER03_ATTN                         = 31  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER04_ATTN                         = 32  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER05_ATTN                         = 33  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV34                                 = 34  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV35                                 = 35  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB00_SPATTN                           = 36  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB01_SPATTN                           = 37  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB10_SPATTN                           = 38  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB11_SPATTN                           = 39  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB20_SPATTN                           = 40  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB21_SPATTN                           = 41  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB30_SPATTN                           = 42  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB31_SPATTN                           = 43  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB40_SPATTN                           = 44  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB41_SPATTN                           = 45  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB50_SPATTN                           = 46  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB51_SPATTN                           = 47  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_ERR                             = 52  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_ERR                             = 53  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_ERR                             = 54  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DIB01_ERR                             = 56  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DIB23_ERR                             = 57  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DIB45_ERR                             = 58  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_SCOM_ERR_DUP                          = 62  ;
static const uint8_t P9N2_PU_PB_IOE_FIR_REG_SCOM_ERR                              = 63  ;

static const uint8_t P9N2_PU_PB_IOE_FIR_WOF_REG_WOF                               = 0   ;
static const uint8_t P9N2_PU_PB_IOE_FIR_WOF_REG_WOF_LEN                           = 64  ;

static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0                   = 0   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0_LEN               = 64  ;

static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1                   = 0   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1_LEN               = 64  ;

static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR00_TRAINED                = 0   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR01_TRAINED                = 1   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR02_TRAINED                = 2   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR03_TRAINED                = 3   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR04_TRAINED                = 4   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR05_TRAINED                = 5   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR06_TRAINED                = 6   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR07_TRAINED                = 7   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_UE                     = 8   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_CE                     = 9   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_SUE                    = 10  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_UE                     = 11  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_CE                     = 12  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_SUE                    = 13  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_UE                     = 14  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_CE                     = 15  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_SUE                    = 16  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_UE                     = 17  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_CE                     = 18  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_SUE                    = 19  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER00_ATTN                = 20  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER01_ATTN                = 21  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER02_ATTN                = 22  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER03_ATTN                = 23  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER04_ATTN                = 24  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER05_ATTN                = 25  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER06_ATTN                = 26  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER07_ATTN                = 27  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER00_ATTN                = 28  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER01_ATTN                = 29  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER02_ATTN                = 30  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER03_ATTN                = 31  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER04_ATTN                = 32  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER05_ATTN                = 33  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER06_ATTN                = 34  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER07_ATTN                = 35  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB00_SPATTN                  = 36  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB01_SPATTN                  = 37  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB10_SPATTN                  = 38  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB11_SPATTN                  = 39  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB20_SPATTN                  = 40  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB21_SPATTN                  = 41  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB30_SPATTN                  = 42  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB31_SPATTN                  = 43  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB40_SPATTN                  = 44  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB41_SPATTN                  = 45  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB50_SPATTN                  = 46  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB51_SPATTN                  = 47  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB60_SPATTN                  = 48  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB61_SPATTN                  = 49  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB70_SPATTN                  = 50  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB71_SPATTN                  = 51  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_ERR                    = 52  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_ERR                    = 53  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_ERR                    = 54  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_ERR                    = 55  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB01_ERR                    = 56  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB23_ERR                    = 57  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB45_ERR                    = 58  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB67_ERR                    = 59  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR_DUP                 = 62  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR                     = 63  ;

static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR00_TRAINED                     = 0   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR01_TRAINED                     = 1   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR02_TRAINED                     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR03_TRAINED                     = 3   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR04_TRAINED                     = 4   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR05_TRAINED                     = 5   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR06_TRAINED                     = 6   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR07_TRAINED                     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_UE                          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_CE                          = 9   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_SUE                         = 10  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_UE                          = 11  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_CE                          = 12  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_SUE                         = 13  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_UE                          = 14  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_CE                          = 15  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_SUE                         = 16  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_UE                          = 17  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_CE                          = 18  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_SUE                         = 19  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER00_ATTN                     = 20  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER01_ATTN                     = 21  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER02_ATTN                     = 22  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER03_ATTN                     = 23  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER04_ATTN                     = 24  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER05_ATTN                     = 25  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER06_ATTN                     = 26  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER07_ATTN                     = 27  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER00_ATTN                     = 28  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER01_ATTN                     = 29  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER02_ATTN                     = 30  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER03_ATTN                     = 31  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER04_ATTN                     = 32  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER05_ATTN                     = 33  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER06_ATTN                     = 34  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER07_ATTN                     = 35  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB00_SPATTN                       = 36  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB01_SPATTN                       = 37  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB10_SPATTN                       = 38  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB11_SPATTN                       = 39  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB20_SPATTN                       = 40  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB21_SPATTN                       = 41  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB30_SPATTN                       = 42  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB31_SPATTN                       = 43  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB40_SPATTN                       = 44  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB41_SPATTN                       = 45  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB50_SPATTN                       = 46  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB51_SPATTN                       = 47  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB60_SPATTN                       = 48  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB61_SPATTN                       = 49  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB70_SPATTN                       = 50  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB71_SPATTN                       = 51  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_ERR                         = 52  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_ERR                         = 53  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_ERR                         = 54  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_ERR                         = 55  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB01_ERR                         = 56  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB23_ERR                         = 57  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB45_ERR                         = 58  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB67_ERR                         = 59  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_SCOM_ERR_DUP                      = 62  ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_SCOM_ERR                          = 63  ;

static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_WOF_REG_WOF                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_WOF_REG_WOF_LEN                       = 64  ;

static const uint8_t P9N2_PU_PB_MISC_CFG_IOE01_IS_LOGICAL_PAIR                    = 0   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_IOE23_IS_LOGICAL_PAIR                    = 1   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_IOE45_IS_LOGICAL_PAIR                    = 2   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE3                                   = 3   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER                 = 4   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER                 = 5   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER                 = 6   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE7                                   = 7   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE8                                   = 8   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE9                                   = 9   ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE10                                  = 10  ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE11                                  = 11  ;
static const uint8_t P9N2_PU_PB_MISC_CFG_LINK_AVP_MODE                            = 12  ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE13                                  = 13  ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE14                                  = 14  ;
static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE15                                  = 15  ;

static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO01_IS_LOGICAL_PAIR                = 0   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO23_IS_LOGICAL_PAIR                = 1   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO45_IS_LOGICAL_PAIR                = 2   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO67_IS_LOGICAL_PAIR                = 3   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER             = 4   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER             = 5   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER             = 6   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK67_RESET_KEEPER             = 7   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS01_TOD_ENABLE                   = 8   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS23_TOD_ENABLE                   = 9   ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS45_TOD_ENABLE                   = 10  ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS67_TOD_ENABLE                   = 11  ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINK_AVP_MODE                        = 12  ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SEL_03_NPU_NOT                       = 13  ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SEL_04_NPU_NOT                       = 14  ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SEL_05_NPU_NOT                       = 15  ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SPARE                                = 16  ;
static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SPARE_LEN                            = 4   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT         = 1   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT     = 9   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT     = 17  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT     = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN = 5   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT         = 33  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT     = 41  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT     = 49  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN = 7   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT         = 1   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT     = 9   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT     = 17  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT     = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN = 5   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT         = 33  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT     = 41  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT     = 49  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN = 7   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT         = 1   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT     = 9   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT     = 17  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT     = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN = 5   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT         = 33  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT     = 41  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT     = 49  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN = 7   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_LIMIT         = 1   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT     = 9   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT     = 17  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT     = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT_LEN = 5   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_LIMIT         = 33  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_LIMIT_LEN     = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT     = 41  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT_LEN = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT     = 49  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN = 7   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY            = 4   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN        = 12  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY            = 20  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN        = 12  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY            = 36  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN        = 12  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY            = 52  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN        = 12  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY            = 4   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY_LEN        = 12  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY            = 20  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY_LEN        = 12  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY            = 36  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY_LEN        = 12  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY            = 52  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY_LEN        = 12  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER0                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER0_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER1                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER1_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER2                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER2_LEN                       = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER3                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER3_LEN                       = 16  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_ENABLE                 = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_ENABLE                 = 1   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_ENABLE                 = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_ENABLE                 = 3   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU4_ENABLE                 = 4   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU5_ENABLE                 = 5   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU6_ENABLE                 = 6   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU7_ENABLE                 = 7   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_FREEZE_MODE          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_COMMON_FREEZE_MODE          = 9   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_RESET_MODE           = 10  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT0_SEL                  = 11  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL                  = 12  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL_LEN              = 4   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL                  = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL_LEN              = 4   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL                  = 20  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL_LEN              = 4   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE                   = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE_LEN               = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE                   = 26  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE_LEN               = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE                   = 28  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE_LEN               = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE                   = 30  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE_LEN               = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU01_LINK_SELECT           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU23_LINK_SELECT           = 33  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU45_LINK_SELECT           = 34  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU67_LINK_SELECT           = 35  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE         = 36  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE         = 38  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE         = 40  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE         = 42  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE         = 44  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE         = 46  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE         = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE         = 50  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN     = 2   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN           = 52  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_GLOBAL_RUN_MODE             = 53  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE                       = 54  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE_LEN                   = 10  ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET                    = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET_LEN                = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT                   = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN               = 8   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0              = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1              = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2              = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3              = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0              = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1              = 40  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2              = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3              = 56  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN          = 8   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0              = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1              = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2              = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3              = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0              = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1              = 40  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2              = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3              = 56  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN          = 8   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0              = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1              = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2              = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3              = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0              = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1              = 40  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2              = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3              = 56  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN          = 8   ;

static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0              = 0   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1              = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2              = 16  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3              = 24  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0              = 32  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1              = 40  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2              = 48  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2_LEN          = 8   ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3              = 56  ;
static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3_LEN          = 8   ;

static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE            = 1   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE                = 2   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_PTSPARE6                        = 3   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_ENABLE                       = 4   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE            = 5   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE                = 6   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_PTSPARE7                        = 7   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_SELECT                       = 8   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN                   = 4   ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_SELECT                       = 12  ;
static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN                   = 4   ;

static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE        = 1   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE            = 2   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE6                    = 3   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_ENABLE                   = 4   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE        = 5   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE            = 6   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE7                    = 7   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT                   = 8   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN               = 4   ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT                   = 12  ;
static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN               = 4   ;

static const uint8_t P9N2_PU_PB_PPE_LFIR_INTERNAL_ERROR                           = 0   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_EXTERNAL_ERROR                           = 1   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_PROGRESS_ERROR                           = 2   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_BREAKPOINT_ERROR                         = 3   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_WATCHDOG                                 = 4   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_HALTED                                   = 5   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_DEBUG_TRIGGER                            = 6   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_SRAM_UE                                  = 7   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_SRAM_CE                                  = 8   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_SRAM_SCRUB_ERR                           = 9   ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_BCE_ERROR                                = 10  ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_SPARE11                                  = 11  ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_FIR_PARITY_ERR_DUP                       = 12  ;
static const uint8_t P9N2_PU_PB_PPE_LFIR_FIR_PARITY_ERR                           = 13  ;

static const uint8_t P9N2_PU_PB_PPE_LFIRACT0_FIR_ACTION0                          = 0   ;
static const uint8_t P9N2_PU_PB_PPE_LFIRACT0_FIR_ACTION0_LEN                      = 14  ;

static const uint8_t P9N2_PU_PB_PPE_LFIRACT1_FIR_ACTION1                          = 0   ;
static const uint8_t P9N2_PU_PB_PPE_LFIRACT1_FIR_ACTION1_LEN                      = 14  ;

static const uint8_t P9N2_PU_PB_PPE_LFIRMASK_FIR_MASK                             = 0   ;
static const uint8_t P9N2_PU_PB_PPE_LFIRMASK_FIR_MASK_LEN                         = 14  ;

static const uint8_t P9N2_PU_PB_PPE_LFIRWOF_LFIR_WOF                              = 0   ;
static const uint8_t P9N2_PU_PB_PPE_LFIRWOF_LFIR_WOF_LEN                          = 14  ;

static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_ADDRESS_PTY                       = 0   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_ATAG_PTY                          = 1   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC0_CREDITERR                     = 2   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC1_CREDITERR                     = 3   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC2_CREDITERR                     = 4   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC3_CREDITERR                     = 5   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CONTROL_ERROR                     = 6   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_PR0_CREDITERR                     = 7   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_PR1_CREDITERR                     = 8   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_RTAG_PTY                          = 9   ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_TTAG_PTY                          = 10  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_VC0_CREDITERR                     = 11  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_VC1_CREDITERR                     = 12  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_ADDRESS_PTY                       = 16  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_ATAG_PTY                          = 17  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC0_CREDITERR                     = 18  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC1_CREDITERR                     = 19  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC2_CREDITERR                     = 20  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC3_CREDITERR                     = 21  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CONTROL_ERROR                     = 22  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_PR0_CREDITERR                     = 23  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_PR1_CREDITERR                     = 24  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_RTAG_PTY                          = 25  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_TTAG_PTY                          = 26  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_VC0_CREDITERR                     = 27  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_VC1_CREDITERR                     = 28  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_ADDRESS_PTY                       = 32  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_ATAG_PTY                          = 33  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC0_CREDITERR                     = 34  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC1_CREDITERR                     = 35  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC2_CREDITERR                     = 36  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC3_CREDITERR                     = 37  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CONTROL_ERROR                     = 38  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_PR0_CREDITERR                     = 39  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_PR1_CREDITERR                     = 40  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_RTAG_PTY                          = 41  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_TTAG_PTY                          = 42  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_VC0_CREDITERR                     = 43  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_VC1_CREDITERR                     = 44  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_ADDRESS_PTY                       = 48  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_ATAG_PTY                          = 49  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC0_CREDITERR                     = 50  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC1_CREDITERR                     = 51  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC2_CREDITERR                     = 52  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC3_CREDITERR                     = 53  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CONTROL_ERROR                     = 54  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_PR0_CREDITERR                     = 55  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_PR1_CREDITERR                     = 56  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_RTAG_PTY                          = 57  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_TTAG_PTY                          = 58  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_VC0_CREDITERR                     = 59  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_VC1_CREDITERR                     = 60  ;
static const uint8_t P9N2_PU_PB_PR0123_ERR_LINK_DOWNQ_E_HOLD                      = 61  ;

static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_ADDRESS_PTY                   = 0   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_ATAG_PTY                      = 1   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC0_CREDITERR                 = 2   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC1_CREDITERR                 = 3   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC2_CREDITERR                 = 4   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC3_CREDITERR                 = 5   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CONTROL_ERROR                 = 6   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_PR0_CREDITERR                 = 7   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_PR1_CREDITERR                 = 8   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_RTAG_PTY                      = 9   ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_TTAG_PTY                      = 10  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_VC0_CREDITERR                 = 11  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_VC1_CREDITERR                 = 12  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_ADDRESS_PTY                   = 16  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_ATAG_PTY                      = 17  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC0_CREDITERR                 = 18  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC1_CREDITERR                 = 19  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC2_CREDITERR                 = 20  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC3_CREDITERR                 = 21  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CONTROL_ERROR                 = 22  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_PR0_CREDITERR                 = 23  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_PR1_CREDITERR                 = 24  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_RTAG_PTY                      = 25  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_TTAG_PTY                      = 26  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_VC0_CREDITERR                 = 27  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_VC1_CREDITERR                 = 28  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_ADDRESS_PTY                   = 32  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_ATAG_PTY                      = 33  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC0_CREDITERR                 = 34  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC1_CREDITERR                 = 35  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC2_CREDITERR                 = 36  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC3_CREDITERR                 = 37  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CONTROL_ERROR                 = 38  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_PR0_CREDITERR                 = 39  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_PR1_CREDITERR                 = 40  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_RTAG_PTY                      = 41  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_TTAG_PTY                      = 42  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_VC0_CREDITERR                 = 43  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_VC1_CREDITERR                 = 44  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_ADDRESS_PTY                   = 48  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_ATAG_PTY                      = 49  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC0_CREDITERR                 = 50  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC1_CREDITERR                 = 51  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC2_CREDITERR                 = 52  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC3_CREDITERR                 = 53  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CONTROL_ERROR                 = 54  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_PR0_CREDITERR                 = 55  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_PR1_CREDITERR                 = 56  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_RTAG_PTY                      = 57  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_TTAG_PTY                      = 58  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_VC0_CREDITERR                 = 59  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_VC1_CREDITERR                 = 60  ;
static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_LINK_DOWNQ_E_HOLD                  = 61  ;

static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_ADDRESS_PTY                   = 0   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_ATAG_PTY                      = 1   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC0_CREDITERR                 = 2   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC1_CREDITERR                 = 3   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC2_CREDITERR                 = 4   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC3_CREDITERR                 = 5   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CONTROL_ERROR                 = 6   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_PR0_CREDITERR                 = 7   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_PR1_CREDITERR                 = 8   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_RTAG_PTY                      = 9   ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_TTAG_PTY                      = 10  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_VC0_CREDITERR                 = 11  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_VC1_CREDITERR                 = 12  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_ADDRESS_PTY                   = 16  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_ATAG_PTY                      = 17  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC0_CREDITERR                 = 18  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC1_CREDITERR                 = 19  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC2_CREDITERR                 = 20  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC3_CREDITERR                 = 21  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CONTROL_ERROR                 = 22  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_PR0_CREDITERR                 = 23  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_PR1_CREDITERR                 = 24  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_RTAG_PTY                      = 25  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_TTAG_PTY                      = 26  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_VC0_CREDITERR                 = 27  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_VC1_CREDITERR                 = 28  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_ADDRESS_PTY                   = 32  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_ATAG_PTY                      = 33  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC0_CREDITERR                 = 34  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC1_CREDITERR                 = 35  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC2_CREDITERR                 = 36  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC3_CREDITERR                 = 37  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CONTROL_ERROR                 = 38  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_PR0_CREDITERR                 = 39  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_PR1_CREDITERR                 = 40  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_RTAG_PTY                      = 41  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_TTAG_PTY                      = 42  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_VC0_CREDITERR                 = 43  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_VC1_CREDITERR                 = 44  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_ADDRESS_PTY                   = 48  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_ATAG_PTY                      = 49  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC0_CREDITERR                 = 50  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC1_CREDITERR                 = 51  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC2_CREDITERR                 = 52  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC3_CREDITERR                 = 53  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CONTROL_ERROR                 = 54  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_PR0_CREDITERR                 = 55  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_PR1_CREDITERR                 = 56  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_RTAG_PTY                      = 57  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_TTAG_PTY                      = 58  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_VC0_CREDITERR                 = 59  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_VC1_CREDITERR                 = 60  ;
static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_LINK_DOWNQ_E_HOLD                  = 61  ;

static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_ADDRESS_PTY                         = 0   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_ATAG_PTY                            = 1   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC0_CREDITERR                       = 2   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC1_CREDITERR                       = 3   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC2_CREDITERR                       = 4   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC3_CREDITERR                       = 5   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CONTROL_ERROR                       = 6   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_PR0_CREDITERR                       = 7   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_PR1_CREDITERR                       = 8   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_RTAG_PTY                            = 9   ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_TTAG_PTY                            = 10  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_VC0_CREDITERR                       = 11  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_VC1_CREDITERR                       = 12  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_ADDRESS_PTY                         = 16  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_ATAG_PTY                            = 17  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC0_CREDITERR                       = 18  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC1_CREDITERR                       = 19  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC2_CREDITERR                       = 20  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC3_CREDITERR                       = 21  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CONTROL_ERROR                       = 22  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_PR0_CREDITERR                       = 23  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_PR1_CREDITERR                       = 24  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_RTAG_PTY                            = 25  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_TTAG_PTY                            = 26  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_VC0_CREDITERR                       = 27  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_VC1_CREDITERR                       = 28  ;
static const uint8_t P9N2_PU_PB_PR45_ERR_LINK_DOWNQ_E_HOLD                        = 29  ;

static const uint8_t P9N2_PU_PB_PSAVE_CFG_ENABLE                                  = 0   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_X0_ACT                                  = 1   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_X1_ACT                                  = 2   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_X2_ACT                                  = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_PS_SPARE1                               = 4   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_WSIZE                                   = 5   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_WSIZE_LEN                               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUC                                     = 8   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUC_LEN                                 = 8   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUC                                     = 16  ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUC_LEN                                 = 8   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUT                                     = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUT_LEN                                 = 5   ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUT                                     = 35  ;
static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUT_LEN                                 = 5   ;

static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_LO                               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_LO_LEN                           = 5   ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_HI                               = 11  ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_HI_LEN                           = 5   ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_LO                               = 19  ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_LO_LEN                           = 5   ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_HI                               = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_HI_LEN                           = 5   ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_LO                               = 35  ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_LO_LEN                           = 5   ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_HI                               = 43  ;
static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_HI_LEN                           = 5   ;

static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00                   = 0   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01                   = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02                   = 6   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03                   = 9   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04                   = 12  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05                   = 15  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06                   = 18  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07                   = 21  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08                   = 24  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09                   = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10                   = 30  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11                   = 33  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12                   = 36  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13                   = 39  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14                   = 42  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15                   = 45  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_X0_WIN_ID                        = 56  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_X0_WIN_ID_LEN                    = 8   ;

static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00                   = 0   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01                   = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02                   = 6   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03                   = 9   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04                   = 12  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05                   = 15  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06                   = 18  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07                   = 21  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08                   = 24  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09                   = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10                   = 30  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11                   = 33  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12                   = 36  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13                   = 39  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14                   = 42  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15                   = 45  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_X0_WIN_ID                        = 56  ;
static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_X0_WIN_ID_LEN                    = 8   ;

static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00                   = 0   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01                   = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02                   = 6   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03                   = 9   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04                   = 12  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05                   = 15  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06                   = 18  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07                   = 21  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08                   = 24  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09                   = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10                   = 30  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11                   = 33  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12                   = 36  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13                   = 39  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14                   = 42  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15                   = 45  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_X1_WIN_ID                        = 56  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_X1_WIN_ID_LEN                    = 8   ;

static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00                   = 0   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01                   = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02                   = 6   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03                   = 9   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04                   = 12  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05                   = 15  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06                   = 18  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07                   = 21  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08                   = 24  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09                   = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10                   = 30  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11                   = 33  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12                   = 36  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13                   = 39  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14                   = 42  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15                   = 45  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_X1_WIN_ID                        = 56  ;
static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_X1_WIN_ID_LEN                    = 8   ;

static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00                   = 0   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01                   = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02                   = 6   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03                   = 9   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04                   = 12  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05                   = 15  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06                   = 18  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07                   = 21  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08                   = 24  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09                   = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10                   = 30  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11                   = 33  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12                   = 36  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13                   = 39  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14                   = 42  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15                   = 45  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_X2_WIN_ID                        = 56  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_X2_WIN_ID_LEN                    = 8   ;

static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00                   = 0   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01                   = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02                   = 6   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03                   = 9   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04                   = 12  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05                   = 15  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06                   = 18  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07                   = 21  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08                   = 24  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09                   = 27  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10                   = 30  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11                   = 33  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12                   = 36  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13                   = 39  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14                   = 42  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15                   = 45  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15_LEN               = 3   ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_X2_WIN_ID                        = 56  ;
static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_X2_WIN_ID_LEN                    = 8   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_LOW_RTY_THRESHOLD_NEXT = 14  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_LOW_RTY_THRESHOLD_NEXT_LEN = 10  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_HIGH_RTY_THRESHOLD_NEXT = 24  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_HIGH_RTY_THRESHOLD_NEXT_LEN = 10  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_LOW_RTY_THRESHOLD_NEXT = 34  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_LOW_RTY_THRESHOLD_NEXT_LEN = 10  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_HIGH_RTY_THRESHOLD_NEXT = 44  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_HIGH_RTY_THRESHOLD_NEXT_LEN = 10  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_SP_LOW_RTY_THRESHOLD_NEXT = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_SP_LOW_RTY_THRESHOLD_NEXT_LEN = 10  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_HIGH_RTY_THRESHOLD_NEXT = 18  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_HIGH_RTY_THRESHOLD_NEXT_LEN = 10  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_GP_CRESP_SAMPLE_TIME_NEXT = 28  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_GP_CRESP_SAMPLE_TIME_NEXT_LEN = 12  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_RGP_CRESP_SAMPLE_TIME_NEXT = 40  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_RGP_CRESP_SAMPLE_TIME_NEXT_LEN = 12  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_CRESP_SAMPLE_TIME_NEXT = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_CRESP_SAMPLE_TIME_NEXT_LEN = 12  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_REQ_SAMPLE_TIME_NEXT = 22  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_REQ_SAMPLE_TIME_NEXT_LEN = 12  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_REQ_SAMPLE_TIME_NEXT = 34  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_REQ_SAMPLE_TIME_NEXT_LEN = 12  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_LOW_JUMP_NEXT  = 46  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_LOW_JUMP_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_HIGH_JUMP_NEXT = 49  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_HIGH_JUMP_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_LOW_JUMP_NEXT  = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_LOW_JUMP_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_HIGH_JUMP_NEXT = 55  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_HIGH_JUMP_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_LOW_JUMP_NEXT = 58  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_LOW_JUMP_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_HIGH_JUMP_NEXT = 61  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_HIGH_JUMP_NEXT_LEN = 3   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG0_CMD_RATE_NEXT        = 28  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG0_CMD_RATE_NEXT_LEN    = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG1_CMD_RATE_NEXT        = 33  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG1_CMD_RATE_NEXT_LEN    = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG2_CMD_RATE_NEXT        = 38  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG2_CMD_RATE_NEXT_LEN    = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG3_CMD_RATE_NEXT        = 43  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG3_CMD_RATE_NEXT_LEN    = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG4_CMD_RATE_NEXT        = 48  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG4_CMD_RATE_NEXT_LEN    = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG5_CMD_RATE_NEXT        = 53  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG5_CMD_RATE_NEXT_LEN    = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG6_CMD_RATE_NEXT        = 58  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG6_CMD_RATE_NEXT_LEN    = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_USE_SLOW_GO_RATE_NEXT      = 63  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_JUMP_LEVEL_NEXT        = 49  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_JUMP_LEVEL_NEXT_LEN    = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_RTY_LEVEL_NEXT         = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_RTY_LEVEL_NEXT_LEN     = 6   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_P7_SLEEP_BACKOFF_NEXT      = 58  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_P7_SLEEP_BACKOFF_NEXT_LEN  = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_RTY_PERCENTAGE_NEXT        = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_RTY_PERCENTAGE_NEXT_LEN    = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_INCLUDE_LPC_RTY_NEXT       = 63  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL0_CHGRATE_CLK_DIV_NEXT = 16  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL0_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL1_CHGRATE_CLK_DIV_NEXT = 19  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL1_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL2_CHGRATE_CLK_DIV_NEXT = 22  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL2_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL3_CHGRATE_CLK_DIV_NEXT = 25  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL3_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL4_CHGRATE_CLK_DIV_NEXT = 28  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL4_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL5_CHGRATE_CLK_DIV_NEXT = 31  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL5_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL6_CHGRATE_CLK_DIV_NEXT = 34  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL6_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL7_CHGRATE_CLK_DIV_NEXT = 37  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL7_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL0_CHGRATE_CLK_DIV_NEXT = 40  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL0_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL1_CHGRATE_CLK_DIV_NEXT = 43  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL1_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL2_CHGRATE_CLK_DIV_NEXT = 46  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL2_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL3_CHGRATE_CLK_DIV_NEXT = 49  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL3_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL4_CHGRATE_CLK_DIV_NEXT = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL4_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL5_CHGRATE_CLK_DIV_NEXT = 55  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL5_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL6_CHGRATE_CLK_DIV_NEXT = 58  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL6_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL7_CHGRATE_CLK_DIV_NEXT = 61  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL7_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL0_CHGRATE_CLK_DIV_NEXT = 32  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL0_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL1_CHGRATE_CLK_DIV_NEXT = 35  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL1_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL2_CHGRATE_CLK_DIV_NEXT = 38  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL2_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL3_CHGRATE_CLK_DIV_NEXT = 41  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL3_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL4_CHGRATE_CLK_DIV_NEXT = 44  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL4_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL5_CHGRATE_CLK_DIV_NEXT = 47  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL5_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL6_CHGRATE_CLK_DIV_NEXT = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL6_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL7_CHGRATE_CLK_DIV_NEXT = 53  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL7_CHGRATE_CLK_DIV_NEXT_LEN = 3   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_ONE_HOP_STARVE_LIMIT_0_NEXT = 20  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_ONE_HOP_STARVE_LIMIT_0_NEXT_LEN = 8   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP0_0_NEXT     = 28  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP0_0_NEXT_LEN = 8   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP1_0_NEXT     = 36  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP1_0_NEXT_LEN = 8   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_SINGLE_LINK_CREDIT_NEXT    = 44  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_XX_HOP_RANDOM_TOK_DISABLE_NEXT = 45  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_UX_ARB_RANDOM_TOK_DISABLE_NEXT = 46  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_WEST_FAIRNESS_DISABLE_NEXT = 47  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_WEST_FORCED_WEIGHT_EN_NEXT = 48  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_WEST_FORCED_WEIGHT_0_NEXT  = 49  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_WEST_FORCED_WEIGHT_0_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_FORCED_WEIGHT_EN_NEXT = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_FORCED_WEIGHT_0_NEXT  = 53  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_FORCED_WEIGHT_0_NEXT_LEN = 3   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_WEST_WEIGHT_ADDER_0_NEXT = 41  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_WEST_WEIGHT_ADDER_0_NEXT_LEN = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_EAST_WEIGHT_ADDER_0_NEXT = 43  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_EAST_WEIGHT_ADDER_0_NEXT_LEN = 2   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_9_SPARE                          = 32  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_9_SPARE_LEN                      = 32  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_NXTP_TOKEN_INIT            = 38  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_NXTP_TOKEN_INIT_LEN        = 4   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_LINK_TOK_AGG_THRESHOLD_NEXT = 42  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_LINK_TOK_AGG_THRESHOLD_NEXT_LEN = 4   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_ON_TOK_SEL_NEXT            = 46  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_ON_TOK_SEL_NEXT_LEN        = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_LOAD_TOKEN_INIT_NEXT       = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_OFF_TOK_SEL_NEXT           = 51  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_OFF_TOK_SEL_NEXT_LEN       = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_ON_TOK_SEL_NEXT         = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_ON_TOK_SEL_NEXT_LEN     = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_OFF_TOK_SEL_NEXT        = 57  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_OFF_TOK_SEL_NEXT_LEN    = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_REMOTE_HOLD_CNT_NEXT       = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_REMOTE_HOLD_CNT_NEXT_LEN   = 4   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_EX_TOKEN_INIT_NEXT         = 51  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_EX_TOKEN_INIT_NEXT_LEN     = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_VAS_TOKEN_INIT_NEXT        = 58  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_VAS_TOKEN_INIT_NEXT_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_REMOTE_HOLD_CNT_NEXT       = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_REMOTE_HOLD_CNT_NEXT_LEN   = 4   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_MAX_OUTSTANDING         = 36  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_MAX_OUTSTANDING_LEN     = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_FORCE_TRUNK             = 39  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_FORCE_EVEN_TRUNK        = 40  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_STV_CNT                 = 41  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_STV_CNT_LEN             = 8   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_STV_EN                  = 49  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_ANY_TIMEZONE            = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_ENABLE_FP               = 51  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_EX_EN            = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_ENES_EN          = 53  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_BLOCK_LOCAL_REQ         = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_FLAG_EN          = 55  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_BUBBLE_EN               = 56  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_SEQ_EN           = 57  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_CFG_REMOTE_HOLD_CNT_NEXT       = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_CFG_REMOTE_HOLD_CNT_NEXT_LEN   = 4   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_LOCK_ON_LINKS           = 12  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_ON_LINK_TOK_AGG_THRESHOLD = 13  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_ON_LINK_TOK_AGG_THRESHOLD_LEN = 4   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_OFF_LINK_TOK_AGG_THRESHOLD = 17  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_OFF_LINK_TOK_AGG_THRESHOLD_LEN = 4   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_AGG_THRESHOLD = 21  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_AGG_THRESHOLD_LEN = 4   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_ON_TOK_SEL_NEXT          = 25  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_ON_TOK_SEL_NEXT_LEN      = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_OFF_TOK_SEL_NEXT         = 28  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_OFF_TOK_SEL_NEXT_LEN     = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_ON_TOK_SEL_NEXT         = 31  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_ON_TOK_SEL_NEXT_LEN     = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_X_PRIORITY      = 34  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_X_PRIORITY_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_A_PRIORITY      = 42  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_A_PRIORITY_LEN  = 8   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_OFF_TOK_SEL_NEXT         = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_OFF_TOK_SEL_NEXT_LEN     = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_ON_TOK_SEL_NEXT          = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_ON_TOK_SEL_NEXT_LEN      = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_OFF_TOK_SEL_NEXT        = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_OFF_TOK_SEL_NEXT_LEN    = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_IND_THRESHOLD = 57  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_IND_THRESHOLD_LEN = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_LOAD_TOKEN_INIT_NEXT       = 59  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_ON_RING_DIS_NEXT         = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_FORCE_STV_PRIORITY      = 61  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_FORCE_HP_MEM_PRIORITY   = 62  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_ENABLE          = 63  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_BYPASS_HP_ENABLE        = 55  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_REMOTE_C_DELAY_FORCE    = 56  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_MAX_OUTSTANDING         = 57  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_MAX_OUTSTANDING_LEN     = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_GATHER_EN               = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_SPARE_MODE              = 61  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_ARBMODE_NEXT = 45  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_ARBMODE_NEXT_LEN = 4   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_VCINIT_NEXT = 49  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_VCINIT_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DOFF_ARBMODE_NEXT = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DOFF_ARBMODE_NEXT_LEN = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_VCINIT_NEXT = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_VCINIT_NEXT_LEN = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_ARBMODE_NEXT = 57  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_ARBMODE_NEXT_LEN = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DON_ARBMODE_NEXT = 59  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DON_ARBMODE_NEXT_LEN = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_VA_DOFF_VCINIT_NEXT = 61  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_VA_DOFF_VCINIT_NEXT_LEN = 3   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_LATE_RD_MODE_NEXT          = 15  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DELAY_SP_RD_NEXT           = 16  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DELAY_SP_RD_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_HW070772_DIS_NEXT              = 20  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_NOP_MODE_NEXT              = 21  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_NOP_MODE_NEXT_LEN          = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_FORCE_FA_ALLOCATION_NEXT   = 31  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_INITIAL_REQ_DLY_NEXT       = 34  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_INITIAL_REQ_DLY_NEXT_LEN   = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DCTR_LAUNCH_NEXT           = 37  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DCTR_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_OUTSTANDING_REQ_COUNT_NEXT = 39  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_REQ_ID_ASSIGNMENT_MODE_NEXT = 40  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_ALLOW_FRAGMENTATION_NEXT   = 41  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DREQ_ID_NEXT               = 42  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DVAL_LAUNCH_NEXT           = 48  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DVAL_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_HSHAKE_NEXT                = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DONE_LAUNCH_NEXT           = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_SPARE_MODE_NEXT            = 53  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_EARLY_REQ_MODE_NEXT        = 28  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_HSHAKE_NEXT                = 33  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_SPARE_MODE_NEXT            = 38  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DCTR_LAUNCH_NEXT           = 41  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DCTR_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_DAT_I2C_SPARE_MODE_NEXT = 43  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DREQ_LAUNCH_NEXT           = 46  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DREQ_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_DAT_C2I_SPARE_MODE_NEXT = 48  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_L3_NOT_USE_DCBFL_NEXT      = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_PTY_INJECT_NEXT            = 53  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_RCMD_SPARE_MODE_NEXT    = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DONE_LAUNCH_NEXT           = 55  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_PTY_RD_CAPTURE_NEXT        = 57  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_PTY_RD_CAPTURE_NEXT_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_FP_I2CRCTL_SPARE_MODE_NEXT = 59  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DVAL_LAUNCH_NEXT           = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DVAL_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_FP_C2ISCTL_HSHAKE_NEXT  = 62  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_FP_C2ISCTL_SPARE_MODE_NEXT = 63  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EXPIRATION_TIME_NEXT = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EXPIRATION_TIME_NEXT_LEN = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT = 59  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT_LEN = 5   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EXPIRATION_TIME_NEXT = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EXPIRATION_TIME_NEXT_LEN = 5   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT = 59  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT_LEN = 5   ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_LATE_RD_MODE_NEXT          = 15  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DELAY_SP_RD_NEXT           = 16  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DELAY_SP_RD_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_HW070772_DIS_NEXT              = 20  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_NOP_MODE_NEXT              = 21  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_NOP_MODE_NEXT_LEN          = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_FORCE_FA_ALLOCATION_NEXT   = 31  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_INITIAL_REQ_DLY_NEXT       = 34  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_INITIAL_REQ_DLY_NEXT_LEN   = 3   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DCTR_LAUNCH_NEXT           = 37  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DCTR_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_OUTSTANDING_REQ_COUNT_NEXT = 39  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_REQ_ID_ASSIGNMENT_MODE_NEXT = 40  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_ALLOW_FRAGMENTATION_NEXT   = 41  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DREQ_ID_NEXT               = 42  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DVAL_LAUNCH_NEXT           = 48  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DVAL_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_HSHAKE_NEXT                = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DONE_LAUNCH_NEXT           = 52  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_SPARE_MODE_NEXT            = 53  ;

static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_EARLY_REQ_MODE_NEXT        = 28  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_HSHAKE_NEXT                = 33  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_SPARE_MODE_NEXT            = 38  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DCTR_LAUNCH_NEXT           = 41  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DCTR_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_DAT_I2C_SPARE_MODE_NEXT = 43  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DREQ_LAUNCH_NEXT           = 46  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DREQ_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_DAT_C2I_SPARE_MODE_NEXT = 48  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_L3_NOT_USE_DCBFL_NEXT      = 50  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_PTY_INJECT_NEXT            = 53  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_RCMD_SPARE_MODE_NEXT    = 54  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DONE_LAUNCH_NEXT           = 55  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_PTY_RD_CAPTURE_NEXT        = 57  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_PTY_RD_CAPTURE_NEXT_LEN    = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_FP_I2CRCTL_SPARE_MODE_NEXT = 59  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DVAL_LAUNCH_NEXT           = 60  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DVAL_LAUNCH_NEXT_LEN       = 2   ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_FP_C2ISCTL_HSHAKE_NEXT  = 62  ;
static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_FP_C2ISCTL_SPARE_MODE_NEXT = 63  ;

static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_HI                               = 0   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_HI_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_LO                               = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_LO_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_HI                               = 8   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_HI_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_LO                               = 12  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_LO_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_HI                               = 16  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_HI_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_LO                               = 20  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_LO_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_HI                               = 24  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_HI_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_LO                               = 28  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_LO_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_HI                               = 32  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_HI_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_LO                               = 36  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_LO_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_HI                               = 40  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_HI_LEN                           = 4   ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_LO                               = 44  ;
static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_LO_LEN                           = 4   ;

static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_HI                           = 0   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_LO                           = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_LO_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_HI                           = 8   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_LO                           = 12  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_LO_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_HI                           = 16  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_LO                           = 20  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_LO_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_HI                           = 24  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_LO                           = 28  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_LO_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_HI                           = 32  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_LO                           = 36  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_LO_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_HI                           = 40  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_LO                           = 44  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_LO_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_HI                           = 48  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_LO                           = 52  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_LO_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_HI                           = 56  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_HI_LEN                       = 4   ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_LO                           = 60  ;
static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_LO_LEN                       = 4   ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0          = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0_LEN      = 34  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1          = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1_LEN      = 34  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW1_ERROR = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW2_ERROR = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_PROTOCOL_ERROR = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_OVERFLOW_ERROR = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW1_ERROR = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW2_ERROR = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_PROTOCOL_ERROR = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_OVERFLOW_ERROR = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW1_ERROR = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW2_ERROR = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_PROTOCOL_ERROR = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_OVERFLOW_ERROR = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW1_ERROR = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW2_ERROR = 13  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_PROTOCOL_ERROR = 14  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_OVERFLOW_ERROR = 15  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_16            = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_17            = 17  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_18            = 18  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_19            = 19  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_20            = 20  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_21            = 21  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_22            = 22  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_23            = 23  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_24            = 24  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_25            = 25  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_26            = 26  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_27            = 27  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_28            = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_29            = 29  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_30            = 30  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_31            = 31  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR            = 32  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR_DUP        = 33  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW1_ERROR    = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW2_ERROR    = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_PROTOCOL_ERROR = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_OVERFLOW_ERROR = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW1_ERROR    = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW2_ERROR    = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_PROTOCOL_ERROR = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_OVERFLOW_ERROR = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW1_ERROR    = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW2_ERROR    = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_PROTOCOL_ERROR = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_OVERFLOW_ERROR = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW1_ERROR    = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW2_ERROR    = 13  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_PROTOCOL_ERROR = 14  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_OVERFLOW_ERROR = 15  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_16                 = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_17                 = 17  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_18                 = 18  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_19                 = 19  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_20                 = 20  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_21                 = 21  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_22                 = 22  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_23                 = 23  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_24                 = 24  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_25                 = 25  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_26                 = 26  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_27                 = 27  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_28                 = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_29                 = 29  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_30                 = 30  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_31                 = 31  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR                 = 32  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP             = 33  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0  = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0_LEN = 64  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1  = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1_LEN = 64  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_EN = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_EN = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_EN = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_EN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_EN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_EN = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_EN = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_EN = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_EN = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_EN = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_EN = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_EN = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID = 32  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID = 36  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID = 40  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID = 44  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID = 48  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID = 52  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID = 56  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID = 60  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN = 4   ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_EN = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_EN = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_EN = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_EN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_EN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_EN = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_EN = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_EN = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_EN = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_EN = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_EN = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_EN = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID = 32  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID = 36  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID = 40  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID = 44  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID = 48  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID = 52  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID = 56  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID = 60  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN = 4   ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_EN     = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_EN     = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_EN     = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_EN     = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_EN     = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_EN     = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_EN     = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS = 13  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS = 14  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID = 19  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID = 22  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID = 25  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID = 31  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID = 34  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_AGGREGATE    = 37  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_FP_DISABLED  = 48  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_INDIRECT_EN  = 49  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE     = 56  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN = 8   ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_EN     = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_EN     = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_EN     = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_EN     = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_EN     = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_EN     = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_EN     = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS = 13  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS = 14  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID = 19  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID = 22  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID = 25  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID = 31  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID = 34  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_AGGREGATE    = 37  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_FP_DISABLED  = 48  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN  = 49  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE     = 56  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN = 8   ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_MASTER_CHIP     = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_TM_MASTER       = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_EN      = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_EN      = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_EN      = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_EN      = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_AGGREGATE     = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_HOP             = 29  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_SMP_OPTICS      = 30  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_CAPI_MODE = 31  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0            = 32  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1            = 34  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2            = 36  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3            = 38  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID = 40  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_SPARE01 = 47  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_SPARE01_LEN = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_A_INDIRECT_EN = 49  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_SPARE2  = 51  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PHYP_IS_GROUP   = 52  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_ADDR_BAR        = 53  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PUMP            = 54  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_DCACHE_CAPP     = 55  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE      = 56  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN  = 8   ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_MASTER_CHIP     = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_TM_MASTER       = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER = 3   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_EN      = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_EN      = 5   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_EN      = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_EN      = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS = 10  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS = 11  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID = 20  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID = 24  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_AGGREGATE     = 28  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_HOP             = 29  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_SMP_OPTICS      = 30  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CAPI            = 31  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0            = 32  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1            = 34  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2            = 36  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3            = 38  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3_LEN        = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID = 40  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_SPARE01 = 47  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_SPARE01_LEN = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_A_INDIRECT_EN = 49  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE = 50  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_SPARE2  = 51  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP   = 52  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_ADDR_BAR        = 53  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PUMP            = 54  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_DCACHE_CAPP     = 55  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE      = 56  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN  = 8   ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_WEST_PBIXXX_INIT         = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_IS_SYSTEM          = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_HNG_CHK_DISABLE         = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_DBG_CLR_MAX_HANG_STAGE      = 9   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT              = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT_LEN          = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK              = 16  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK_LEN          = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK              = 23  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK_LEN          = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK             = 30  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK_LEN         = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE = 36  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE_LEN = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK = 42  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN = 7   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_PPE_SERIAL_CONTROL      = 56  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_REQ_GATHER_ENABLE       = 57  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_CD_PULSE         = 58  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_OPTION_AB        = 59  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SERIAL_READ_ENABLE      = 60  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SERIAL_READ_SEL         = 61  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SERIAL_READ_SEL_LEN     = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_RESET_ERROR_CAPTURE = 63  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG                 = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SLOW            = 1   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT     = 2   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN = 6   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT          = 8   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT_LEN      = 4   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA      = 12  ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN  = 52  ;

static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE              = 0   ;
static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE_LEN          = 64  ;

static const uint8_t P9N2_PEC_PCB_OPCG_GO_OPCGGO                                  = 0   ;

static const uint8_t P9N2_PEC_PCB_OPCG_STOP_OPCGSTOP                              = 0   ;

static const uint8_t P9N2_PEC_PCS_M1_CONTROL_REG_CONTROL                          = 48  ;
static const uint8_t P9N2_PEC_PCS_M1_CONTROL_REG_CONTROL_LEN                      = 16  ;

static const uint8_t P9N2_PEC_PCS_M2_CONTROL_REG_CONTROL                          = 48  ;
static const uint8_t P9N2_PEC_PCS_M2_CONTROL_REG_CONTROL_LEN                      = 16  ;

static const uint8_t P9N2_PEC_PCS_M3_CONTROL_REG_CONTROL                          = 48  ;
static const uint8_t P9N2_PEC_PCS_M3_CONTROL_REG_CONTROL_LEN                      = 16  ;

static const uint8_t P9N2_PEC_PCS_M4_CONTROL_REG_CONTROL                          = 48  ;
static const uint8_t P9N2_PEC_PCS_M4_CONTROL_REG_CONTROL_LEN                      = 16  ;

static const uint8_t P9N2_PEC_PCS_SYS_CONTROL_REG_CONTROL                         = 48  ;
static const uint8_t P9N2_PEC_PCS_SYS_CONTROL_REG_CONTROL_LEN                     = 16  ;

static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_EN                          = 0   ;
static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_P8_MODE                     = 1   ;
static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG                 = 12  ;
static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG_LEN             = 4   ;
static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG                     = 16  ;
static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG_LEN                 = 48  ;

static const uint8_t P9N2_PEC_PECAPP_SEC_BAR_PE_CAPP                              = 0   ;
static const uint8_t P9N2_PEC_PECAPP_SEC_BAR_PE_CAPP_LEN                          = 26  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_SIZE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_SIZE_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_MATCH                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_MATCH_LEN               = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_RESERVED1               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_RESERVED1_LEN           = 3   ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_SIZE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_SIZE_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_MATCH                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_MATCH_LEN               = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_RESERVED1               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_RESERVED1_LEN           = 3   ;

static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_SIZE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_SIZE_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_MATCH                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_MATCH_LEN               = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_RESERVED1               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_RESERVED1_LEN           = 3   ;

static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_SIZE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_SIZE_LEN                = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_MATCH                   = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_MATCH_LEN               = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_RESERVED1               = 41  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_RESERVED1_LEN           = 3   ;

static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_SIZE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_SIZE_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_MATCH                      = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_MATCH_LEN                  = 35  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_RESERVED1                  = 41  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_RESERVED1_LEN              = 3   ;

static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_ENABLE                          = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_RESETMODE                       = 1   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_FREEZEMODE                      = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_DISABLE_PMISC                   = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PMISC_MODE                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_CASCADE                         = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_CASCADE_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C0                     = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C0_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C1                     = 10  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C1_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C2                     = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C2_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C3                     = 14  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C3_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT0                          = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT1                          = 24  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT2                          = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT3                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_LATENCY                         = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_LATENCY_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_RESERVED                        = 51  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_RESERVED_LEN                    = 13  ;

static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2__SM1_PERF_CONFIG_ENABLE                                 = 0   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_RESETMODE                              = 1   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_FREEZEMODE                             = 2   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_DISABLE_PMISC                          = 3   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PMISC_MODE                             = 4   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_CASCADE                                = 5   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_CASCADE_LEN                            = 3   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C0                            = 8   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C0_LEN                        = 2   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C1                            = 10  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C1_LEN                        = 2   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C2                            = 12  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C2_LEN                        = 2   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C3                            = 14  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C3_LEN                        = 2   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT0                                 = 16  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT0_LEN                             = 8   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT1                                 = 24  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT1_LEN                             = 8   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT2                                 = 32  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT2_LEN                             = 8   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT3                                 = 40  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT3_LEN                             = 8   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_LATENCY                                = 48  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_LATENCY_LEN                            = 3   ;
static const uint8_t P9N2__SM1_PERF_CONFIG_RESERVED                               = 51  ;
static const uint8_t P9N2__SM1_PERF_CONFIG_RESERVED_LEN                           = 13  ;

static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_ENABLE                         = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_RESETMODE                      = 1   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_FREEZEMODE                     = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_DISABLE_PMISC                  = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PMISC_MODE                     = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_CASCADE                        = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_CASCADE_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0                    = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1                    = 10  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2                    = 12  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3                    = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT0                         = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT0_LEN                     = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT1                         = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT1_LEN                     = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT2                         = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT2_LEN                     = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT3                         = 40  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT3_LEN                     = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATSTART                       = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATSTART_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATCANCEL                      = 53  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATCANCEL_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATFINISH                      = 58  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATFINISH_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATFILTER                      = 63  ;

static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATSTART                     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATSTART_LEN                 = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATCANCEL                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATCANCEL_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATFINISH                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATFINISH_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_RESERVED1                    = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT0                       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT0_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT1                       = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT1_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT2                       = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT2_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT3                       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT3_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_RESERVED2                    = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_RESERVED2_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATFILTER                    = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_ACT                          = 63  ;

static const uint8_t P9N2__SM0_PERF_CONFIG_ENABLE                                 = 0   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_RESETMODE                              = 1   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_FREEZEMODE                             = 2   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_DISABLE_PMISC                          = 3   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PMISC_MODE                             = 4   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_CASCADE                                = 5   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_CASCADE_LEN                            = 3   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C0                            = 8   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C0_LEN                        = 2   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C1                            = 10  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C1_LEN                        = 2   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C2                            = 12  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C2_LEN                        = 2   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C3                            = 14  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C3_LEN                        = 2   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT0                                 = 16  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT0_LEN                             = 8   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT1                                 = 24  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT1_LEN                             = 8   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT2                                 = 32  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT2_LEN                             = 8   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT3                                 = 40  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT3_LEN                             = 8   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_LATENCY                                = 48  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_LATENCY_LEN                            = 3   ;
static const uint8_t P9N2__SM0_PERF_CONFIG_RESERVED                               = 51  ;
static const uint8_t P9N2__SM0_PERF_CONFIG_RESERVED_LEN                           = 13  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATSTART                     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATSTART_LEN                 = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATCANCEL                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATCANCEL_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATFINISH                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATFINISH_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_RESERVED1                    = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT0                       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT0_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT1                       = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT1_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT2                       = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT2_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT3                       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT3_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_RESERVED2                    = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_RESERVED2_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATFILTER                    = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_ACT                          = 63  ;

static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_RESETMODE                        = 1   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_FREEZEMODE                       = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_DISABLE_PMISC                    = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PMISC_MODE                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_CASCADE                          = 5   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_CASCADE_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C0                      = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C0_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C1                      = 10  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C1_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C2                      = 12  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C2_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C3                      = 14  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C3_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT0                           = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT0_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT1                           = 24  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT1_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT2                           = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT2_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT3                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT3_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_LATENCY                          = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_LATENCY_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_RESERVED                         = 51  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_RESERVED_LEN                     = 13  ;

static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_ENABLE                           = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_RESETMODE                        = 1   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_FREEZEMODE                       = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_DISABLE_PMISC                    = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PMISC_MODE                       = 4   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_CASCADE                          = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_CASCADE_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C0                      = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C0_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C1                      = 10  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C1_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C2                      = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C2_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C3                      = 14  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C3_LEN                  = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT0                           = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT0_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT1                           = 24  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT1_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT2                           = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT2_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT3                           = 40  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT3_LEN                       = 8   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_LATENCY                          = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_LATENCY_LEN                      = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_RESERVED                         = 51  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_RESERVED_LEN                     = 13  ;

static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATSTART                        = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATSTART_LEN                    = 9   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATCANCEL                       = 9   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATCANCEL_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATFINISH                       = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATFINISH_LEN                   = 9   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_RESERVED1                       = 27  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT0                          = 28  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT1                          = 36  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT2                          = 44  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT3                          = 52  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_RESERVED2                       = 60  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_RESERVED2_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATFILTER                       = 62  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_ACT                             = 63  ;

static const uint8_t P9N2_NV_PERF_CONFIG_ENABLE                                   = 0   ;
static const uint8_t P9N2_NV_PERF_CONFIG_RESETMODE                                = 1   ;
static const uint8_t P9N2_NV_PERF_CONFIG_FREEZEMODE                               = 2   ;
static const uint8_t P9N2_NV_PERF_CONFIG_DISABLE_PMISC                            = 3   ;
static const uint8_t P9N2_NV_PERF_CONFIG_PMISC_MODE                               = 4   ;
static const uint8_t P9N2_NV_PERF_CONFIG_CASCADE                                  = 5   ;
static const uint8_t P9N2_NV_PERF_CONFIG_CASCADE_LEN                              = 3   ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C0                              = 8   ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C0_LEN                          = 2   ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C1                              = 10  ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C1_LEN                          = 2   ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C2                              = 12  ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C2_LEN                          = 2   ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C3                              = 14  ;
static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C3_LEN                          = 2   ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT0                                   = 16  ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT0_LEN                               = 8   ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT1                                   = 24  ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT1_LEN                               = 8   ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT2                                   = 32  ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT2_LEN                               = 8   ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT3                                   = 40  ;
static const uint8_t P9N2_NV_PERF_CONFIG_EVENT3_LEN                               = 8   ;
static const uint8_t P9N2_NV_PERF_CONFIG_LATSTART                                 = 48  ;
static const uint8_t P9N2_NV_PERF_CONFIG_LATSTART_LEN                             = 5   ;
static const uint8_t P9N2_NV_PERF_CONFIG_LATCANCEL                                = 53  ;
static const uint8_t P9N2_NV_PERF_CONFIG_LATCANCEL_LEN                            = 5   ;
static const uint8_t P9N2_NV_PERF_CONFIG_LATFINISH                                = 58  ;
static const uint8_t P9N2_NV_PERF_CONFIG_LATFINISH_LEN                            = 5   ;
static const uint8_t P9N2_NV_PERF_CONFIG_LATFILTER                                = 63  ;

static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_ENABLE                          = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_RESETMODE                       = 1   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_FREEZEMODE                      = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_DISABLE_PMISC                   = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PMISC_MODE                      = 4   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_CASCADE                         = 5   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_CASCADE_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C0                     = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C0_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C1                     = 10  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C1_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C2                     = 12  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C2_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C3                     = 14  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C3_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT0                          = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT0_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT1                          = 24  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT1_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT2                          = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT2_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT3                          = 40  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT3_LEN                      = 8   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_LATENCY                         = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_LATENCY_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_RESERVED                        = 51  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_RESERVED_LEN                    = 13  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATSTART                     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATSTART_LEN                 = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATCANCEL                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATCANCEL_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATFINISH                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATFINISH_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_RESERVED1                    = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT0                       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT0_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT1                       = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT1_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT2                       = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT2_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT3                       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT3_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_RESERVED2                    = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_RESERVED2_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATFILTER                    = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_ACT                          = 63  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATSTART                     = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATSTART_LEN                 = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATCANCEL                    = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATCANCEL_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATFINISH                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATFINISH_LEN                = 9   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_RESERVED1                    = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT0                       = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT0_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT1                       = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT1_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT2                       = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT2_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT3                       = 52  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT3_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_RESERVED2                    = 60  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_RESERVED2_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATFILTER                    = 62  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_ACT                          = 63  ;

static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT0                     = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT0_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT1                     = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT1_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT2                     = 32  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT2_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT3                     = 48  ;
static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT3_LEN                 = 16  ;

static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0_LEN                = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1                    = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1_LEN                = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2                    = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2_LEN                = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3                    = 48  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3_LEN                = 16  ;

static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT0                            = 0   ;
static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT0_LEN                        = 16  ;
static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT1                            = 16  ;
static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT1_LEN                        = 16  ;
static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT2                            = 32  ;
static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT2_LEN                        = 16  ;
static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT3                            = 48  ;
static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT3_LEN                        = 16  ;

static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT0                      = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT0_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT1                      = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT1_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT2                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT2_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT3                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT3_LEN                  = 16  ;

static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT0                      = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT0_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT1                      = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT1_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT2                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT2_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT3                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT3_LEN                  = 16  ;

static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT0                              = 0   ;
static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT0_LEN                          = 16  ;
static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT1                              = 16  ;
static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT1_LEN                          = 16  ;
static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT2                              = 32  ;
static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT2_LEN                          = 16  ;
static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT3                              = 48  ;
static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT3_LEN                          = 16  ;

static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT0                     = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT0_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT1                     = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT1_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT2                     = 32  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT2_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT3                     = 48  ;
static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT3_LEN                 = 16  ;

static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT0                            = 0   ;
static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT0_LEN                        = 16  ;
static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT1                            = 16  ;
static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT1_LEN                        = 16  ;
static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT2                            = 32  ;
static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT2_LEN                        = 16  ;
static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT3                            = 48  ;
static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT3_LEN                        = 16  ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SRC_BUS                 = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SRC_BUS_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TTYPE                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TTYPE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TSIZE                   = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TSIZE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_NVBE                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_UT                      = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ATYPE                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ATYPE_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_CRESP                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_CRESP_LEN               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SCOPE                   = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SCOPE_LEN               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_MCMD                    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_MCMD_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ALLOC                   = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ALLOC_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_RESERVED1               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_RESERVED1_LEN           = 2   ;

static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMCMD                     = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMCMD_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMEXCMD                   = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMEXCMD_LEN               = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_BE                        = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_CS                        = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_CS_LEN                    = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_AECS                      = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_AECS_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_PE                        = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_PE_LEN                    = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SRC_BUS                 = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SRC_BUS_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TTYPE                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TTYPE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TSIZE                   = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TSIZE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_NVBE                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_UT                      = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ATYPE                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ATYPE_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_CRESP                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_CRESP_LEN               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SCOPE                   = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SCOPE_LEN               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_MCMD                    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_MCMD_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ALLOC                   = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ALLOC_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_RESERVED1               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_RESERVED1_LEN           = 2   ;

static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SRC_BUS                 = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SRC_BUS_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TTYPE                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TTYPE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TSIZE                   = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TSIZE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_NVBE                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_UT                      = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ATYPE                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ATYPE_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_CRESP                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_CRESP_LEN               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SCOPE                   = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SCOPE_LEN               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_MCMD                    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_MCMD_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ALLOC                   = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ALLOC_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_RESERVED1               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_RESERVED1_LEN           = 2   ;

static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMCMD                               = 0   ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMCMD_LEN                           = 8   ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMEXCMD                             = 8   ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMEXCMD_LEN                         = 5   ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_BE                                  = 13  ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_CS                                  = 14  ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_CS_LEN                              = 6   ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_AECS                                = 20  ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_AECS_LEN                            = 16  ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_PE                                  = 36  ;
static const uint8_t P9N2_NV_PERF_MASK_CONFIG_PE_LEN                              = 4   ;

static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SRC_BUS                 = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SRC_BUS_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TTYPE                   = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TTYPE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TSIZE                   = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TSIZE_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_NVBE                    = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_UT                      = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ATYPE                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ATYPE_LEN               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_CRESP                   = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_CRESP_LEN               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SCOPE                   = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SCOPE_LEN               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_MCMD                    = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_MCMD_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ALLOC                   = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ALLOC_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_RESERVED1               = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_RESERVED1_LEN           = 2   ;

static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SRC_BUS                    = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SRC_BUS_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TTYPE                      = 2   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TTYPE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TSIZE                      = 10  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TSIZE_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_NVBE                       = 18  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_UT                         = 19  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ATYPE                      = 20  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ATYPE_LEN                  = 4   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_CRESP                      = 24  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_CRESP_LEN                  = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SCOPE                      = 29  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SCOPE_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_MCMD                       = 32  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_MCMD_LEN                   = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ALLOC                      = 40  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ALLOC_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_RESERVED1                  = 46  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_RESERVED1_LEN              = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SRC_BUS                = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SRC_BUS_LEN            = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TTYPE                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TTYPE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TSIZE                  = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TSIZE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_NVBE                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_UT                     = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ATYPE                  = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ATYPE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_CRESP                  = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_CRESP_LEN              = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SCOPE                  = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SCOPE_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_MCMD                   = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_MCMD_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ALLOC                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ALLOC_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_RESERVED1              = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_RESERVED1_LEN          = 2   ;

static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMCMD                    = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMCMD_LEN                = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMEXCMD                  = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMEXCMD_LEN              = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_BE                       = 13  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_CS                       = 14  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_CS_LEN                   = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_AECS                     = 20  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_AECS_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_PE                       = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_PE_LEN                   = 4   ;

static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SRC_BUS                = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SRC_BUS_LEN            = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TTYPE                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TTYPE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TSIZE                  = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TSIZE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_NVBE                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_UT                     = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ATYPE                  = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ATYPE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_CRESP                  = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_CRESP_LEN              = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SCOPE                  = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SCOPE_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_MCMD                   = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_MCMD_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ALLOC                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ALLOC_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_RESERVED1              = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_RESERVED1_LEN          = 2   ;

static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SRC_BUS                = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SRC_BUS_LEN            = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TTYPE                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TTYPE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TSIZE                  = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TSIZE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_NVBE                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_UT                     = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ATYPE                  = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ATYPE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_CRESP                  = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_CRESP_LEN              = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SCOPE                  = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SCOPE_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_MCMD                   = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_MCMD_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ALLOC                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ALLOC_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_RESERVED1              = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_RESERVED1_LEN          = 2   ;

static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMCMD                              = 0   ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMCMD_LEN                          = 8   ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMEXCMD                            = 8   ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMEXCMD_LEN                        = 5   ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_BE                                 = 13  ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_CS                                 = 14  ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_CS_LEN                             = 6   ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_AECS                               = 20  ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_AECS_LEN                           = 16  ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_PE                                 = 36  ;
static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_PE_LEN                             = 4   ;

static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SRC_BUS                = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SRC_BUS_LEN            = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TTYPE                  = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TTYPE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TSIZE                  = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TSIZE_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_NVBE                   = 18  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_UT                     = 19  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ATYPE                  = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ATYPE_LEN              = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_CRESP                  = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_CRESP_LEN              = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SCOPE                  = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SCOPE_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_MCMD                   = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_MCMD_LEN               = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ALLOC                  = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ALLOC_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_RESERVED1              = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN          = 2   ;

static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SRC_BUS                   = 0   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SRC_BUS_LEN               = 2   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TTYPE                     = 2   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TTYPE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TSIZE                     = 10  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TSIZE_LEN                 = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_NVBE                      = 18  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_UT                        = 19  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ATYPE                     = 20  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ATYPE_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_CRESP                     = 24  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_CRESP_LEN                 = 5   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SCOPE                     = 29  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SCOPE_LEN                 = 3   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_MCMD                      = 32  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_MCMD_LEN                  = 8   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ALLOC                     = 40  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ALLOC_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_RESERVED1                 = 46  ;
static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_RESERVED1_LEN             = 2   ;

static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_NOTJUSTOWN_DIS                   = 0   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_DYN_ADJ_DIS                      = 1   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_DYN_LVL_ADJ_DIS                  = 2   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_RTY_CNTR_DIV2_EN                 = 3   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_MAX_LVL_CNT_QUAL                 = 4   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_MAX_LVL_CNT_QUAL_LEN             = 4   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD1_QUAL              = 8   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD1_QUAL_LEN          = 6   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD2_QUAL              = 14  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD2_QUAL_LEN          = 6   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_MSTR_RTY_BACKOFF_EN              = 20  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_NOTJUSTOWN_DIS                   = 21  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_DYN_ADJ_DIS                      = 22  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_DYN_LVL_ADJ_DIS                  = 23  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_RTY_CNTR_DIV2_EN                 = 24  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_MAX_LVL_CNT_QUAL                 = 25  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_MAX_LVL_CNT_QUAL_LEN             = 4   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD1_QUAL              = 29  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD1_QUAL_LEN          = 6   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD2_QUAL              = 35  ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD2_QUAL_LEN          = 6   ;
static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_MSTR_RTY_BACKOFF_EN              = 41  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE                 = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE_LEN             = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE                 = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE_LEN             = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE                 = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE_LEN             = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE                 = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE_LEN             = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE                 = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE_LEN             = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE                 = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE_LEN             = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE                  = 0   ;
static const uint8_t P9N2__NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE_LEN              = 37  ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE0_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE1_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE10_DMA_STOPPED_STATE                 = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE11_DMA_STOPPED_STATE                 = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE12_DMA_STOPPED_STATE                 = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE13_DMA_STOPPED_STATE                 = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE14_DMA_STOPPED_STATE                 = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE15_DMA_STOPPED_STATE                 = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE2_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE3_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE4_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE5_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE6_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE7_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE8_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2__NTL0_PESTB_DATA_PE9_DMA_STOPPED_STATE                  = 0   ;

static const uint8_t P9N2_PHB_PE_DFREEZE_REG_DFREEZE                              = 0   ;
static const uint8_t P9N2_PHB_PE_DFREEZE_REG_DFREEZE_LEN                          = 28  ;

static const uint8_t P9N2_PEC_STACK0_PE_DFREEZE_REG_DFREEZE                       = 0   ;
static const uint8_t P9N2_PEC_STACK0_PE_DFREEZE_REG_DFREEZE_LEN                   = 28  ;

static const uint8_t P9N2_PHB_PFIRACTION0_REG_PFIRACTION0                         = 0   ;
static const uint8_t P9N2_PHB_PFIRACTION0_REG_PFIRACTION0_LEN                     = 7   ;

static const uint8_t P9N2_PHB_PFIRACTION1_REG_PFIRACTION1                         = 0   ;
static const uint8_t P9N2_PHB_PFIRACTION1_REG_PFIRACTION1_LEN                     = 7   ;

static const uint8_t P9N2_PHB_PFIRMASK_REG_PFIRMASK                               = 0   ;
static const uint8_t P9N2_PHB_PFIRMASK_REG_PFIRMASK_LEN                           = 7   ;

static const uint8_t P9N2_PHB_PFIR_REG_PFIRPFIR                                   = 0   ;
static const uint8_t P9N2_PHB_PFIR_REG_PFIRPFIR_LEN                               = 7   ;

static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VLD                     = 0   ;
static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_4B                           = 1   ;
static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_AUTO_INC                         = 2   ;
static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE                   = 51  ;
static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE_LEN               = 11  ;

static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_ENABLE                        = 0   ;
static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_CMP_VALUE                     = 12  ;
static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_CMP_VALUE_LEN                 = 8   ;
static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_MSK_VALUE                     = 44  ;
static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_MSK_VALUE_LEN                 = 8   ;

static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_CMP_ENABLE                    = 0   ;
static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_CMP_VALUE                     = 12  ;
static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_CMP_VALUE_LEN                 = 40  ;

static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_MSK_VALUE                     = 12  ;
static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_MSK_VALUE_LEN                 = 40  ;

static const uint8_t P9N2_PHB_PHBBAR_REG_PE_PHB_BAR                               = 0   ;
static const uint8_t P9N2_PHB_PHBBAR_REG_PE_PHB_BAR_LEN                           = 42  ;

static const uint8_t P9N2_PEC_STACK0_PHBBAR_REG_PE_PHB_BAR                        = 0   ;
static const uint8_t P9N2_PEC_STACK0_PHBBAR_REG_PE_PHB_BAR_LEN                    = 42  ;

static const uint8_t P9N2_PHB_PHBRESET_REG_PE_ETU_RESET                           = 0   ;

static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_RESERVED1                        = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_RESERVED1_LEN                    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_GROUP                     = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_GROUP_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_CHIP                      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_CHIP_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_ADDR                      = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_ADDR_LEN                  = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_POISON                    = 31  ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_RESERVED1                        = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_RESERVED1_LEN                    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_GROUP                     = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_GROUP_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_CHIP                      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_CHIP_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_ADDR                      = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_ADDR_LEN                  = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_POISON                    = 31  ;

static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_ENABLE                       = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_RESERVED1                           = 1   ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_RESERVED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP                        = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP_LEN                    = 4   ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP                         = 7   ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR                         = 10  ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR_LEN                     = 21  ;
static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_POISON                       = 31  ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_RESERVED1                        = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_RESERVED1_LEN                    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_GROUP                     = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_GROUP_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_CHIP                      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_CHIP_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_ADDR                      = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_ADDR_LEN                  = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_POISON                    = 31  ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_ENABLE                    = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_RESERVED1                        = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_RESERVED1_LEN                    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_GROUP                     = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_GROUP_LEN                 = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_CHIP                      = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_CHIP_LEN                  = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_ADDR                      = 10  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_ADDR_LEN                  = 21  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_POISON                    = 31  ;

static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ENABLE_0                = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0                    = 1   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0_LEN                = 4   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0              = 8   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0_LEN          = 8   ;

static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ENABLE_1                = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1                    = 1   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1_LEN                = 4   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1              = 8   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1_LEN          = 8   ;

static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ENABLE_2                = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2                    = 1   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2_LEN                = 4   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2              = 8   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2_LEN          = 8   ;

static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ENABLE_3                = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3                    = 1   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3_LEN                = 4   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3              = 8   ;
static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3_LEN          = 8   ;

static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_B_CC_READ_ENABLE_0          = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_B_CC_WRITE_ENABLE_0         = 1   ;

static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_C_CC_READ_ENABLE_1          = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_C_CC_WRITE_ENABLE_1         = 1   ;

static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_D_CC_READ_ENABLE_2          = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_D_CC_WRITE_ENABLE_2         = 1   ;

static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_E_CC_READ_ENABLE_3          = 0   ;
static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_E_CC_WRITE_ENABLE_3         = 1   ;

static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_POINTER                      = 48  ;
static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_POINTER_LEN                  = 16  ;

static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER                   = 48  ;
static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER_LEN               = 16  ;

static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_PIB       = 0   ;
static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_PIB      = 1   ;
static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_DISABLE_ECC                  = 2   ;
static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_FACES     = 3   ;
static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_FACES    = 4   ;
static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_CHKSW_AR012                  = 5   ;

static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_0_DATA                        = 0   ;
static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_0_DATA_LEN                    = 2   ;

static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_1_DATA                        = 0   ;
static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_1_DATA_LEN                    = 64  ;

static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_2_DATA                        = 0   ;
static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_2_DATA_LEN                    = 64  ;

static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_3_DATA                        = 0   ;
static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_3_DATA_LEN                    = 64  ;

static const uint8_t P9N2_PU_PIBMEM_RESET_REGISTER_RESET                          = 0   ;
static const uint8_t P9N2_PU_PIBMEM_RESET_REGISTER_RESET_LEN                      = 2   ;

static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_INVALID_PIB                   = 0   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_INVALID_PIB                  = 1   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_INVALID_PIB                   = 2   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB          = 3   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_PIB            = 4   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_PIB              = 5   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_PIB            = 6   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_PIB             = 7   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE                  = 12  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE_LEN              = 7   ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_INVALID_FACES                 = 19  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_INVALID_FACES                = 20  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_INVALID_FACES                 = 21  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_FACES        = 22  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_FACES          = 23  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_FACES            = 24  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_FACES          = 25  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_FACES           = 26  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB                = 32  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB_LEN            = 16  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES              = 48  ;
static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES_LEN          = 16  ;

static const uint8_t P9N2_PU_PIB_CMD_REG_RNW                                      = 0   ;
static const uint8_t P9N2_PU_PIB_CMD_REG_ADR                                      = 30  ;
static const uint8_t P9N2_PU_PIB_CMD_REG_ADR_LEN                                  = 31  ;

static const uint8_t P9N2_PU_PIB_DATA_REG_DATA                                    = 0   ;
static const uint8_t P9N2_PU_PIB_DATA_REG_DATA_LEN                                = 64  ;

static const uint8_t P9N2_PU_PIB_RESET_REG_RESET                                  = 0   ;
static const uint8_t P9N2_PU_PIB_RESET_REG_STATE                                  = 1   ;
static const uint8_t P9N2_PU_PIB_RESET_REG_ABORTED_CMD                            = 2   ;

static const uint8_t P9N2_PEC_PLL_LOCK_REG_LOCK                                   = 0   ;
static const uint8_t P9N2_PEC_PLL_LOCK_REG_LOCK_LEN                               = 4   ;

static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_EN                              = 0   ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_EN_LEN                          = 16  ;
static const uint8_t P9N2_PEC_PMONCTL_REG_RESERVED                                = 16  ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_ALL_ENGINES                     = 17  ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_STK                             = 18  ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_STK_LEN                         = 2   ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_RD_TYPE                         = 20  ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_RD_TYPE_LEN                     = 2   ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0                       = 22  ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0_LEN                   = 3   ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1                       = 25  ;
static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1_LEN                   = 3   ;

static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_ENABLE                          = 0   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_CASCADE_SELECT                  = 1   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_CASCADE_SELECT_LEN              = 3   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_FREEZE_MODE             = 7   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_RESET_MODE              = 8   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_PRESCALER_SELECT       = 9   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT        = 11  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_PRESCALER_SELECT       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT        = 18  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_PRESCALER_SELECT       = 23  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT        = 25  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_PRESCALER_SELECT       = 30  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT        = 32  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT                     = 37  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT_LEN                 = 2   ;

static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_0                           = 0   ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_0_LEN                       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_1                           = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_1_LEN                       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_2                           = 32  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_2_LEN                       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_3                           = 48  ;
static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_3_LEN                       = 16  ;

static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_ENABLE                          = 0   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_CASCADE_SELECT                  = 1   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_CASCADE_SELECT_LEN              = 3   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_FREEZE_MODE             = 7   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_RESET_MODE              = 8   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_PRESCALER_SELECT       = 9   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT        = 11  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_PRESCALER_SELECT       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT        = 18  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_PRESCALER_SELECT       = 23  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT        = 25  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_PRESCALER_SELECT       = 30  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_PRESCALER_SELECT_LEN   = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT        = 32  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN    = 2   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT                     = 37  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT_LEN                 = 2   ;

static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_0                           = 0   ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_0_LEN                       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_1                           = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_1_LEN                       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_2                           = 32  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_2_LEN                       = 16  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_3                           = 48  ;
static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_3_LEN                       = 16  ;

static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_ENABLE                        = 0   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_RESETMODE                     = 1   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_FREEZEMODE                    = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_DISABLE_PMISC                 = 3   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PMISC_MODE                    = 4   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_CASCADE                       = 5   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_CASCADE_LEN                   = 3   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0                   = 8   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN               = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1                   = 10  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN               = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2                   = 12  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN               = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3                   = 14  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN               = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0                  = 16  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN              = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1                  = 18  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN              = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2                  = 20  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN              = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3                  = 22  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN              = 2   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0                     = 24  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN                 = 8   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1                     = 32  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN                 = 8   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2                     = 40  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN                 = 8   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3                     = 48  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN                 = 8   ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_RESERVED0                     = 56  ;
static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_RESERVED0_LEN                 = 8   ;

static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_RESETMODE                = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_FREEZEMODE               = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_DISABLE_PMISC            = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PMISC_MODE               = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_CASCADE                  = 5   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_CASCADE_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1              = 10  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2              = 12  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3              = 14  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C0             = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C1             = 18  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C2             = 20  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C3             = 22  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C0                = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C1                = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C2                = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C3                = 48  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_RESERVED0                = 56  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_RESERVED0_LEN            = 8   ;

static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_RESETMODE                = 1   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_FREEZEMODE               = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_DISABLE_PMISC            = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PMISC_MODE               = 4   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_CASCADE                  = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_CASCADE_LEN              = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0              = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1              = 10  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2              = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3              = 14  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C0             = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C1             = 18  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C2             = 20  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C3             = 22  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C0                = 24  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C1                = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C2                = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C3                = 48  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN            = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_RESERVED0                = 56  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_RESERVED0_LEN            = 8   ;

static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_ENABLE                  = 0   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_RESETMODE               = 1   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_FREEZEMODE              = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_DISABLE_PMISC           = 3   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PMISC_MODE              = 4   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_CASCADE                 = 5   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_CASCADE_LEN             = 3   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0             = 8   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1             = 10  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2             = 12  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3             = 14  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0            = 16  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN        = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1            = 18  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN        = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2            = 20  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN        = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3            = 22  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN        = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0               = 24  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN           = 8   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1               = 32  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN           = 8   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2               = 40  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN           = 8   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3               = 48  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN           = 8   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_RESERVED0               = 56  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_RESERVED0_LEN           = 8   ;

static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_ENABLE                         = 0   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_RESETMODE                      = 1   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_FREEZEMODE                     = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_DISABLE_PMISC                  = 3   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PMISC_MODE                     = 4   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_CASCADE                        = 5   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_CASCADE_LEN                    = 3   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0                    = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN                = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1                    = 10  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN                = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2                    = 12  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN                = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3                    = 14  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN                = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C0                   = 16  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN               = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C1                   = 18  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN               = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C2                   = 20  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN               = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C3                   = 22  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN               = 2   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C0                      = 24  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN                  = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C1                      = 32  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN                  = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C2                      = 40  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN                  = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C3                      = 48  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN                  = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_RESERVED0                      = 56  ;
static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_RESERVED0_LEN                  = 8   ;

static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_ENABLE                         = 0   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_RESETMODE                      = 1   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_FREEZEMODE                     = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_DISABLE_PMISC                  = 3   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PMISC_MODE                     = 4   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_CASCADE                        = 5   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_CASCADE_LEN                    = 3   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0                    = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN                = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1                    = 10  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN                = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2                    = 12  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN                = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3                    = 14  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN                = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C0                   = 16  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN               = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C1                   = 18  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN               = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C2                   = 20  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN               = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C3                   = 22  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN               = 2   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C0                      = 24  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN                  = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C1                      = 32  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN                  = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C2                      = 40  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN                  = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C3                      = 48  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN                  = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_RESERVED0                      = 56  ;
static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_RESERVED0_LEN                  = 8   ;

static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA              = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA              = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB              = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY           = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN       = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_RESERVED1                = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_RESERVED1_LEN            = 24  ;

static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA              = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB              = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA              = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB              = 24  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY           = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN       = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_RESERVED1                = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_RESERVED1_LEN            = 24  ;

static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA                    = 0   ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB                    = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA                    = 16  ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB                    = 24  ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY                 = 32  ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN             = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_RESERVED1                      = 40  ;
static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_RESERVED1_LEN                  = 24  ;

static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA                    = 0   ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB                    = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA                    = 16  ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB                    = 24  ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY                 = 32  ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN             = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_RESERVED1                      = 40  ;
static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_RESERVED1_LEN                  = 24  ;

static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA              = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA              = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB              = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY           = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN       = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_RESERVED2                = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_RESERVED2_LEN            = 24  ;

static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA              = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB              = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA              = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB              = 24  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN          = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY           = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN       = 8   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_RESERVED2                = 40  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_RESERVED2_LEN            = 24  ;

static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA                    = 0   ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB                    = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA                    = 16  ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB                    = 24  ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN                = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY                 = 32  ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN             = 8   ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_RESERVED2                      = 40  ;
static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_RESERVED2_LEN                  = 24  ;

static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA                    = 0   ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB                    = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA                    = 16  ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB                    = 24  ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN                = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY                 = 32  ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN             = 8   ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_RESERVED2                      = 40  ;
static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_RESERVED2_LEN                  = 24  ;

static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT0                           = 0   ;
static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT0_LEN                       = 16  ;
static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT1                           = 16  ;
static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT1_LEN                       = 16  ;
static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT2                           = 32  ;
static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT2_LEN                       = 16  ;
static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT3                           = 48  ;
static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT3_LEN                       = 16  ;

static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT0                      = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT0_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT1                      = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT1_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT2                      = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT2_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT3                      = 48  ;
static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT3_LEN                  = 16  ;

static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT0                      = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT0_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT1                      = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT1_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT2                      = 32  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT2_LEN                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT3                      = 48  ;
static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT3_LEN                  = 16  ;

static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT0                     = 0   ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT0_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT1                     = 16  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT1_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT2                     = 32  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT2_LEN                 = 16  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT3                     = 48  ;
static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT3_LEN                 = 16  ;

static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT0                            = 0   ;
static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT0_LEN                        = 16  ;
static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT1                            = 16  ;
static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT1_LEN                        = 16  ;
static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT2                            = 32  ;
static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT2_LEN                        = 16  ;
static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT3                            = 48  ;
static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT3_LEN                        = 16  ;

static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT0                            = 0   ;
static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT0_LEN                        = 16  ;
static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT1                            = 16  ;
static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT1_LEN                        = 16  ;
static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT2                            = 32  ;
static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT2_LEN                        = 16  ;
static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT3                            = 48  ;
static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT3_LEN                        = 16  ;

static const uint8_t P9N2_PU_PPE_FIR_ACTION0_REG_ACTION0                          = 0   ;
static const uint8_t P9N2_PU_PPE_FIR_ACTION0_REG_ACTION0_LEN                      = 13  ;

static const uint8_t P9N2_PU_PPE_FIR_ACTION1_REG_ACTION1                          = 0   ;
static const uint8_t P9N2_PU_PPE_FIR_ACTION1_REG_ACTION1_LEN                      = 13  ;

static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ERROR                               = 0   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ERROR_LEN                           = 4   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_HALTED                              = 4   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_WATCHDOG_TIMEOUT                    = 5   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_MMIO_DATA_IN                        = 6   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ARB_MISSED_SCRUB_TICK               = 7   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ARB_ARY_UE                          = 8   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ARB_ARY_CE                          = 9   ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_RESERVED                            = 10  ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR                 = 11  ;
static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE           = 12  ;

static const uint8_t P9N2_PU_PPE_FIR_REG_ERROR                                    = 0   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_ERROR_LEN                                = 4   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_HALTED                                   = 4   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_WATCHDOG_TIMEOUT                         = 5   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_MMIO_DATA_IN                             = 6   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_ARB_MISSED_SCRUB_TICK                    = 7   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_ARB_ARY_UE                               = 8   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_ARB_ARY_CE                               = 9   ;
static const uint8_t P9N2_PU_PPE_FIR_REG_RESERVED                                 = 10  ;
static const uint8_t P9N2_PU_PPE_FIR_REG_SCOMFIR_ERROR                            = 11  ;
static const uint8_t P9N2_PU_PPE_FIR_REG_SCOMFIR_ERROR_CLONE                      = 12  ;

static const uint8_t P9N2_PU_PPE_FIR_WOF_REG_WOF                                  = 0   ;
static const uint8_t P9N2_PU_PPE_FIR_WOF_REG_WOF_LEN                              = 13  ;

static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HS                                  = 0   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HC                                  = 1   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HC_LEN                              = 3   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HCP                                 = 4   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_RIP                                 = 5   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_SIP                                 = 6   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_TRAP                                = 7   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_IAC                                 = 8   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_SIBRC                          = 9   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                      = 3   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_DACR                                = 12  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_DACW                                = 13  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_WE                             = 14  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_TRH                                 = 15  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_SMS                                 = 16  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_SMS_LEN                             = 4   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_LP                             = 20  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_EP                                  = 21  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_PTR                                 = 24  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_ST                                  = 25  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_MFE                                 = 28  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_MCS                                 = 29  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_MCS_LEN                             = 3   ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_IAR                                     = 32  ;
static const uint8_t P9N2_PU_PPE_XIDBGPRO_IAR_LEN                                 = 30  ;

static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HS                                  = 0   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HC                                  = 1   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HC_LEN                              = 3   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HCP                                 = 4   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_RIP                                 = 5   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_SIP                                 = 6   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_TRAP                                = 7   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_IAC                                 = 8   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_SIBRC                          = 9   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                      = 3   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_DACR                                = 12  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_DACW                                = 13  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_WE                             = 14  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_TRH                                 = 15  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_SMS                                 = 16  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_SMS_LEN                             = 4   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_LP                             = 20  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_EP                                  = 21  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_PTR                                 = 24  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_ST                                  = 25  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_MFE                                 = 28  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_MCS                                 = 29  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_MCS_LEN                             = 3   ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XIRAMRA_SPRG0                           = 32  ;
static const uint8_t P9N2_PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                       = 32  ;

static const uint8_t P9N2_PU_PPE_XIRAMEDR_XIRAMGA_IR                              = 0   ;
static const uint8_t P9N2_PU_PPE_XIRAMEDR_XIRAMGA_IR_LEN                          = 32  ;
static const uint8_t P9N2_PU_PPE_XIRAMEDR_EDR                                     = 32  ;
static const uint8_t P9N2_PU_PPE_XIRAMEDR_EDR_LEN                                 = 32  ;

static const uint8_t P9N2_PU_PPE_XIRAMGA_IR                                       = 0   ;
static const uint8_t P9N2_PU_PPE_XIRAMGA_IR_LEN                                   = 32  ;
static const uint8_t P9N2_PU_PPE_XIRAMGA_XIRAMRA_SPRG0                            = 32  ;
static const uint8_t P9N2_PU_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                        = 32  ;

static const uint8_t P9N2_PU_PPE_XIRAMRA_XIXCR_XCR                                = 1   ;
static const uint8_t P9N2_PU_PPE_XIRAMRA_XIXCR_XCR_LEN                            = 3   ;
static const uint8_t P9N2_PU_PPE_XIRAMRA_SPRG0                                    = 32  ;
static const uint8_t P9N2_PU_PPE_XIRAMRA_SPRG0_LEN                                = 32  ;

static const uint8_t P9N2_PU_PPE_XIXCR_XCR                                        = 1   ;
static const uint8_t P9N2_PU_PPE_XIXCR_XCR_LEN                                    = 3   ;

static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_START                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_START_LEN                         = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_END                               = 17  ;
static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_END_LEN                           = 7   ;

static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_START                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_START_LEN                         = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_END                               = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_END_LEN                           = 7   ;

static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED1_LEN                           = 5   ;
static const uint8_t P9N2__SM2_PRB_HA_PTR_START                                   = 5   ;
static const uint8_t P9N2__SM2_PRB_HA_PTR_START_LEN                               = 7   ;
static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED2_LEN                           = 5   ;
static const uint8_t P9N2__SM2_PRB_HA_PTR_END                                     = 17  ;
static const uint8_t P9N2__SM2_PRB_HA_PTR_END_LEN                                 = 7   ;

static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED1_LEN                           = 5   ;
static const uint8_t P9N2__SM1_PRB_HA_PTR_START                                   = 5   ;
static const uint8_t P9N2__SM1_PRB_HA_PTR_START_LEN                               = 7   ;
static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED2_LEN                           = 5   ;
static const uint8_t P9N2__SM1_PRB_HA_PTR_END                                     = 17  ;
static const uint8_t P9N2__SM1_PRB_HA_PTR_END_LEN                                 = 7   ;

static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK0                                  = 0   ;
static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK0_LEN                              = 32  ;
static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK1                                  = 32  ;
static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK1_LEN                              = 16  ;
static const uint8_t P9N2_PEC_PRDSTKOVR_REG_ENABLE                                = 48  ;

static const uint8_t P9N2_PEC_PREDV_REG_PE_RD_TIMEOUT_MASK                        = 0   ;
static const uint8_t P9N2_PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN                    = 8   ;
static const uint8_t P9N2_PEC_PREDV_REG_PE_WR_TIMEOUT_MASK                        = 8   ;
static const uint8_t P9N2_PEC_PREDV_REG_PE_WR_TIMEOUT_MASK_LEN                    = 8   ;

static const uint8_t P9N2_PEC_PRE_COUNTER_REG_COUNTER                             = 0   ;
static const uint8_t P9N2_PEC_PRE_COUNTER_REG_COUNTER_LEN                         = 8   ;

static const uint8_t P9N2_PU_PRGM_REGISTER_PRGM_ADDR                              = 0   ;
static const uint8_t P9N2_PU_PRGM_REGISTER_PRGM_ADDR_LEN                          = 32  ;
static const uint8_t P9N2_PU_PRGM_REGISTER_PRG_BIT_LOCATION                       = 32  ;
static const uint8_t P9N2_PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN                   = 6   ;

static const uint8_t P9N2_PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS                 = 0   ;
static const uint8_t P9N2_PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN             = 6   ;

static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_NDL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_NDL_LEN                          = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_PHY                              = 2   ;
static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_PHY_LEN                          = 2   ;

static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_NDL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_NDL_LEN                           = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_PHY                               = 2   ;
static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_PHY_LEN                           = 2   ;

static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_NDL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_NDL_LEN                          = 2   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_PHY                              = 2   ;
static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_PHY_LEN                          = 2   ;

static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_NDL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_NDL_LEN                           = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_PHY                               = 2   ;
static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_PHY_LEN                           = 2   ;

static const uint8_t P9N2__SM2_PRI_CONFIG_NDL                                     = 0   ;
static const uint8_t P9N2__SM2_PRI_CONFIG_NDL_LEN                                 = 2   ;
static const uint8_t P9N2__SM2_PRI_CONFIG_PHY                                     = 2   ;
static const uint8_t P9N2__SM2_PRI_CONFIG_PHY_LEN                                 = 2   ;

static const uint8_t P9N2__SM1_PRI_CONFIG_NDL                                     = 0   ;
static const uint8_t P9N2__SM1_PRI_CONFIG_NDL_LEN                                 = 2   ;
static const uint8_t P9N2__SM1_PRI_CONFIG_PHY                                     = 2   ;
static const uint8_t P9N2__SM1_PRI_CONFIG_PHY_LEN                                 = 2   ;

static const uint8_t P9N2_PU_PROBE_PROTECT_STATUS_BITS                            = 0   ;
static const uint8_t P9N2_PU_PROBE_PROTECT_STATUS_BITS_LEN                        = 42  ;

static const uint8_t P9N2_PEC_PROTECT_MODE_REG_READ_ENABLE                        = 0   ;
static const uint8_t P9N2_PEC_PROTECT_MODE_REG_WRITE_ENABLE                       = 1   ;

static const uint8_t P9N2_PU_PRV_MISC_TPSBE_TPBR_SBE_INTR                         = 0   ;
static const uint8_t P9N2_PU_PRV_MISC_CHKSW_AR012                                 = 1   ;
static const uint8_t P9N2_PU_PRV_MISC_RESERVED_18                                 = 2   ;
static const uint8_t P9N2_PU_PRV_MISC_RESERVED_18_LEN                             = 2   ;
static const uint8_t P9N2_PU_PRV_MISC_SBE_EXTERNAL_FIRS                           = 4   ;
static const uint8_t P9N2_PU_PRV_MISC_SBE_EXTERNAL_FIRS_LEN                       = 4   ;
static const uint8_t P9N2_PU_PRV_MISC_RESERVED_17                                 = 8   ;
static const uint8_t P9N2_PU_PRV_MISC_RESERVED_17_LEN                             = 4   ;
static const uint8_t P9N2_PU_PRV_MISC_TPSBE_TPIO_TPM_RESET                        = 12  ;
static const uint8_t P9N2_PU_PRV_MISC_TPSBE_TPOCC_HALT_COMPLEX                    = 13  ;
static const uint8_t P9N2_PU_PRV_MISC_RESERVED_16                                 = 14  ;
static const uint8_t P9N2_PU_PRV_MISC_RESERVED_16_LEN                             = 2   ;
static const uint8_t P9N2_PU_PRV_MISC_I2C_TIMEOUT_VALUE                           = 16  ;
static const uint8_t P9N2_PU_PRV_MISC_I2C_TIMEOUT_VALUE_LEN                       = 32  ;

static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 = 0   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               = 1   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           = 2   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_DL_RETURN_P0                     = 3   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  = 4   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_UL_P0                            = 5   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      = 6   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            = 7   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  = 8   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  = 10  ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              = 11  ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               = 12  ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            = 13  ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               = 14  ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  = 15  ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 = 0   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               = 1   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           = 2   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_DL_RETURN_P0                     = 3   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  = 4   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_UL_P0                            = 5   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      = 6   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            = 7   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  = 8   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  = 10  ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              = 11  ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               = 12  ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            = 13  ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               = 14  ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  = 15  ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                    = 0   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                  = 1   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY              = 2   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_DL_RETURN_P0                        = 3   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_UL_RDATA_PARITY                     = 4   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_UL_P0                               = 5   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE         = 6   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE               = 7   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH     = 8   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH     = 10  ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                 = 11  ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                  = 12  ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID               = 13  ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                  = 14  ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                     = 15  ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 = 0   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               = 1   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           = 2   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_DL_RETURN_P0                     = 3   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  = 4   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_UL_P0                            = 5   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      = 6   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            = 7   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  = 8   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  = 10  ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              = 11  ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               = 12  ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            = 13  ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               = 14  ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  = 15  ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                   = 0   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                 = 1   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY             = 2   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_DL_RETURN_P0                       = 3   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_UL_RDATA_PARITY                    = 4   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_UL_P0                              = 5   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE        = 6   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE              = 7   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH    = 8   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH    = 10  ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                = 11  ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                 = 12  ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID              = 13  ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                 = 14  ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                    = 15  ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 = 0   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               = 1   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           = 2   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_DL_RETURN_P0                     = 3   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  = 4   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_UL_P0                            = 5   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      = 6   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            = 7   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  = 8   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  = 10  ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              = 11  ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               = 12  ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            = 13  ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               = 14  ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  = 15  ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     = 0   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    = 1   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_UNUSED_BIT_2                       = 2   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_WATCHDOG_ENABLE                    = 4   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    = 5   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                = 2   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_FORCE_ALL_RINGS                    = 7   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_RESERVED_LT                        = 9   ;
static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_RESERVED_LT_LEN                    = 3   ;

static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     = 0   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    = 1   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_UNUSED_BIT_2                       = 2   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_WATCHDOG_ENABLE                    = 4   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    = 5   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                = 2   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_FORCE_ALL_RINGS                    = 7   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_RESERVED_LT                        = 9   ;
static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_RESERVED_LT_LEN                    = 3   ;

static const uint8_t P9N2_PU_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR        = 0   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR       = 1   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_UNUSED_BIT_2                          = 2   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_WATCHDOG_ENABLE                       = 4   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT                       = 5   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                   = 2   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_FORCE_ALL_RINGS                       = 7   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_RESERVED_LT                           = 9   ;
static const uint8_t P9N2_PU_PSCOM_MODE_REG_RESERVED_LT_LEN                       = 3   ;

static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     = 0   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    = 1   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_UNUSED_BIT_2                       = 2   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_WATCHDOG_ENABLE                    = 4   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    = 5   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                = 2   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_FORCE_ALL_RINGS                    = 7   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_RESERVED_LT                        = 9   ;
static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_RESERVED_LT_LEN                    = 3   ;

static const uint8_t P9N2_PEC_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR       = 0   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR      = 1   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_UNUSED_BIT_2                         = 2   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_WATCHDOG_ENABLE                      = 4   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT                      = 5   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                  = 2   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_FORCE_ALL_RINGS                      = 7   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_RESERVED_LT                          = 9   ;
static const uint8_t P9N2_PEC_PSCOM_MODE_REG_RESERVED_LT_LEN                      = 3   ;

static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     = 0   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    = 1   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_UNUSED_BIT_2                       = 2   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_WATCHDOG_ENABLE                    = 4   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    = 5   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                = 2   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_FORCE_ALL_RINGS                    = 7   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_RESERVED_LT                        = 9   ;
static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_RESERVED_LT_LEN                    = 3   ;

static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   = 3   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          = 5   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   = 18  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       = 21  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    = 22  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              = 23  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    = 33  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34  ;
static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35  ;

static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   = 3   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          = 5   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   = 18  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       = 21  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    = 22  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              = 23  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    = 33  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34  ;
static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35  ;

static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY  = 0   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0      = 3   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY   = 4   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0             = 5   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT   = 15  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY      = 18  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY    = 19  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0          = 21  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY       = 22  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                 = 23  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD   = 29  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD    = 30  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY    = 32  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT       = 33  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34  ;
static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35  ;

static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   = 3   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          = 5   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   = 18  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       = 21  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    = 22  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              = 23  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    = 33  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34  ;
static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35  ;

static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0     = 3   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY  = 4   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0            = 5   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT  = 15  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY     = 18  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY   = 19  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0         = 21  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY      = 22  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                = 23  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD  = 29  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD   = 30  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY   = 32  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT      = 33  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34  ;
static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35  ;

static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   = 3   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          = 5   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   = 18  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       = 21  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    = 22  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              = 23  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    = 33  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34  ;
static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35  ;

static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS               = 0   ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS_LEN           = 2   ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ONCE                   = 2   ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_CONST                  = 3   ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS                = 8   ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS_LEN            = 2   ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ONCE                    = 10  ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_CONST                   = 11  ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_TRACE_SEL                            = 16  ;
static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_TRACE_SEL_LEN                        = 4   ;

static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_1                       = 16  ;
static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_1_LEN                   = 12  ;
static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE               = 32  ;
static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE_LEN           = 12  ;
static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_2                       = 48  ;
static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_2_LEN                   = 5   ;

static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_CE                  = 0   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_UE                  = 1   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_SUE                 = 2   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_ERROR           = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_FSP             = 4   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_CE                 = 5   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_UE                 = 6   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_ERROR_STATE                    = 7   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INVALID_TTYPE                  = 8   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INVALID_CRESP                  = 9   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_DATA_TIME_OUT               = 10  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_PARITY_ERROR                = 11  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_FSP_ACCESS_TRUSTED_SPACE       = 12  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_UNEXPECTED_PB                  = 13  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_CHANGE_WHILE_ACTIVE  = 14  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT0_ADDRESS_ERROR       = 15  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT1_ADDRESS_ERROR       = 16  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT2_ADDRESS_ERROR       = 17  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT3_ADDRESS_ERROR       = 18  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT4_ADDRESS_ERROR       = 19  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT5_ADDRESS_ERROR       = 20  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_0          = 21  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_1          = 22  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_UPSTREAM                       = 23  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_SPARE                          = 24  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_SPARE_LEN                      = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_SCOM_ERROR                     = 27  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PARITY_ERROR                   = 28  ;

static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_CE                  = 0   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_UE                  = 1   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_SUE                 = 2   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_ERROR           = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_FSP             = 4   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_CE                 = 5   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_UE                 = 6   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_ERROR_STATE                    = 7   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INVALID_TTYPE                  = 8   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INVALID_CRESP                  = 9   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_DATA_TIME_OUT               = 10  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_PARITY_ERROR                = 11  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_FSP_ACCESS_TRUSTED_SPACE       = 12  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_UNEXPECTED_PB                  = 13  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_CHANGE_WHILE_ACTIVE  = 14  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT0_ADDRESS_ERROR       = 15  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT1_ADDRESS_ERROR       = 16  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT2_ADDRESS_ERROR       = 17  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT3_ADDRESS_ERROR       = 18  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT4_ADDRESS_ERROR       = 19  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT5_ADDRESS_ERROR       = 20  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_0          = 21  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_1          = 22  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_UPSTREAM                       = 23  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_SPARE                          = 24  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_SPARE_LEN                      = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_SCOM_ERROR                     = 27  ;
static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PARITY_ERROR                   = 28  ;

static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_CE                     = 0   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_UE                     = 1   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_SUE                    = 2   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_ERROR              = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_FSP                = 4   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_CE                    = 5   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_UE                    = 6   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_ERROR_STATE                       = 7   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INVALID_TTYPE                     = 8   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INVALID_CRESP                     = 9   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_DATA_TIME_OUT                  = 10  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_PARITY_ERROR                   = 11  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_FSP_ACCESS_TRUSTED_SPACE          = 12  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_UNEXPECTED_PB                     = 13  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT_CHANGE_WHILE_ACTIVE     = 14  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT0_ADDRESS_ERROR          = 15  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT1_ADDRESS_ERROR          = 16  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT2_ADDRESS_ERROR          = 17  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT3_ADDRESS_ERROR          = 18  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT4_ADDRESS_ERROR          = 19  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT5_ADDRESS_ERROR          = 20  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_0             = 21  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_1             = 22  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_UPSTREAM                          = 23  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_SPARE                             = 24  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_SPARE_LEN                         = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_SCOM_ERROR                        = 27  ;
static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PARITY_ERROR                      = 28  ;

static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_ECC_ERR_CE                          = 0   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_ECC_ERR_UE                          = 1   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_ECC_ERR_SUE                         = 2   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT_FROM_ERROR                   = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT_FROM_FSP                     = 4   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_FSP_ECC_ERR_CE                         = 5   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_FSP_ECC_ERR_UE                         = 6   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_ERROR_STATE                            = 7   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INVALID_TTYPE                          = 8   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INVALID_CRESP                          = 9   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_DATA_TIME_OUT                       = 10  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_PARITY_ERROR                        = 11  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_FSP_ACCESS_TRUSTED_SPACE               = 12  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_UNEXPECTED_PB                          = 13  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT_CHANGE_WHILE_ACTIVE          = 14  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT0_ADDRESS_ERROR               = 15  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT1_ADDRESS_ERROR               = 16  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT2_ADDRESS_ERROR               = 17  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT3_ADDRESS_ERROR               = 18  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT4_ADDRESS_ERROR               = 19  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT5_ADDRESS_ERROR               = 20  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_0                  = 21  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_1                  = 22  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_UPSTREAM                               = 23  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_SPARE                                  = 24  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_SPARE_LEN                              = 3   ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_SCOM_ERROR                             = 27  ;
static const uint8_t P9N2_PU_PSIHB_FIR_REG_PARITY_ERROR                           = 28  ;

static const uint8_t P9N2_PU_PSIHB_INTERRUPT_CONTROL_ESB_OR_LSI_INTERRUPTS        = 0   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_CONTROL_SM_RESET                     = 1   ;

static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_PSI_INTERRUPT_HIGH             = 0   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_OCC_INTERRUPT_HIGH             = 1   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_FSI_INTERRUPT_HIGH             = 2   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LPC_INTERRUPT_HIGH             = 3   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LOCAL_INTERRUPT_HIGH           = 4   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_SYSTEM_ATTENTION_HIGH          = 5   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_TPM_INTERRUPT_HIGH             = 6   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH       = 7   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH_LEN   = 4   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_SBE_OR_I2C_INTERRUPT_HIGH      = 11  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_DIO_INTERRUPT_HIGH             = 12  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_PSU_INTERRUPT_HIGH             = 13  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_I2C_C_INTERRUPT_HIGH           = 14  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_I2C_D_INTERRUPT_HIGH           = 15  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_I2C_E_INTERRUPT_HIGH           = 16  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_RESERVED                       = 17  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_RESERVED_LEN                   = 2   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_PURE_SBE_INTERRUPT_HIGH        = 19  ;

static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_PSI_INTERRUPT_PENDING         = 0   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_OCC_INTERRUPT_PENDING         = 1   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_FSI_INTERRUPT_PENDING         = 2   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LPC_INTERRUPT_PENDING         = 3   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LOCAL_INTERRUPT_PENDING       = 4   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_SYSTEM_ATTENTION              = 5   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_TPM_INTERRUPT_PENDING         = 6   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING   = 7   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING_LEN = 4   ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_SBE_INTERRUPT_PENDING         = 11  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_DIO_INTERRUPT_PENDING         = 12  ;
static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_PSU_INTERRUPT_PENDING         = 13  ;

static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_CMD_ENABLE                  = 0   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_ENABLE                 = 1   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PHBCSR_SPARE                    = 2   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INT_ENABLE                  = 3   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_ERR_RSP_ENABLE              = 4   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_LINK_ENABLE                 = 5   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_RESET                       = 6   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIHBC_RESET                    = 7   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK                   = 8   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK_LEN               = 4   ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_ST_EOI_ENABLE                   = 12  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_CEC_PSI_INTERRUPT               = 16  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INTERRUPT                   = 17  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_LINK_ACTIVE                 = 18  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_OUTBOUND_ACTIVE             = 19  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INBOUND_ACTIVE              = 20  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_LOAD_OUTSTANDING         = 21  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMAR_OUTSTANDING         = 22  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_INT_BUSY                 = 23  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_XMIT_ERROR                  = 32  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_LINK_INACTIVE_TRANS         = 33  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_ACK_TIMEOUT              = 34  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LOAD_TIMEOUT        = 35  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LENGTH_ERR          = 36  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_ADDR_ERR            = 37  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_TYPE_ERR            = 38  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_UE                          = 39  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_PERR                     = 40  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_ALERT1                      = 41  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_ALERT2                      = 42  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ERR                  = 43  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ADDR_ERR             = 48  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_TCE_EXTENT_ERR           = 49  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_PAGE_FAULT               = 50  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_INV_OP                   = 51  ;
static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INV_READ                    = 52  ;

static const uint8_t P9N2_PU_PSI_BRIDGE_BAR_REG_BAR                               = 8   ;
static const uint8_t P9N2_PU_PSI_BRIDGE_BAR_REG_BAR_LEN                           = 36  ;
static const uint8_t P9N2_PU_PSI_BRIDGE_BAR_REG_EN                                = 63  ;

static const uint8_t P9N2_PU_PSI_BRIDGE_FSP_BAR_REG_BAR                           = 8   ;
static const uint8_t P9N2_PU_PSI_BRIDGE_FSP_BAR_REG_BAR_LEN                       = 36  ;

static const uint8_t P9N2_PU_PSI_FSP_MMR_REG_MMR                                  = 32  ;
static const uint8_t P9N2_PU_PSI_FSP_MMR_REG_MMR_LEN                              = 12  ;

static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ADDR                                = 14  ;
static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ADDR_LEN                            = 34  ;
static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ENTRIES                             = 61  ;
static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ENTRIES_LEN                         = 3   ;

static const uint8_t P9N2_CAPP_PSLTTMAP0_VALID                                    = 0   ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_MATCH                              = 1   ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_MATCH_LEN                          = 5   ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MATCH                              = 6   ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MATCH_LEN                          = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MASK                               = 13  ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MASK_LEN                           = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_REPLACE                            = 20  ;
static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_REPLACE_LEN                        = 6   ;

static const uint8_t P9N2_CAPP_PSLTTMAP1_VALID                                    = 0   ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_MATCH                              = 1   ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_MATCH_LEN                          = 5   ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MATCH                              = 6   ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MATCH_LEN                          = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MASK                               = 13  ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MASK_LEN                           = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_REPLACE                            = 20  ;
static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_REPLACE_LEN                        = 6   ;

static const uint8_t P9N2_CAPP_PSLTTMAP2_VALID                                    = 0   ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_MATCH                              = 1   ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_MATCH_LEN                          = 5   ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MATCH                              = 6   ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MATCH_LEN                          = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MASK                               = 13  ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MASK_LEN                           = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_REPLACE                            = 20  ;
static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_REPLACE_LEN                        = 6   ;

static const uint8_t P9N2_CAPP_PSLTTMAP3_VALID                                    = 0   ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_MATCH                              = 1   ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_MATCH_LEN                          = 5   ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MATCH                              = 6   ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MATCH_LEN                          = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MASK                               = 13  ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MASK_LEN                           = 7   ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_REPLACE                            = 20  ;
static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_REPLACE_LEN                        = 6   ;

static const uint8_t P9N2_PU_NPU_PSL_DAR_AN_CO_EA                                 = 0   ;
static const uint8_t P9N2_PU_NPU_PSL_DAR_AN_CO_EA_LEN                             = 64  ;

static const uint8_t P9N2_PU_PSL_DAR_AN_CO_EA                                     = 0   ;
static const uint8_t P9N2_PU_PSL_DAR_AN_CO_EA_LEN                                 = 64  ;

static const uint8_t P9N2__SM3_PSL_DAR_AN_CO_EA                                   = 0   ;
static const uint8_t P9N2__SM3_PSL_DAR_AN_CO_EA_LEN                               = 64  ;

static const uint8_t P9N2_PU_NPU_SM3_PSL_DAR_AN_CO_EA                             = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_DAR_AN_CO_EA_LEN                         = 64  ;

static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_TF                                  = 3   ;
static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_S                                   = 38  ;
static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_CO_RSP                              = 56  ;
static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_CO_RSP_LEN                          = 8   ;

static const uint8_t P9N2_PU_PSL_DSISR_AN_TF                                      = 3   ;
static const uint8_t P9N2_PU_PSL_DSISR_AN_S                                       = 38  ;
static const uint8_t P9N2_PU_PSL_DSISR_AN_CO_RSP                                  = 56  ;
static const uint8_t P9N2_PU_PSL_DSISR_AN_CO_RSP_LEN                              = 8   ;

static const uint8_t P9N2__SM3_PSL_DSISR_AN_TF                                    = 3   ;
static const uint8_t P9N2__SM3_PSL_DSISR_AN_S                                     = 38  ;
static const uint8_t P9N2__SM3_PSL_DSISR_AN_CO_RSP                                = 56  ;
static const uint8_t P9N2__SM3_PSL_DSISR_AN_CO_RSP_LEN                            = 8   ;

static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_TF                              = 3   ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_S                               = 38  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_CO_RSP                          = 56  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_CO_RSP_LEN                      = 8   ;

static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_COMMAND_DIAL                    = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_COMMAND_DIAL_LEN                = 16  ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_PENDING_DIAL                    = 16  ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_LINK_DIAL                       = 48  ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_LINK_DIAL_LEN                   = 16  ;

static const uint8_t P9N2__DAT_PSL_LLCMD_A0_COMMAND_DIAL                          = 0   ;
static const uint8_t P9N2__DAT_PSL_LLCMD_A0_COMMAND_DIAL_LEN                      = 16  ;
static const uint8_t P9N2__DAT_PSL_LLCMD_A0_PENDING_DIAL                          = 16  ;
static const uint8_t P9N2__DAT_PSL_LLCMD_A0_LINK_DIAL                             = 48  ;
static const uint8_t P9N2__DAT_PSL_LLCMD_A0_LINK_DIAL_LEN                         = 16  ;

static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_AFUTAG                           = 16  ;
static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_AFUTAG_LEN                       = 16  ;
static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_PE_HANDLE                        = 48  ;
static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_PE_HANDLE_LEN                    = 16  ;

static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_AFUTAG                               = 16  ;
static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_AFUTAG_LEN                           = 16  ;
static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_PE_HANDLE                            = 48  ;
static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_PE_HANDLE_LEN                        = 16  ;

static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_AFUTAG                             = 16  ;
static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_AFUTAG_LEN                         = 16  ;
static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_PE_HANDLE                          = 48  ;
static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_PE_HANDLE_LEN                      = 16  ;

static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_AFUTAG                       = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_AFUTAG_LEN                   = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_PE_HANDLE                    = 48  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_PE_HANDLE_LEN                = 16  ;

static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_MULTI_AFU_DIAL                  = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_PC_DIAL                         = 48  ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_SS_DIAL                         = 54  ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_SS_DIAL_LEN                     = 2   ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_SC_DIAL                         = 63  ;

static const uint8_t P9N2__DAT_PSL_SCNTL_A0_MULTI_AFU_DIAL                        = 0   ;
static const uint8_t P9N2__DAT_PSL_SCNTL_A0_PC_DIAL                               = 48  ;
static const uint8_t P9N2__DAT_PSL_SCNTL_A0_SS_DIAL                               = 54  ;
static const uint8_t P9N2__DAT_PSL_SCNTL_A0_SS_DIAL_LEN                           = 2   ;
static const uint8_t P9N2__DAT_PSL_SCNTL_A0_SC_DIAL                               = 63  ;

static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A0_ADDR_DIAL                        = 4   ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A0_ADDR_DIAL_LEN                    = 48  ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A0_VALID_DIAL                       = 63  ;

static const uint8_t P9N2__DAT_PSL_SPAP_A0_ADDR_DIAL                              = 4   ;
static const uint8_t P9N2__DAT_PSL_SPAP_A0_ADDR_DIAL_LEN                          = 48  ;
static const uint8_t P9N2__DAT_PSL_SPAP_A0_VALID_DIAL                             = 63  ;

static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A1_ADDR_DIAL                        = 4   ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A1_ADDR_DIAL_LEN                    = 48  ;
static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A1_VALID_DIAL                       = 63  ;

static const uint8_t P9N2__DAT_PSL_SPAP_A1_ADDR_DIAL                              = 4   ;
static const uint8_t P9N2__DAT_PSL_SPAP_A1_ADDR_DIAL_LEN                          = 48  ;
static const uint8_t P9N2__DAT_PSL_SPAP_A1_VALID_DIAL                             = 63  ;

static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_ACK                                   = 28  ;
static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_C                                     = 29  ;
static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_AE                                    = 30  ;
static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_R                                     = 31  ;

static const uint8_t P9N2_PU_PSL_TFC_AN_ACK                                       = 28  ;
static const uint8_t P9N2_PU_PSL_TFC_AN_C                                         = 29  ;
static const uint8_t P9N2_PU_PSL_TFC_AN_AE                                        = 30  ;
static const uint8_t P9N2_PU_PSL_TFC_AN_R                                         = 31  ;

static const uint8_t P9N2__SM3_PSL_TFC_AN_ACK                                     = 28  ;
static const uint8_t P9N2__SM3_PSL_TFC_AN_C                                       = 29  ;
static const uint8_t P9N2__SM3_PSL_TFC_AN_AE                                      = 30  ;
static const uint8_t P9N2__SM3_PSL_TFC_AN_R                                       = 31  ;

static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_ACK                               = 28  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_C                                 = 29  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_AE                                = 30  ;
static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_R                                 = 31  ;

static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_0                              = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_1                              = 1   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_2                              = 2   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_3                              = 3   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_4                              = 4   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_5                              = 5   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_6                              = 6   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_7                              = 7   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_8                              = 8   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_9                              = 9   ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_10                             = 10  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_11                             = 11  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_12                             = 12  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_13                             = 13  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_14                             = 14  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_15                             = 15  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_0                         = 16  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_1                         = 17  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_2                         = 18  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_3                         = 19  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_4                         = 20  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_5                         = 21  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_6                         = 22  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_7                         = 23  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_8                         = 24  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_9                         = 25  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_10                        = 26  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_11                        = 27  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_12                        = 28  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_13                        = 29  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_14                        = 30  ;
static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_15                        = 31  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX0_REG_MBOX0                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX0_REG_MBOX0_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX1_REG_MBOX1                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX1_REG_MBOX1_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX2_REG_MBOX2                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX2_REG_MBOX2_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX3_REG_MBOX3                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX3_REG_MBOX3_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX4_REG_MBOX4                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX4_REG_MBOX4_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX5_REG_MBOX5                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX5_REG_MBOX5_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX6_REG_MBOX6                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX6_REG_MBOX6_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX7_REG_MBOX7                         = 0   ;
static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX7_REG_MBOX7_LEN                     = 64  ;

static const uint8_t P9N2_PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT                     = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT_LEN                 = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT                     = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT_LEN                 = 16  ;

static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_CONTENT                        = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_CONTENT_LEN                    = 32  ;
static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_MASK                           = 32  ;
static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_MASK_LEN                       = 32  ;

static const uint8_t P9N2_PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR0_STOP_TIMER_REG_TIMER                      = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR0_STOP_TIMER_REG_TIMER_LEN                  = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT                     = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT_LEN                 = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT                     = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT_LEN                 = 16  ;

static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_CONTENT                        = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_CONTENT_LEN                    = 32  ;
static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_MASK                           = 32  ;
static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_MASK_LEN                       = 32  ;

static const uint8_t P9N2_PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR1_STOP_TIMER_REG_TIMER                      = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR1_STOP_TIMER_REG_TIMER_LEN                  = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT                     = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT_LEN                 = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT                     = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT_LEN                 = 16  ;

static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_CONTENT                        = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_CONTENT_LEN                    = 32  ;
static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_MASK                           = 32  ;
static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_MASK_LEN                       = 32  ;

static const uint8_t P9N2_PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT               = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT_LEN           = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR2_STOP_TIMER_REG_TIMER                      = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR2_STOP_TIMER_REG_TIMER_LEN                  = 40  ;

static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE                = 0   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE_LEN            = 2   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_TIMER_EN       = 2   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT    = 3   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT_LEN = 3   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_START               = 6   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP                = 7   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE                = 8   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE_LEN            = 2   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_TIMER_EN       = 10  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT    = 11  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT_LEN = 3   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_START               = 14  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP                = 15  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE                = 16  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE_LEN            = 2   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_TIMER_EN       = 18  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT    = 19  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT_LEN = 3   ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_START               = 22  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP                = 23  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_CYCLECNT_RUNNING    = 24  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_BUSYCNT_RUNNING     = 25  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_CYCLECNT_RUNNING    = 26  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_BUSYCNT_RUNNING     = 27  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_CYCLECNT_RUNNING    = 28  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_BUSYCNT_RUNNING     = 29  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOPPED_ON_ERROR    = 30  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOPPED_ON_ERROR    = 31  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOPPED_ON_ERROR    = 32  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_RESET               = 33  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_RESET               = 34  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_RESET               = 35  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INCLUDE_TRAFFIC            = 36  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED                   = 37  ;
static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED_LEN               = 3   ;

static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST              = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST_LEN          = 64  ;

static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST           = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST_LEN       = 64  ;

static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST           = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST_LEN       = 64  ;

static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_MANUAL_MODE_EN      = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_START_NOT_STOP      = 1   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FREEZE_HISTORY      = 2   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESET_HISTORY       = 3   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_TRACE_TRAFFIC       = 4   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT    = 5   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT_LEN = 3   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FILTER_RD_NOT_WR    = 8   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FILTER_MASK_RD_NOT_WR = 9   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED            = 10  ;
static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED_LEN        = 6   ;

static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS                  = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS_LEN              = 32  ;
static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_MASK                     = 32  ;
static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_MASK_LEN                 = 32  ;

static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST                 = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST_LEN             = 64  ;

static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST              = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST_LEN          = 64  ;

static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST              = 0   ;
static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST_LEN          = 64  ;

static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_0                               = 0   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_1                               = 1   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_2                               = 2   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_3                               = 3   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_4                               = 4   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_5                               = 5   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_6                               = 6   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_7                               = 7   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_8                               = 8   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_9                               = 9   ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_10                              = 10  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_11                              = 11  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_12                              = 12  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_13                              = 13  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_14                              = 14  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_15                              = 15  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_0                          = 16  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_1                          = 17  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_2                          = 18  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_3                          = 19  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_4                          = 20  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_5                          = 21  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_6                          = 22  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_7                          = 23  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_8                          = 24  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_9                          = 25  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_10                         = 26  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_11                         = 27  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_12                         = 28  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_13                         = 29  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_14                         = 30  ;
static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_15                         = 31  ;

static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0                 = 0   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1                 = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2                 = 16  ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3                 = 24  ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4                 = 32  ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5                 = 40  ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6                 = 48  ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7                 = 56  ;
static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7_LEN             = 8   ;

static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8                 = 0   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9                 = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9_LEN             = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10                = 16  ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10_LEN            = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11                = 24  ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11_LEN            = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12                = 32  ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12_LEN            = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13                = 40  ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13_LEN            = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14                = 48  ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14_LEN            = 8   ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15                = 56  ;
static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN            = 8   ;

static const uint8_t P9N2_PEC_RECOV_INTERRUPT_REG_RECOV                           = 0   ;

static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_WSRC                             = 17  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_WSRC_LEN                         = 5   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_RSRC                             = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_RSRC_LEN                         = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_AIDX                             = 24  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_AIDX_LEN                         = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_ABANK                            = 32  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_ABANK_LEN                        = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_WSRC                             = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_WSRC_LEN                         = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_RSRC                             = 36  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_RSRC_LEN                         = 6   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_AIDX                             = 42  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_AIDX_LEN                         = 8   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_ABANK                            = 50  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_ABANK_LEN                        = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_WSRC                             = 52  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_WSRC_LEN                         = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_RSRC                             = 54  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_RSRC_LEN                         = 2   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_AIDX                             = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_AIDX_LEN                         = 8   ;

static const uint8_t P9N2_PU_NPU2_NTL1_REM1_PBRX_RTAG                             = 34  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM1_PBRX_RTAG_LEN                         = 22  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_ADR                               = 56  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_ADR_LEN                           = 3   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_TYPE                              = 59  ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_TYPE_LEN                          = 4   ;
static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_SZ                                = 63  ;

static const uint8_t P9N2_PU_RESET_REGISTER_CHICKEN_SWITCH                        = 0   ;

static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0  = 0   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0_LEN = 16  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0    = 32  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0_LEN = 8   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_LBUS_PARITY_ERR1_0 = 40  ;

static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1  = 0   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1_LEN = 16  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1    = 32  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1_LEN = 8   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_LBUS_PARITY_ERR1_1 = 40  ;

static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2  = 0   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2_LEN = 16  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2    = 32  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2_LEN = 8   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_LBUS_PARITY_ERR1_2 = 40  ;

static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3  = 0   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3_LEN = 16  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3    = 32  ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3_LEN = 8   ;
static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_LBUS_PARITY_ERR1_3 = 40  ;

static const uint8_t P9N2_PEC_RFIR_IN0                                            = 0   ;
static const uint8_t P9N2_PEC_RFIR_LFIR_RECOV_ERR                                 = 1   ;
static const uint8_t P9N2_PEC_RFIR_IN4                                            = 2   ;
static const uint8_t P9N2_PEC_RFIR_IN5                                            = 3   ;
static const uint8_t P9N2_PEC_RFIR_IN6                                            = 4   ;
static const uint8_t P9N2_PEC_RFIR_IN7                                            = 5   ;
static const uint8_t P9N2_PEC_RFIR_IN7_LEN                                        = 19  ;

static const uint8_t P9N2_PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE                  = 1   ;
static const uint8_t P9N2_PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              = 15  ;

static const uint8_t P9N2_PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE                  = 1   ;
static const uint8_t P9N2_PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              = 15  ;

static const uint8_t P9N2_PU_RING_FENCE_MASK_LATCH_REG_ENABLE                     = 1   ;
static const uint8_t P9N2_PU_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                 = 15  ;

static const uint8_t P9N2_PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE                  = 1   ;
static const uint8_t P9N2_PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              = 15  ;

static const uint8_t P9N2_PEC_RING_FENCE_MASK_LATCH_REG_ENABLE                    = 1   ;
static const uint8_t P9N2_PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                = 15  ;

static const uint8_t P9N2_PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE                  = 1   ;
static const uint8_t P9N2_PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              = 15  ;

static const uint8_t P9N2__CTL_RLX_CONFIG_BRK0_CLUSTER                            = 0   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK0_CLUSTER_LEN                        = 3   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK1_CLUSTER                            = 3   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK1_CLUSTER_LEN                        = 3   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK2_CLUSTER                            = 6   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK2_CLUSTER_LEN                        = 3   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK3_CLUSTER                            = 9   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK3_CLUSTER_LEN                        = 3   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK4_CLUSTER                            = 12  ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK4_CLUSTER_LEN                        = 3   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK5_CLUSTER                            = 15  ;
static const uint8_t P9N2__CTL_RLX_CONFIG_BRK5_CLUSTER_LEN                        = 3   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_RESERVED1                               = 18  ;
static const uint8_t P9N2__CTL_RLX_CONFIG_RESERVED1_LEN                           = 2   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_SYNC_BRK                                = 20  ;
static const uint8_t P9N2__CTL_RLX_CONFIG_SYNC_BRK_LEN                            = 6   ;
static const uint8_t P9N2__CTL_RLX_CONFIG_IDIAL_ISSYNC                            = 26  ;
static const uint8_t P9N2__CTL_RLX_CONFIG_IDIAL_ISSYNC_LEN                        = 6   ;

static const uint8_t P9N2_PU_RNG_FAILED_INT_ENABLE                                = 0   ;
static const uint8_t P9N2_PU_RNG_FAILED_INT_ADDRESS                               = 8   ;
static const uint8_t P9N2_PU_RNG_FAILED_INT_ADDRESS_LEN                           = 44  ;

static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED1_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_START                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_START_LEN                        = 9   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED2_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_END                              = 15  ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_END_LEN                          = 9   ;

static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_START                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_START_LEN                         = 9   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_END                               = 15  ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_END_LEN                           = 9   ;

static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED1_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_START                            = 3   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_START_LEN                        = 9   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED2_LEN                    = 3   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_END                              = 15  ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_END_LEN                          = 9   ;

static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED1_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_START                             = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_START_LEN                         = 9   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED2_LEN                     = 3   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_END                               = 15  ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_END_LEN                           = 9   ;

static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED1_LEN                           = 3   ;
static const uint8_t P9N2__SM2_RSP_DA_PTR_START                                   = 3   ;
static const uint8_t P9N2__SM2_RSP_DA_PTR_START_LEN                               = 9   ;
static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED2_LEN                           = 3   ;
static const uint8_t P9N2__SM2_RSP_DA_PTR_END                                     = 15  ;
static const uint8_t P9N2__SM2_RSP_DA_PTR_END_LEN                                 = 9   ;

static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED1_LEN                           = 3   ;
static const uint8_t P9N2__SM1_RSP_DA_PTR_START                                   = 3   ;
static const uint8_t P9N2__SM1_RSP_DA_PTR_START_LEN                               = 9   ;
static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED2_LEN                           = 3   ;
static const uint8_t P9N2__SM1_RSP_DA_PTR_END                                     = 15  ;
static const uint8_t P9N2__SM1_RSP_DA_PTR_END_LEN                                 = 9   ;

static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_START                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_START_LEN                         = 7   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_END                               = 17  ;
static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_END_LEN                           = 7   ;

static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED1                        = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED1_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_START                            = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_START_LEN                        = 7   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED2                        = 12  ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED2_LEN                    = 5   ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_END                              = 17  ;
static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_END_LEN                          = 7   ;

static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED1                         = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED1_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_START                             = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_START_LEN                         = 7   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED2                         = 12  ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED2_LEN                     = 5   ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_END                               = 17  ;
static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_END_LEN                           = 7   ;

static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED1_LEN                           = 5   ;
static const uint8_t P9N2__SM2_RSP_HA_PTR_START                                   = 5   ;
static const uint8_t P9N2__SM2_RSP_HA_PTR_START_LEN                               = 7   ;
static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED2_LEN                           = 5   ;
static const uint8_t P9N2__SM2_RSP_HA_PTR_END                                     = 17  ;
static const uint8_t P9N2__SM2_RSP_HA_PTR_END_LEN                                 = 7   ;

static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED1                               = 0   ;
static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED1_LEN                           = 5   ;
static const uint8_t P9N2__SM1_RSP_HA_PTR_START                                   = 5   ;
static const uint8_t P9N2__SM1_RSP_HA_PTR_START_LEN                               = 7   ;
static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED2                               = 12  ;
static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED2_LEN                           = 5   ;
static const uint8_t P9N2__SM1_RSP_HA_PTR_END                                     = 17  ;
static const uint8_t P9N2__SM1_RSP_HA_PTR_END_LEN                                 = 7   ;

static const uint8_t P9N2_PU_RX_CH_FSM_REG_RX_CH_FSM                              = 0   ;
static const uint8_t P9N2_PU_RX_CH_FSM_REG_RX_CH_FSM_LEN                          = 2   ;

static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_0                        = 0   ;
static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_1                        = 1   ;
static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_2                        = 2   ;
static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_3                        = 3   ;
static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_4                        = 4   ;
static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_5                        = 5   ;
static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_6                        = 6   ;
static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_7                        = 7   ;

static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM0                                  = 0   ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM0_LEN                              = 3   ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM1                                  = 3   ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM1_LEN                              = 4   ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_TFRAMESIZE                            = 7   ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_TFRAMESIZE_LEN                        = 5   ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_WEN0                                  = 12  ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_WEN1                                  = 13  ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_WEN2                                  = 14  ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_EN_SCRD                               = 15  ;
static const uint8_t P9N2_PU_RX_CH_MISC_REG_STTRTOGX                              = 16  ;

static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF                 = 0   ;
static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_RXSC                                = 1   ;
static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI            = 2   ;
static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_CRC_MODE                            = 3   ;
static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_ENABLE_SCRD_FR_RXRF                 = 4   ;
static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_ENABLE_STREAMING_MODE               = 5   ;
static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_CHIP_INTERFACEMODE                  = 6   ;
static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_CHIP_PERSONALISATION                = 7   ;

static const uint8_t P9N2_PU_RX_DBFF_REG0_DATA_BUFF0                              = 0   ;
static const uint8_t P9N2_PU_RX_DBFF_REG0_DATA_BUFF0_LEN                          = 32  ;

static const uint8_t P9N2_PU_RX_DBFF_REG1_DATA_BUFF1                              = 0   ;
static const uint8_t P9N2_PU_RX_DBFF_REG1_DATA_BUFF1_LEN                          = 32  ;

static const uint8_t P9N2_PU_RX_DF_FSM_REG_RX_DF_FSM                              = 0   ;
static const uint8_t P9N2_PU_RX_DF_FSM_REG_RX_DF_FSM_LEN                          = 4   ;

static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_RFGSHIFT_PCK                = 0   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_RZRTMP_PCK                  = 1   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_DATA_PCK                    = 2   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXEI_SHIFT_PCK                    = 3   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXEI_TRANSMIT_PCK                 = 4   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_OVERRUN                     = 5   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXBFF_DATA_PCK                    = 6   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXBFF_DATAO_PCK                   = 7   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXBFF_RFC_PCK                     = 8   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_FSM_PCK                      = 9   ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRXLC_DATA_BUFF_PCK                = 10  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_DATA_PCK                     = 11  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_RADDR_PCK                    = 12  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_RCTRL_PCK                    = 13  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRXLC_UE_RF                        = 14  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C0_PSIRXLC_CE_RF                        = 15  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_DATA_GXST1_PCK_2N            = 16  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRFACC_RADDR_PCK                   = 17  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRFACC_RCTRL_PCK                   = 18  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRFACC_RFSM_PCK                    = 19  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRFACC_RDL_FSM_PCK                 = 20  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C4_PSIRFACC_RXSC_PCK                    = 21  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C0_PSIRFACC_RLINK_STATE_LT_02           = 22  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C0_PSIRFACC_C_RXDATA_RDY_ERR            = 23  ;
static const uint8_t P9N2_PU_RX_ERROR_REG_C0_ERRACK_RISE                          = 24  ;

static const uint8_t P9N2_PU_RX_ERR_MODE_RX_ERR_MODE_0                            = 0   ;
static const uint8_t P9N2_PU_RX_ERR_MODE_RX_ERR_MODE_1                            = 1   ;

static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_RFGSHIFT_PCK                    = 0   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_RZRTMP_PCK                      = 1   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_DATA_PCK                        = 2   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXEI_SHIFT_PCK                        = 3   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXEI_TRANSMIT_PCK                     = 4   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_OVERRUN                         = 5   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXBFF_DATA_PCK                        = 6   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXBFF_DATAO_PCK                       = 7   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXBFF_RFC_PCK                         = 8   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_FSM_PCK                          = 9   ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_DATA_BUFF_PCK                    = 10  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_DATA_PCK                         = 11  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_RADDR_PCK                        = 12  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_RCTRL_PCK                        = 13  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_UE_RF                            = 14  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_CE_RF                            = 15  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_DATA_GXST1_PCK_2N                = 16  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RADDR_PCK                       = 17  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RCTRL_PCK                       = 18  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RFSM_PCK                        = 19  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RDL_FSM_PCK                     = 20  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RXSC_PCK                        = 21  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RLINK_STATE_LT_02               = 22  ;
static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_C_RXDATA_RDY_ERR                = 23  ;
static const uint8_t P9N2_PU_RX_MASK_REG_C0_ERRACK_RISE                           = 24  ;

static const uint8_t P9N2_PU_RX_PSI_CNTL_RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL      = 0   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_PATTERN_CHECK_EN                         = 1   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_PATTERN_SEL                              = 2   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_PATTERN_SEL_LEN                          = 2   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_CLK_INVERT                               = 4   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_LANE_INVERT                              = 5   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_PDWN                                     = 6   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_CLK_DLY                                  = 7   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_CLK_DLY_LEN                              = 7   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_DATA_DLY                                 = 14  ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_DATA_DLY_LEN                             = 7   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY                         = 21  ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY_LEN                     = 5   ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY                        = 26  ;
static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY_LEN                    = 5   ;

static const uint8_t P9N2_PU_RX_PSI_MODE_VREF                                     = 0   ;
static const uint8_t P9N2_PU_RX_PSI_MODE_VREF_LEN                                 = 8   ;
static const uint8_t P9N2_PU_RX_PSI_MODE_TERM_TEST                                = 12  ;
static const uint8_t P9N2_PU_RX_PSI_MODE_TERM_ENC                                 = 15  ;
static const uint8_t P9N2_PU_RX_PSI_MODE_TERM_ENC_LEN                             = 5   ;
static const uint8_t P9N2_PU_RX_PSI_MODE_PEAK                                     = 20  ;
static const uint8_t P9N2_PU_RX_PSI_MODE_PEAK_LEN                                 = 3   ;
static const uint8_t P9N2_PU_RX_PSI_MODE_SPARE                                    = 24  ;
static const uint8_t P9N2_PU_RX_PSI_MODE_SPARE_LEN                                = 8   ;

static const uint8_t P9N2_PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_PASS_RO_SIGNAL    = 0   ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_FAIL_RO_SIGNAL    = 1   ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_RX_PSI_NO_PATTERN_FOUND_RO_SIGNAL      = 2   ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_LD_UNLD_DLY                            = 4   ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_LD_UNLD_DLY_LEN                        = 4   ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_OVER_OR_UNDERRUN_ERR                   = 8   ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_CLEAR                                  = 9   ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_SPARE                                  = 10  ;
static const uint8_t P9N2_PU_RX_PSI_STATUS_SPARE_LEN                              = 6   ;

static const uint8_t P9N2_PEC_SCAN32_SCAN32_REG                                   = 0   ;
static const uint8_t P9N2_PEC_SCAN32_SCAN32_REG_LEN                               = 32  ;

static const uint8_t P9N2_PEC_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG                   = 0   ;
static const uint8_t P9N2_PEC_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG_LEN               = 32  ;

static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_SYSTEM_FAST_INIT                   = 0   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_VITL                               = 3   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_PERV                               = 4   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT1                              = 5   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT2                              = 6   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT3                              = 7   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT4                              = 8   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT5                              = 9   ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT6                              = 10  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT7                              = 11  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT8                              = 12  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT9                              = 13  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT10                             = 14  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_FUNC                               = 48  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_CFG                                = 49  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_CCFG_GPTR                          = 50  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_REGF                               = 51  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_LBIST                              = 52  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_ABIST                              = 53  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_REPR                               = 54  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_TIME                               = 55  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_BNDY                               = 56  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_FARR                               = 57  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_CMSK                               = 58  ;
static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_INEX                               = 59  ;

static const uint8_t P9N2_PEC_SCOM0X00_LINKEN                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X00_LINKRST                                    = 49  ;
static const uint8_t P9N2_PEC_SCOM0X00_CFGPTR                                     = 51  ;
static const uint8_t P9N2_PEC_SCOM0X00_CFGPTR_LEN                                 = 2   ;
static const uint8_t P9N2_PEC_SCOM0X00_CFGEXT                                     = 53  ;
static const uint8_t P9N2_PEC_SCOM0X00_CFGACT                                     = 54  ;
static const uint8_t P9N2_PEC_SCOM0X00_RXLOOP                                     = 55  ;
static const uint8_t P9N2_PEC_SCOM0X00_TXRSTEN                                    = 56  ;
static const uint8_t P9N2_PEC_SCOM0X00_PLLSEL                                     = 57  ;
static const uint8_t P9N2_PEC_SCOM0X00_DCKSEL                                     = 59  ;
static const uint8_t P9N2_PEC_SCOM0X00_BWSEL                                      = 60  ;
static const uint8_t P9N2_PEC_SCOM0X00_BWSEL_LEN                                  = 2   ;
static const uint8_t P9N2_PEC_SCOM0X00_RTSEL                                      = 62  ;
static const uint8_t P9N2_PEC_SCOM0X00_RTSEL_LEN                                  = 2   ;

static const uint8_t P9N2_PEC_SCOM0X01_SPSEL                                      = 50  ;
static const uint8_t P9N2_PEC_SCOM0X01_SPSEL_LEN                                  = 2   ;
static const uint8_t P9N2_PEC_SCOM0X01_FRCERR                                     = 52  ;
static const uint8_t P9N2_PEC_SCOM0X01_ERROR                                      = 54  ;
static const uint8_t P9N2_PEC_SCOM0X01_SYNC                                       = 55  ;
static const uint8_t P9N2_PEC_SCOM0X01_TPGMD                                      = 57  ;
static const uint8_t P9N2_PEC_SCOM0X01_MPCHK                                      = 58  ;
static const uint8_t P9N2_PEC_SCOM0X01_PRST                                       = 59  ;
static const uint8_t P9N2_PEC_SCOM0X01_TPSEL                                      = 60  ;
static const uint8_t P9N2_PEC_SCOM0X01_TPSEL_LEN                                  = 4   ;

static const uint8_t P9N2_PEC_SCOM0X02_ZCALOVRD                                   = 55  ;
static const uint8_t P9N2_PEC_SCOM0X02_OCOEF                                      = 60  ;
static const uint8_t P9N2_PEC_SCOM0X02_COEFRST                                    = 61  ;
static const uint8_t P9N2_PEC_SCOM0X02_OSEG                                       = 62  ;
static const uint8_t P9N2_PEC_SCOM0X02_ALOAD                                      = 63  ;

static const uint8_t P9N2_PEC_SCOM0X03_ASPAREC                                    = 53  ;
static const uint8_t P9N2_PEC_SCOM0X03_ASPAREC_LEN                                = 3   ;
static const uint8_t P9N2_PEC_SCOM0X03_DRVHIZ                                     = 58  ;
static const uint8_t P9N2_PEC_SCOM0X03_SASIMP                                     = 59  ;
static const uint8_t P9N2_PEC_SCOM0X03_SSTBW                                      = 63  ;

static const uint8_t P9N2_PEC_SCOM0X04_DCCEN                                      = 59  ;

static const uint8_t P9N2_PEC_SCOM0X05_CSSTEP                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X05_CSLOCK                                     = 49  ;
static const uint8_t P9N2_PEC_SCOM0X05_ALIGNSAM                                   = 56  ;
static const uint8_t P9N2_PEC_SCOM0X05_RSYNCC                                     = 57  ;
static const uint8_t P9N2_PEC_SCOM0X05_THRSHCNT                                   = 58  ;
static const uint8_t P9N2_PEC_SCOM0X05_THRSHCNT_LEN                               = 4   ;
static const uint8_t P9N2_PEC_SCOM0X05_THRSHMULT                                  = 62  ;
static const uint8_t P9N2_PEC_SCOM0X05_THRSHMULT_LEN                              = 2   ;

static const uint8_t P9N2_PEC_SCOM0X06_CALSSTN                                    = 50  ;
static const uint8_t P9N2_PEC_SCOM0X06_CALSSTN_LEN                                = 7   ;
static const uint8_t P9N2_PEC_SCOM0X06_CALSSTP                                    = 57  ;
static const uint8_t P9N2_PEC_SCOM0X06_CALSSTP_LEN                                = 7   ;

static const uint8_t P9N2_PEC_SCOM0X07_OFFSET                                     = 53  ;
static const uint8_t P9N2_PEC_SCOM0X07_OFFSET_LEN                                 = 5   ;
static const uint8_t P9N2_PEC_SCOM0X07_OVRDOFF                                    = 58  ;
static const uint8_t P9N2_PEC_SCOM0X07_OFFSETOVRD                                 = 59  ;
static const uint8_t P9N2_PEC_SCOM0X07_OFFSETOVRD_LEN                             = 5   ;

static const uint8_t P9N2_PEC_SCOM0X08_MARGIN                                     = 51  ;
static const uint8_t P9N2_PEC_SCOM0X08_MARGIN_LEN                                 = 3   ;
static const uint8_t P9N2_PEC_SCOM0X08_POSTCOEF                                   = 54  ;
static const uint8_t P9N2_PEC_SCOM0X08_POSTCOEF_LEN                               = 5   ;
static const uint8_t P9N2_PEC_SCOM0X08_PRECOEFF                                   = 59  ;
static const uint8_t P9N2_PEC_SCOM0X08_PRECOEFF_LEN                               = 5   ;

static const uint8_t P9N2_PEC_SCOM0X09_BYTE1                                      = 48  ;
static const uint8_t P9N2_PEC_SCOM0X09_BYTE1_LEN                                  = 8   ;
static const uint8_t P9N2_PEC_SCOM0X09_BYTE0                                      = 56  ;
static const uint8_t P9N2_PEC_SCOM0X09_BYTE0_LEN                                  = 8   ;

static const uint8_t P9N2_PEC_SCOM0X0A_REQWOV                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X0A_SMODE                                      = 53  ;
static const uint8_t P9N2_PEC_SCOM0X0A_SMODE_LEN                                  = 3   ;
static const uint8_t P9N2_PEC_SCOM0X0A_ADCORR                                     = 56  ;
static const uint8_t P9N2_PEC_SCOM0X0A_TRAINEN                                    = 57  ;
static const uint8_t P9N2_PEC_SCOM0X0A_ASAMPQ                                     = 58  ;
static const uint8_t P9N2_PEC_SCOM0X0A_ASAMPQ_LEN                                 = 3   ;
static const uint8_t P9N2_PEC_SCOM0X0A_ASAMP                                      = 61  ;
static const uint8_t P9N2_PEC_SCOM0X0A_ASAMP_LEN                                  = 3   ;

static const uint8_t P9N2_PEC_SCOM0X0B_MARGIN                                     = 51  ;
static const uint8_t P9N2_PEC_SCOM0X0B_MARGIN_LEN                                 = 3   ;
static const uint8_t P9N2_PEC_SCOM0X0B_POSTCOEFF                                  = 54  ;
static const uint8_t P9N2_PEC_SCOM0X0B_POSTCOEFF_LEN                              = 5   ;
static const uint8_t P9N2_PEC_SCOM0X0B_PRECOEFF                                   = 59  ;
static const uint8_t P9N2_PEC_SCOM0X0B_PRECOEFF_LEN                               = 5   ;

static const uint8_t P9N2_PEC_SCOM0X0C_PEAK                                       = 48  ;
static const uint8_t P9N2_PEC_SCOM0X0C_PEAK_LEN                                   = 6   ;
static const uint8_t P9N2_PEC_SCOM0X0C_SHORTV                                     = 54  ;
static const uint8_t P9N2_PEC_SCOM0X0C_PEAKIND                                    = 56  ;
static const uint8_t P9N2_PEC_SCOM0X0C_PEAKIND_LEN                                = 2   ;
static const uint8_t P9N2_PEC_SCOM0X0C_VGAIN                                      = 58  ;
static const uint8_t P9N2_PEC_SCOM0X0C_VGAIN_LEN                                  = 6   ;

static const uint8_t P9N2_PEC_SCOM0X0D_TXPOL                                      = 57  ;
static const uint8_t P9N2_PEC_SCOM0X0D_TXPOL_LEN                                  = 3   ;
static const uint8_t P9N2_PEC_SCOM0X0D_LBPOL                                      = 60  ;
static const uint8_t P9N2_PEC_SCOM0X0D_NXTPOL                                     = 61  ;
static const uint8_t P9N2_PEC_SCOM0X0D_NXTPOL_LEN                                 = 3   ;

static const uint8_t P9N2_PEC_SCOM0X0E_REFVOLT                                    = 52  ;
static const uint8_t P9N2_PEC_SCOM0X0E_REFVOLT_LEN                                = 8   ;
static const uint8_t P9N2_PEC_SCOM0X0E_PRESULT                                    = 60  ;
static const uint8_t P9N2_PEC_SCOM0X0E_NRESULT                                    = 61  ;
static const uint8_t P9N2_PEC_SCOM0X0E_TDREN                                      = 63  ;

static const uint8_t P9N2_PEC_SCOM0X0F_OFFSET                                     = 59  ;
static const uint8_t P9N2_PEC_SCOM0X0F_OFFSET_LEN                                 = 5   ;

static const uint8_t P9N2_PEC_SCOM0X10_PRESEG0P                                   = 53  ;
static const uint8_t P9N2_PEC_SCOM0X10_PRESEG0P_LEN                               = 11  ;

static const uint8_t P9N2_PEC_SCOM0X11_PRESEG1P                                   = 53  ;
static const uint8_t P9N2_PEC_SCOM0X11_PRESEG1P_LEN                               = 11  ;

static const uint8_t P9N2_PEC_SCOM0X12_MAINSEG0P                                  = 49  ;
static const uint8_t P9N2_PEC_SCOM0X12_MAINSEG0P_LEN                              = 15  ;

static const uint8_t P9N2_PEC_SCOM0X13_MAINSEG1P                                  = 49  ;
static const uint8_t P9N2_PEC_SCOM0X13_MAINSEG1P_LEN                              = 15  ;

static const uint8_t P9N2_PEC_SCOM0X14_POSTSEG0P                                  = 50  ;
static const uint8_t P9N2_PEC_SCOM0X14_POSTSEG0P_LEN                              = 14  ;

static const uint8_t P9N2_PEC_SCOM0X15_POSTSEG1P                                  = 50  ;
static const uint8_t P9N2_PEC_SCOM0X15_POSTSEG1P_LEN                              = 14  ;

static const uint8_t P9N2_PEC_SCOM0X16_PRESEG0N                                   = 53  ;
static const uint8_t P9N2_PEC_SCOM0X16_PRESEG0N_LEN                               = 11  ;

static const uint8_t P9N2_PEC_SCOM0X17_PRESEG1N                                   = 53  ;
static const uint8_t P9N2_PEC_SCOM0X17_PRESEG1N_LEN                               = 11  ;

static const uint8_t P9N2_PEC_SCOM0X18_MAINSEG0N                                  = 49  ;
static const uint8_t P9N2_PEC_SCOM0X18_MAINSEG0N_LEN                              = 15  ;

static const uint8_t P9N2_PEC_SCOM0X19_MAINSEG1N                                  = 49  ;
static const uint8_t P9N2_PEC_SCOM0X19_MAINSEG1N_LEN                              = 15  ;

static const uint8_t P9N2_PEC_SCOM0X1A_POSTSEG0N                                  = 50  ;
static const uint8_t P9N2_PEC_SCOM0X1A_POSTSEG0N_LEN                              = 14  ;

static const uint8_t P9N2_PEC_SCOM0X1B_POSTSEG1N                                  = 50  ;
static const uint8_t P9N2_PEC_SCOM0X1B_POSTSEG1N_LEN                              = 14  ;

static const uint8_t P9N2_PEC_SCOM0X1C_DPCMD                                      = 49  ;
static const uint8_t P9N2_PEC_SCOM0X1C_DPCCVG                                     = 50  ;
static const uint8_t P9N2_PEC_SCOM0X1C_DPCTGT                                     = 52  ;
static const uint8_t P9N2_PEC_SCOM0X1C_DPCTGT_LEN                                 = 3   ;
static const uint8_t P9N2_PEC_SCOM0X1C_BLKH1T                                     = 55  ;
static const uint8_t P9N2_PEC_SCOM0X1C_BLKOAE                                     = 56  ;
static const uint8_t P9N2_PEC_SCOM0X1C_H1TGT                                      = 57  ;
static const uint8_t P9N2_PEC_SCOM0X1C_H1TGT_LEN                                  = 3   ;
static const uint8_t P9N2_PEC_SCOM0X1C_OAE                                        = 60  ;
static const uint8_t P9N2_PEC_SCOM0X1C_OAE_LEN                                    = 4   ;

static const uint8_t P9N2_PEC_SCOM0X1D_OLS                                        = 48  ;
static const uint8_t P9N2_PEC_SCOM0X1D_OLS_LEN                                    = 5   ;
static const uint8_t P9N2_PEC_SCOM0X1D_OES                                        = 53  ;
static const uint8_t P9N2_PEC_SCOM0X1D_OES_LEN                                    = 5   ;
static const uint8_t P9N2_PEC_SCOM0X1D_BLKODEC                                    = 58  ;
static const uint8_t P9N2_PEC_SCOM0X1D_VIEWSCAN                                   = 59  ;
static const uint8_t P9N2_PEC_SCOM0X1D_ODEC                                       = 60  ;
static const uint8_t P9N2_PEC_SCOM0X1D_ODEC_LEN                                   = 4   ;

static const uint8_t P9N2_PEC_SCOM0X1E_XDATA                                      = 48  ;
static const uint8_t P9N2_PEC_SCOM0X1E_XDATA_LEN                                  = 16  ;

static const uint8_t P9N2_PEC_SCOM0X1F_XADDR                                      = 58  ;
static const uint8_t P9N2_PEC_SCOM0X1F_XADDR_LEN                                  = 5   ;

static const uint8_t P9N2_PEC_SCOM0X20_XDAT10                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X20_XDAT10_LEN                                 = 16  ;

static const uint8_t P9N2_PEC_SCOM0X21_XDAT32                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X21_XDAT32_LEN                                 = 16  ;

static const uint8_t P9N2_PEC_SCOM0X22_XDAT54                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X22_XDAT54_LEN                                 = 16  ;

static const uint8_t P9N2_PEC_SCOM0X23_XDAT76                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X23_XDAT76_LEN                                 = 16  ;

static const uint8_t P9N2_PEC_SCOM0X24_LOFO4                                      = 50  ;
static const uint8_t P9N2_PEC_SCOM0X24_LOFO4_LEN                                  = 6   ;
static const uint8_t P9N2_PEC_SCOM0X24_LOFO3                                      = 58  ;
static const uint8_t P9N2_PEC_SCOM0X24_LOFO3_LEN                                  = 6   ;

static const uint8_t P9N2_PEC_SCOM0X25_E1AMP                                      = 50  ;
static const uint8_t P9N2_PEC_SCOM0X25_E1AMP_LEN                                  = 6   ;
static const uint8_t P9N2_PEC_SCOM0X25_E0AMP                                      = 58  ;
static const uint8_t P9N2_PEC_SCOM0X25_E0AMP_LEN                                  = 6   ;

static const uint8_t P9N2_PEC_SCOM0X26_FINITLOFF                                  = 48  ;
static const uint8_t P9N2_PEC_SCOM0X26_LFREG                                      = 51  ;
static const uint8_t P9N2_PEC_SCOM0X26_LFRC                                       = 52  ;
static const uint8_t P9N2_PEC_SCOM0X26_LFSEL                                      = 53  ;
static const uint8_t P9N2_PEC_SCOM0X26_LFSEL_LEN                                  = 3   ;
static const uint8_t P9N2_PEC_SCOM0X26_PKINIT                                     = 58  ;
static const uint8_t P9N2_PEC_SCOM0X26_PKINIT_LEN                                 = 6   ;

static const uint8_t P9N2_PEC_SCOM0X27_SDPDOV                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X27_OFFAMP                                     = 51  ;
static const uint8_t P9N2_PEC_SCOM0X27_OFFAMP_LEN                                 = 5   ;
static const uint8_t P9N2_PEC_SCOM0X27_SDACDC                                     = 56  ;
static const uint8_t P9N2_PEC_SCOM0X27_SDPDN                                      = 57  ;
static const uint8_t P9N2_PEC_SCOM0X27_SIGDET                                     = 58  ;
static const uint8_t P9N2_PEC_SCOM0X27_SDLVL                                      = 59  ;
static const uint8_t P9N2_PEC_SCOM0X27_SDLVL_LEN                                  = 5   ;

static const uint8_t P9N2_PEC_SCOM0X28_DCCTIMEDOUT                                = 48  ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCTIMEEN                                  = 49  ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCLOCK                                    = 50  ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCOFFSET                                  = 51  ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCOFFSET_LEN                              = 5   ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCSTEP                                    = 56  ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCSTEP_LEN                                = 2   ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCASTEP                                   = 58  ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCASTEP_LEN                               = 5   ;
static const uint8_t P9N2_PEC_SCOM0X28_DCCAEN                                     = 63  ;

static const uint8_t P9N2_PEC_SCOM0X29_DCCOUT                                     = 51  ;
static const uint8_t P9N2_PEC_SCOM0X29_DCCCLK                                     = 52  ;
static const uint8_t P9N2_PEC_SCOM0X29_DCCHOLD                                    = 53  ;
static const uint8_t P9N2_PEC_SCOM0X29_DCCSIGN                                    = 54  ;
static const uint8_t P9N2_PEC_SCOM0X29_DCCSIGN_LEN                                = 2   ;
static const uint8_t P9N2_PEC_SCOM0X29_DCCAMP                                     = 56  ;
static const uint8_t P9N2_PEC_SCOM0X29_DCCAMP_LEN                                 = 7   ;
static const uint8_t P9N2_PEC_SCOM0X29_DCCOEN                                     = 63  ;

static const uint8_t P9N2_PEC_SCOM0X2A_DCCTMOUT                                   = 48  ;
static const uint8_t P9N2_PEC_SCOM0X2A_DCCTMOUT_LEN                               = 16  ;

static const uint8_t P9N2_PEC_SCOM0X2B_DCCASIGNNEG                                = 55  ;
static const uint8_t P9N2_PEC_SCOM0X2B_DCCASIGNPOS                                = 56  ;
static const uint8_t P9N2_PEC_SCOM0X2B_DCCAAMP                                    = 57  ;
static const uint8_t P9N2_PEC_SCOM0X2B_DCCAAMP_LEN                                = 7   ;

static const uint8_t P9N2_PEC_SCOM0X2C_VREFSEL                                    = 48  ;
static const uint8_t P9N2_PEC_SCOM0X2C_VREFSEL_LEN                                = 5   ;
static const uint8_t P9N2_PEC_SCOM0X2C_RDETCNTL                                   = 53  ;
static const uint8_t P9N2_PEC_SCOM0X2C_RDETCNTL_LEN                               = 5   ;
static const uint8_t P9N2_PEC_SCOM0X2C_RDETDRV                                    = 58  ;
static const uint8_t P9N2_PEC_SCOM0X2C_RDETDRV_LEN                                = 3   ;
static const uint8_t P9N2_PEC_SCOM0X2C_RDETWAIT                                   = 61  ;
static const uint8_t P9N2_PEC_SCOM0X2C_RDETWAIT_LEN                               = 3   ;

static const uint8_t P9N2_PEC_SCOM0X2D_RCVDETMFT                                  = 48  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETOUTN                                   = 55  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETOUTP                                   = 56  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETRSLT1                                  = 57  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETRSLT2                                  = 58  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETEN                                     = 59  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETOVRD                                   = 60  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETVAL                                    = 61  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETBYP                                    = 62  ;
static const uint8_t P9N2_PEC_SCOM0X2D_RDETFRC                                    = 63  ;

static const uint8_t P9N2_PEC_SCOM0X2E_TXEQ1                                      = 48  ;
static const uint8_t P9N2_PEC_SCOM0X2E_TXEQ1_LEN                                  = 16  ;

static const uint8_t P9N2_PEC_SCOM0X2F_TXEQ2                                      = 48  ;
static const uint8_t P9N2_PEC_SCOM0X2F_TXEQ2_LEN                                  = 16  ;

static const uint8_t P9N2_PEC_SCOM0X30_PDC2CLK                                    = 56  ;
static const uint8_t P9N2_PEC_SCOM0X30_SPARE                                      = 57  ;
static const uint8_t P9N2_PEC_SCOM0X30_PDM3                                       = 58  ;
static const uint8_t P9N2_PEC_SCOM0X30_PDM2                                       = 59  ;
static const uint8_t P9N2_PEC_SCOM0X30_PDM1                                       = 60  ;
static const uint8_t P9N2_PEC_SCOM0X30_PDSER                                      = 61  ;
static const uint8_t P9N2_PEC_SCOM0X30_PDTSTVRCV                                  = 62  ;
static const uint8_t P9N2_PEC_SCOM0X30_PDSST                                      = 63  ;

static const uint8_t P9N2_PEC_SCOM0X31_H_VALUE                                    = 51  ;
static const uint8_t P9N2_PEC_SCOM0X31_H_VALUE_LEN                                = 12  ;

static const uint8_t P9N2_PEC_SCOM0X32_LOFFFBINV                                  = 49  ;
static const uint8_t P9N2_PEC_SCOM0X32_H1CALFBINV                                 = 50  ;
static const uint8_t P9N2_PEC_SCOM0X32_H1AFBINV                                   = 51  ;
static const uint8_t P9N2_PEC_SCOM0X32_INITLOFFFBINV                              = 52  ;
static const uint8_t P9N2_PEC_SCOM0X32_SDFBINV                                    = 53  ;
static const uint8_t P9N2_PEC_SCOM0X32_H0FBINV                                    = 54  ;
static const uint8_t P9N2_PEC_SCOM0X32_CMFBINV                                    = 55  ;
static const uint8_t P9N2_PEC_SCOM0X32_LOFFSGNINV                                 = 58  ;
static const uint8_t P9N2_PEC_SCOM0X32_H212SGNINV                                 = 59  ;
static const uint8_t P9N2_PEC_SCOM0X32_H1SGNINV                                   = 60  ;
static const uint8_t P9N2_PEC_SCOM0X32_ASGNINV                                    = 61  ;
static const uint8_t P9N2_PEC_SCOM0X32_SDSGNINV                                   = 62  ;
static const uint8_t P9N2_PEC_SCOM0X32_OFFSGNINV                                  = 63  ;

static const uint8_t P9N2_PEC_SCOM0X33_KPGAIN                                     = 56  ;
static const uint8_t P9N2_PEC_SCOM0X33_KPGAIN_LEN                                 = 5   ;
static const uint8_t P9N2_PEC_SCOM0X33_KIGAIN                                     = 61  ;
static const uint8_t P9N2_PEC_SCOM0X33_KIGAIN_LEN                                 = 3   ;

static const uint8_t P9N2_PEC_SCOM0X34_H1SNMT                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X34_TUNE4                                      = 49  ;
static const uint8_t P9N2_PEC_SCOM0X34_TUNE3                                      = 50  ;
static const uint8_t P9N2_PEC_SCOM0X34_TUNE2                                      = 51  ;
static const uint8_t P9N2_PEC_SCOM0X34_TUNE1                                      = 52  ;
static const uint8_t P9N2_PEC_SCOM0X34_TUNE0                                      = 53  ;
static const uint8_t P9N2_PEC_SCOM0X34_TENZP                                      = 54  ;
static const uint8_t P9N2_PEC_SCOM0X34_TENZN                                      = 55  ;
static const uint8_t P9N2_PEC_SCOM0X34_TRFIX                                      = 56  ;
static const uint8_t P9N2_PEC_SCOM0X34_TREFBNKA                                   = 57  ;
static const uint8_t P9N2_PEC_SCOM0X34_TREFBNKB                                   = 58  ;
static const uint8_t P9N2_PEC_SCOM0X34_TREFODD                                    = 59  ;
static const uint8_t P9N2_PEC_SCOM0X34_TREFPOL                                    = 60  ;
static const uint8_t P9N2_PEC_SCOM0X34_TREFSPE                                    = 61  ;
static const uint8_t P9N2_PEC_SCOM0X34_TREFEN1                                    = 62  ;
static const uint8_t P9N2_PEC_SCOM0X34_TREFEN2                                    = 63  ;

static const uint8_t P9N2_PEC_SCOM0X35_WAIT                                       = 48  ;
static const uint8_t P9N2_PEC_SCOM0X35_WAIT_LEN                                   = 8   ;
static const uint8_t P9N2_PEC_SCOM0X35_AVGS                                       = 56  ;
static const uint8_t P9N2_PEC_SCOM0X35_AVGS_LEN                                   = 3   ;
static const uint8_t P9N2_PEC_SCOM0X35_COPY                                       = 60  ;
static const uint8_t P9N2_PEC_SCOM0X35_CLEAR                                      = 61  ;
static const uint8_t P9N2_PEC_SCOM0X35_START                                      = 62  ;
static const uint8_t P9N2_PEC_SCOM0X35_ENABLE                                     = 63  ;

static const uint8_t P9N2_PEC_SCOM0X36_SUM1                                       = 48  ;
static const uint8_t P9N2_PEC_SCOM0X36_SUM1_LEN                                   = 16  ;

static const uint8_t P9N2_PEC_SCOM0X37_SUM2                                       = 48  ;
static const uint8_t P9N2_PEC_SCOM0X37_SUM2_LEN                                   = 16  ;

static const uint8_t P9N2_PEC_SCOM0X38_NFAILID                                    = 49  ;
static const uint8_t P9N2_PEC_SCOM0X38_NFAILID_LEN                                = 15  ;

static const uint8_t P9N2_PEC_SCOM0X39_PFAILID                                    = 49  ;
static const uint8_t P9N2_PEC_SCOM0X39_PFAILID_LEN                                = 15  ;

static const uint8_t P9N2_PEC_SCOM0X3A_TOTFAILS                                   = 55  ;
static const uint8_t P9N2_PEC_SCOM0X3A_TOTFAILS_LEN                               = 9   ;

static const uint8_t P9N2_PEC_SCOM0X3B_PFFSEQ                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X3B_PFFSEQ_LEN                                 = 8   ;
static const uint8_t P9N2_PEC_SCOM0X3B_NFFSEQ                                     = 56  ;
static const uint8_t P9N2_PEC_SCOM0X3B_NFFSEQ_LEN                                 = 8   ;

static const uint8_t P9N2_PEC_SCOM0X3C_DRVPERR                                    = 48  ;
static const uint8_t P9N2_PEC_SCOM0X3C_DRVNERR                                    = 49  ;
static const uint8_t P9N2_PEC_SCOM0X3C_DTESTEN                                    = 51  ;
static const uint8_t P9N2_PEC_SCOM0X3C_LSBEN                                      = 52  ;
static const uint8_t P9N2_PEC_SCOM0X3C_TSTRCVP                                    = 53  ;
static const uint8_t P9N2_PEC_SCOM0X3C_TSTRCVN                                    = 54  ;
static const uint8_t P9N2_PEC_SCOM0X3C_SEQNUM                                     = 56  ;
static const uint8_t P9N2_PEC_SCOM0X3C_SEQNUM_LEN                                 = 8   ;

static const uint8_t P9N2_PEC_SCOM0X3D_TSTCNT                                     = 48  ;
static const uint8_t P9N2_PEC_SCOM0X3D_TSTCNT_LEN                                 = 13  ;
static const uint8_t P9N2_PEC_SCOM0X3D_SLEWCODE                                   = 61  ;
static const uint8_t P9N2_PEC_SCOM0X3D_SLEWCODE_LEN                               = 2   ;
static const uint8_t P9N2_PEC_SCOM0X3D_ASEGEN                                     = 63  ;

static const uint8_t P9N2_PEC_SCOM0X3E_AECMDVAL                                   = 49  ;
static const uint8_t P9N2_PEC_SCOM0X3E_AECMD1312                                  = 50  ;
static const uint8_t P9N2_PEC_SCOM0X3E_AECMD1312_LEN                              = 2   ;
static const uint8_t P9N2_PEC_SCOM0X3E_ASODD                                      = 52  ;
static const uint8_t P9N2_PEC_SCOM0X3E_ASODD_LEN                                  = 3   ;
static const uint8_t P9N2_PEC_SCOM0X3E_ASEVEN                                     = 55  ;
static const uint8_t P9N2_PEC_SCOM0X3E_ASEVEN_LEN                                 = 3   ;
static const uint8_t P9N2_PEC_SCOM0X3E_AECMD50                                    = 58  ;
static const uint8_t P9N2_PEC_SCOM0X3E_AECMD50_LEN                                = 6   ;

static const uint8_t P9N2_PEC_SCOM0X3F_TSTDCLKEN                                  = 48  ;
static const uint8_t P9N2_PEC_SCOM0X3F_TSTCTL                                     = 49  ;
static const uint8_t P9N2_PEC_SCOM0X3F_TSTCTL_LEN                                 = 6   ;
static const uint8_t P9N2_PEC_SCOM0X3F_STSTMD                                     = 55  ;
static const uint8_t P9N2_PEC_SCOM0X3F_BSOUT                                      = 57  ;
static const uint8_t P9N2_PEC_SCOM0X3F_BSIN                                       = 58  ;
static const uint8_t P9N2_PEC_SCOM0X3F_JTAGAMPL                                   = 59  ;
static const uint8_t P9N2_PEC_SCOM0X3F_JTAGAMPL_LEN                               = 2   ;
static const uint8_t P9N2_PEC_SCOM0X3F_JTAGOE                                     = 61  ;
static const uint8_t P9N2_PEC_SCOM0X3F_TXOE                                       = 62  ;
static const uint8_t P9N2_PEC_SCOM0X3F_OBS                                        = 63  ;

static const uint8_t P9N2_PU_SCOM_PPE_CNTL_IORESET                                = 0   ;
static const uint8_t P9N2_PU_SCOM_PPE_CNTL_PDWN                                   = 1   ;
static const uint8_t P9N2_PU_SCOM_PPE_CNTL_INTERRUPT                              = 2   ;
static const uint8_t P9N2_PU_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR                     = 3   ;
static const uint8_t P9N2_PU_SCOM_PPE_CNTL_SPARES                                 = 4   ;
static const uint8_t P9N2_PU_SCOM_PPE_CNTL_SPARES_LEN                             = 12  ;

static const uint8_t P9N2_PU_SCOM_PPE_FLAGS_FIELD                                 = 0   ;
static const uint8_t P9N2_PU_SCOM_PPE_FLAGS_FIELD_LEN                             = 16  ;

static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG1_WORK1                             = 0   ;
static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG1_WORK1_LEN                         = 32  ;

static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG2_WORK2                             = 0   ;
static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG2_WORK2_LEN                         = 32  ;

static const uint8_t P9N2_PU_SCRATCH0_SCRATCH_N                                   = 0   ;
static const uint8_t P9N2_PU_SCRATCH0_SCRATCH_N_LEN                               = 64  ;

static const uint8_t P9N2_PU_NPU2_NTL1_SCRATCH0_IDIAL                             = 0   ;
static const uint8_t P9N2_PU_NPU2_NTL1_SCRATCH0_IDIAL_LEN                         = 64  ;

static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH1_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH1_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2_PU_NPU_SM2_SCRATCH1_IDIAL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM2_SCRATCH1_IDIAL_LEN                           = 64  ;

static const uint8_t P9N2__SM0_SCRATCH1_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM0_SCRATCH1_IDIAL_LEN                                 = 64  ;

static const uint8_t P9N2_PU_NPU_SM0_SCRATCH1_IDIAL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_SCRATCH1_IDIAL_LEN                           = 64  ;

static const uint8_t P9N2_PU_NPU1_SM2_SCRATCH1_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM2_SCRATCH1_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2_PU_SCRATCH1_SCRATCH_N                                   = 0   ;
static const uint8_t P9N2_PU_SCRATCH1_SCRATCH_N_LEN                               = 64  ;

static const uint8_t P9N2_PU_NPU_SM1_SCRATCH1_IDIAL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_SCRATCH1_IDIAL_LEN                           = 64  ;

static const uint8_t P9N2__SM2_SCRATCH1_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM2_SCRATCH1_IDIAL_LEN                                 = 64  ;

static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH1_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH1_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2__SM1_SCRATCH1_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM1_SCRATCH1_IDIAL_LEN                                 = 64  ;

static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH2_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH2_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2__SM0_SCRATCH2_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM0_SCRATCH2_IDIAL_LEN                                 = 64  ;

static const uint8_t P9N2_PU_NPU_SM0_SCRATCH2_IDIAL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_SCRATCH2_IDIAL_LEN                           = 64  ;

static const uint8_t P9N2_PU_SCRATCH2_SCRATCH_N                                   = 0   ;
static const uint8_t P9N2_PU_SCRATCH2_SCRATCH_N_LEN                               = 64  ;

static const uint8_t P9N2_PU_NPU_SM1_SCRATCH2_IDIAL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_SCRATCH2_IDIAL_LEN                           = 64  ;

static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH2_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH2_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2__SM1_SCRATCH2_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM1_SCRATCH2_IDIAL_LEN                                 = 64  ;

static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH3_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH3_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2__SM0_SCRATCH3_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM0_SCRATCH3_IDIAL_LEN                                 = 64  ;

static const uint8_t P9N2_PU_NPU_SM0_SCRATCH3_IDIAL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM0_SCRATCH3_IDIAL_LEN                           = 64  ;

static const uint8_t P9N2_PU_SCRATCH3_SCRATCH_N                                   = 0   ;
static const uint8_t P9N2_PU_SCRATCH3_SCRATCH_N_LEN                               = 64  ;

static const uint8_t P9N2_PU_NPU_SM1_SCRATCH3_IDIAL                               = 0   ;
static const uint8_t P9N2_PU_NPU_SM1_SCRATCH3_IDIAL_LEN                           = 64  ;

static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH3_IDIAL                              = 0   ;
static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH3_IDIAL_LEN                          = 64  ;

static const uint8_t P9N2__SM1_SCRATCH3_IDIAL                                     = 0   ;
static const uint8_t P9N2__SM1_SCRATCH3_IDIAL_LEN                                 = 64  ;

static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS               = 0   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY         = 1   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_SECONDARY       = 2   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LOCAL_QUIESCE_ACHIEVED      = 3   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK         = 4   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LOCALITY_4_ACCESS           = 5   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_SECURE_DEBUG                = 6   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_CMFSI_ACCESS_PROTCT         = 7   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_ABUS_LOCK                   = 8   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_NX_RAND_NUM_GEN_LOCK        = 9   ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE0              = 10  ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE1              = 11  ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_I2CM_TPM_DECONFIG_PROTECT   = 12  ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE0              = 13  ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE1              = 14  ;
static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE2              = 15  ;

static const uint8_t P9N2_PU_SEND_WC_BASE_ADDR_BAR                                = 8   ;
static const uint8_t P9N2_PU_SEND_WC_BASE_ADDR_BAR_LEN                            = 33  ;

static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0                         = 0   ;
static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0_LEN                     = 3   ;
static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT            = 36  ;
static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN        = 2   ;

static const uint8_t P9N2_PEC_SKITTER_FORCE_REG_F_READ                            = 0   ;

static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_SAMPLE                        = 0   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_DISABLE_STICKINESS                 = 1   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_UNUSED1                            = 2   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_UNUSED1_LEN                        = 2   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL                   = 4   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN               = 2   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_RESET_TRIG_SEL                     = 6   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN                 = 2   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_SAMPLE_GUTS                        = 8   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_SAMPLE_GUTS_LEN                    = 2   ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER           = 44  ;
static const uint8_t P9N2_PEC_SKITTER_MODE_REG_DATA_V_LT                          = 45  ;

static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK       = 0   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN         = 1   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP         = 2   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK         = 3   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT              = 4   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO          = 5   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_PM_DISABLE                     = 6   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE                 = 7   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_ERROR_MASK                         = 8   ;
static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN                     = 6   ;

static const uint8_t P9N2_PU_SMF_CONFIG_REG_0_CONFIG0                             = 0   ;
static const uint8_t P9N2_PU_SMF_CONFIG_REG_0_CONFIG0_LEN                         = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_CREQ0                          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PRB0                           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_CREQ1                          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PRB1                           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_XATS                           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PWR0                           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PWR1                           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_CHGRATE                        = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBGP                          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBGP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBSP                          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBSP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE0                         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE0_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE1                         = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE1_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBLN                           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBNNG                          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBRNVG                         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N0REQ                          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N0DGD                          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N1REQ                          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N1DGD                          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MMIO                           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_ATSXLATE                       = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBRSP                          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N0RSP                          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N1RSP                          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_XARSP                          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_SACOLL                         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FREE                           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_RESERVED1                      = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBCP                          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBCP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PERF_LSTATE                    = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PERF_LSTATE_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_RESERVED2                      = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_RESERVED2_LEN                  = 2   ;

static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_CREQ0                             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PRB0                              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_CREQ1                             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PRB1                              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_XATS                              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PWR0                              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PWR1                              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_CHGRATE                           = 7   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBGP                             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBGP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBSP                             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBSP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE0                            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE0_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE1                            = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE1_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBLN                              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBNNG                             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBRNVG                            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N0REQ                             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N0DGD                             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N1REQ                             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N1DGD                             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MMIO                              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_ATSXLATE                          = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBRSP                             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N0RSP                             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N1RSP                             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_XARSP                             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_SACOLL                            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FREE                              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_RESERVED1                         = 39  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBCP                             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBCP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PERF_LSTATE                       = 44  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PERF_LSTATE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_RESERVED2                         = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_CREQ0                             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PRB0                              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_CREQ1                             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PRB1                              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_XATS                              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PWR0                              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PWR1                              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_CHGRATE                           = 7   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBGP                             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBGP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBSP                             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBSP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE0                            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE0_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE1                            = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE1_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBLN                              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBNNG                             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBRNVG                            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N0REQ                             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N0DGD                             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N1REQ                             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N1DGD                             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MMIO                              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_ATSXLATE                          = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBRSP                             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N0RSP                             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N1RSP                             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_XARSP                             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_SACOLL                            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FREE                              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_RESERVED1                         = 39  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBCP                             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBCP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PERF_LSTATE                       = 44  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PERF_LSTATE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_RESERVED2                         = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_CREQ0                             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PRB0                              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_CREQ1                             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PRB1                              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_XATS                              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PWR0                              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PWR1                              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_CHGRATE                           = 7   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBGP                             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBGP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBSP                             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBSP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE0                            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE0_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE1                            = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE1_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBLN                              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBNNG                             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBRNVG                            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N0REQ                             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N0DGD                             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N1REQ                             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N1DGD                             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MMIO                              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_ATSXLATE                          = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBRSP                             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N0RSP                             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N1RSP                             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_XARSP                             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_SACOLL                            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FREE                              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_RESERVED1                         = 39  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBCP                             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBCP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PERF_LSTATE                       = 44  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PERF_LSTATE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_RESERVED2                         = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_CREQ0                          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PRB0                           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_CREQ1                          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PRB1                           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_XATS                           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PWR0                           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PWR1                           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_CHGRATE                        = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBGP                          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBGP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBSP                          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBSP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE0                         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE0_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE1                         = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE1_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBLN                           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBNNG                          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBRNVG                         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N0REQ                          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N0DGD                          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N1REQ                          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N1DGD                          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MMIO                           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_ATSXLATE                       = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBRSP                          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N0RSP                          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N1RSP                          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_XARSP                          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_SACOLL                         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FREE                           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_RESERVED1                      = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBCP                          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBCP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PERF_LSTATE                    = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PERF_LSTATE_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_RESERVED2                      = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_RESERVED2_LEN                  = 2   ;

static const uint8_t P9N2_PU_NPU0_SM_STATUS_CREQ0                                 = 0   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PRB0                                  = 1   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_CREQ1                                 = 2   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PRB1                                  = 3   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_XATS                                  = 4   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PWR0                                  = 5   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PWR1                                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_CHGRATE                               = 7   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBGP                                 = 8   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBGP_LEN                             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBSP                                 = 12  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBSP_LEN                             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE0                                = 16  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE0_LEN                            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE1                                = 20  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE1_LEN                            = 4   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBLN                                  = 24  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBNNG                                 = 25  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBRNVG                                = 26  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_N0REQ                                 = 27  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_N0DGD                                 = 28  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_N1REQ                                 = 29  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_N1DGD                                 = 30  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_MMIO                                  = 31  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_ATSXLATE                              = 32  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBRSP                                 = 33  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_N0RSP                                 = 34  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_N1RSP                                 = 35  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_XARSP                                 = 36  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_SACOLL                                = 37  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_FREE                                  = 38  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_RESERVED1                             = 39  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBCP                                 = 40  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBCP_LEN                             = 4   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PERF_LSTATE                           = 44  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_PERF_LSTATE_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_RESERVED2                             = 46  ;
static const uint8_t P9N2_PU_NPU0_SM_STATUS_RESERVED2_LEN                         = 2   ;

static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_CREQ0                             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PRB0                              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_CREQ1                             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PRB1                              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_XATS                              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PWR0                              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PWR1                              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_CHGRATE                           = 7   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBGP                             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBGP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBSP                             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBSP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE0                            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE0_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE1                            = 20  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE1_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBLN                              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBNNG                             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBRNVG                            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N0REQ                             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N0DGD                             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N1REQ                             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N1DGD                             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MMIO                              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_ATSXLATE                          = 32  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBRSP                             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N0RSP                             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N1RSP                             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_XARSP                             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_SACOLL                            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FREE                              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_RESERVED1                         = 39  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBCP                             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBCP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PERF_LSTATE                       = 44  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PERF_LSTATE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_RESERVED2                         = 46  ;
static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_CREQ0                              = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PRB0                               = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_CREQ1                              = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PRB1                               = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_XATS                               = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PWR0                               = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PWR1                               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_CHGRATE                            = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBGP                              = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBGP_LEN                          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBSP                              = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBSP_LEN                          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE0                             = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE0_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE1                             = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE1_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBLN                               = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBNNG                              = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBRNVG                             = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N0REQ                              = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N0DGD                              = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N1REQ                              = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N1DGD                              = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MMIO                               = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_ATSXLATE                           = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBRSP                              = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N0RSP                              = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N1RSP                              = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_XARSP                              = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_SACOLL                             = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FREE                               = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_RESERVED1                          = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBCP                              = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBCP_LEN                          = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PERF_LSTATE                        = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PERF_LSTATE_LEN                    = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_RESERVED2                          = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_RESERVED2_LEN                      = 2   ;

static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_CREQ0                             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PRB0                              = 1   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_CREQ1                             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PRB1                              = 3   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_XATS                              = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PWR0                              = 5   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PWR1                              = 6   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_CHGRATE                           = 7   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBGP                             = 8   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBGP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBSP                             = 12  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBSP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE0                            = 16  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE0_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE1                            = 20  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE1_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBLN                              = 24  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBNNG                             = 25  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBRNVG                            = 26  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N0REQ                             = 27  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N0DGD                             = 28  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N1REQ                             = 29  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N1DGD                             = 30  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MMIO                              = 31  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_ATSXLATE                          = 32  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBRSP                             = 33  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N0RSP                             = 34  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N1RSP                             = 35  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_XARSP                             = 36  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_SACOLL                            = 37  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FREE                              = 38  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_RESERVED1                         = 39  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBCP                             = 40  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBCP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PERF_LSTATE                       = 44  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PERF_LSTATE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_RESERVED2                         = 46  ;
static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_CREQ0                             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PRB0                              = 1   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_CREQ1                             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PRB1                              = 3   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_XATS                              = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PWR0                              = 5   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PWR1                              = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_CHGRATE                           = 7   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBGP                             = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBGP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBSP                             = 12  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBSP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE0                            = 16  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE0_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE1                            = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE1_LEN                        = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBLN                              = 24  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBNNG                             = 25  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBRNVG                            = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N0REQ                             = 27  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N0DGD                             = 28  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N1REQ                             = 29  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N1DGD                             = 30  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MMIO                              = 31  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_ATSXLATE                          = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBRSP                             = 33  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N0RSP                             = 34  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N1RSP                             = 35  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_XARSP                             = 36  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_SACOLL                            = 37  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FREE                              = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_RESERVED1                         = 39  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBCP                             = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBCP_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PERF_LSTATE                       = 44  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PERF_LSTATE_LEN                   = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_RESERVED2                         = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_RESERVED2_LEN                     = 2   ;

static const uint8_t P9N2_PU_NPU2_SM_STATUS_CREQ0                                 = 0   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PRB0                                  = 1   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_CREQ1                                 = 2   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PRB1                                  = 3   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_XATS                                  = 4   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PWR0                                  = 5   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PWR1                                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_CHGRATE                               = 7   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBGP                                 = 8   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBGP_LEN                             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBSP                                 = 12  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBSP_LEN                             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE0                                = 16  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE0_LEN                            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE1                                = 20  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE1_LEN                            = 4   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBLN                                  = 24  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBNNG                                 = 25  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBRNVG                                = 26  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_N0REQ                                 = 27  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_N0DGD                                 = 28  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_N1REQ                                 = 29  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_N1DGD                                 = 30  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_MMIO                                  = 31  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_ATSXLATE                              = 32  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBRSP                                 = 33  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_N0RSP                                 = 34  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_N1RSP                                 = 35  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_XARSP                                 = 36  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_SACOLL                                = 37  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_FREE                                  = 38  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_RESERVED1                             = 39  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBCP                                 = 40  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBCP_LEN                             = 4   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PERF_LSTATE                           = 44  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_PERF_LSTATE_LEN                       = 2   ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_RESERVED2                             = 46  ;
static const uint8_t P9N2_PU_NPU2_SM_STATUS_RESERVED2_LEN                         = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_CREQ0                          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PRB0                           = 1   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_CREQ1                          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PRB1                           = 3   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_XATS                           = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PWR0                           = 5   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PWR1                           = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_CHGRATE                        = 7   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBGP                          = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBGP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBSP                          = 12  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBSP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE0                         = 16  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE0_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE1                         = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE1_LEN                     = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBLN                           = 24  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBNNG                          = 25  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBRNVG                         = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N0REQ                          = 27  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N0DGD                          = 28  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N1REQ                          = 29  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N1DGD                          = 30  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MMIO                           = 31  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_ATSXLATE                       = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBRSP                          = 33  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N0RSP                          = 34  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N1RSP                          = 35  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_XARSP                          = 36  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_SACOLL                         = 37  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FREE                           = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_RESERVED1                      = 39  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBCP                          = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBCP_LEN                      = 4   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PERF_LSTATE                    = 44  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PERF_LSTATE_LEN                = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_RESERVED2                      = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_RESERVED2_LEN                  = 2   ;

static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG0                    = 0   ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG1                    = 1   ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_GLB_PULSE                        = 2   ;
static const uint8_t P9N2_PU_SND_MODE_REG_SINGLE_OUTSTANDING_CMD                  = 3   ;
static const uint8_t P9N2_PU_SND_MODE_REG_PROG_REQ_DELAY                          = 4   ;
static const uint8_t P9N2_PU_SND_MODE_REG_PROG_REQ_DELAY_LEN                      = 4   ;
static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_ERR_CMD                         = 8   ;
static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_HTM_CMD                         = 9   ;
static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_TRACE_CMD                       = 10  ;
static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_TOD_CMD                         = 11  ;
static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_XSCOM_CMD                       = 12  ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_CLR_ERR_CMD                      = 13  ;
static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_ERR_CMD                 = 14  ;
static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_HTM_CMD                 = 15  ;
static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_TRACE_CMD               = 16  ;
static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_TOD_CMD                 = 17  ;
static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_XSCOM_CMD               = 18  ;
static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_CHECKSTOP                       = 19  ;
static const uint8_t P9N2_PU_SND_MODE_REG_MANUAL_SET_PB_STOP                      = 20  ;
static const uint8_t P9N2_PU_SND_MODE_REG_MANUAL_CLR_PB_STOP                      = 21  ;
static const uint8_t P9N2_PU_SND_MODE_REG_PB_STOP                                 = 22  ;
static const uint8_t P9N2_PU_SND_MODE_REG_MANUAL_PB_SWITCH_ABCD                   = 25  ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER              = 26  ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER_LEN          = 2   ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TOD                  = 28  ;
static const uint8_t P9N2_PU_SND_MODE_REG_RESET_TOD_STATE                         = 29  ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_PB_SWITCH_AB                     = 30  ;
static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_PB_SWITCH_CD                     = 31  ;

static const uint8_t P9N2_PU_SND_STAT_REG_ERR_CMD_OVERRUN                         = 0   ;
static const uint8_t P9N2_PU_SND_STAT_REG_TRC_CMD_OVERRUN                         = 1   ;
static const uint8_t P9N2_PU_SND_STAT_REG_XSC_CMD_OVERRUN                         = 2   ;
static const uint8_t P9N2_PU_SND_STAT_REG_HTM_CMD_OVERRUN                         = 3   ;
static const uint8_t P9N2_PU_SND_STAT_REG_TOD_CMD_OVERRUN                         = 4   ;
static const uint8_t P9N2_PU_SND_STAT_REG_CMD_COUNT_ERR                           = 5   ;
static const uint8_t P9N2_PU_SND_STAT_REG_PB_OP_HANG_ERR                          = 6   ;
static const uint8_t P9N2_PU_SND_STAT_REG_INVALID_CRESP_ERR                       = 16  ;
static const uint8_t P9N2_PU_SND_STAT_REG_RCV_TTAG_PARITY_ERR                     = 32  ;
static const uint8_t P9N2_PU_SND_STAT_REG_RCV_PB_OP_HANG_ERR                      = 33  ;
static const uint8_t P9N2_PU_SND_STAT_REG_TOD_HANG_ERR                            = 34  ;
static const uint8_t P9N2_PU_SND_STAT_REG_RCV_TOD_STATE                           = 48  ;
static const uint8_t P9N2_PU_SND_STAT_REG_RCV_TOD_STATE_LEN                       = 4   ;

static const uint8_t P9N2_PEC_SPATTN_IN                                           = 0   ;
static const uint8_t P9N2_PEC_SPATTN_IN_LEN                                       = 10  ;

static const uint8_t P9N2_PEC_SPA_MASK_IN                                         = 0   ;
static const uint8_t P9N2_PEC_SPA_MASK_IN_LEN                                     = 10  ;

static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE              = 0   ;
static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE_LEN          = 6   ;
static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT               = 6   ;
static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT_LEN           = 6   ;
static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY                = 12  ;
static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY_LEN            = 6   ;
static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT                = 18  ;
static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT_LEN            = 6   ;

static const uint8_t P9N2_PU_SPIPSS_100NS_REG_OUT                                 = 0   ;
static const uint8_t P9N2_PU_SPIPSS_100NS_REG_OUT_LEN                             = 32  ;

static const uint8_t P9N2_PU_SPIPSS_ADC_CMD_REG_HWCTRL_START_SAMPLING             = 0   ;

static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_FSM_ENABLE               = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_DEVICE                   = 1   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPOL                     = 2   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPHA                     = 3   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER            = 4   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER_LEN        = 10  ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES             = 14  ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES_LEN         = 4   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 18  ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE              = 19  ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE_LEN          = 3   ;

static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY        = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY_LEN    = 17  ;

static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0                  = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0_LEN              = 64  ;

static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1                  = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1_LEN              = 64  ;

static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2                  = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2_LEN              = 64  ;

static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3                  = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3_LEN              = 64  ;

static const uint8_t P9N2_PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL                     = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL_LEN                 = 2   ;

static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_ONGOING                 = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_1                     = 1   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_2                     = 2   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_3                     = 3   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_INVALID_NUMBER_OF_FRAMES = 4   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 5   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_6                     = 6   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_FSM_ERR                 = 7   ;

static const uint8_t P9N2_PU_SPIPSS_ADC_WDATA_REG_HWCTRL                          = 0   ;
static const uint8_t P9N2_PU_SPIPSS_ADC_WDATA_REG_HWCTRL_LEN                      = 16  ;

static const uint8_t P9N2_PU_SPIPSS_P2S_COMMAND_REG_START                         = 0   ;

static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE                      = 0   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE_LEN                  = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1                      = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1_LEN                  = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1                       = 12  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1_LEN                   = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1                       = 18  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1_LEN                   = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2                      = 24  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2_LEN                  = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2                       = 30  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2_LEN                   = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2                       = 36  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2_LEN                   = 6   ;

static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_BRIDGE_ENABLE                   = 0   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_DEVICE                          = 1   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CPOL                            = 2   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CPHA                            = 3   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER                   = 4   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER_LEN               = 10  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_RESERVED                        = 14  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_RESERVED_LEN                    = 3   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_NR_OF_FRAMES                    = 17  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 18  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1         = 19  ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1_LEN     = 3   ;

static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY               = 0   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY_LEN           = 17  ;

static const uint8_t P9N2_PU_SPIPSS_P2S_RDATA_REG_RDATA                           = 0   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_RDATA_REG_RDATA_LEN                       = 32  ;

static const uint8_t P9N2_PU_SPIPSS_P2S_RESET_REGISTER_RESET                      = 0   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_RESET_REGISTER_RESET_LEN                  = 2   ;

static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_ONGOING                        = 0   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_1                     = 1   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_2                     = 2   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_3                     = 3   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_4                     = 4   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_WRITE_WHILE_BRIDGE_BUSY_ERR    = 5   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED6                      = 6   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_FSM_ERR                        = 7   ;

static const uint8_t P9N2_PU_SPIPSS_P2S_WDATA_REG_WDATA                           = 0   ;
static const uint8_t P9N2_PU_SPIPSS_P2S_WDATA_REG_WDATA_LEN                       = 32  ;

static const uint8_t P9N2_PU_SRAM_SRBV0_BOOT_VECTOR_WORD0                         = 0   ;
static const uint8_t P9N2_PU_SRAM_SRBV0_BOOT_VECTOR_WORD0_LEN                     = 32  ;

static const uint8_t P9N2_PU_SRAM_SRBV1_BOOT_VECTOR_WORD1                         = 0   ;
static const uint8_t P9N2_PU_SRAM_SRBV1_BOOT_VECTOR_WORD1_LEN                     = 32  ;

static const uint8_t P9N2_PU_SRAM_SRBV2_BOOT_VECTOR_WORD2                         = 0   ;
static const uint8_t P9N2_PU_SRAM_SRBV2_BOOT_VECTOR_WORD2_LEN                     = 32  ;

static const uint8_t P9N2_PU_SRAM_SRBV3_BOOT_VECTOR_WORD3                         = 0   ;
static const uint8_t P9N2_PU_SRAM_SRBV3_BOOT_VECTOR_WORD3_LEN                     = 32  ;

static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_WRFSM_DLY_DIS                      = 0   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_ALLOW1_RD                          = 1   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_ALLOW1_WR                          = 2   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_ALLOW1_RDWR                        = 3   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_OCI_PARCHK_DIS                     = 4   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_TANK_RDDATA_PARCHK_DIS             = 5   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_SPARE_6                            = 6   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_VAL_BE_ADDR_CHK_DIS                = 7   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_SO_SPARE                           = 8   ;
static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_SO_SPARE_LEN                       = 2   ;

static const uint8_t P9N2_PU_SRAM_SREAR_ERROR_ADDRESS                             = 0   ;
static const uint8_t P9N2_PU_SRAM_SREAR_ERROR_ADDRESS_LEN                         = 17  ;

static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_SOURCE                              = 0   ;
static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_SOURCE_LEN                          = 14  ;
static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_DEST                                = 16  ;
static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_DEST_LEN                            = 14  ;

static const uint8_t P9N2_PU_SRAM_SRMR_ENABLE_REMAP                               = 0   ;
static const uint8_t P9N2_PU_SRAM_SRMR_ARB_EN_SEND_ALL_WRITES                     = 1   ;
static const uint8_t P9N2_PU_SRAM_SRMR_DISABLE_LFSR                               = 2   ;
static const uint8_t P9N2_PU_SRAM_SRMR_LFSR_FAIRNESS_MASK                         = 3   ;
static const uint8_t P9N2_PU_SRAM_SRMR_LFSR_FAIRNESS_MASK_LEN                     = 5   ;
static const uint8_t P9N2_PU_SRAM_SRMR_ERROR_INJECT_ENABLE                        = 8   ;
static const uint8_t P9N2_PU_SRAM_SRMR_CTL_TRACE_EN                               = 9   ;
static const uint8_t P9N2_PU_SRAM_SRMR_CTL_TRACE_SEL                              = 10  ;
static const uint8_t P9N2_PU_SRAM_SRMR_SPARE                                      = 11  ;
static const uint8_t P9N2_PU_SRAM_SRMR_SPARE_LEN                                  = 5   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_ADDR_NVLD                            = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_WRITE_NVLD                           = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_READ_NVLD                            = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_INVLD_CMD_ERR                        = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_CORR_ERR                             = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_UNCORR_ERROR                         = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_DATA_REG_0_31                        = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_DATA_REG_0_31_LEN                    = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_39_43                         = 39  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_39_43_LEN                     = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_CTRL_BUSY                            = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_DCOMP_ERR                            = 45  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_INVLD_PRGM_ERR                       = 46  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_47_51                         = 47  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_47_51_LEN                     = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_COMMAND_COMPLETE                     = 52  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_53                            = 53  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_RDWR_OP_BUSY                         = 54  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_DCOMP_ENGINE_BUSY                    = 55  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_RD_DATA_COUNT                        = 56  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_RD_DATA_COUNT_LEN                    = 8   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0                    = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_WRITE_NVLD_0                   = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_READ_NVLD_0                    = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_ADDR_P_ERR_0                   = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_PAR_ERR_0                      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_LB_PARITY_ERROR_0              = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_PIB_DATA0TO7_0                     = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_PIB_DATA0TO7_0_LEN                 = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_WAITING_IN_I2C_QUEUE_0         = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_ECC_CORRECTED_ERROR_0              = 41  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0            = 42  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0                 = 43  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_BUSY_0                         = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0              = 45  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0                 = 46  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0       = 47  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0        = 48  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0       = 49  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0          = 50  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_DATA_REQUEST_0                 = 51  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_COMMAND_COMPLETE_0             = 52  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0                   = 53  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_I2C_PORT_BUSY_0                = 54  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_I2C_INTERFACE_BUSY_0           = 55  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0             = 56  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0_LEN         = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_PCBIF_ERRS_0                       = 60  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_B_PCBIF_ERRS_0_LEN                   = 4   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_ADDR_NVLD_1                    = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_WRITE_NVLD_1                   = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_READ_NVLD_1                    = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_ADDR_P_ERR_1                   = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_PAR_ERR_1                      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_LB_PARITY_ERROR_1              = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_PIB_DATA0TO7_1                     = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_PIB_DATA0TO7_1_LEN                 = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_WAITING_IN_I2C_QUEUE_1         = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_ECC_CORRECTED_ERROR_1              = 41  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_ECC_UNCORRECTED_ERROR_1            = 42  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_ECC_CONFIG_ERROR_1                 = 43  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_BUSY_1                         = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_INVALID_COMMAND_1              = 45  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_PARITY_ERROR_1                 = 46  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_BACK_END_OVERRUN_ERROR_1       = 47  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_BACK_END_ACCESS_ERROR_1        = 48  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_ARBITRATION_LOST_ERROR_1       = 49  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_NACK_RECEIVED_ERROR_1          = 50  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_DATA_REQUEST_1                 = 51  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_COMMAND_COMPLETE_1             = 52  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_STOP_ERROR_1                   = 53  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_I2C_PORT_BUSY_1                = 54  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_I2C_INTERFACE_BUSY_1           = 55  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1             = 56  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1_LEN         = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_PCBIF_ERRS_1                       = 60  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_C_PCBIF_ERRS_1_LEN                   = 4   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_ADDR_NVLD_2                    = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_WRITE_NVLD_2                   = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_READ_NVLD_2                    = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_ADDR_P_ERR_2                   = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_PAR_ERR_2                      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_LB_PARITY_ERROR_2              = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_PIB_DATA0TO7_2                     = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_PIB_DATA0TO7_2_LEN                 = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_WAITING_IN_I2C_QUEUE_2         = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_ECC_CORRECTED_ERROR_2              = 41  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_ECC_UNCORRECTED_ERROR_2            = 42  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_ECC_CONFIG_ERROR_2                 = 43  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_BUSY_2                         = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_INVALID_COMMAND_2              = 45  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_PARITY_ERROR_2                 = 46  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_BACK_END_OVERRUN_ERROR_2       = 47  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_BACK_END_ACCESS_ERROR_2        = 48  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_ARBITRATION_LOST_ERROR_2       = 49  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_NACK_RECEIVED_ERROR_2          = 50  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_DATA_REQUEST_2                 = 51  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_COMMAND_COMPLETE_2             = 52  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_STOP_ERROR_2                   = 53  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_I2C_PORT_BUSY_2                = 54  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_I2C_INTERFACE_BUSY_2           = 55  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2             = 56  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2_LEN         = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_PCBIF_ERRS_2                       = 60  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_D_PCBIF_ERRS_2_LEN                   = 4   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_ADDR_NVLD_3                    = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_WRITE_NVLD_3                   = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_READ_NVLD_3                    = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_ADDR_P_ERR_3                   = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_PAR_ERR_3                      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_LB_PARITY_ERROR_3              = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_PIB_DATA0TO7_3                     = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_PIB_DATA0TO7_3_LEN                 = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_WAITING_IN_I2C_QUEUE_3         = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_ECC_CORRECTED_ERROR_3              = 41  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_ECC_UNCORRECTED_ERROR_3            = 42  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_ECC_CONFIG_ERROR_3                 = 43  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_BUSY_3                         = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_INVALID_COMMAND_3              = 45  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_PARITY_ERROR_3                 = 46  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_BACK_END_OVERRUN_ERROR_3       = 47  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_BACK_END_ACCESS_ERROR_3        = 48  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_ARBITRATION_LOST_ERROR_3       = 49  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_NACK_RECEIVED_ERROR_3          = 50  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_DATA_REQUEST_3                 = 51  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_COMMAND_COMPLETE_3             = 52  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_STOP_ERROR_3                   = 53  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_I2C_PORT_BUSY_3                = 54  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_I2C_INTERFACE_BUSY_3           = 55  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3             = 56  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3_LEN         = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_PCBIF_ERRS_3                       = 60  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_E_PCBIF_ERRS_3_LEN                   = 4   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_INVALID_CMD_0               = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERROR_0         = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_BE_OV_ERROR_0               = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_BE_ACC_ERROR_0              = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_ARBITRATION_LOST_ERROR_0    = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_NACK_RECEIVED_ERROR_0       = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_DATA_REQUEST_0              = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_STOP_ERROR_0                = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_BUSY                        = 22  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_SELF_BUSY_0                 = 23  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0          = 28  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0_LEN      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0                = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0_LEN            = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERR1_0          = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0   = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0_LEN = 4   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_INVALID_CMD_1               = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERROR_1         = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_BE_OV_ERROR_1               = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_BE_ACC_ERROR_1              = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_ARBITRATION_LOST_ERROR_1    = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_NACK_RECEIVED_ERROR_1       = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_DATA_REQUEST_1              = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_STOP_ERROR_1                = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_BUSY                        = 22  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_SELF_BUSY_1                 = 23  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1          = 28  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1_LEN      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1                = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1_LEN            = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERR1_1          = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1   = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1_LEN = 4   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_INVALID_CMD_2               = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERROR_2         = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_BE_OV_ERROR_2               = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_BE_ACC_ERROR_2              = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_ARBITRATION_LOST_ERROR_2    = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_NACK_RECEIVED_ERROR_2       = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_DATA_REQUEST_2              = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_STOP_ERROR_2                = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_BUSY                        = 22  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_SELF_BUSY_2                 = 23  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2          = 28  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2_LEN      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2                = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2_LEN            = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERR1_2          = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2   = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2_LEN = 4   ;

static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_INVALID_CMD_3               = 0   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERROR_3         = 1   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_BE_OV_ERROR_3               = 2   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_BE_ACC_ERROR_3              = 3   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_ARBITRATION_LOST_ERROR_3    = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_NACK_RECEIVED_ERROR_3       = 5   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_DATA_REQUEST_3              = 6   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_STOP_ERROR_3                = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_BUSY                        = 22  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_SELF_BUSY_3                 = 23  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3          = 28  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3_LEN      = 4   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3                = 32  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3_LEN            = 8   ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERR1_3          = 40  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3   = 44  ;
static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3_LEN = 4   ;

static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN0                              = 0   ;
static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN1                              = 1   ;
static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN2                              = 2   ;
static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN3                              = 3   ;
static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN4                              = 4   ;

static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_ENABLE                               = 0   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_DONE                                 = 1   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_SUMMARY                              = 2   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT             = 4   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT_LEN         = 4   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT                 = 8   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT_LEN             = 4   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT                   = 12  ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT_LEN               = 4   ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_SWC_VALUE                            = 16  ;
static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_SWC_VALUE_LEN                        = 16  ;

static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_0_0                              = 0   ;
static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_0_0_LEN                          = 64  ;

static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_1_1                              = 0   ;
static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_1_1_LEN                          = 17  ;

static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO                        = 0   ;
static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH3_SYM                             = 57  ;
static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH2_SYM                             = 58  ;
static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH4_GZIP                            = 61  ;
static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH1_EFT                             = 62  ;
static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH0_EFT                             = 63  ;

static const uint8_t P9N2_PU_SU_ERAT_ERROR_RPT_RPT                                = 0   ;
static const uint8_t P9N2_PU_SU_ERAT_ERROR_RPT_RPT_LEN                            = 48  ;

static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD           = 8   ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD_LEN       = 4   ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD         = 12  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD_LEN     = 4   ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIP_COMP_PREFETCH_ENABLE   = 16  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIP_DECOMP_PREFETCH_ENABLE = 17  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFT_COMP_PREFETCH_ENABLE    = 23  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFT_DECOMP_PREFETCH_ENABLE  = 24  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD                = 25  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD_LEN            = 4   ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD            = 33  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD_LEN        = 4   ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD          = 37  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD_LEN      = 4   ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_SYM_CPB_CHECK_DISABLE       = 48  ;
static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFT_SPBC_ENABLE             = 56  ;

static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID                            = 0   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID_LEN                        = 12  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID_MASK                       = 12  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID_MASK_LEN                   = 12  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID                             = 24  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID_LEN                         = 20  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID_MASK                        = 44  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID_MASK_LEN                    = 20  ;

static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT                  = 27  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT_LEN              = 2   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_842_FC_SELECT                   = 29  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_842_FC_SELECT_LEN               = 2   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT                  = 31  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT_LEN              = 4   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT                  = 35  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT_LEN              = 3   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT                 = 38  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT_LEN             = 3   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT                 = 41  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT_LEN             = 4   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT                 = 45  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT_LEN             = 3   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT                  = 48  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT_LEN              = 4   ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_SHA_LATENCY_CFG                 = 52  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_MD5_LATENCY_CFG                 = 54  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_AES_LATENCY_CFG                 = 56  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_AESSHA_LATENCY_CFG              = 58  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_LATENCY_CFG                = 60  ;
static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_842_LATENCY_CFG                 = 62  ;

static const uint8_t P9N2_PU_SU_STATUS_HMI_ACTIVE                                 = 54  ;
static const uint8_t P9N2_PU_SU_STATUS_PBI_IDLE                                   = 55  ;
static const uint8_t P9N2_PU_SU_STATUS_DMA_CH0_IDLE                               = 56  ;
static const uint8_t P9N2_PU_SU_STATUS_DMA_CH1_IDLE                               = 57  ;
static const uint8_t P9N2_PU_SU_STATUS_DMA_CH2_IDLE                               = 58  ;
static const uint8_t P9N2_PU_SU_STATUS_DMA_CH3_IDLE                               = 59  ;
static const uint8_t P9N2_PU_SU_STATUS_DMA_CH4_IDLE                               = 60  ;

static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT_RPT                                = 0   ;
static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT_RPT_LEN                            = 56  ;

static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT1_RPT1                              = 0   ;
static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT1_RPT1_LEN                          = 6   ;

static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              = 4   ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          = 12  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               = 20  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           = 20  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               = 44  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           = 16  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            = 63  ;

static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                   = 8   ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               = 46  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              = 54  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          = 3   ;

static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      = 4   ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  = 8   ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           = 15  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       = 9   ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX           = 27  ;
static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN       = 9   ;

static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              = 4   ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          = 12  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               = 20  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           = 20  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               = 44  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           = 16  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            = 63  ;

static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                   = 8   ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               = 46  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              = 54  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          = 3   ;

static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      = 4   ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  = 8   ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           = 15  ;
static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       = 9   ;

static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LIMIT                               = 0   ;
static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LIMIT_LEN                           = 5   ;
static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_SRC_DDE                             = 5   ;
static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_SRC_DDE_LEN                         = 8   ;
static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_TARGET_DDE                          = 13  ;
static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_TARGET_DDE_LEN                      = 8   ;
static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LO_PRIOR_LIMIT                      = 21  ;
static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LO_PRIOR_LIMIT_LEN                  = 5   ;

static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_DELAY                             = 0   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_DELAY_LEN                         = 4   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_LISTEN_TO_PULSE_DIS                     = 4   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_INPUT_SEL                         = 5   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_USE_FOR_SCAN                            = 6   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED                = 7   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE               = 8   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_DISABLE_PCB_ITR                         = 9   ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK                 = 10  ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_OUT_DIS                           = 11  ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_MODE                          = 12  ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_E1                            = 13  ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_E2                            = 14  ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_E3                            = 15  ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE              = 16  ;
static const uint8_t P9N2_PEC_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE_LEN          = 8   ;

static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE           = 0   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_INVALID_COMMAND                 = 1   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_INVALID_ADDRESS_ALIGNMENT       = 2   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_OPB_ERROR                       = 3   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_OPB_TIMEOUT                     = 4   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_OPB_MASTER_HANG_TIMEOUT         = 5   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_CMD_BUFFER_PAR_ERR              = 6   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_DAT_BUFFER_PAR_ERR              = 7   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_RETURNQ_ERR                     = 8   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_RESERVED                        = 9   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR2                = 10  ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR                 = 11  ;

static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_INVALID_TRANSFER_SIZE           = 0   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_INVALID_COMMAND                 = 1   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_INVALID_ADDRESS_ALIGNMENT       = 2   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_OPB_ERROR                       = 3   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_OPB_TIMEOUT                     = 4   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_OPB_MASTER_HANG_TIMEOUT         = 5   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_CMD_BUFFER_PAR_ERR              = 6   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_DAT_BUFFER_PAR_ERR              = 7   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_RETURNQ_ERR                     = 8   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_RESERVED                        = 9   ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR2                = 10  ;
static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR                 = 11  ;

static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_INVALID_TRANSFER_SIZE              = 0   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_INVALID_COMMAND                    = 1   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_INVALID_ADDRESS_ALIGNMENT          = 2   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_OPB_ERROR                          = 3   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_OPB_TIMEOUT                        = 4   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_OPB_MASTER_HANG_TIMEOUT            = 5   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_CMD_BUFFER_PAR_ERR                 = 6   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_DAT_BUFFER_PAR_ERR                 = 7   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_RETURNQ_ERR                        = 8   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_RESERVED                           = 9   ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR2                   = 10  ;
static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR                    = 11  ;

static const uint8_t P9N2_PU_SYNC_FIR_REG_INVALID_TRANSFER_SIZE                   = 0   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_INVALID_COMMAND                         = 1   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_INVALID_ADDRESS_ALIGNMENT               = 2   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_OPB_ERROR                               = 3   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_OPB_TIMEOUT                             = 4   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_OPB_MASTER_HANG_TIMEOUT                 = 5   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_CMD_BUFFER_PAR_ERR                      = 6   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_DAT_BUFFER_PAR_ERR                      = 7   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_RETURNQ_ERR                             = 8   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_RESERVED                                = 9   ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_PARITY_ERR2                             = 10  ;
static const uint8_t P9N2_PU_SYNC_FIR_REG_PARITY_ERR                              = 11  ;

static const uint8_t P9N2_PU_SYNC_FIR_WOF_REG_WOF                                 = 0   ;
static const uint8_t P9N2_PU_SYNC_FIR_WOF_REG_WOF_LEN                             = 6   ;

static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ALL                            = 0   ;
static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ONE                            = 2   ;
static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_PE_NUMBER                      = 4   ;
static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_PE_NUMBER_LEN                  = 4   ;
static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ADDRESS                        = 15  ;
static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ADDRESS_LEN                    = 37  ;

static const uint8_t P9N2__SM2_TEST_CERR_ATR_ERR_INJ_PEND                         = 0   ;
static const uint8_t P9N2__SM2_TEST_CERR_MAP_ERR_INJ_PEND                         = 1   ;
static const uint8_t P9N2__SM2_TEST_CERR_REGSEL                                   = 56  ;
static const uint8_t P9N2__SM2_TEST_CERR_REGSEL_LEN                               = 2   ;
static const uint8_t P9N2__SM2_TEST_CERR_BITSEL                                   = 58  ;
static const uint8_t P9N2__SM2_TEST_CERR_BITSEL_LEN                               = 6   ;

static const uint8_t P9N2_CAPP_TFMR_MAX_CYC_BET_STEPS                             = 0   ;
static const uint8_t P9N2_CAPP_TFMR_MAX_CYC_BET_STEPS_LEN                         = 8   ;
static const uint8_t P9N2_CAPP_TFMR_N_CLKS_PER_STEP                               = 8   ;
static const uint8_t P9N2_CAPP_TFMR_N_CLKS_PER_STEP_LEN                           = 2   ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT10                                = 10  ;
static const uint8_t P9N2_CAPP_TFMR_SYNC_BIT_SEL                                  = 11  ;
static const uint8_t P9N2_CAPP_TFMR_SYNC_BIT_SEL_LEN                              = 3   ;
static const uint8_t P9N2_CAPP_TFMR_TB_ECLIPZ                                     = 14  ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT15                                = 15  ;
static const uint8_t P9N2_CAPP_TFMR_LOAD_TOD_MOD                                  = 16  ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT17                                = 17  ;
static const uint8_t P9N2_CAPP_TFMR_MOVE_CHIP_TOD_TO_TB                           = 18  ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT19                                = 19  ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT20                                = 20  ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT21                                = 21  ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT22                                = 22  ;
static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT23                                = 23  ;
static const uint8_t P9N2_CAPP_TFMR_CLEAR_TB_ERRORS                               = 24  ;
static const uint8_t P9N2_CAPP_TFMR_TBST_CORRUPT                                  = 27  ;
static const uint8_t P9N2_CAPP_TFMR_TBST_ENCODED                                  = 28  ;
static const uint8_t P9N2_CAPP_TFMR_TBST_ENCODED_LEN                              = 4   ;
static const uint8_t P9N2_CAPP_TFMR_TBST_LAST                                     = 32  ;
static const uint8_t P9N2_CAPP_TFMR_TBST_LAST_LEN                                 = 4   ;
static const uint8_t P9N2_CAPP_TFMR_TB_ENABLED                                    = 40  ;
static const uint8_t P9N2_CAPP_TFMR_TB_VALID                                      = 41  ;
static const uint8_t P9N2_CAPP_TFMR_TB_SYNC_OCCURRED                              = 42  ;
static const uint8_t P9N2_CAPP_TFMR_TB_MISSING_SYNC                               = 43  ;
static const uint8_t P9N2_CAPP_TFMR_TB_MISSING_STEP                               = 44  ;
static const uint8_t P9N2_CAPP_TFMR_TB_RESIDUE_ERR                                = 45  ;
static const uint8_t P9N2_CAPP_TFMR_FIRMWARE_CONTROL_ERROR                        = 46  ;
static const uint8_t P9N2_CAPP_TFMR_CHIP_TOD_STATUS                               = 47  ;
static const uint8_t P9N2_CAPP_TFMR_CHIP_TOD_STATUS_LEN                           = 4   ;
static const uint8_t P9N2_CAPP_TFMR_CHIP_TOD_INTERRUPT                            = 51  ;
static const uint8_t P9N2_CAPP_TFMR_TFMR_CORRUPT                                  = 60  ;

static const uint8_t P9N2_PEC_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR                  = 0   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_FORCE_THRES_ACT                      = 1   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_TRIP_ENA                       = 2   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_TRIP_ENA_LEN                   = 3   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_SAMPLE_ENA                       = 5   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT                     = 6   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN                 = 4   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_ENA                            = 10  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_ENA_LEN                        = 2   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_TRIGGER                          = 12  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_TRIGGER_SEL                      = 13  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_OVERFLOW_MASK                  = 14  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_UNUSED                               = 15  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_READ_SEL                         = 16  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_READ_SEL_LEN                     = 4   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_ENABLE_L1                        = 20  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_ENABLE_L1_LEN                    = 2   ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1                  = 35  ;
static const uint8_t P9N2_PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN              = 2   ;

static const uint8_t P9N2_PEC_TIMEOUT_REG_INT_TIMEOUT                             = 0   ;
static const uint8_t P9N2_PEC_TIMEOUT_REG_INT_TIMEOUT_LEN                         = 2   ;

static const uint8_t P9N2_PEC_TIMESTAMP_COUNTER_READ_VALUE                        = 0   ;
static const uint8_t P9N2_PEC_TIMESTAMP_COUNTER_READ_VALUE_LEN                    = 44  ;
static const uint8_t P9N2_PEC_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR                 = 44  ;

static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_TIMEOUT                       = 0   ;
static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SEQ_ERR                       = 1   ;
static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SEQ_PERR                      = 2   ;
static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_BAD_OP_ERR                    = 3   ;
static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR                 = 4   ;
static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR                 = 5   ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_LVALID                           = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_PVALID                           = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_PID                              = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_PID_LEN                          = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_LPID                             = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_LPID_LEN                         = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_LVALID                           = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_PVALID                           = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_PID                              = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_PID_LEN                          = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_LPID                             = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_LPID_LEN                         = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_LVALID                           = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_PVALID                           = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_PID                              = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_PID_LEN                          = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_LPID                             = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_LPID_LEN                         = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_LVALID                           = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_PVALID                           = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_PID                              = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_PID_LEN                          = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_LPID                             = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_LPID_LEN                         = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_LVALID                           = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_PVALID                           = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_PID                              = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_PID_LEN                          = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_LPID                             = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_LPID_LEN                         = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_LVALID                           = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_PVALID                           = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_PID                              = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_PID_LEN                          = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_LPID                             = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_LPID_LEN                         = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_LVALID                            = 0   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_PVALID                            = 1   ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_PID                               = 32  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_PID_LEN                           = 20  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_LPID                              = 52  ;
static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_LPID_LEN                          = 12  ;

static const uint8_t P9N2_CAPP_TLBI_QOS_COMPARE                                   = 0   ;
static const uint8_t P9N2_CAPP_TLBI_QOS_COMPARE_LEN                               = 8   ;
static const uint8_t P9N2_CAPP_TLBI_QOS_INC                                       = 8   ;
static const uint8_t P9N2_CAPP_TLBI_QOS_INC_LEN                                   = 8   ;
static const uint8_t P9N2_CAPP_TLBI_QOS_DEC                                       = 16  ;
static const uint8_t P9N2_CAPP_TLBI_QOS_DEC_LEN                                   = 8   ;
static const uint8_t P9N2_CAPP_TLBI_QOS_EN                                        = 24  ;

static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC0_COUNT                  = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC0_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC1_COUNT                  = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC1_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC2_COUNT                  = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC2_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC3_COUNT                  = 24  ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC3_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP0_COUNT                 = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP0_COUNT_LEN             = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP2_COUNT                 = 40  ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP2_COUNT_LEN             = 8   ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP3_COUNT                 = 48  ;
static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP3_COUNT_LEN             = 8   ;

static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC0_COUNT                        = 0   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC0_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC1_COUNT                        = 8   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC1_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC2_COUNT                        = 16  ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC2_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC3_COUNT                        = 24  ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC3_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP0_COUNT                       = 32  ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP0_COUNT_LEN                   = 8   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP2_COUNT                       = 40  ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP2_COUNT_LEN                   = 8   ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP3_COUNT                       = 48  ;
static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP3_COUNT_LEN                   = 8   ;

static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC0_COUNT                        = 0   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC0_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC1_COUNT                        = 8   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC1_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC2_COUNT                        = 16  ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC2_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC3_COUNT                        = 24  ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC3_COUNT_LEN                    = 8   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP0_COUNT                       = 32  ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP0_COUNT_LEN                   = 8   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP2_COUNT                       = 40  ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP2_COUNT_LEN                   = 8   ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP3_COUNT                       = 48  ;
static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP3_COUNT_LEN                   = 8   ;

static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC0_COUNT                  = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC0_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC1_COUNT                  = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC1_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC2_COUNT                  = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC2_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC3_COUNT                  = 24  ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC3_COUNT_LEN              = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP0_COUNT                 = 32  ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP0_COUNT_LEN             = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP2_COUNT                 = 40  ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP2_COUNT_LEN             = 8   ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP3_COUNT                 = 48  ;
static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP3_COUNT_LEN             = 8   ;

static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT              = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN          = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT              = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN          = 16  ;

static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT                    = 0   ;
static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN                = 16  ;
static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT                    = 16  ;
static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN                = 16  ;

static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT                    = 0   ;
static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN                = 16  ;
static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT                    = 16  ;
static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN                = 16  ;

static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT              = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN          = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT              = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN          = 16  ;

static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC0_COUNT                = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN            = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC1_COUNT                = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN            = 16  ;
static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC2_COUNT                = 32  ;
static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN            = 16  ;

static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC0_COUNT                      = 0   ;
static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN                  = 16  ;
static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC1_COUNT                      = 16  ;
static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN                  = 16  ;
static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC2_COUNT                      = 32  ;
static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN                  = 16  ;

static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC0_COUNT                      = 0   ;
static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN                  = 16  ;
static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC1_COUNT                      = 16  ;
static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN                  = 16  ;
static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC2_COUNT                      = 32  ;
static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN                  = 16  ;

static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC0_COUNT                = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN            = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC1_COUNT                = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN            = 16  ;
static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC2_COUNT                = 32  ;
static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN            = 16  ;

static const uint8_t P9N2_PU_TOD_CMD_REG_ADR                                      = 30  ;
static const uint8_t P9N2_PU_TOD_CMD_REG_ADR_LEN                                  = 31  ;

static const uint8_t P9N2_PU_TOD_DATA_RCV_REG_PCB                                 = 0   ;
static const uint8_t P9N2_PU_TOD_DATA_RCV_REG_PCB_LEN                             = 64  ;

static const uint8_t P9N2_PU_TOD_DATA_SND_REG_PCB                                 = 0   ;
static const uint8_t P9N2_PU_TOD_DATA_SND_REG_PCB_LEN                             = 64  ;

static const uint8_t P9N2_CAPP_TOD_SYNC000_TIMEBASE                               = 55  ;
static const uint8_t P9N2_CAPP_TOD_SYNC000_TIMEBASE_LEN                           = 5   ;
static const uint8_t P9N2_CAPP_TOD_SYNC000_CHIP_STATUS                            = 60  ;
static const uint8_t P9N2_CAPP_TOD_SYNC000_CHIP_STATUS_LEN                        = 4   ;

static const uint8_t P9N2_PEC_TRACE_HI_DATA_REG_DATA                              = 0   ;
static const uint8_t P9N2_PEC_TRACE_HI_DATA_REG_DATA_LEN                          = 64  ;

static const uint8_t P9N2_PU_TRACE_HI_DATA_REG_DATA                               = 0   ;
static const uint8_t P9N2_PU_TRACE_HI_DATA_REG_DATA_LEN                           = 64  ;

static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_DATA                              = 0   ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_DATA_LEN                          = 32  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_ADDRESS                           = 32  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_ADDRESS_LEN                       = 10  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_LAST_BANK                         = 42  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_LAST_BANK_LEN                     = 9   ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_LAST_BANK_VALID                   = 51  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_WRITE_ON_RUN                      = 52  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_RUNNING                           = 53  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_HOLD_ADDRESS                      = 54  ;
static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN                  = 10  ;

static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_DATA                               = 0   ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_DATA_LEN                           = 32  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_ADDRESS                            = 32  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_ADDRESS_LEN                        = 10  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_LAST_BANK                          = 42  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_LAST_BANK_LEN                      = 9   ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_LAST_BANK_VALID                    = 51  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_WRITE_ON_RUN                       = 52  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_RUNNING                            = 53  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_HOLD_ADDRESS                       = 54  ;
static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN                   = 10  ;

static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE              = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE               = 1   ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE                = 2   ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN            = 8   ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_BANK_MODE                       = 10  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_ENH_MODE                        = 11  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL        = 12  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN    = 2   ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_SELECT_CONTROL                  = 14  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN              = 4   ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF                    = 18  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_RUN_STATUS                      = 19  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_RUN_STICKY                      = 20  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT        = 21  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED                  = 22  ;
static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN              = 6   ;

static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE               = 0   ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE                = 1   ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE                 = 2   ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN             = 8   ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_BANK_MODE                        = 10  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_ENH_MODE                         = 11  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL         = 12  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN     = 2   ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_SELECT_CONTROL                   = 14  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN               = 4   ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF                     = 18  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_RUN_STATUS                       = 19  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_RUN_STICKY                       = 20  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT         = 21  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED                   = 22  ;
static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN               = 6   ;

static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63            = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN        = 64  ;

static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63             = 0   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN         = 64  ;

static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87         = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN     = 24  ;

static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87          = 0   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN      = 24  ;

static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNA                      = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN                  = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNB                      = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN                  = 24  ;

static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNA                       = 0   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN                   = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNB                       = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN                   = 24  ;

static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERNC                      = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN                  = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERND                      = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERND_LEN                  = 24  ;

static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERNC                       = 0   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN                   = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERND                       = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERND_LEN                   = 24  ;

static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKA                         = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKA_LEN                     = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKB                         = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKB_LEN                     = 24  ;

static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKA                          = 0   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKA_LEN                      = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKB                          = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKB_LEN                      = 24  ;

static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKC                         = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKC_LEN                     = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKD                         = 24  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKD_LEN                     = 24  ;

static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKC                          = 0   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKC_LEN                      = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKD                          = 24  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKD_LEN                      = 24  ;

static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION           = 0   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL                 = 2   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN             = 2   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL                 = 4   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN             = 2   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL                 = 6   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN             = 2   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL                 = 8   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN             = 2   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK                 = 10  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN             = 4   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK                = 14  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN            = 4   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK                 = 18  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN             = 4   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK                = 22  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN            = 4   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE                = 26  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE                = 27  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE                = 28  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN            = 4   ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK                = 32  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN             = 33  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP                 = 34  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP                 = 35  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES    = 36  ;
static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_SPARE_LT                      = 37  ;

static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION            = 0   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL                  = 2   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN              = 2   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL                  = 4   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN              = 2   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL                  = 6   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN              = 2   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL                  = 8   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN              = 2   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK                  = 10  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN              = 4   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK                 = 14  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN             = 4   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK                  = 18  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN              = 4   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK                 = 22  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN             = 4   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE                 = 26  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE                 = 27  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE                 = 28  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN             = 4   ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK                 = 32  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN              = 33  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP                  = 34  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP                  = 35  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES     = 36  ;
static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_SPARE_LT                       = 37  ;

static const uint8_t P9N2_PU_TRUST_CONTROL_FSP_TCE_ENABLE                         = 2   ;
static const uint8_t P9N2_PU_TRUST_CONTROL_SECURE_BOOTH                           = 3   ;

static const uint8_t P9N2_PHB_TUNNEL_BAR_REG_PE                                   = 0   ;
static const uint8_t P9N2_PHB_TUNNEL_BAR_REG_PE_LEN                               = 43  ;

static const uint8_t P9N2_PEC_STACK0_TUNNEL_BAR_REG_PE                            = 0   ;
static const uint8_t P9N2_PEC_STACK0_TUNNEL_BAR_REG_PE_LEN                        = 43  ;

static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_CTRL_CE                          = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_CTRL_UE                          = 1   ;
static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_DATA_CE                          = 2   ;
static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_DATA_UE                          = 3   ;
static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_CTRL_PEND                        = 4   ;
static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_DATA_PEND                        = 5   ;

static const uint8_t P9N2__CTL_TXI_ERR_INJ_CTRL_CE                                = 0   ;
static const uint8_t P9N2__CTL_TXI_ERR_INJ_CTRL_UE                                = 1   ;
static const uint8_t P9N2__CTL_TXI_ERR_INJ_DATA_CE                                = 2   ;
static const uint8_t P9N2__CTL_TXI_ERR_INJ_DATA_UE                                = 3   ;
static const uint8_t P9N2__CTL_TXI_ERR_INJ_CTRL_PEND                              = 4   ;
static const uint8_t P9N2__CTL_TXI_ERR_INJ_DATA_PEND                              = 5   ;

static const uint8_t P9N2__SM3_TXI_ERR_INJ_CTRL_CE                                = 0   ;
static const uint8_t P9N2__SM3_TXI_ERR_INJ_CTRL_UE                                = 1   ;
static const uint8_t P9N2__SM3_TXI_ERR_INJ_DATA_CE                                = 2   ;
static const uint8_t P9N2__SM3_TXI_ERR_INJ_DATA_UE                                = 3   ;
static const uint8_t P9N2__SM3_TXI_ERR_INJ_CTRL_PEND                              = 4   ;
static const uint8_t P9N2__SM3_TXI_ERR_INJ_DATA_PEND                              = 5   ;

static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_CTRL_CE                          = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_CTRL_UE                          = 1   ;
static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_DATA_CE                          = 2   ;
static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_DATA_UE                          = 3   ;
static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_CTRL_PEND                        = 4   ;
static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_DATA_PEND                        = 5   ;

static const uint8_t P9N2_PU_TX_CH_FSM_REG_TX_CH_FSM                              = 0   ;
static const uint8_t P9N2_PU_TX_CH_FSM_REG_TX_CH_FSM_LEN                          = 3   ;

static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_0                        = 0   ;
static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_1                        = 1   ;
static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_2                        = 2   ;
static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_3                        = 3   ;
static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_4                        = 4   ;
static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_5                        = 5   ;
static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_6                        = 6   ;
static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_7                        = 7   ;

static const uint8_t P9N2_PU_TX_CH_MISC_REG_FSM                                   = 0   ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_FSM_LEN                               = 4   ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_TFRAMESIZE                            = 7   ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_TFRAMESIZE_LEN                        = 5   ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_WEN0                                  = 12  ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_WEN1                                  = 13  ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_WEN2                                  = 14  ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_DATA_REQ                              = 15  ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_START_TRANS                           = 16  ;
static const uint8_t P9N2_PU_TX_CH_MISC_REG_GXDATAAVAIL_Q                         = 17  ;

static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_ENABLE_SCWR_TO_TXRF                 = 0   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_GXC_PSI             = 1   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_TXRF_PSI            = 2   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_CRC_MODE                            = 3   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_CHIP_PERSONALISATION                = 4   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_ENABLE_STREAMING_MODE               = 5   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_CHIP_INTERFACEMODE                  = 6   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_DISABLE_TIMEOUT_AND_RETRY           = 7   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_FENCE_IO_INTERFACE                  = 8   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_FENCE_GX_INTERFACE                  = 9   ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_GX_ENABLE_OVERWRITE                 = 10  ;
static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_TXSC                                = 11  ;

static const uint8_t P9N2_PU_TX_DBFF_REG0_DATA_BUFF0                              = 0   ;
static const uint8_t P9N2_PU_TX_DBFF_REG0_DATA_BUFF0_LEN                          = 32  ;

static const uint8_t P9N2_PU_TX_DBFF_REG1_DATA_BUFF1                              = 0   ;
static const uint8_t P9N2_PU_TX_DBFF_REG1_DATA_BUFF1_LEN                          = 32  ;

static const uint8_t P9N2_PU_TX_DF_FSM_REG_TX_DF_FSM                              = 0   ;
static const uint8_t P9N2_PU_TX_DF_FSM_REG_TX_DF_FSM_LEN                          = 4   ;

static const uint8_t P9N2_PU_NPU_CTL_TX_DL_CREDIT_STATUS_COUNT                    = 0   ;
static const uint8_t P9N2_PU_NPU_CTL_TX_DL_CREDIT_STATUS_COUNT_LEN                = 12  ;

static const uint8_t P9N2__CTL_TX_DL_CREDIT_STATUS_COUNT                          = 0   ;
static const uint8_t P9N2__CTL_TX_DL_CREDIT_STATUS_COUNT_LEN                      = 12  ;

static const uint8_t P9N2__SM3_TX_DL_CREDIT_STATUS_COUNT                          = 0   ;
static const uint8_t P9N2__SM3_TX_DL_CREDIT_STATUS_COUNT_LEN                      = 12  ;

static const uint8_t P9N2_PU_NPU_SM3_TX_DL_CREDIT_STATUS_COUNT                    = 0   ;
static const uint8_t P9N2_PU_NPU_SM3_TX_DL_CREDIT_STATUS_COUNT_LEN                = 12  ;

static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_DATA_PCK                    = 0   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_TZRTMP_PCK                  = 1   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXEI_SHIFT_PCK                    = 2   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXEI_TRANSMIT_PCK                 = 3   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_PARITY                      = 4   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_UNDERRUN                    = 5   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXBFF_DATA_PCK                    = 6   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXBFF_TDO_PCK                     = 7   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXBFF_TFC_PCK                     = 8   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_FSM_PCK                      = 9   ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_DATA_BUFF_PCK                = 10  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_TDO_PCK                      = 11  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_TADDR_PCK                    = 12  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_TCTRL_PCK                    = 13  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_UE_RF                        = 14  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C0_PSITXLC_CE_RF                        = 15  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_UE_GX_2N                     = 16  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C0_PSITXLC_CE_GX_2N                     = 17  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST2_PCK_2N            = 18  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST3_PCK_2N            = 19  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TADDR_PCK                   = 20  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TCTRL_PCK                   = 21  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_CMD_CTRL_PCK            = 22  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RSP_CTRL_PCK            = 23  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TFSM_PCK                    = 24  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_FSM_PCK                 = 25  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C4_PSIRFACC_TXSC_PCK                    = 26  ;
static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RETRY_ERR               = 27  ;

static const uint8_t P9N2_PU_TX_ERR_MODE_TX_ERR_MODE_0                            = 0   ;
static const uint8_t P9N2_PU_TX_ERR_MODE_TX_ERR_MODE_1                            = 1   ;

static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_DATA_PCK                        = 0   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_TZRTMP_PCK                      = 1   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXEI_SHIFT_PCK                        = 2   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXEI_TRANSMIT_PCK                     = 3   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_PARITY                          = 4   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_UNDERRUN                        = 5   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXBFF_DATA_PCK                        = 6   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXBFF_TDO_PCK                         = 7   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXBFF_TFC_PCK                         = 8   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_FSM_PCK                          = 9   ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_DATA_BUFF_PCK                    = 10  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_TDO_PCK                          = 11  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_TADDR_PCK                        = 12  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_TCTRL_PCK                        = 13  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_UE_RF                            = 14  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_CE_RF                            = 15  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_UE_GX_2N                         = 16  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_CE_GX_2N                         = 17  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_DATA_GXST2_PCK_2N                = 18  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_DATA_GXST3_PCK_2N                = 19  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TADDR_PCK                       = 20  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TCTRL_PCK                       = 21  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_CMD_CTRL_PCK                = 22  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_RSP_CTRL_PCK                = 23  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TFSM_PCK                        = 24  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_FSM_PCK                     = 25  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TXSC_PCK                        = 26  ;
static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_RETRY_ERR                   = 27  ;

static const uint8_t P9N2_PU_TX_PSI_CNTL_TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL      = 0   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_DRV_PATTERN_EN                           = 1   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_PATTERN_SEL                              = 2   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_PATTERN_SEL_LEN                          = 2   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_P                            = 4   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_P_LEN                        = 2   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_N                            = 6   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_N_LEN                        = 2   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_LANE_QUIESCE                             = 8   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_LANE_QUIESCE_LEN                         = 2   ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_INVERT                               = 10  ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_LANE_INVERT                              = 11  ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_PDWN                                     = 12  ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_BIST_EN                                  = 13  ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_SPARE                                    = 24  ;
static const uint8_t P9N2_PU_TX_PSI_CNTL_SPARE_LEN                                = 8   ;

static const uint8_t P9N2_PU_TX_PSI_MODE_PC_TEST                                  = 0   ;
static const uint8_t P9N2_PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC                        = 4   ;
static const uint8_t P9N2_PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC_LEN                    = 4   ;
static const uint8_t P9N2_PU_TX_PSI_MODE_PC_SLICE_EN_ENC                          = 12  ;
static const uint8_t P9N2_PU_TX_PSI_MODE_PC_SLICE_EN_ENC_LEN                      = 4   ;
static const uint8_t P9N2_PU_TX_PSI_MODE_SLEWCTL                                  = 16  ;
static const uint8_t P9N2_PU_TX_PSI_MODE_SLEWCTL_LEN                              = 4   ;
static const uint8_t P9N2_PU_TX_PSI_MODE_PVTNL_ENC                                = 24  ;
static const uint8_t P9N2_PU_TX_PSI_MODE_PVTNL_ENC_LEN                            = 2   ;
static const uint8_t P9N2_PU_TX_PSI_MODE_PVTPL_ENC                                = 28  ;
static const uint8_t P9N2_PU_TX_PSI_MODE_PVTPL_ENC_LEN                            = 2   ;

static const uint8_t P9N2_PU_TX_PSI_STATUS_SPARE                                  = 0   ;
static const uint8_t P9N2_PU_TX_PSI_STATUS_SPARE_LEN                              = 4   ;
static const uint8_t P9N2_PU_TX_PSI_STATUS_BIST_ERROR                             = 4   ;
static const uint8_t P9N2_PU_TX_PSI_STATUS_BIST_ERROR_LEN                         = 3   ;
static const uint8_t P9N2_PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL             = 7   ;
static const uint8_t P9N2_PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL_LEN         = 3   ;

static const uint8_t P9N2_PU_TX_TO_RT_REG_TIMEOUT_VALUE                           = 0   ;
static const uint8_t P9N2_PU_TX_TO_RT_REG_TIMEOUT_VALUE_LEN                       = 4   ;
static const uint8_t P9N2_PU_TX_TO_RT_REG_RETRY_VALUE                             = 4   ;
static const uint8_t P9N2_PU_TX_TO_RT_REG_RETRY_VALUE_LEN                         = 4   ;

static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_CRB_READS_ENBL                   = 1   ;
static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_CRB_READS_HALTED                 = 2   ;
static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_IDLE                             = 3   ;
static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCE_REQUEST                  = 4   ;
static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCE_ACHEIVED                 = 5   ;
static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCE_FAILED                   = 6   ;
static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCED                         = 7   ;
static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_PASTE_ADDR_ALIGN                 = 8   ;

static const uint8_t P9N2_PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT                      = 49  ;
static const uint8_t P9N2_PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT_LEN                  = 7   ;
static const uint8_t P9N2_PU_VAS_BUFCTL_CONSUMED_BUF_COUNT                        = 57  ;
static const uint8_t P9N2_PU_VAS_BUFCTL_CONSUMED_BUF_COUNT_LEN                    = 7   ;

static const uint8_t P9N2_PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0                       = 0   ;
static const uint8_t P9N2_PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0_LEN                   = 64  ;

static const uint8_t P9N2_PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1                       = 0   ;
static const uint8_t P9N2_PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1_LEN                   = 64  ;

static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_RESET                           = 0   ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT4                            = 4   ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT5                            = 5   ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT6                            = 6   ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT7                            = 7   ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT8                            = 8   ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT9                            = 9   ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT10                           = 10  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT11                           = 11  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT12                           = 12  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT13                           = 13  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT14                           = 14  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT15                           = 15  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT16                           = 16  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT17                           = 17  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT18                           = 18  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT19                           = 19  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT20                           = 20  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT21                           = 21  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT22                           = 22  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT23                           = 23  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT24                           = 24  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT25                           = 25  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT26                           = 26  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT27                           = 27  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT28                           = 28  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT29                           = 29  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT30                           = 30  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT31                           = 31  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT32                           = 32  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT33                           = 33  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT34                           = 34  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT35                           = 35  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT36                           = 36  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT37                           = 37  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT38                           = 38  ;
static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT39                           = 39  ;

static const uint8_t P9N2_PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63                      = 0   ;
static const uint8_t P9N2_PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63_LEN                  = 64  ;

static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO                    = 0   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO_LEN                = 2   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI                    = 2   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI_LEN                = 2   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01                      = 4   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01_LEN                  = 2   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23                      = 6   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23_LEN                  = 2   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO                   = 8   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI                   = 11  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01                 = 14  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23                 = 17  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO                   = 20  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI                   = 23  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01                 = 26  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23                 = 29  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_IN_TRACE                         = 32  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_RG_TRACE                         = 33  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0                  = 34  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0_LEN              = 2   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_PMU_DATA                         = 36  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1                  = 37  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1_LEN              = 3   ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_IN_PMU_COUNTING                  = 40  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_RG_PMU_COUNTING                  = 41  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_LO                    = 42  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_HI                    = 43  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_LO                    = 44  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_HI                    = 45  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_LO                    = 46  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_HI                    = 47  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_01                    = 48  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_23                    = 49  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_01                    = 50  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_23                    = 51  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_01                    = 52  ;
static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_23                    = 53  ;

static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_LO               = 0   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_HI               = 1   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_LO               = 2   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_HI               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_01               = 4   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_23               = 5   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_01               = 6   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_23               = 7   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO                   = 8   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO_LEN               = 4   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI                   = 12  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI_LEN               = 4   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01                 = 16  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01_LEN             = 2   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23                 = 18  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23_LEN             = 2   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO                   = 20  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI                   = 23  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01                 = 26  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23                 = 29  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO                   = 32  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI                   = 35  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI_LEN               = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01                 = 38  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23                 = 41  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23_LEN             = 3   ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_EG_TRACE                         = 44  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_WC_TRACE                         = 45  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_CQ_TRACE                         = 46  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_LO                    = 47  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_HI                    = 48  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_LO                    = 49  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_LO                 = 50  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_HI                 = 51  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_EG_PMU_COUNTING                  = 52  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_HI                    = 53  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_CQ_PMU_COUNTING                  = 54  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_LO                    = 55  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_HI                    = 56  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_01                    = 57  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_23                    = 58  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_01                    = 59  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_23                    = 60  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_01                    = 61  ;
static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_23                    = 62  ;

static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87                     = 0   ;
static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87_LEN                 = 24  ;
static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS                   = 24  ;
static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS_LEN               = 4   ;

static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_RESET                           = 0   ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT4                            = 4   ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT5                            = 5   ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT6                            = 6   ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT7                            = 7   ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT8                            = 8   ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT9                            = 9   ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT10                           = 10  ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT11                           = 11  ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS                      = 12  ;
static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS_LEN                  = 8   ;

static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_ENA                = 0   ;
static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_TYP                = 1   ;
static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_FRQ                = 2   ;
static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED             = 3   ;
static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN         = 5   ;

static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_ENA                = 0   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_TYP                = 1   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_FRQ                = 2   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL                = 3   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL_LEN            = 2   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_ENA                = 5   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_TYP                = 6   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_FRQ                = 7   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_SEL                = 8   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED                = 9   ;
static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED_LEN            = 3   ;

static const uint8_t P9N2_PU_VAS_FIR_ACTION0_REG_ACTION0                          = 0   ;
static const uint8_t P9N2_PU_VAS_FIR_ACTION0_REG_ACTION0_LEN                      = 54  ;

static const uint8_t P9N2_PU_VAS_FIR_ACTION1_REG_ACTION1                          = 0   ;
static const uint8_t P9N2_PU_VAS_FIR_ACTION1_REG_ACTION1_LEN                      = 54  ;

static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_LOGIC_HW_ERROR                   = 0   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_LOGIC_HW_ERROR                   = 1   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_LOGIC_HW_ERROR                   = 2   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_LOGIC_HW_ERROR                   = 3   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_LOGIC_HW_ERROR                   = 4   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_PARITY_ERROR                  = 5   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_RD_ADDR_ERROR                 = 6   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_WR_ADDR_ERROR                 = 7   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_ECC_CE_ERROR                     = 8   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_ECC_CE_ERROR                     = 9   ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_ECC_CE_ERROR                     = 10  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_ECC_CE_ERROR                     = 11  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_ECC_CE_ERROR                     = 12  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_OB_CE_ERROR                   = 13  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_OB_UE_ERROR                   = 14  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_MASTER_FSM_HANG               = 15  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_ECC_UE_ERROR                     = 16  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_ECC_UE_ERROR                     = 17  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_ECC_UE_ERROR                     = 18  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_ECC_UE_ERROR                     = 19  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_ECC_UE_ERROR                     = 20  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_PARITY_ERROR                     = 21  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_SW_CAST_ERROR                    = 22  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_SMF_ACCESS_ERROR                 = 23  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_ECC_SUE_ERROR                    = 24  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_ECC_SUE_ERROR                    = 25  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_ECC_SUE_ERROR                    = 26  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_ECC_SUE_ERROR                    = 27  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_ECC_SUE_ERROR                    = 28  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_RD_LINK_ERROR                 = 29  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_WR_LINK_ERROR                 = 30  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_LINK_ABORT                    = 31  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_HYP_RD_ADDR_ERR                = 32  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_OS_RD_ADDR_ERR                 = 33  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_HYP_WR_ADDR_ERR                = 34  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_OS_WR_ADDR_ERR                 = 35  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_NON8B_HYP_ERR                  = 36  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_NON8B_OS_ERR                   = 37  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WM_WIN_NOT_OPEN_ERR                 = 38  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WM_MULTIHIT_ERR                     = 39  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_PG_MIG_DISABLED_ERR                 = 40  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_PG_MIG_SIZE_MISMATCH_ERR            = 41  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_NOTIFY_FAILED_ERR                   = 42  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WR_MON_NOT_DISABLED_ERR             = 43  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_REJECTED_PASTE_CMD                  = 44  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_DATA_HANG_DETECTED                  = 45  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_INCOMING_PB_PARITY_ERR              = 46  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOM1_SAT_ERR                       = 47  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_NX_LOCAL_XSTOP                      = 48  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOM_MMIO_ADDR_ERR                  = 49  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_UNUSED50                            = 50  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_UNUSED51                            = 51  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_0                   = 52  ;
static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_1                   = 53  ;

static const uint8_t P9N2_PU_VAS_FIR_REG_EG_LOGIC_HW_ERROR                        = 0   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_IN_LOGIC_HW_ERROR                        = 1   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_LOGIC_HW_ERROR                        = 2   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_WC_LOGIC_HW_ERROR                        = 3   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_RG_LOGIC_HW_ERROR                        = 4   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_PARITY_ERROR                       = 5   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_RD_ADDR_ERROR                      = 6   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_WR_ADDR_ERROR                      = 7   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_EG_ECC_CE_ERROR                          = 8   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_IN_ECC_CE_ERROR                          = 9   ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_ECC_CE_ERROR                          = 10  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_WC_ECC_CE_ERROR                          = 11  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_RG_ECC_CE_ERROR                          = 12  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_OB_CE_ERROR                        = 13  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_OB_UE_ERROR                        = 14  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_MASTER_FSM_HANG                    = 15  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_EG_ECC_UE_ERROR                          = 16  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_IN_ECC_UE_ERROR                          = 17  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_ECC_UE_ERROR                          = 18  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_WC_ECC_UE_ERROR                          = 19  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_RG_ECC_UE_ERROR                          = 20  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_IN_PARITY_ERROR                          = 21  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_IN_SW_CAST_ERROR                         = 22  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_SMF_ACCESS_ERROR                      = 23  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_EG_ECC_SUE_ERROR                         = 24  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_IN_ECC_SUE_ERROR                         = 25  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_ECC_SUE_ERROR                         = 26  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_WC_ECC_SUE_ERROR                         = 27  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_RG_ECC_SUE_ERROR                         = 28  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_RD_LINK_ERROR                      = 29  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_WR_LINK_ERROR                      = 30  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_LINK_ABORT                         = 31  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_HYP_RD_ADDR_ERR                     = 32  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_OS_RD_ADDR_ERR                      = 33  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_HYP_WR_ADDR_ERR                     = 34  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_OS_WR_ADDR_ERR                      = 35  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_NON8B_HYP_ERR                       = 36  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_NON8B_OS_ERR                        = 37  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_WM_WIN_NOT_OPEN_ERR                      = 38  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_WM_MULTIHIT_ERR                          = 39  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_PG_MIG_DISABLED_ERR                      = 40  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_PG_MIG_SIZE_MISMATCH_ERR                 = 41  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_NOTIFY_FAILED_ERR                        = 42  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_WR_MON_NOT_DISABLED_ERR                  = 43  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_REJECTED_PASTE_CMD                       = 44  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_DATA_HANG_DETECTED                       = 45  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_INCOMING_PB_PARITY_ERR                   = 46  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_SCOM1_SAT_ERR                            = 47  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_NX_LOCAL_XSTOP                           = 48  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_SCOM_MMIO_ADDR_ERR                       = 49  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_UNUSED50                                 = 50  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_UNUSED51                                 = 51  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_SCOMFIR_INT_ERR_0                        = 52  ;
static const uint8_t P9N2_PU_VAS_FIR_REG_SCOMFIR_INT_ERR_1                        = 53  ;

static const uint8_t P9N2_PU_VAS_FIR_WOF_REG_WOF                                  = 0   ;
static const uint8_t P9N2_PU_VAS_FIR_WOF_REG_WOF_LEN                              = 54  ;

static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_RESET                           = 0   ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT4                            = 4   ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT5                            = 5   ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT6                            = 6   ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT7                            = 7   ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT8                            = 8   ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT9                            = 9   ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT10                           = 10  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT11                           = 11  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT12                           = 12  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT13                           = 13  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT14                           = 14  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT15                           = 15  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT16                           = 16  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT17                           = 17  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT18                           = 18  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT19                           = 19  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT20                           = 20  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT21                           = 21  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT22                           = 22  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT23                           = 23  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT24                           = 24  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT25                           = 25  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT26                           = 26  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT27                           = 27  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT28                           = 28  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT29                           = 29  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT30                           = 30  ;
static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT31                           = 31  ;

static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_4VS64                           = 0   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_ACCEPT_PASTE                    = 1   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_ENABLE_WRMON                    = 2   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_DISABLE_PUSH2MEM_LIMIT          = 3   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_QUIESCE_REQUEST                 = 4   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_PREFETCH_DISABLE                = 5   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_WCMBAR_ENABLE                   = 6   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UWCMBAR_ENABLE                  = 7   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_RMABAR_ENABLE                   = 8   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS                     = 9   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS_LEN                 = 7   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_LOC              = 47  ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_ALL              = 48  ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION                    = 49  ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION_LEN                = 7   ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_CAM_INVAL_DONE                  = 56  ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS2                    = 57  ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_HMI_ACTIVE                      = 58  ;
static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_RG_IS_IDLE                      = 59  ;

static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_INIT                            = 0   ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_COMP                            = 1   ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OPTYPE                          = 2   ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_ACTYPE                          = 3   ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OP_ERR                          = 4   ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_UNUSED                          = 5   ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_UNUSED_LEN                      = 3   ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OFFSET                          = 36  ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OFFSET_LEN                      = 12  ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_WINID                           = 48  ;
static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_WINID_LEN                       = 16  ;

static const uint8_t P9N2_PU_VAS_MMIODATA_MMIO_DATA                               = 0   ;
static const uint8_t P9N2_PU_VAS_MMIODATA_MMIO_DATA_LEN                           = 64  ;

static const uint8_t P9N2_PU_VAS_MMIOECC_MMIO_ECC                                 = 0   ;
static const uint8_t P9N2_PU_VAS_MMIOECC_MMIO_ECC_LEN                             = 8   ;

static const uint8_t P9N2_PU_VAS_MMIO_BASE_ADDR_BAR                               = 8   ;
static const uint8_t P9N2_PU_VAS_MMIO_BASE_ADDR_BAR_LEN                           = 31  ;

static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_ADDR_EXT_MASK                     = 0   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_ADDR_EXT_MASK_LEN                 = 7   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT                 = 7   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT_LEN             = 4   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_SMF_CONFIG                        = 11  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_SMF_CONFIG_LEN                    = 2   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_UNUSED1                           = 13  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_UNUSED1_LEN                       = 2   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT                   = 15  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT_LEN               = 4   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_DISABLE_WR_RD_PUSH                = 19  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_CE                            = 20  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_UE                            = 21  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_SUE                           = 22  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_ARRAY_SEL                     = 23  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_FREQ                          = 24  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_TO_TRACE                    = 25  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_TO_TRACE_LEN                = 4   ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_DISABLES                    = 29  ;
static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_DISABLES_LEN                = 3   ;

static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_LN_WR                             = 0   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_G_WR                              = 1   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_VG_WR                             = 2   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_NN_WR                             = 3   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_LN_RD                             = 4   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_G_RD                              = 5   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_VG_RD                             = 6   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_NN_RD                             = 7   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED1                           = 8   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED1_LEN                       = 4   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_RD_GO_M_QOS                               = 12  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_ADDR_BAR_MODE                             = 13  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_SKIP_G                                    = 14  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_HANG_SM_ON_ARE                            = 15  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_HANG_SM_ON_LINK_FAIL                      = 16  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_CFG_PUMP_MODE                             = 17  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_WR_NOT_INJ                            = 18  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_PART_WR_NOT_INJ                       = 19  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK                       = 20  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK_LEN                   = 8   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK                       = 28  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK_LEN                   = 8   ;
static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED2                           = 36  ;
static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED2_LEN                       = 16  ;

static const uint8_t P9N2_PU_VAS_PMCNTL_PU_BIT_ENABLES                            = 0   ;
static const uint8_t P9N2_PU_VAS_PMCNTL_PU_BIT_ENABLES_LEN                        = 32  ;
static const uint8_t P9N2_PU_VAS_PMCNTL_PU_CNTL_UNUSED                            = 32  ;
static const uint8_t P9N2_PU_VAS_PMCNTL_PU_CNTL_UNUSED_LEN                        = 4   ;

static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_RESET                           = 0   ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT4                            = 4   ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT5                            = 5   ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT6                            = 6   ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT7                            = 7   ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT8                            = 8   ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT9                            = 9   ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT10                           = 10  ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT11                           = 11  ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT12                           = 12  ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT13                           = 13  ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS                     = 14  ;
static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS_LEN                 = 10  ;

static const uint8_t P9N2_PU_VAS_RMABAR_RMA_BAR                                   = 8   ;
static const uint8_t P9N2_PU_VAS_RMABAR_RMA_BAR_LEN                               = 44  ;

static const uint8_t P9N2_PU_VAS_RMABARM_RMA_BAR_MASK                             = 8   ;
static const uint8_t P9N2_PU_VAS_RMABARM_RMA_BAR_MASK_LEN                         = 44  ;

static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_SCRUB              = 0   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_ECC                = 1   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_SINGLE_THREAD              = 2   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE         = 3   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_STAMP_DEBUG                = 4   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EN_FAST_SCRUB                 = 5   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_DIS_SIMULT_RD_WR              = 6   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_ENA_NOTIFY_ORDER              = 7   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_WC_IDLE_BIT                   = 8   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_CQ_IDLE_BIT                   = 9   ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_IDLE_BIT                   = 10  ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED                        = 11  ;
static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED_LEN                    = 5   ;

static const uint8_t P9N2_PU_VAS_UWMBAR_BASE_ADDR                                 = 8   ;
static const uint8_t P9N2_PU_VAS_UWMBAR_BASE_ADDR_LEN                             = 28  ;

static const uint8_t P9N2_PU_VAS_WCBSBAR_WC_BS_BAR                                = 8   ;
static const uint8_t P9N2_PU_VAS_WCBSBAR_WC_BS_BAR_LEN                            = 33  ;

static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_RESET                           = 0   ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT4                            = 4   ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT5                            = 5   ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT6                            = 6   ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT7                            = 7   ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT8                            = 8   ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT9                            = 9   ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT10                           = 10  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT11                           = 11  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT12                           = 12  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT13                           = 13  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT14                           = 14  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT15                           = 15  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT16                           = 16  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT17                           = 17  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT18                           = 18  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT19                           = 19  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT20                           = 20  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT21                           = 21  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT22                           = 22  ;
static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT23                           = 23  ;

static const uint8_t P9N2_PU_VAS_WCMBAR_BASE_ADDR                                 = 8   ;
static const uint8_t P9N2_PU_VAS_WCMBAR_BASE_ADDR_LEN                             = 31  ;

static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_TIMER_ENBL             = 0   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV                = 1   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV_LEN            = 4   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_TIMER_ENBL             = 5   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV                = 6   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV_LEN            = 4   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_TIMER_ENBL             = 10  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV                = 11  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV_LEN            = 4   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_TIMER_ENBL             = 15  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV                = 16  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV_LEN            = 4   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_TIMER_ENBL             = 20  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV                = 21  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV_LEN            = 4   ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_ENBL             = 25  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV          = 26  ;
static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV_LEN      = 4   ;

static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0                = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0_LEN            = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0                   = 32  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0_LEN               = 8   ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_LBUS_PARITY_ERR1_0             = 40  ;

static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1                = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1_LEN            = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1                   = 32  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1_LEN               = 8   ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_LBUS_PARITY_ERR1_1             = 40  ;

static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2                = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2_LEN            = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2                   = 32  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2_LEN               = 8   ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_LBUS_PARITY_ERR1_2             = 40  ;

static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3                = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3_LEN            = 16  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3                   = 32  ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN               = 8   ;
static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3             = 40  ;

static const uint8_t P9N2_PHB_WOF_REG_AIB_COMMAND_INVALID                         = 0   ;
static const uint8_t P9N2_PHB_WOF_REG_AIB_ADDRESSING_ERROR                        = 1   ;
static const uint8_t P9N2_PHB_WOF_REG_AIB_ACCESS_ERROR                            = 2   ;
static const uint8_t P9N2_PHB_WOF_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED     = 3   ;
static const uint8_t P9N2_PHB_WOF_REG_AIB_FATAL_CLASS_ERROR                       = 4   ;
static const uint8_t P9N2_PHB_WOF_REG_AIB_INF_CLASS_ERROR                         = 5   ;
static const uint8_t P9N2_PHB_WOF_REG_PE_STOP_STATE_ERROR                         = 6   ;
static const uint8_t P9N2_PHB_WOF_REG_AIB_DAT_ERR_SIGNALED                        = 7   ;
static const uint8_t P9N2_PHB_WOF_REG_OUT_COMMON_ARRAY_FATAL_ERROR                = 8   ;
static const uint8_t P9N2_PHB_WOF_REG_OUT_COMMON_LATCH_FATAL_ERROR                = 9   ;
static const uint8_t P9N2_PHB_WOF_REG_OUT_COMMON_LOGIC_FATAL_ERROR                = 10  ;
static const uint8_t P9N2_PHB_WOF_REG_BLIF_OUT_INTERFACE_PARITY_ERROR             = 11  ;
static const uint8_t P9N2_PHB_WOF_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE            = 12  ;
static const uint8_t P9N2_PHB_WOF_REG_MMIO_REQUEST_TIMEOUT                        = 13  ;
static const uint8_t P9N2_PHB_WOF_REG_OUT_RRB_SOURCED_ERROR                       = 14  ;
static const uint8_t P9N2_PHB_WOF_REG_CFG_LOGIC_SIGNALED_ERROR                    = 15  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_REG_REQUEST_ADDRESS_ERROR               = 16  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_FDA_FATAL_ERROR                         = 17  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_FDA_INF_ERROR                           = 18  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_FDB_FATAL_ERROR                         = 19  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_FDB_INF_ERROR                           = 20  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_ERR_FATAL_ERROR                         = 21  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_ERR_INF_ERROR                           = 22  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_DBG_FATAL_ERROR                         = 23  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_DBG_INF_ERROR                           = 24  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_PCIE_REQUEST_ACCESS_ERROR               = 25  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_BUS_LOGIC_ERROR                         = 26  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_UVI_FATAL_ERROR                         = 27  ;
static const uint8_t P9N2_PHB_WOF_REG_RSB_UVI_INF_ERROR                           = 28  ;
static const uint8_t P9N2_PHB_WOF_REG_SCOM_FATAL_ERROR                            = 29  ;
static const uint8_t P9N2_PHB_WOF_REG_SCOM_INF_ERROR                              = 30  ;
static const uint8_t P9N2_PHB_WOF_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS              = 31  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_IODA_FATAL_ERROR                        = 32  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_MSI_PE_MATCH_ERROR                      = 33  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_MSI_ADDRESS_ERROR                       = 34  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_TVT_ERROR                               = 35  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_RCVD_FATAL_ERROR_MSG                    = 36  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_RCVD_NONFATAL_ERROR_MSG                 = 37  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG              = 38  ;
static const uint8_t P9N2_PHB_WOF_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED      = 39  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_COMMON_FATAL_ERROR                      = 40  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_TABLE_BAR_DISABLED_ERROR                = 41  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_BLIF_COMPLETION_ERROR                   = 42  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_PCT_TIMEOUT_ERROR                       = 43  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_ECC_CORRECTABLE_ERROR                   = 44  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_ECC_UNCORRECTABLE_ERROR                 = 45  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_TLP_POISON_SIGNALED                     = 46  ;
static const uint8_t P9N2_PHB_WOF_REG_ARB_RTT_PENUM_INVALID_ERROR                 = 47  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_COMMON_FATAL_ERROR                      = 48  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_TABLE_BAR_DISABLED_ERROR                = 49  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_ECC_CORRECTABLE_ERROR                   = 50  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_ECC_UNCORRECTABLE_ERROR                 = 51  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_AIB2_TX_TIMEOUT_ERROR                   = 52  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_MRT_ERROR                               = 53  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_RESERVED01                              = 54  ;
static const uint8_t P9N2_PHB_WOF_REG_MRG_RESERVED02                              = 55  ;
static const uint8_t P9N2_PHB_WOF_REG_TCE_IODA_PAGE_ACCESS_ERROR                  = 56  ;
static const uint8_t P9N2_PHB_WOF_REG_TCE_REQUEST_TIMEOUT_ERROR                   = 57  ;
static const uint8_t P9N2_PHB_WOF_REG_TCE_UNEXPECTED_RESPONSE_ERROR               = 58  ;
static const uint8_t P9N2_PHB_WOF_REG_TCE_COMMON_FATAL_ERRORS                     = 59  ;
static const uint8_t P9N2_PHB_WOF_REG_TCE_ECC_CORRECTABLE_ERROR                   = 60  ;
static const uint8_t P9N2_PHB_WOF_REG_TCE_ECC_UNCORRECTABLE_ERROR                 = 61  ;
static const uint8_t P9N2_PHB_WOF_REG_TCE_RESERVED01                              = 62  ;
static const uint8_t P9N2_PHB_WOF_REG_LEM_FIR_INTERNAL_PARITY_ERROR               = 63  ;

static const uint8_t P9N2_PU_N3_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             = 0   ;
static const uint8_t P9N2_PU_N3_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    = 1   ;

static const uint8_t P9N2_PU_N1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             = 0   ;
static const uint8_t P9N2_PU_N1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    = 1   ;

static const uint8_t P9N2_PU_WRITE_PROTECT_ENABLE_REG_RING_LOCKING                = 0   ;
static const uint8_t P9N2_PU_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING       = 1   ;

static const uint8_t P9N2_PU_N2_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             = 0   ;
static const uint8_t P9N2_PU_N2_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    = 1   ;

static const uint8_t P9N2_PEC_WRITE_PROTECT_ENABLE_REG_RING_LOCKING               = 0   ;
static const uint8_t P9N2_PEC_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING      = 1   ;

static const uint8_t P9N2_PU_N0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             = 0   ;
static const uint8_t P9N2_PU_N0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    = 1   ;

static const uint8_t P9N2_PU_N3_WRITE_PROTECT_RINGS_REG_RINGS                     = 0   ;
static const uint8_t P9N2_PU_N3_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 = 16  ;

static const uint8_t P9N2_PU_N1_WRITE_PROTECT_RINGS_REG_RINGS                     = 0   ;
static const uint8_t P9N2_PU_N1_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 = 16  ;

static const uint8_t P9N2_PU_WRITE_PROTECT_RINGS_REG_RINGS                        = 0   ;
static const uint8_t P9N2_PU_WRITE_PROTECT_RINGS_REG_RINGS_LEN                    = 16  ;

static const uint8_t P9N2_PU_N2_WRITE_PROTECT_RINGS_REG_RINGS                     = 0   ;
static const uint8_t P9N2_PU_N2_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 = 16  ;

static const uint8_t P9N2_PEC_WRITE_PROTECT_RINGS_REG_RINGS                       = 0   ;
static const uint8_t P9N2_PEC_WRITE_PROTECT_RINGS_REG_RINGS_LEN                   = 16  ;

static const uint8_t P9N2_PU_N0_WRITE_PROTECT_RINGS_REG_RINGS                     = 0   ;
static const uint8_t P9N2_PU_N0_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 = 16  ;

static const uint8_t P9N2_PEC_XFIR_IN0                                            = 0   ;
static const uint8_t P9N2_PEC_XFIR_IN1                                            = 1   ;
static const uint8_t P9N2_PEC_XFIR_IN2                                            = 2   ;
static const uint8_t P9N2_PEC_XFIR_IN3                                            = 3   ;
static const uint8_t P9N2_PEC_XFIR_IN4                                            = 4   ;
static const uint8_t P9N2_PEC_XFIR_IN5                                            = 5   ;
static const uint8_t P9N2_PEC_XFIR_IN6                                            = 6   ;
static const uint8_t P9N2_PEC_XFIR_IN7                                            = 7   ;
static const uint8_t P9N2_PEC_XFIR_IN7_LEN                                        = 19  ;
static const uint8_t P9N2_PEC_XFIR_IN26                                           = 26  ;

static const uint8_t P9N2_CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE                = 0   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE_LEN            = 10  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD              = 10  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD_LEN          = 4   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS     = 14  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 4   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV               = 18  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV_LEN           = 4   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT                 = 22  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT_LEN             = 4   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_RESERVED                               = 26  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_RESERVED_LEN                           = 2   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT                      = 28  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT_LEN                  = 9   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_BENIGN_PTR_DATA                        = 37  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_EN                         = 38  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD                  = 39  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD_LEN              = 3   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT                  = 42  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT_LEN              = 4   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT                  = 46  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT_LEN              = 8   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_BUFF_MIN                            = 58  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_BUFF_MIN_LEN                        = 4   ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_BUFF_AVAIL                          = 62  ;
static const uint8_t P9N2_CAPP_XPT_CONTROL_LOAD_CI_BUFF                           = 63  ;

static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PSL_CMD_UE_ERRHOLD                = 0   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PSL_CMD_SUE_ERRHOLD               = 1   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SC_RDATA_PARITY_ERRHOLD           = 2   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_APC_SC_RDATA_PARITY_ERRHOLD       = 3   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SN_SC_RDATA_PARITY_ERRHOLD        = 4   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NX_DATA_RTAG_PARITY_ERRHOLD       = 5   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_CE_ERRHOLD      = 6   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_UE_ERRHOLD      = 7   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD     = 8   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_DBG_CTL_REG_PARITY_ERRHOLD        = 9   ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CFG_REG_PARITY_ERRHOLD            = 10  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD = 11  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD  = 12  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD  = 13  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PMU_EVENT_SEL_REG_PARITY_ERRHOLD  = 14  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PE0_CXA_LINKDOWN_ERRHOLD          = 15  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PE1_CXA_LINKDOWN_ERRHOLD          = 16  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SB_SCOM_ERRHOLD                   = 17  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PBXMIT_MSGQ_SEQ_ERRHOLD           = 18  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PBXMIT_DXMIT_SEQ_ERRHOLD          = 19  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD = 20  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_FAILED_ERRHOLD       = 21  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RCS_STATE_MACHINE_ERRHOLD         = 22  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD = 23  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD = 24  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_LNK_RSP_PKT_DISCARDED_ERRHOLD     = 25  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD = 26  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SECURE_LNK_SCOM_CONFLICT_ERRHOLD  = 27  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_UNSOLICITED_DATA_RCV_ERRHOLD      = 28  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_RCMD0_PARITY_ERR_ERRHOLD       = 29  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_REGS_PARITY_ERR_ERRHOLD        = 30  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_SM_ERRHOLD                     = 31  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_REG_RDATA_PERR_ERRHOLD         = 32  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_DFS_SM_ERRHOLD                    = 33  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_FIR_ERR_ERRHOLD                = 34  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_CMD_DISCARDED_ERRHOLD          = 35  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_REG_RDATA_PERR_ERRHOLD         = 36  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RNG_WR_ENBL_REG_PERR_ERRHOLD      = 37  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_UE_ERRHOLD             = 38  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_CE_ERRHOLD             = 39  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_SUE_ERRHOLD            = 40  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_SUE_ERRHOLD            = 41  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_CE_ERRHOLD             = 42  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_UE_ERRHOLD             = 43  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_CE_ERRHOLD        = 44  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_UE_ERRHOLD        = 45  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_APC0_SC_RDATA_PARITY_ERRHOLD      = 46  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CREDIT_TIMEOUT_ERRHOLD            = 47  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TLBI_SC_RDATA_PARITY_ERRHOLD      = 48  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TLBI_REGS_PARITY_ERRHOLD          = 49  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_TIMEOUT_ERRHOLD      = 50  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST0_BADIN_ERRHOLD               = 51  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST6_BADIN_ERRHOLD               = 52  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST7_BADIN_ERRHOLD               = 53  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TWO_TFMRCMDS_ERR_ERRHOLD          = 54  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_MISSING_SYNC_ERRHOLD           = 55  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_MISSING_STEP_ERRHOLD           = 56  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_RESIDUE_ERR_ERRHOLD            = 57  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TX_TFMR_CORRUPT_ERRHOLD           = 58  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST_CORRUPT_ERRHOLD              = 59  ;
static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST9_BADIN_ERRHOLD               = 60  ;

static const uint8_t P9N2_CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT               = 0   ;
static const uint8_t P9N2_CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN           = 4   ;

static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC                                   = 8   ;
static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_LEN                               = 22  ;
static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_RESET                             = 61  ;
static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_DISABLE                           = 62  ;
static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_DISABLE_LOCAL_SHORTCUT            = 63  ;

static const uint8_t P9N2_PU_XSCOM_DAT0_REG_DAT0                                  = 0   ;
static const uint8_t P9N2_PU_XSCOM_DAT0_REG_DAT0_LEN                              = 64  ;

static const uint8_t P9N2_PU_XSCOM_DAT1_REG_DAT1                                  = 0   ;
static const uint8_t P9N2_PU_XSCOM_DAT1_REG_DAT1_LEN                              = 64  ;

static const uint8_t P9N2_PU_XSCOM_ERR_REG_ADDRESS                                = 0   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_TSIZE                                  = 1   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_RC_TTAG_PAR                            = 2   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_CR_TTAG_PAR                            = 3   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_CR_ATAG_PAR                            = 4   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_RC_ADDR_PAR                            = 5   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_PB_ECC_CE                              = 8   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_PB_ECC_UE                              = 9   ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_PB_ECC_SUE                             = 10  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_RTAG_PARITY                            = 11  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_CRESP_HANG                             = 12  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_PIB_HANG                               = 13  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_PBDATA_HANG                            = 14  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_ADS_HANG                               = 15  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_FSM_PERR                               = 16  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_SPARE0                                 = 17  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_SPARE1                                 = 18  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_UNEXPECT_DATA                          = 19  ;
static const uint8_t P9N2_PU_XSCOM_ERR_REG_ILL_CRESP                              = 20  ;

static const uint8_t P9N2_PU_XSCOM_LOG_REG_CMD_IN_PROG                            = 0   ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_CMD_STATUS                             = 1   ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_CMD_STATUS_LEN                         = 3   ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_WRITE_CMD                              = 4   ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_ADDR_TAG                               = 5   ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_ADDR_TAG_LEN                           = 22  ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_THR_ID                                 = 27  ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_THR_ID_LEN                             = 3   ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_PIB_COMPONENT_BUSY                     = 31  ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_PIB_ADDR                               = 33  ;
static const uint8_t P9N2_PU_XSCOM_LOG_REG_PIB_ADDR_LEN                           = 31  ;

static const uint8_t P9N2_PU_XSCOM_MODE_REG_SPARE                                 = 0   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_SPARE_LEN                             = 4   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR1                     = 4   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR2                     = 5   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR3                     = 6   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR4                     = 7   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR5                     = 8   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR6                     = 9   ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR7                     = 10  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_HANG_PIB_RESET                        = 11  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_HANG_RESET                            = 12  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_RESET_ON_PARITY                       = 13  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR1                  = 14  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR2                  = 15  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR3                  = 16  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR4                  = 17  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR5                  = 18  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR6                  = 19  ;
static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR7                  = 20  ;

static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DONE                            = 0   ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_RESULT                          = 1   ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_RESULT_LEN                      = 3   ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_COREID                          = 4   ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_COREID_LEN                      = 6   ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_THRID                           = 10  ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_THRID_LEN                       = 3   ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID                    = 13  ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID_LEN                = 4   ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID                     = 17  ;
static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID_LEN                 = 3   ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_ATD_DIAL                                 = 53  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_ATD_DIAL_LEN                             = 11  ;

static const uint8_t P9N2__DAT_XSL_ATD_DIAL                                       = 53  ;
static const uint8_t P9N2__DAT_XSL_ATD_DIAL_LEN                                   = 11  ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_TO_DIAL                           = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_TRNSO_DIAL                        = 1   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_DVS_DIAL                          = 8   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_DVS_DIAL_LEN                      = 16  ;

static const uint8_t P9N2__DAT_XSL_DBG_WR_TO_DIAL                                 = 0   ;
static const uint8_t P9N2__DAT_XSL_DBG_WR_TRNSO_DIAL                              = 1   ;
static const uint8_t P9N2__DAT_XSL_DBG_WR_DVS_DIAL                                = 8   ;
static const uint8_t P9N2__DAT_XSL_DBG_WR_DVS_DIAL_LEN                            = 16  ;

static const uint8_t P9N2__NTL0_XSL_DEBUG0_CONFIG_DIAL                            = 0   ;
static const uint8_t P9N2__NTL0_XSL_DEBUG0_CONFIG_DIAL_LEN                        = 64  ;

static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG0_CONFIG_DIAL                      = 0   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG0_CONFIG_DIAL_LEN                  = 64  ;

static const uint8_t P9N2__NTL0_XSL_DEBUG1_CONFIG_DIAL                            = 0   ;
static const uint8_t P9N2__NTL0_XSL_DEBUG1_CONFIG_DIAL_LEN                        = 64  ;

static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG1_CONFIG_DIAL                      = 0   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG1_CONFIG_DIAL_LEN                  = 64  ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_MEE_DIAL                             = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_MEE_DIAL_LEN                         = 4   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITL_DIAL                             = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITL_DIAL_LEN                         = 3   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITE_DIAL                             = 8   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITE_DIAL_LEN                         = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_CTXM_DIAL                            = 24  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_CO_RTRY_LIM_DIAL                     = 61  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_CO_RTRY_LIM_DIAL_LEN                 = 2   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_DEFE_DIAL                            = 63  ;

static const uint8_t P9N2__DAT_XSL_DEF_MEE_DIAL                                   = 0   ;
static const uint8_t P9N2__DAT_XSL_DEF_MEE_DIAL_LEN                               = 4   ;
static const uint8_t P9N2__DAT_XSL_DEF_ITL_DIAL                                   = 5   ;
static const uint8_t P9N2__DAT_XSL_DEF_ITL_DIAL_LEN                               = 3   ;
static const uint8_t P9N2__DAT_XSL_DEF_ITE_DIAL                                   = 8   ;
static const uint8_t P9N2__DAT_XSL_DEF_ITE_DIAL_LEN                               = 5   ;
static const uint8_t P9N2__DAT_XSL_DEF_CTXM_DIAL                                  = 24  ;
static const uint8_t P9N2__DAT_XSL_DEF_CO_RTRY_LIM_DIAL                           = 61  ;
static const uint8_t P9N2__DAT_XSL_DEF_CO_RTRY_LIM_DIAL_LEN                       = 2   ;
static const uint8_t P9N2__DAT_XSL_DEF_DEFE_DIAL                                  = 63  ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_ECMD_DIAL                            = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_ETYPE_DIAL                           = 2   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_ETYPE_DIAL_LEN                       = 6   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_RSPCODE_DIAL                         = 8   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_RSPCODE_DIAL_LEN                     = 8   ;

static const uint8_t P9N2__DAT_XSL_EEI_ECMD_DIAL                                  = 0   ;
static const uint8_t P9N2__DAT_XSL_EEI_ETYPE_DIAL                                 = 2   ;
static const uint8_t P9N2__DAT_XSL_EEI_ETYPE_DIAL_LEN                             = 6   ;
static const uint8_t P9N2__DAT_XSL_EEI_RSPCODE_DIAL                               = 8   ;
static const uint8_t P9N2__DAT_XSL_EEI_RSPCODE_DIAL_LEN                           = 8   ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_EVT_DIAL                             = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_ET_DIAL                              = 1   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_ET_DIAL_LEN                          = 7   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_EI_DIAL                              = 8   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_EI_DIAL_LEN                          = 56  ;

static const uint8_t P9N2__DAT_XSL_FEC_EVT_DIAL                                   = 0   ;
static const uint8_t P9N2__DAT_XSL_FEC_ET_DIAL                                    = 1   ;
static const uint8_t P9N2__DAT_XSL_FEC_ET_DIAL_LEN                                = 7   ;
static const uint8_t P9N2__DAT_XSL_FEC_EI_DIAL                                    = 8   ;
static const uint8_t P9N2__DAT_XSL_FEC_EI_DIAL_LEN                                = 56  ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_GP_BITS_DIAL                             = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_GP_BITS_DIAL_LEN                         = 19  ;

static const uint8_t P9N2__DAT_XSL_GP_BITS_DIAL                                   = 0   ;
static const uint8_t P9N2__DAT_XSL_GP_BITS_DIAL_LEN                               = 19  ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_MLPID_DIAL                   = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_MPID_DIAL                    = 1   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_MADDR_DIAL                   = 2   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVR_DIAL                    = 3   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_PRS_DIAL                     = 4   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL                = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL_LEN            = 3   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVALL_DIAL                  = 8   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_SEGSIZE_DIAL                 = 10  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVEA_DIAL                   = 11  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVADDR_DIAL                 = 12  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVADDR_DIAL_LEN             = 52  ;

static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_MLPID_DIAL                         = 0   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_MPID_DIAL                          = 1   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_MADDR_DIAL                         = 2   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVR_DIAL                          = 3   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_PRS_DIAL                           = 4   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL                      = 5   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL_LEN                  = 3   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVALL_DIAL                        = 8   ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_SEGSIZE_DIAL                       = 10  ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVEA_DIAL                         = 11  ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVADDR_DIAL                       = 12  ;
static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVADDR_DIAL_LEN                   = 52  ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_PID_DIAL                         = 12  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_PID_DIAL_LEN                     = 20  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_LPID_DIAL                        = 52  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_LPID_DIAL_LEN                    = 12  ;

static const uint8_t P9N2__DAT_XSL_INV_LPP_PID_DIAL                               = 12  ;
static const uint8_t P9N2__DAT_XSL_INV_LPP_PID_DIAL_LEN                           = 20  ;
static const uint8_t P9N2__DAT_XSL_INV_LPP_LPID_DIAL                              = 52  ;
static const uint8_t P9N2__DAT_XSL_INV_LPP_LPID_DIAL_LEN                          = 12  ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL0_DIAL                       = 3   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL0_DIAL_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL1_DIAL                       = 11  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL1_DIAL_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL2_DIAL                       = 19  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL2_DIAL_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL3_DIAL                       = 27  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL3_DIAL_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL4_DIAL                       = 35  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL4_DIAL_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL5_DIAL                       = 43  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL5_DIAL_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL6_DIAL                       = 51  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL6_DIAL_LEN                   = 5   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL7_DIAL                       = 59  ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL7_DIAL_LEN                   = 5   ;

static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL0_DIAL                             = 3   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL0_DIAL_LEN                         = 5   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL1_DIAL                             = 11  ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL1_DIAL_LEN                         = 5   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL2_DIAL                             = 19  ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL2_DIAL_LEN                         = 5   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL3_DIAL                             = 27  ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL3_DIAL_LEN                         = 5   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL4_DIAL                             = 35  ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL4_DIAL_LEN                         = 5   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL5_DIAL                             = 43  ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL5_DIAL_LEN                         = 5   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL6_DIAL                             = 51  ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL6_DIAL_LEN                         = 5   ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL7_DIAL                             = 59  ;
static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL7_DIAL_LEN                         = 5   ;

static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_RCVR_DIAL                        = 0   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MTYPE_DIAL                       = 4   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MTYPE_DIAL_LEN                   = 4   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MID_DIAL                         = 8   ;
static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MID_DIAL_LEN                     = 8   ;

static const uint8_t P9N2__DAT_XSL_RECOVER_RCVR_DIAL                              = 0   ;
static const uint8_t P9N2__DAT_XSL_RECOVER_MTYPE_DIAL                             = 4   ;
static const uint8_t P9N2__DAT_XSL_RECOVER_MTYPE_DIAL_LEN                         = 4   ;
static const uint8_t P9N2__DAT_XSL_RECOVER_MID_DIAL                               = 8   ;
static const uint8_t P9N2__DAT_XSL_RECOVER_MID_DIAL_LEN                           = 8   ;

static const uint8_t P9N2__NTL0_XSL_WRAP_CFG_XSLO_CLOCK_ENABLE                    = 0   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_CFG_RESERVED                             = 1   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_CFG_RESERVED_LEN                         = 7   ;

static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_CFG_XSLO_CLOCK_ENABLE              = 0   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_CFG_RESERVED                       = 1   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_CFG_RESERVED_LEN                   = 7   ;

static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_MMIO_INVALIDATE_REQ_WHILE_1_INPROG = 0   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_0             = 1   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_1             = 2   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_RD_PEE_COMPLETION       = 3   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_CO_RESP                 = 4   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_XLAT_REQ_WHILE_SPAP_INVALID        = 5   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_INVALID_PEE                        = 6   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_BLOOM_FILTER_ARY                   = 7   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED_XSLO                      = 8   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED_XSLO_LEN                  = 2   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR0_SBE                          = 10  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR1_SBE                          = 11  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB0_SBE                           = 12  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB1_SBE                           = 13  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_FITA_SBE                           = 14  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR0_UE                           = 15  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR1_UE                           = 16  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB0_UE                            = 17  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB1_UE                            = 18  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_FITA_UE                            = 19  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RQDB_PE                            = 20  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED0                          = 21  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RSDB_PE                            = 22  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_MDB0_PE                            = 23  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_MDB1_PE                            = 24  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED1                          = 25  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX0A_PE                           = 26  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX0B_PE                           = 27  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX1A_PE                           = 28  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX1B_PE                           = 29  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX2A_PE                           = 30  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX2B_PE                           = 31  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX3A_PE                           = 32  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX3B_PE                           = 33  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA0A_PE                          = 34  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA0B_PE                          = 35  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA1A_PE                          = 36  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA1B_PE                          = 37  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA2A_PE                          = 38  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA2B_PE                          = 39  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA3A_PE                          = 40  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA3B_PE                          = 41  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX0A_PE                         = 42  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX0B_PE                         = 43  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX1A_PE                         = 44  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX1B_PE                         = 45  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX2A_PE                         = 46  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX2B_PE                         = 47  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX3A_PE                         = 48  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX3B_PE                         = 49  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_STLBI_PE                           = 50  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_STLBI_OVERFLOW_ERR                 = 51  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CORESP_DATA_CE                     = 52  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CORESP_DATA_UE                     = 53  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CORESP_DATA_SUE                    = 54  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_PEE_DATA_CE                        = 55  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_PEE_DATA_UE                        = 56  ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_PEE_DATA_SUE                       = 57  ;

static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_MMIO_INVALIDATE_REQ_WHILE_1_INPROG = 0   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_0       = 1   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_1       = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_RD_PEE_COMPLETION = 3   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_CO_RESP           = 4   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_XLAT_REQ_WHILE_SPAP_INVALID  = 5   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_INVALID_PEE                  = 6   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_BLOOM_FILTER_ARY             = 7   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED_XSLO                = 8   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED_XSLO_LEN            = 2   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR0_SBE                    = 10  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR1_SBE                    = 11  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB0_SBE                     = 12  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB1_SBE                     = 13  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_FITA_SBE                     = 14  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR0_UE                     = 15  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR1_UE                     = 16  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB0_UE                      = 17  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB1_UE                      = 18  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_FITA_UE                      = 19  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RQDB_PE                      = 20  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED0                    = 21  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RSDB_PE                      = 22  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_MDB0_PE                      = 23  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_MDB1_PE                      = 24  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED1                    = 25  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX0A_PE                     = 26  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX0B_PE                     = 27  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX1A_PE                     = 28  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX1B_PE                     = 29  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX2A_PE                     = 30  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX2B_PE                     = 31  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX3A_PE                     = 32  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX3B_PE                     = 33  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA0A_PE                    = 34  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA0B_PE                    = 35  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA1A_PE                    = 36  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA1B_PE                    = 37  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA2A_PE                    = 38  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA2B_PE                    = 39  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA3A_PE                    = 40  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA3B_PE                    = 41  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX0A_PE                   = 42  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX0B_PE                   = 43  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX1A_PE                   = 44  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX1B_PE                   = 45  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX2A_PE                   = 46  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX2B_PE                   = 47  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX3A_PE                   = 48  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX3B_PE                   = 49  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_STLBI_PE                     = 50  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_STLBI_OVERFLOW_ERR           = 51  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CORESP_DATA_CE               = 52  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CORESP_DATA_UE               = 53  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CORESP_DATA_SUE              = 54  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_PEE_DATA_CE                  = 55  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_PEE_DATA_UE                  = 56  ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_PEE_DATA_SUE                 = 57  ;

static const uint8_t P9N2__NTL0_XSL_WRAP_ERR_MASK_DIAL                            = 0   ;
static const uint8_t P9N2__NTL0_XSL_WRAP_ERR_MASK_DIAL_LEN                        = 58  ;

static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERR_MASK_DIAL                      = 0   ;
static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERR_MASK_DIAL_LEN                  = 58  ;

static const uint8_t P9N2_PEC_XSTOP1_MASK_B                                       = 0   ;
static const uint8_t P9N2_PEC_XSTOP1_ALIGNED                                      = 1   ;
static const uint8_t P9N2_PEC_XSTOP1_TRIGGER_OPCG_ON                              = 2   ;
static const uint8_t P9N2_PEC_XSTOP1_WAIT_ALLWAYS                                 = 3   ;
static const uint8_t P9N2_PEC_XSTOP1_PERV                                         = 4   ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT1                                        = 5   ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT2                                        = 6   ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT3                                        = 7   ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT4                                        = 8   ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT5                                        = 9   ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT6                                        = 10  ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT7                                        = 11  ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT8                                        = 12  ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT9                                        = 13  ;
static const uint8_t P9N2_PEC_XSTOP1_UNIT10                                       = 14  ;
static const uint8_t P9N2_PEC_XSTOP1_WAIT_CYCLES                                  = 48  ;
static const uint8_t P9N2_PEC_XSTOP1_WAIT_CYCLES_LEN                              = 12  ;

static const uint8_t P9N2_PEC_XSTOP2_MASK_B                                       = 0   ;
static const uint8_t P9N2_PEC_XSTOP2_ALIGNED                                      = 1   ;
static const uint8_t P9N2_PEC_XSTOP2_TRIGGER_OPCG_ON                              = 2   ;
static const uint8_t P9N2_PEC_XSTOP2_WAIT_ALLWAYS                                 = 3   ;
static const uint8_t P9N2_PEC_XSTOP2_PERV                                         = 4   ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT1                                        = 5   ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT2                                        = 6   ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT3                                        = 7   ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT4                                        = 8   ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT5                                        = 9   ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT6                                        = 10  ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT7                                        = 11  ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT8                                        = 12  ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT9                                        = 13  ;
static const uint8_t P9N2_PEC_XSTOP2_UNIT10                                       = 14  ;
static const uint8_t P9N2_PEC_XSTOP2_WAIT_CYCLES                                  = 48  ;
static const uint8_t P9N2_PEC_XSTOP2_WAIT_CYCLES_LEN                              = 12  ;

static const uint8_t P9N2_PEC_XSTOP3_MASK_B                                       = 0   ;
static const uint8_t P9N2_PEC_XSTOP3_ALIGNED                                      = 1   ;
static const uint8_t P9N2_PEC_XSTOP3_TRIGGER_OPCG_ON                              = 2   ;
static const uint8_t P9N2_PEC_XSTOP3_WAIT_ALLWAYS                                 = 3   ;
static const uint8_t P9N2_PEC_XSTOP3_PERV                                         = 4   ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT1                                        = 5   ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT2                                        = 6   ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT3                                        = 7   ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT4                                        = 8   ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT5                                        = 9   ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT6                                        = 10  ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT7                                        = 11  ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT8                                        = 12  ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT9                                        = 13  ;
static const uint8_t P9N2_PEC_XSTOP3_UNIT10                                       = 14  ;
static const uint8_t P9N2_PEC_XSTOP3_WAIT_CYCLES                                  = 48  ;
static const uint8_t P9N2_PEC_XSTOP3_WAIT_CYCLES_LEN                              = 12  ;

static const uint8_t P9N2_PEC_XSTOP_INTERRUPT_REG_XSTOP                           = 0   ;

static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN      = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN     = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_FWD_PROG_RATE2             = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_CTL_TICK                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_CTL_TICK_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH0_TICK                  = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH0_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH1_TICK                  = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH1_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE1              = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE2              = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN     = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN      = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN     = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_FWD_PROG_RATE2             = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_CTL_TICK                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_CTL_TICK_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH0_TICK                  = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH0_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH1_TICK                  = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH1_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE1              = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE2              = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN     = 2   ;

static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1             = 0   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN         = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2            = 8   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN        = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                = 14  ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK                      = 20  ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK_LEN                  = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK                     = 26  ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK                     = 32  ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK_LEN                 = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1                 = 38  ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN             = 2   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2                 = 40  ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN             = 6   ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1            = 46  ;
static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN        = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN      = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN     = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_FWD_PROG_RATE2             = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_FWD_PROG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_CTL_TICK                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_CTL_TICK_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH0_TICK                  = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH0_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH1_TICK                  = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH1_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE1              = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE1_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE2              = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN     = 2   ;

static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1          = 0   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN      = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN      = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2         = 8   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN     = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_FWD_PROG_RATE2             = 14  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN         = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_CTL_TICK                   = 20  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_CTL_TICK_LEN               = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH0_TICK                  = 26  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH0_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH1_TICK                  = 32  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH1_TICK_LEN              = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE1              = 38  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN          = 2   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE2              = 40  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN          = 6   ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1         = 46  ;
static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN     = 2   ;

static const uint8_t P9N2_PEC_XTRA_TRACE_MODE_DATA                                = 0   ;
static const uint8_t P9N2_PEC_XTRA_TRACE_MODE_DATA_LEN                            = 42  ;

static const uint8_t P9N2_PU_XTRA_TRACE_MODE_DATA                                 = 0   ;
static const uint8_t P9N2_PU_XTRA_TRACE_MODE_DATA_LEN                             = 42  ;

static const uint8_t P9N2__SM2_XTS_ATRMISS_ADDR                                   = 15  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_ADDR_LEN                               = 37  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_OTHER                             = 54  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_PREF                              = 55  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_DMD                               = 56  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_MAP                               = 57  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_FENCE                             = 58  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_RETIRE                                 = 59  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_IRQENA                                 = 60  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_SECOND                                 = 61  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_TRIGGERED                              = 62  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS_ENA                                    = 63  ;

static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_GPA                           = 27  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_BDF                           = 28  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_BDF_LEN                       = 16  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_PASID                         = 44  ;
static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_PASID_LEN                     = 20  ;

static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_ADDR                        = 15  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_ADDR_LEN                    = 37  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_OTHER                  = 54  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_PREF                   = 55  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_DMD                    = 56  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_MAP                    = 57  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_FENCE                  = 58  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_RETIRE                      = 59  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_IRQENA                      = 60  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_SECOND                      = 61  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_TRIGGERED                   = 62  ;
static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_ENA                         = 63  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP0_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP0_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP0_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP1_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP1_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP1_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP2_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP2_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP2_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP3_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP3_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP3_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP4_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP4_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP4_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP5_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP5_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP5_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP6_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP6_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP6_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM3_XTS_ATSD_HYP7_MSRHV                                = 51  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP7_LPARID                               = 52  ;
static const uint8_t P9N2__SM3_XTS_ATSD_HYP7_LPARID_LEN                           = 12  ;

static const uint8_t P9N2__SM2_XTS_CONFIG_BRAZOS                                  = 0   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_MMIOSD                                  = 1   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_BIG_RSP                                 = 2   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_CHOP1G                                  = 3   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_DIS_NCNP                                = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_OVR_PM                                  = 5   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_TRY_ATR_RO                              = 6   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_SPLURGE                                 = 7   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_LIM_PS                                  = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF2DMD                                = 9   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREFEVOD                                = 10  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_EAINJ                                   = 11  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_SPL_ONLY                                = 12  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_BYPASS_CO                               = 13  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_UNUSED                                  = 14  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_OPENCAPI                                = 15  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_DEC_RATE                          = 16  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_DEC_RATE_LEN                      = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_INC_RATE                          = 24  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_INC_RATE_LEN                      = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_CNT_THRESH                        = 32  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_CNT_THRESH_LEN                    = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_WAIT_MISS                               = 40  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_TIMEOUT                            = 41  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_TIMEOUT_LEN                        = 3   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_DEPTH                              = 44  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_DEPTH_LEN                          = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH0                             = 48  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH0_LEN                         = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH1                             = 52  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH1_LEN                         = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH2                             = 56  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH2_LEN                         = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH3                             = 60  ;
static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH3_LEN                         = 4   ;

static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_ENABLE                            = 0   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_RESETMODE                         = 1   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_FREEZEMODE                        = 2   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_DISABLE_PMISC                     = 3   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PMISC_MODE                        = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_CASCADE                           = 5   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_CASCADE_LEN                       = 3   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C0                       = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C0_LEN                   = 2   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C1                       = 10  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C1_LEN                   = 2   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C2                       = 12  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C2_LEN                   = 2   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C3                       = 14  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C3_LEN                   = 2   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT0                            = 16  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT0_LEN                        = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT1                            = 24  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT1_LEN                        = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT2                            = 32  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT2_LEN                        = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT3                            = 40  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT3_LEN                        = 8   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_RADDR_BND                              = 48  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_NO_FLUSH_ENA                           = 49  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_MAP_ILOCK                              = 50  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_ADJUST_PLS_RATE                        = 51  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_TLBIE_HV_EN                            = 52  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_TLBIE_PACING_CNT_EN                    = 53  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_XSL1_ENA                               = 54  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_XSL2_ENA                               = 55  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_ATSD_TIMEOUT                           = 56  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_ATSD_TIMEOUT_LEN                       = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_ATR_TIMEOUT                            = 60  ;
static const uint8_t P9N2__SM2_XTS_CONFIG2_ATR_TIMEOUT_LEN                        = 4   ;

static const uint8_t P9N2__SM2_XTS_CONFIG3_CAP_RESERVE                            = 0   ;
static const uint8_t P9N2__SM2_XTS_CONFIG3_CAP_RESERVE_LEN                        = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG3_ATSD_ALIGN                             = 4   ;
static const uint8_t P9N2__SM2_XTS_CONFIG3_UNUSED                                 = 5   ;
static const uint8_t P9N2__SM2_XTS_CONFIG3_UNUSED_LEN                             = 59  ;

static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT0                                   = 0   ;
static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT0_LEN                               = 16  ;
static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT1                                   = 16  ;
static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT1_LEN                               = 16  ;
static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT2                                   = 32  ;
static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT2_LEN                               = 16  ;
static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT3                                   = 48  ;
static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT3_LEN                               = 16  ;

#endif
