/* IBM_PROLOG_BEGIN_TAG                                                   */
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/* $Source: import/chips/p9/common/include/p9_obus_scom_addresses_fld.H $ */
/*                                                                        */
/* OpenPOWER HCODE Project                                                */
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/* COPYRIGHT 2015,2017                                                    */
/* [+] International Business Machines Corp.                              */
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/* IBM_PROLOG_END_TAG                                                     */
///
/// @file p9_obus_scom_addresses_fld.H
/// @brief  Defines constants for scom addresses
///
// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: SOA
// *HWP Level: 3
// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE

#include <p9_const_common.H>

#ifndef __P9_OBUS_SCOM_ADDRESSES_FLD_H
#define __P9_OBUS_SCOM_ADDRESSES_FLD_H


#include <p9_scom_template_consts.H>
#include <p9_obus_scom_addresses_fld_fixes.H>

REG64_FLD( OBUS_FIR_ACTION0_REG_ACTION0                            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION0    );
REG64_FLD( OBUS_FIR_ACTION0_REG_ACTION0_LEN                        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION0_LEN );

REG64_FLD( OBUS_FIR_ACTION1_REG_ACTION1                            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION1    );
REG64_FLD( OBUS_FIR_ACTION1_REG_ACTION1_LEN                        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION1_LEN );

REG64_FLD( OBUS_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR      , 0   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_RX_INVALID_STATE_OR_PARITY_ERROR );
REG64_FLD( OBUS_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR      , 1   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_TX_INVALID_STATE_OR_PARITY_ERROR );
REG64_FLD( OBUS_FIR_MASK_REG_GCR_HANG_ERROR                        , 2   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_GCR_HANG_ERROR );
REG64_FLD( OBUS_FIR_MASK_REG_UNUSED                                , 3   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_UNUSED     );
REG64_FLD( OBUS_FIR_MASK_REG_UNUSED_LEN                            , 45  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_UNUSED_LEN );
REG64_FLD( OBUS_FIR_MASK_REG_INTERNAL_SCOM_ERROR                   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_INTERNAL_SCOM_ERROR );
REG64_FLD( OBUS_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_INTERNAL_SCOM_ERROR_CLONE );

REG64_FLD( OBUS_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_RX_INVALID_STATE_OR_PARITY_ERROR );
REG64_FLD( OBUS_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR           , 1   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_TX_INVALID_STATE_OR_PARITY_ERROR );
REG64_FLD( OBUS_FIR_REG_GCR_HANG_ERROR                             , 2   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_GCR_HANG_ERROR );
REG64_FLD( OBUS_FIR_REG_UNUSED                                     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_UNUSED     );
REG64_FLD( OBUS_FIR_REG_UNUSED_LEN                                 , 45  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_UNUSED_LEN );
REG64_FLD( OBUS_FIR_REG_SCOMFIR_ERROR                              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_SCOMFIR_ERROR );
REG64_FLD( OBUS_FIR_REG_SCOMFIR_ERROR_CLONE                        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_SCOMFIR_ERROR_CLONE );

REG64_FLD( OBUS_FIR_WOF_REG_WOF                                    , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_WOF        );
REG64_FLD( OBUS_FIR_WOF_REG_WOF_LEN                                , 50  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_WOF_LEN    );

REG64_FLD( OBUS_LL0_IOOL_CONFIG_LINK_PAIR                          , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK_PAIR  );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_DISABLE_SL_ECC                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLE_SL_ECC );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_CRC_LANE_ID                        , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CRC_LANE_ID );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_EDPL_LANE_ID                       , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EDPL_LANE_ID );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_SL_UE_CRC_ERR                      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SL_UE_CRC_ERR );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_REPORT_SL_CHKBIT_ERR               , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPORT_SL_CHKBIT_ERR );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_BW_SAMPLE_SIZE                     , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BW_SAMPLE_SIZE );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_BW_WINDOW_SIZE                     , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BW_WINDOW_SIZE );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED1                            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED1    );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED1_LEN                        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED1_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_PACKET_DELAY_LIMIT                 , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PACKET_DELAY_LIMIT );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_PACKET_DELAY_LIMIT_LEN             , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PACKET_DELAY_LIMIT_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_TDM_DELAY                          , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDM_DELAY  );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_TDM_DELAY_LEN                      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDM_DELAY_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_TX                        , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AUTO_TDM_TX );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_RX                        , 21  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AUTO_TDM_RX );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_AND_NOT_OR                , 22  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AUTO_TDM_AND_NOT_OR );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED2                            , 23  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED2    );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_BW_DIFF                   , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AUTO_TDM_BW_DIFF );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_BW_DIFF_LEN               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AUTO_TDM_BW_DIFF_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_ERROR_RATE                , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AUTO_TDM_ERROR_RATE );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_ERROR_RATE_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AUTO_TDM_ERROR_RATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED3                            , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED3    );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED3_LEN                        , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED3_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMEOUT                            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TIMEOUT    );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMEOUT_LEN                        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TIMEOUT_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMER_1US                          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TIMER_1US  );
REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMER_1US_LEN                      , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TIMER_1US_LEN );

REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_PHY_TRAINING );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_STARTUP );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_HOLD_PATT_A                 , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_HOLD_PATT_A );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_HOLD_PATT_B                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_HOLD_PATT_B );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_DISABLE            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_RUN_LANE_DISABLE );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE           , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_RUN_LANE_OVERRIDE );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_IGNORE_PHY                  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_IGNORE_PHY );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_IGNORE_FENCE                , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_IGNORE_FENCE );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ERR_INJ_COMMAND );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ERR_INJ_COMMAND_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES       , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED0                           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED0    );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED0_LEN                       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED0_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_COMMAND                     , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_COMMAND );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_COMMAND_LEN                 , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_COMMAND_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING                , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_PHY_TRAINING );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP                     , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_STARTUP );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_HOLD_PATT_A                 , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_HOLD_PATT_A );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_HOLD_PATT_B                 , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_HOLD_PATT_B );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_DISABLE            , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_RUN_LANE_DISABLE );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE           , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_RUN_LANE_OVERRIDE );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_IGNORE_PHY                  , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_IGNORE_PHY );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_IGNORE_FENCE                , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_IGNORE_FENCE );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND             , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ERR_INJ_COMMAND );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ERR_INJ_COMMAND_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES       , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED1                           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED1    );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED1_LEN                       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED1_LEN );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_COMMAND                     , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_COMMAND );
REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_COMMAND_LEN                 , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_COMMAND_LEN );

REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_CURRENT_STATE            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_CURRENT_STATE );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_CURRENT_STATE_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_CURRENT_STATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_PRIOR_STATE              , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_PRIOR_STATE );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_PRIOR_STATE_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_PRIOR_STATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_OPTICS_RST_B             , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_OPTICS_RST_B );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_OPTICS_IRQ               , 17  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_OPTICS_IRQ );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_TRAINING                 , 18  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_TRAINING );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_MAX_PKT_TIMER            , 19  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_MAX_PKT_TIMER );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN        , 5   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK0_MAX_PKT_TIMER_LEN );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_CURRENT_STATE            , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_CURRENT_STATE );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_CURRENT_STATE_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_CURRENT_STATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_PRIOR_STATE              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_PRIOR_STATE );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_PRIOR_STATE_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_PRIOR_STATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_OPTICS_RST_B             , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_OPTICS_RST_B );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_OPTICS_IRQ               , 41  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_OPTICS_IRQ );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_TRAINING                 , 42  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_TRAINING );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_MAX_PKT_TIMER            , 43  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_MAX_PKT_TIMER );
REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN        , 5   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LINK1_MAX_PKT_TIMER_LEN );

REG64_FLD( OBUS_LL0_IOOL_ERR_INJ_LFSR_LFSR                         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LFSR       );
REG64_FLD( OBUS_LL0_IOOL_ERR_INJ_LFSR_LFSR_LEN                     , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LFSR_LEN   );

REG64_FLD( OBUS_LL0_IOOL_FIR_WOF_REG_WOF                           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_WOF        );
REG64_FLD( OBUS_LL0_IOOL_FIR_WOF_REG_WOF_LEN                       , 64  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_WOF_LEN    );

REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID        , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ROUND_TRIP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ROUND_TRIP );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN          , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ROUND_TRIP_LEN );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ROUND_TRIP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP              , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ROUND_TRIP );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN          , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ROUND_TRIP_LEN );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCAL_LATENCY_DIFFERENCE_VALID );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK     , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCAL_LATENCY_LONGER_LINK );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE      , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCAL_LATENCY_DIFFERENCE );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN  , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCAL_LATENCY_DIFFERENCE_LEN );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REMOTE_LATENCY_DIFFERENCE_VALID );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK    , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REMOTE_LATENCY_LONGER_LINK );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE     , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REMOTE_LATENCY_DIFFERENCE );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REMOTE_LATENCY_DIFFERENCE_LEN );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_TOD_LATENCY             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_TOD_LATENCY );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN         , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_TOD_LATENCY_LEN );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_TOD_LATENCY             , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_TOD_LATENCY );
REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN         , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_TOD_LATENCY_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_0           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_0 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_0_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_1           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_1 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_1_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_2           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_2 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_2_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_3           , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_3 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_3_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_4           , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_4 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_4_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_5           , 20  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_5 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_5_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_6           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_6 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_6_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_7           , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_7 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_7_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_8           , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_8 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_8_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_9           , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_9 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_9_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_10          , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_10 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_10_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_11          , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_11 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_11_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_KEEPER );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_CE                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CE         );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_CE_LEN                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CE_LEN     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UE                     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UE         );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UE_LEN                 , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UE_LEN     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_OSC                    , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OSC        );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_OSC_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OSC_LEN    );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_TRAIN                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAIN      );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_TRAIN_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAIN_LEN  );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UNRECOV                , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNRECOV    );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UNRECOV_LEN            , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNRECOV_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_INTERNAL               , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INTERNAL   );
REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_INTERNAL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INTERNAL_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_MAX_TIMEOUT                    , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MAX_TIMEOUT );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_MAX_TIMEOUT_LEN                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MAX_TIMEOUT_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_VALID                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_INST                 , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_INST );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_ADDR                 , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_ADDR );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_ADDR_LEN             , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_ADDR_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_SYN                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_SYN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_SYN_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_SYN_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_VALID               , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_INST                , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_INST );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_INST_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_INST_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_ADDR                , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_ADDR );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_ADDR_LEN            , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_ADDR_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_SYN                 , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_SYN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_SYN_LEN             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_SYN_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_VALID             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_FIFO_CAP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_ADDR              , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_FIFO_CAP_ADDR );
REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN          , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_TX_BW                       , 1   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_TX_BW      );
REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_TX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_TX_BW_LEN  );
REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_RX_BW                       , 13  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_RX_BW      );
REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_RX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_RX_BW_LEN  );
REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_ERROR_RATE                  , 25  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_RATE );
REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_ERROR_RATE_LEN              , 23  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_RATE_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_DISABLED            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLED   );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_DISABLED_LEN        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLED_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_BRINGUP             , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BRINGUP    );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_BRINGUP_LEN         , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BRINGUP_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_SPARED              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARED     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_SPARED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARED_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_LOCKED              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCKED     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_LOCKED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCKED_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN        , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0     , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN0 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1     , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN1 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN2     , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN2 );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN2_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN2_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC_LANE );
REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN   , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC_LANE_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE00              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE00     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE00_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE00_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE01              , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE01     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE01_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE01_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE02              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE02     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE02_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE02_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE03              , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE03     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE03_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE03_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE04              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE04     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE04_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE04_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE05              , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE05     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE05_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE05_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE06              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE06     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE06_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE06_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE07              , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE07     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE07_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE07_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE08              , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE08     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE08_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE08_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE09              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE09     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE09_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE09_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE10              , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE10     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE10_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE10_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE11              , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE11     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE11_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE11_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED     );
REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_0           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_0 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_0_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_1           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_1 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_1_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_2           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_2 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_2_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_3           , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_3 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_3_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_4           , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_4 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_4_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_5           , 20  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_5 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_5_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_6           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_6 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_6_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_7           , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_7 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_7_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_8           , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_8 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_8_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_9           , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_9 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_9_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_10          , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_10 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_10_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_11          , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_11 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_COUNT_11_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_KEEPER );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_CE                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CE         );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_CE_LEN                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CE_LEN     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UE                     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UE         );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UE_LEN                 , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UE_LEN     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_OSC                    , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OSC        );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_OSC_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OSC_LEN    );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_TRAIN                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAIN      );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_TRAIN_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAIN_LEN  );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UNRECOV                , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNRECOV    );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UNRECOV_LEN            , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNRECOV_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_INTERNAL               , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INTERNAL   );
REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_INTERNAL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INTERNAL_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_MAX_TIMEOUT                    , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MAX_TIMEOUT );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_MAX_TIMEOUT_LEN                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MAX_TIMEOUT_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_VALID                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_INST                 , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_INST );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_ADDR                 , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_ADDR );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_ADDR_LEN             , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_ADDR_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_SYN                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_SYN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_SYN_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRAME_CAP_SYN_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_VALID               , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_INST                , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_INST );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_INST_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_INST_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_ADDR                , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_ADDR );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_ADDR_LEN            , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_ADDR_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_SYN                 , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_SYN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_SYN_LEN             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_CAP_SYN_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_VALID             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_FIFO_CAP_VALID );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_ADDR              , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_FIFO_CAP_ADDR );
REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN          , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_TX_BW                       , 1   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_TX_BW      );
REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_TX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_TX_BW_LEN  );
REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_RX_BW                       , 13  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_RX_BW      );
REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_RX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_RX_BW_LEN  );
REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_ERROR_RATE                  , 25  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_RATE );
REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_ERROR_RATE_LEN              , 23  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ERROR_RATE_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_DISABLED            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLED   );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_DISABLED_LEN        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLED_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_BRINGUP             , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BRINGUP    );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_BRINGUP_LEN         , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BRINGUP_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_SPARED              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARED     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_SPARED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARED_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_LOCKED              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCKED     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_LOCKED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCKED_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN        , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0     , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN0 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1     , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN1 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN2     , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN2 );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN2_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_SLECC_SYN2_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC_LANE );
REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN   , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_LINK_CAP_CRC_LANE_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE00              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE00     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE00_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE00_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE01              , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE01     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE01_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE01_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE02              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE02     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE02_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE02_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE03              , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE03     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE03_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE03_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE04              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE04     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE04_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE04_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE05              , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE05     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE05_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE05_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE06              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE06     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE06_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE06_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE07              , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE07     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE07_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE07_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE08              , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE08     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE08_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE08_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE09              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE09     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE09_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE09_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE10              , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE10     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE10_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE10_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE11              , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE11     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE11_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE11_LEN );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED     );
REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FAILED_LEN );

REG64_FLD( OBUS_LL0_IOOL_LINKX_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_KEEPER );
REG64_FLD( OBUS_LL0_IOOL_LINKX_ERROR_STATUS_STATUS                 , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_STATUS     );
REG64_FLD( OBUS_LL0_IOOL_LINKX_ERROR_STATUS_STATUS_LEN             , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_STATUS_LEN );

REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_DISABLE_BAD_LANE_COUNT     , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLE_BAD_LANE_COUNT );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_DISABLE_CLEAR_BAD_LANE_COUNT , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLE_CLEAR_BAD_LANE_COUNT );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED1                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED1 );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED1_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED1_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BAD_LANE_DURATION );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BAD_LANE_DURATION_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED2                , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED2 );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX               , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BAD_LANE_MAX );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX_LEN           , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BAD_LANE_MAX_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_DISABLE_LINK_FAIL_COUNT    , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLE_LINK_FAIL_COUNT );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED3                , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED3 );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED3_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED3_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION         , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK_FAIL_DURATION );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK_FAIL_DURATION_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED4                , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED4 );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX              , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK_FAIL_MAX );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK_FAIL_MAX_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_CLEAR_LINK_FAIL_COUNTER    , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLEAR_LINK_FAIL_COUNTER );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_CLEAR_BAD_LANE_COUNTER     , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLEAR_BAD_LANE_COUNTER );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED5                , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED5 );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED5_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OPT_UNUSED5_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ELEVEN_LANE_MODE           , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ELEVEN_LANE_MODE );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_ELEVEN_LANE_SHIFT    , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_ELEVEN_LANE_SHIFT );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_ELEVEN_LANE_SHIFT    , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_ELEVEN_LANE_SHIFT );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_RX_LANE_SWAP         , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_RX_LANE_SWAP );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_TX_LANE_SWAP         , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_TX_LANE_SWAP );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_RX_LANE_SWAP         , 42  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_RX_LANE_SWAP );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_TX_LANE_SWAP         , 43  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_TX_LANE_SWAP );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_LOW              , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_QUEUE_LOW );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_LOW_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_QUEUE_LOW_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_START            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_QUEUE_START );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_START_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_QUEUE_START_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_HIGH             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_QUEUE_HIGH );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_HIGH_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACK_QUEUE_HIGH_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_REPLAY_BUFFER_SIZE         , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_BUFFER_SIZE );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_REPLAY_BUFFER_SIZE_LEN     , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REPLAY_BUFFER_SIZE_LEN );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_OLL_ENABLED          , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK0_OLL_ENABLED );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_OLL_ENABLED          , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LINK1_OLL_ENABLED );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NPU_TRANSPORT_SWAP         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NPU_TRANSPORT_SWAP );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NV0_NPU_ENABLED            , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NV0_NPU_ENABLED );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NV1_NPU_ENABLED            , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NV1_NPU_ENABLED );
REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NV2_NPU_ENABLED            , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NV2_NPU_ENABLED );

REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN       , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_1         , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_1 );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_1_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_2         , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_2 );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_2_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_3         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_3 );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_3_LEN );

REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_4         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_4 );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_4_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_5         , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_5 );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_5_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_6         , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_6 );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_6_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_7         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_7 );
REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
           SH_FLD_PERFMON_COUNTER_7_LEN );

REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0                  , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_0   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_0_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1                  , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_1   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_1_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_2                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_2   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_2_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_2_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_3                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_3   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_3_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_3_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4                  , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_4   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_4_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5                  , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_5   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_5_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_6                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_6   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_6_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_6_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_7                  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_7   );
REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_7_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SELECT_7_LEN );

REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_0   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_0_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_1   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_1_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_2                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_2   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_2_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_2_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_3                , 6   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_3   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_3_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_3_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4                , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_4   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_4_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5                , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_5   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_5_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_6                , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_6   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_6_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_6_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_7                , 14  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_7   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_7_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_7_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_0     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_0_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1                  , 18  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_1     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_1_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_2                  , 20  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_2     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_2_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_2_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_3                  , 22  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_3     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_3_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_3_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_4     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_4_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5                  , 26  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_5     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_5_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_6                  , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_6     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_6_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_6_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_7                  , 30  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_7     );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_7_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SIZE_7_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE      , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PMULET_FREEZE_MODE );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE      , 33  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_COMMON_FREEZE_MODE );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_RESET_MODE              , 34  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_RESET_MODE );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE        , 35  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PERFTRACE_ENABLE );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW  , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PERFTRACE_FIXED_WINDOW );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE      , 37  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PERFTRACE_PRESCALE );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_MODE          , 38  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PERFTRACE_MODE );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN      , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PERFTRACE_MODE_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_0                , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_CONFIG_0   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_0_LEN            , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_CONFIG_0_LEN );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_1                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_CONFIG_1   );
REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_1_LEN            , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_CONFIG_1_LEN );

REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_ADJ                    , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_A_ADJ );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_ADJ_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_A_ADJ_LEN );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_ADJ                    , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_B_ADJ );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_ADJ_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_B_ADJ_LEN );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_TIME                     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_TIME );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_TIME_LEN                 , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_TIME_LEN );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_HYST                   , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_A_HYST );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_HYST_LEN               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_A_HYST_LEN );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_HYST                   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_B_HYST );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_HYST_LEN               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_TRAIN_B_HYST_LEN );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_PHASE_SELECT              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PRBS_PHASE_SELECT );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_PHASE_SELECT_LEN          , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PRBS_PHASE_SELECT_LEN );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS                           , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PRBS       );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_LEN                       , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PRBS_LEN   );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_INVERT                    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_PRBS_INVERT );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_UNUSED                         , 51  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_UNUSED     );
REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_UNUSED_LEN                     , 13  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_UNUSED_LEN );

REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TB_SEL            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TB_SEL );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TB_SEL_LEN );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TAP_SEL           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TAP_SEL );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TAP_SEL_LEN );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_ENABLE            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_ENABLE );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_ENABLE_LEN );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED1           , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED1 );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN       , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED1_LEN );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR       , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR       , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR      , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TB_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR     , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TAP_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP      , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TAP_STOP );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED2           , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED2 );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT       , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_COUNT );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_COUNT_LEN );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_COUNT );
REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_COUNT_LEN );

REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TB_SEL           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TB_SEL );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TB_SEL_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TB_SEL_LEN );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TAP_SEL          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TAP_SEL );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TAP_SEL_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TAP_SEL_LEN );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_ENABLE           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_ENABLE );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_ENABLE_LEN       , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_ENABLE_LEN );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED1          , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED1 );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED1_LEN      , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED1_LEN );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_CLEAR      , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_CLEAR      , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TB_CLEAR     , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TB_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TAP_CLEAR    , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TAP_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TAP_STOP     , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TAP_STOP );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED2          , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED2 );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_COUNT      , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_COUNT );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_COUNT_LEN  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_COUNT_LEN );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_COUNT      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_COUNT );
REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_COUNT_LEN  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_COUNT_LEN );

REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_ENABLE_ERR_INJ                 , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ENABLE_ERR_INJ );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED4                        , 1   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_UNUSED4    );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED4_LEN                    , 15  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_UNUSED4_LEN );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SBE_ERROR_RATE                 , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SBE_ERROR_RATE );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SBE_ERROR_RATE_LEN             , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SBE_ERROR_RATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_RAND_ERROR_RATE                , 18  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_RAND_ERROR_RATE );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_RAND_ERROR_RATE_LEN            , 6   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_RAND_ERROR_RATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_INV_SH_ERROR_RATE              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_INV_SH_ERROR_RATE );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_INV_SH_ERROR_RATE_LEN          , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_INV_SH_ERROR_RATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SYNC_HEADER_ERROR_RATE         , 26  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SYNC_HEADER_ERROR_RATE );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SYNC_HEADER_ERROR_RATE_LEN     , 6   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_SYNC_HEADER_ERROR_RATE_LEN );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED5                        , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_UNUSED5    );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED5_LEN                    , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_UNUSED5_LEN );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_EDPL_RATE                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_EDPL_RATE  );
REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_EDPL_RATE_LEN                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_EDPL_RATE_LEN );

REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TB_SEL            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TB_SEL );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TB_SEL_LEN );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TAP_SEL           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TAP_SEL );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_TAP_SEL_LEN );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_ENABLE            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_ENABLE );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN        , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_ENABLE_LEN );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED1           , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED1 );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN       , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED1_LEN );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR       , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR       , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR      , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TB_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR     , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TAP_CLEAR );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP      , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_DIS_TAP_STOP );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED2           , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_UNUSED2 );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT       , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_COUNT );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK0_COUNT_LEN );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_COUNT );
REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_THRESH_LINK1_COUNT_LEN );

REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINED     , 0   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TRAINED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINED     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TRAINED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_OP_IRQ      , 2   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_OP_IRQ );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_OP_IRQ      , 3   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_OP_IRQ );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD , 4   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_REPLAY_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD , 5   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_REPLAY_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_CRC_ERROR   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_CRC_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_CRC_ERROR   , 7   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_CRC_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NAK_RECEIVED , 8   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_NAK_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NAK_RECEIVED , 9   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_NAK_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL , 10  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL , 11  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD , 12  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SL_ECC_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD , 13  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SL_ECC_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE , 14  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE , 15  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_UE   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SL_ECC_UE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_UE   , 17  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SL_ECC_UE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_RETRAIN_THRESHOLD , 18  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_RETRAIN_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_RETRAIN_THRESHOLD , 19  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_RETRAIN_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_LOSS_BLOCK_ALIGN , 20  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_LOSS_BLOCK_ALIGN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_LOSS_BLOCK_ALIGN , 21  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_LOSS_BLOCK_ALIGN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_INVALID_BLOCK , 22  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_INVALID_BLOCK );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_INVALID_BLOCK , 23  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_INVALID_BLOCK );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_DESKEW_ERROR , 24  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_DESKEW_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_DESKEW_ERROR , 25  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_DESKEW_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_DESKEW_OVERFLOW , 26  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_DESKEW_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_DESKEW_OVERFLOW , 27  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_DESKEW_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SW_RETRAIN  , 28  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SW_RETRAIN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SW_RETRAIN  , 29  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SW_RETRAIN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_ACK_QUEUE_OVERFLOW , 30  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_ACK_QUEUE_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_ACK_QUEUE_OVERFLOW , 31  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_ACK_QUEUE_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_ACK_QUEUE_UNDERFLOW , 32  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_ACK_QUEUE_UNDERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_ACK_QUEUE_UNDERFLOW , 33  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_ACK_QUEUE_UNDERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NUM_REPLAY  , 34  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_NUM_REPLAY );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NUM_REPLAY  , 35  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_NUM_REPLAY );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINING_SET_RECEIVED , 36  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TRAINING_SET_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINING_SET_RECEIVED , 37  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TRAINING_SET_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_PRBS_SELECT_ERROR , 38  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_PRBS_SELECT_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_PRBS_SELECT_ERROR , 39  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_PRBS_SELECT_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD , 40  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TCOMPLETE_BAD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD , 41  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TCOMPLETE_BAD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SPARE_DONE  , 44  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SPARE_DONE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SPARE_DONE  , 45  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SPARE_DONE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NPU_ERROR   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_NPU_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NPU_ERROR   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_NPU_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINKX_NPU_ERROR   , 50  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINKX_NPU_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_OSC_SWITCH        , 51  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_OSC_SWITCH );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM2_OR , SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM2_OR , SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM2_OR , SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_OBUS     ,
           SH_ACS_SCOM2_OR , SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINING_FAILED , 56  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TRAINING_FAILED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINING_FAILED , 57  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TRAINING_FAILED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_INTERNAL_ERROR , 60  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_INTERNAL_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_INTERNAL_ERROR , 61  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_INTERNAL_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_SCOM_ERR_DUP      , 62  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_SCOM_ERR_DUP );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_SCOM_ERR          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_SCOM_ERR   );

REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TRAINED          , 0   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TRAINED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TRAINED          , 1   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TRAINED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_OP_IRQ           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_OP_IRQ );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_OP_IRQ           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_OP_IRQ );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_REPLAY_THRESHOLD , 4   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_REPLAY_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_REPLAY_THRESHOLD , 5   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_REPLAY_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_CRC_ERROR        , 6   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_CRC_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_CRC_ERROR        , 7   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_CRC_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_NAK_RECEIVED     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_NAK_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_NAK_RECEIVED     , 9   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_NAK_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_REPLAY_BUFFER_FULL , 10  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_REPLAY_BUFFER_FULL , 11  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_THRESHOLD , 12  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SL_ECC_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_THRESHOLD , 13  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SL_ECC_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_CORRECTABLE , 14  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_CORRECTABLE , 15  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_UE        , 16  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SL_ECC_UE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_UE        , 17  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SL_ECC_UE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_RETRAIN_THRESHOLD , 18  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_RETRAIN_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_RETRAIN_THRESHOLD , 19  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_RETRAIN_THRESHOLD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_LOSS_BLOCK_ALIGN , 20  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_LOSS_BLOCK_ALIGN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_LOSS_BLOCK_ALIGN , 21  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_LOSS_BLOCK_ALIGN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_INVALID_BLOCK    , 22  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_INVALID_BLOCK );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_INVALID_BLOCK    , 23  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_INVALID_BLOCK );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_DESKEW_ERROR     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_DESKEW_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_DESKEW_ERROR     , 25  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_DESKEW_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_DESKEW_OVERFLOW  , 26  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_DESKEW_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_DESKEW_OVERFLOW  , 27  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_DESKEW_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SW_RETRAIN       , 28  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SW_RETRAIN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SW_RETRAIN       , 29  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SW_RETRAIN );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_ACK_QUEUE_OVERFLOW , 30  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_ACK_QUEUE_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_ACK_QUEUE_OVERFLOW , 31  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_ACK_QUEUE_OVERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_ACK_QUEUE_UNDERFLOW , 32  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_ACK_QUEUE_UNDERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_ACK_QUEUE_UNDERFLOW , 33  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_ACK_QUEUE_UNDERFLOW );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_NUM_REPLAY       , 34  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_NUM_REPLAY );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_NUM_REPLAY       , 35  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_NUM_REPLAY );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TRAINING_SET_RECEIVED , 36  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TRAINING_SET_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TRAINING_SET_RECEIVED , 37  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TRAINING_SET_RECEIVED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_PRBS_SELECT_ERROR , 38  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_PRBS_SELECT_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_PRBS_SELECT_ERROR , 39  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_PRBS_SELECT_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TCOMPLETE_BAD    , 40  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TCOMPLETE_BAD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TCOMPLETE_BAD    , 41  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TCOMPLETE_BAD );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SPARE_DONE       , 44  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_SPARE_DONE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SPARE_DONE       , 45  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_SPARE_DONE );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_NPU_ERROR        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_NPU_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_NPU_ERROR        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_NPU_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINKX_NPU_ERROR        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINKX_NPU_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_OSC_SWITCH             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_OSC_SWITCH );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TRAINING_FAILED  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_TRAINING_FAILED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TRAINING_FAILED  , 57  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_TRAINING_FAILED );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_INTERNAL_ERROR   , 60  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK0_INTERNAL_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_INTERNAL_ERROR   , 61  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_LINK1_INTERNAL_ERROR );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_SCOM_ERR_DUP           , 62  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_SCOM_ERR_DUP );
REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_SCOM_ERR               , 63  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
           SH_FLD_SCOM_ERR   );

REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION0_REG_ACTION0                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION0    );
REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION0_REG_ACTION0_LEN            , 64  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION0_LEN );

REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION1_REG_ACTION1                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION1    );
REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION1_REG_ACTION1_LEN            , 64  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
           SH_FLD_ACTION1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_EDGE_TRACK_CNTL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_WOBBLE_EDGE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_A   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DDC_B   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_TO_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SL_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_BUMP_SR_1UI );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_USE_DFE_CLOCK_B );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_A_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_DATA_B_OFFSET_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_LOCK_DONE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_DDC_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_STOP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_TRACE_WOBBLE_SM );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_RESET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_SEL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_SEL_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PIPE_MARGIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_MODE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PIPE_DATA_SHIFT );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DIG_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_DPIPE_MUX_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_A );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DECOUPLE_EDGE_B );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_DIG_REQ_DIS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_ANA_REQ_DIS );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_OFF  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_FW_INERTIA_AMT_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_DLY_CFG_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DDC_CFG_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_COARSE_MODE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PR_PHASE_STEP_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PR_DFE_CLKADJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BANK_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_ANA_PDWN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PRBS_TEST_DATA_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BANK_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CONTROLS_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CNTL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_E1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O0_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1 );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_OFFSET_O1_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_COARSE_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_CTLE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1E_VAL_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL  );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1O_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_CONTROLS_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_VAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_E_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET   );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_OFFSET_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_INTEG_COARSE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_ODD_INTEG_FINE_GAIN );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PRBS_TEST_TIME );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PRBS_TEST_TIME_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE         , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_BUS_DATA_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME        , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PRBS_PROP_TIME );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_PRBS_PROP_TIME_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DACTEST_LLMT );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN           , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DACTEST_LLMT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_RESET              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DACTEST_RESET );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_START              , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DACTEST_START );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DACTEST_HLMT );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN           , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DACTEST_HLMT_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_WIDTH_VALID );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_WIDTH_LANE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH         , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_WIDTH );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_WIDTH_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_HEIGHT_VALID );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT        , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_HEIGHT );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN    , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_HEIGHT_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_EN                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_EN     );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN         , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_TIMER_FREEZE_EN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN         , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_COUNT_FREEZE_EN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL               , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_COUNT_SEL );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_COUNT_SEL_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL               , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_TIMER_SEL );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_TIMER_SEL_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN    , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CLR_COUNT_ON_READ_EN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN    , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_CLR_TIMER_ON_READ_EN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRC_MODE   );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRC_MODE_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_MODE   );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_MODE_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_CURRENT_STATE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN       , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_CURRENT_STATE_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_ENABLE_ENC );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_ENABLE_ENC_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE              , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_NEXT_STATE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_NEXT_STATE_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE              , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_GOTO_STATE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_GOTO_STATE_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_RETURN_STATE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INT_RETURN_STATE_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_OP   );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN                , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_OP_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL8_EO_PG_SERVO_DONE                  , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_DONE );

REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_EN                     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_EN    );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE         , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_EXT_START_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_INIT_DISABLE );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN       , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_INIT_DISABLE_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_CUPLL_LOCK_CHECK_EN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_STORE_EYES_LANE_SEL );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL    , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_STORE_EYES_BANK_SEL );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT              , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PERVASIVE_CAPT );
REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_LL_TEST_EN             , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_LL_TEST_EN );

REG64_FLD( OBUS_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG        , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_PHY_GCRMSG );
REG64_FLD( OBUS_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN    , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CAL_LANE_PHY_GCRMSG_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_INIT_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_INIT_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_RECAL_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN          , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_RECAL_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG              , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_INIT_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN          , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_INIT_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG             , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_RECAL_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN         , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_RECAL_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG                    , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_CFG    );
REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_CFG_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_INIT_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_INIT_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_RECAL_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN          , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_RECAL_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_CM_CFG                     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CFG     );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_CM_CFG_LEN                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG                   , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMIN_CFG   );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN               , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMIN_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG                , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_USERDEF_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_USERDEF_CFG_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_CHG_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_CHG_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG                 , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DAC_BO_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN             , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DAC_BO_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE                , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FILTER_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FILTER_MODE_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG                   , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MISC_CFG   );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN               , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MISC_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR           , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLE_H1_CLEAR );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG                   , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_VOFF_CFG   );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN               , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_VOFF_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN                , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOFF_AMP_EN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL              , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_OFFSET_VAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_OFFSET_VAL_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_THRESH1 );
REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_THRESH1_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2              , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_THRESH2 );
REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_THRESH2_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_INIT_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_INIT_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_RECAL_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_RECAL_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_INIT_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_INIT_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_RECAL_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PEAK_RECAL_TIMEOUT_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_INIT_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_INIT_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_RECAL_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OFF_RECAL_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT                 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN             , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CM_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT               , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMIN_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMIN_TIMEOUT_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_USERDEF_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_USERDEF_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT                , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BER_TIMEOUT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT             , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE4_TIMEOUT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE4_TIMEOUT_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMAX_HIGH  );
REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMAX_HIGH_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW                   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMAX_LOW   );
REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN               , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMAX_LOW_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP0_FILTER_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN       , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP0_FILTER_MASK_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP1_FILTER_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN       , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP1_FILTER_MASK_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTLE_GAIN_MAX );
REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTLE_GAIN_MAX_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_START_VAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_START_VAL_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLKDIST_PDWN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLKDIST_PDWN_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH          , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_MIN_EYE_WIDTH );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN      , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_MIN_EYE_WIDTH_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_A_BIST_EN                   , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BIST_EN  );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_B_BIST_EN                   , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BIST_EN  );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_E_BIST_EN                   , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_E_BIST_EN  );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BISTCLK_EN                  , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BISTCLK_EN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BISTCLK_EN_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BISTCLK_EN_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_DISABLE_BANK_PDWN           , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLE_BANK_PDWN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE1_O_PG_MINIKERF                     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MINIKERF   );
REG64_FLD( OBUS_RX0_RX_CTL_MODE1_O_PG_MINIKERF_LEN                 , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MINIKERF_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DFE_CONVERGED_CNT_MAX );
REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN  , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DFE_CONVERGED_CNT_MAX_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AP110_AP010_DELTA_MAX );
REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN  , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AP110_AP010_DELTA_MAX_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_CTLE_COARSE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL          , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_DAC_H1_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_VGA_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_DFE_H1_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK          , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_H1AP_TWEAK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DDC                 , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_DDC );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL       , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_CM_COARSE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL         , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_CM_FINE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_EDGE_OFFSET_CAL , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_OFFSET_CAL , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL );

REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL  , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_CTLE_COARSE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_DAC_H1_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL          , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_VGA_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL       , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_DFE_H1_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK       , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_H1AP_TWEAK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC              , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_DDC );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_CM_COARSE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL      , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_CM_FINE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_EDGE_OFFSET_CAL , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_OFFSET_CAL , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL );

REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC               , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IREF_RES_DAC );
REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IREF_RES_DAC_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_BYPASS                , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IREF_BYPASS );
REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_PDWN_B                , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IREF_PDWN_B );

REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG                   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_H1AP_CFG   );
REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN               , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_H1AP_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTLE_UPDATE_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_USER_FILTER_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN       , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_USER_FILTER_MASK_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_VGA_AMAX_MODE );

REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_VGA_AMAX_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_AUTO_RECAL       , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RC_ENABLE_AUTO_RECAL );

REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DC_ENABLE_CM_COARSE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DC_ENABLE_CM_FINE_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL );

REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_APX111_HIGH );
REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_APX111_HIGH_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW                 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_APX111_LOW );
REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_APX111_LOW_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DFE_CA_CFG );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DFE_CA_CFG_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL               , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_CONTROL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOPE_CONTROL_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RECAL_REQ_DL_MASK           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ_DL_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RECAL_DONE_DL_MASK          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_DONE_DL_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RUN_LANE_DL_MASK            , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE_DL_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RECAL_ABORT_DL_MASK         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT_DL_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_INIT_DONE_DL_MASK           , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INIT_DONE_DL_MASK );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE  , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DATA_PIPE_CLR_ON_READ_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_CFG_LTE_MC                  , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CFG_LTE_MC );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_CFG_LTE_MC_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CFG_LTE_MC_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_OCTANT_SELECT                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OCTANT_SELECT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_OCTANT_SELECT_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_OCTANT_SELECT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_SPEED_SELECT                 , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPEED_SELECT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_SPEED_SELECT_LEN             , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPEED_SELECT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_AC_COUPLED                   , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AC_COUPLED );

REG64_FLD( OBUS_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL        , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRACKING_TIMEOUT_SEL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRACKING_TIMEOUT_SEL_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CONVERGED_END_COUNT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CONVERGED_END_COUNT_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE     , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_WIDTH_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE );
REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX            , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_GAIN_CNT_MAX );
REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AMP_GAIN_CNT_MAX_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ABORT_CHECK_TIMEOUT_SEL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL         , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_POLLING_TIMEOUT_SEL );
REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_POLLING_TIMEOUT_SEL_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH               , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MIN_EYE_WIDTH );
REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN           , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MIN_EYE_WIDTH_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MIN_EYE_HEIGHT );
REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MIN_EYE_HEIGHT_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_RESULT );
REG64_FLD( OBUS_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_RESULT_LEN );

REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_INIT_DONE );
REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_DONE                   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_DONE  );
REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_LL_ERR                 , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_LL_ERR );
REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_NO_EDGE_DET );
REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_EYE_A_WIDTH );
REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN        , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_EYE_A_WIDTH_LEN );
REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH            , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_EYE_B_WIDTH );
REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN        , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_EYE_B_WIDTH_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 52  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_0                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_1                      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_2                      , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_3                      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_4                      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_5                      , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_6                      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_7                      , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_CONFIG );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SERVO_CONFIG_LEN );
REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_CLKDIST_PDWN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_BER_COUNT_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_BER_COUNT_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_BER_COUNT_SATURATED_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL , 60  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL , 61  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_BER_TIMER_SATURATED_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SERVO_STATUS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SERVO_STATUS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_IREF_PARITY_CHK_RO_SIGNAL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_IREF_PARITY_CHK_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_IREF_PARITY_CHK_RO_SIGNAL_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_IREF_PARITY_CHK_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PRVCPT_CHANGE_DET_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN            , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_RX0_RX_FIR1_MASK_PG_ERRS                           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX0_RX_FIR1_MASK_PG_ERRS_LEN                       , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL  , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL   , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL             , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PL_FIR_ERR_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CNT_SINGLE_LANE_RECAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_LANE_TO_MONITOR );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_LANE_TO_MONITOR_LEN );

REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MANUAL_RECAL_REQUEST );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE         , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MANUAL_RECAL_LANE );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN     , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MANUAL_RECAL_LANE_LEN );

REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS             , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLR_PAR_ERRS );
REG64_FLD( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET                , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIR_RESET  );

REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_0                       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_1                       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_2                       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_3                       , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_4                       , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_5                       , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_6                       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_7                       , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_CNT_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_CNT_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DACTEST_ISGT_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DACTEST_ISLT_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DACTEST_ISEQ_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INT_REQ_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INT_REQ_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN );
REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_MANUAL_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_RX_ID1_PG_BUS_ID                               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BUS_ID     );
REG64_FLD( OBUS_RX0_RX_ID1_PG_BUS_ID_LEN                           , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BUS_ID_LEN );

REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_0                             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_1                             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_2                             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_3                             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_4                             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );

REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_LANE   );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUN_DCCAL  );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_REQ  );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RECAL_ABORT );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_DISABLED );

REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_INIT_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_DCCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_LANE_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_RECAL_DONE_RO_SIGNAL );

REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_REGS_IORESET );

REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_A );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_B );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_ERR_E );

REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_BAD_DFE_CONV );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_H1AP_AT_LIMIT );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP       );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_AP_LEN   );

REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_A_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_EVEN_LEN );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD );
REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_B_PATH_OFF_ODD_LEN );

REG64_FLD( OBUS_RX_FIR_ERROR_INJECT_PB_ERRS_INJ                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_INJ   );
REG64_FLD( OBUS_RX_FIR_ERROR_INJECT_PB_ERRS_INJ_LEN                , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_INJ_LEN );

REG64_FLD( OBUS_RX_FIR_MASK_PB_ERRS                                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_RX_FIR_MASK_PB_ERRS_LEN                            , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );

REG64_FLD( OBUS_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL                 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL );
REG64_FLD( OBUS_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL_LEN             , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL_LEN );

REG64_FLD( OBUS_RX_FIR_RESET_PB_CLR_PAR_ERRS                       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLR_PAR_ERRS );
REG64_FLD( OBUS_RX_FIR_RESET_PB_RESET                              , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET      );

REG64_FLD( OBUS_SCOM_MODE_PB_GCR_TEST                              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GCR_TEST   );
REG64_FLD( OBUS_SCOM_MODE_PB_ENABLE_GCR_OFL_BUFF                   , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_GCR_OFL_BUFF );
REG64_FLD( OBUS_SCOM_MODE_PB_IORESET_HARD_BUS0                     , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET_HARD_BUS0 );
REG64_FLD( OBUS_SCOM_MODE_PB_MMIO_PG_REG_ACCESS                    , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MMIO_PG_REG_ACCESS );
REG64_FLD( OBUS_SCOM_MODE_PB_SPARES1                               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARES1    );
REG64_FLD( OBUS_SCOM_MODE_PB_SPARES1_LEN                           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARES1_LEN );
REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_DET_SEL                      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GCR_HANG_DET_SEL );
REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_DET_SEL_LEN                  , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GCR_HANG_DET_SEL_LEN );
REG64_FLD( OBUS_SCOM_MODE_PB_GCR_BUFFER_ENABLED_RO_SIGNAL          , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL );
REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_ERROR_MASK                   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GCR_HANG_ERROR_MASK );
REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_ERROR_INJ                    , 13  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GCR_HANG_ERROR_INJ );
REG64_FLD( OBUS_SCOM_MODE_PB_PPE_GCR                               , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PPE_GCR    );
REG64_FLD( OBUS_SCOM_MODE_PB_CHAN_FAIL_MASK                        , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CHAN_FAIL_MASK );
REG64_FLD( OBUS_SCOM_MODE_PB_CHAN_FAIL_MASK_LEN                    , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CHAN_FAIL_MASK_LEN );
REG64_FLD( OBUS_SCOM_MODE_PB_SPARES2                               , 23  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARES2    );
REG64_FLD( OBUS_SCOM_MODE_PB_SPARES2_LEN                           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARES2_LEN );

REG64_FLD( OBUS_SPARE_MODE_PB_0                                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_SPARE_MODE_PB_1                                    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_SPARE_MODE_PB_2                                    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_SPARE_MODE_PB_3                                    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_SPARE_MODE_PB_4                                    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_SPARE_MODE_PB_5                                    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_SPARE_MODE_PB_6                                    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_SPARE_MODE_PB_7                                    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );

REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_RESERVED_LAST_LT               , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESERVED_LAST_LT );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );

REG64_FLD( OBUS_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG_MASK              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASK       );
REG64_FLD( OBUS_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN          , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASK_LEN   );

REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_A             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_A );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_B             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_B );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_A             , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_A );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_B             , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_B );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C1_INAROW_MODE          , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C1_INAROW_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1       , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AND_TRIGGER_MODE1 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1       , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NOT_TRIGGER_MODE1 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1      , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EDGE_TRIGGER_MODE1 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED                  , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED     );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED_LEN              , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C2_INAROW_MODE          , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C2_INAROW_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2       , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AND_TRIGGER_MODE2 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2       , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NOT_TRIGGER_MODE2 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2      , 42  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EDGE_TRIGGER_MODE2 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED_2                , 43  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED_2   );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED_2_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED_2_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET      , 46  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND3_ENABLE_RESET );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EXACT_TO_MODE           , 47  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXACT_TO_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C2TIMER_ON_C1 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0          , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C3_ON_C0 );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_SLOW_TO_MODE            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SLOW_TO_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXACT_RESET_C3_ON_TO );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C1_COUNT_LT             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C1_COUNT_LT );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C1_COUNT_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C2_COUNT_LT             , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C2_COUNT_LT );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C2_COUNT_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_SELECT         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C3_SELECT );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C3_SELECT_LEN );

REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_A );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_B );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A   , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_A );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B   , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_B );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_TO_CMP_LT               , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TO_CMP_LT  );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TO_CMP_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_FORCE_TEST_MODE         , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FORCE_TEST_MODE );

REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_3_SP_COUNT_LT             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SP_COUNT_LT );
REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SP_COUNT_LT_LEN );

REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_A             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_A );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_B             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_B );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND1_SEL_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_A             , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_A );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_B             , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_B );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND2_SEL_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C1_INAROW_MODE          , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C1_INAROW_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1       , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AND_TRIGGER_MODE1 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1       , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NOT_TRIGGER_MODE1 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1      , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EDGE_TRIGGER_MODE1 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED                  , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED     );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED_LEN              , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C2_INAROW_MODE          , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C2_INAROW_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2       , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_AND_TRIGGER_MODE2 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2       , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NOT_TRIGGER_MODE2 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2      , 42  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EDGE_TRIGGER_MODE2 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED_2                , 43  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED_2   );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED_2_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNUSED_2_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET      , 46  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_COND3_ENABLE_RESET );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EXACT_TO_MODE           , 47  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXACT_TO_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C2TIMER_ON_C1 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0          , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C3_ON_C0 );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_SLOW_TO_MODE            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SLOW_TO_MODE );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXACT_RESET_C3_ON_TO );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C1_COUNT_LT             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C1_COUNT_LT );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C1_COUNT_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C2_COUNT_LT             , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C2_COUNT_LT );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_C2_COUNT_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_SELECT         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C3_SELECT );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET_C3_SELECT_LEN );

REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_A );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_B );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A   , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_A );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B   , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_B );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_TO_CMP_LT               , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TO_CMP_LT  );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TO_CMP_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_FORCE_TEST_MODE         , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FORCE_TEST_MODE );

REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_3_SP_COUNT_LT             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SP_COUNT_LT );
REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SP_COUNT_LT_LEN );

REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_GLB_BRCST                       , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GLB_BRCST  );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_GLB_BRCST_LEN                   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GLB_BRCST_LEN );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRACE_SEL                       , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRACE_SEL  );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRACE_SEL_LEN                   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRACE_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRIG_SEL                        , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG_SEL   );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRIG_SEL_LEN                    , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_STOP_ON_XSTOP_SELECTION );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION     , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION        , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_STOP_ON_SPATTN_SELECTION );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_FREEZE_SEL                      , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FREEZE_SEL );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_SYNC_BRCST                      , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SYNC_BRCST );
REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_SYNC_BRCST_LEN                  , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SYNC_BRCST_LEN );

REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_IMM_FREEZE              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IMM_FREEZE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR             , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_STOP_ON_ERR );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH      , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_ON_RUNN_MATCH );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_FORCE_TEST              , 19  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FORCE_TEST );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_ACCUM_HIST              , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUM_HIST );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ        , 21  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FRZ_COUNT_ON_FRZ );

REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_COND3_ENABLE           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_COND3_ENABLE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_COND3_ENABLE           , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_COND3_ENABLE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST3_COND3_ENABLE           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST3_COND3_ENABLE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST4_COND3_ENABLE           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST4_COND3_ENABLE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_SLOW_LFSR_MODE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE         , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_SLOW_LFSR_MODE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE         , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST3_SLOW_LFSR_MODE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE         , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST4_SLOW_LFSR_MODE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL    , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION1_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL    , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION2_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL    , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL    , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION1_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL    , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION2_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL    , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP             , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXT_TRIG_ON_STOP );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE           , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXT_TRIG_ON_FREEZE );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL           , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CORE_RAS0_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN       , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL           , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CORE_RAS1_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN       , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL               , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PC_TP_TRIG_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PC_TP_TRIG_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_ARM_SEL                      , 46  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ARM_SEL    );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_ARM_SEL_LEN                  , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ARM_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL              , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG0_LEVEL_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG0_LEVEL_SEL_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL              , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG1_LEVEL_SEL );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG1_LEVEL_SEL_LEN );

REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO   , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION1_ACTION_DO );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION2_ACTION_DO );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO   , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION1_ACTION_DO );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO   , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION2_ACTION_DO );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO   , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION1_ACTION_BANK );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CONDITION2_ACTION_BANK );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION1_ACTION_BANK );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CONDITION2_ACTION_BANK );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CHECKSTOP_MODE_LT );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN  , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CHECKSTOP_MODE_LT );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN  , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );

REG64_FLD( OBUS_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_START         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOM_TRACE_START );
REG64_FLD( OBUS_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP          , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOM_TRACE_STOP );
REG64_FLD( OBUS_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET         , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOM_TRACE_RESET );

REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PCB_WDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY          , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PCB_ADDRESS_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY      , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DL_RETURN_WDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_DL_RETURN_P0                , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DL_RETURN_P0 );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_UL_RDATA_PARITY             , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UL_RDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_UL_P0                       , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UL_P0      );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE       , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PARITY_ON_P2S_MACHINE );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD         , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PARALLEL_WRITE_NVLD );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PARALLEL_READ_NVLD );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID       , 13  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PARALLEL_ADDR_INVALID );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY          , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PCB_COMMAND_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT             , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_GENERAL_TIMEOUT );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );

REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_WATCHDOG_ENABLE               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_WATCHDOG_ENABLE );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_SCOM_HANG_LIMIT               , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOM_HANG_LIMIT );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SCOM_HANG_LIMIT_LEN );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_FORCE_ALL_RINGS               , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FORCE_ALL_RINGS );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_RESERVED_LT                   , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESERVED_LT );
REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_RESERVED_LT_LEN               , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESERVED_LT_LEN );

REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0     , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_UL_P0 );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  ,
           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0  , 21  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_DL_RETURN_P0 );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_UL_RDATA_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0         , 23  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_UL_P0 );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );

REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE             , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE     );
REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN         , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENABLE_LEN );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG_DATA              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_DATA       );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN          , 64  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_DATA_LEN   );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_DATA              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_DATA       );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN          , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_DATA_LEN   );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS           , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ADDRESS    );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_ADDRESS_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK         , 42  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LAST_BANK  );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LAST_BANK_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_LAST_BANK_VALID );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_WRITE_ON_RUN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_RUNNING    );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_HOLD_ADDRESS );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
           SH_FLD_HOLD_ADDRESS_LEN );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_STORE_ON_TRIG_MODE );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_WRITE_ON_RUN_MODE );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXTEND_TRIG_MODE );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXTEND_TRIG_MODE_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE       , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BANK_MODE  );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE        , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ENH_MODE   );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LOCAL_CLOCK_GATE_CONTROL );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL   , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SELCT_CONTROL );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SELCT_CONTROL_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL   , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_CONTROL );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_CONTROL_LEN );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CMP_MSK_LT_B_TO_63 );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERNA   );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERNA_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERNB   );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERNB_LEN );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERNC   );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERNC_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERND   );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PATTERND_LEN );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKA      );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKA_LEN  );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKB      );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKB_LEN  );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKC      );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKC_LEN  );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKD      );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MASKD_LEN  );

REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DISABLE_COMPRESSION );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHA_MUXSEL );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHA_MUXSEL_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHB_MUXSEL );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHB_MUXSEL_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHC_MUXSEL );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHC_MUXSEL_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHD_MUXSEL );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCHD_MUXSEL_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG0_OR_MASK );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG0_OR_MASK_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG0_AND_MASK );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG0_AND_MASK_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG1_OR_MASK );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG1_OR_MASK_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG1_AND_MASK );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG1_AND_MASK_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG0_NOT_MODE );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TRIG1_NOT_MODE );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCH_NOT_MODE );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MATCH_NOT_MODE_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERROR_MODE_LT );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERROR_MODE_LT_LEN );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_DD1_STRETCH_TRIGGER_PULSES );
REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT      , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_LT   );

REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING        , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RING_LOCKING );
REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESERVED_RING_LOCKING );

REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_RINGS_REG_RINGS                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RINGS      );
REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_RINGS_REG_RINGS_LEN            , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RINGS_LEN  );

REG64_FLD( OBUS_TCOB0_XTRA_TRACE_MODE_DATA                         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DATA       );
REG64_FLD( OBUS_TCOB0_XTRA_TRACE_MODE_DATA_LEN                     , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DATA_LEN   );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5   , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     ,
           SH_ACS_SCOM     , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_IORESET    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_ENABLE );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_PDWN  );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_INVERT );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_QUIESCE_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSAVE_REQ_DIS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_ENABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_0 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_1 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_2 );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SPARE_MODE_3 );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FIFO_L2U_DLY_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_CLK_DISABLE );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RXCAL      );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_UNLOAD_SEL_LEN );

REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ERR );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_LANE_BIST_ACTVITY_DET );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_STATUS_LEN );
REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN               , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_PRE_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN           , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_PRE_EN_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_PRE_SEL );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN          , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_PRE_SEL_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_EN               , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_POST_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_EN_LEN           , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_POST_EN_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_POST_SEL );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_SEL_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_POST_SEL_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN               , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_PRE_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN           , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_PRE_EN_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_PRE_SEL );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN          , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_PRE_SEL_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_EN               , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_POST_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_EN_LEN           , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_POST_EN_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_POST_SEL );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_SEL_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_POST_SEL_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_MARGINPU_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_MARGINPU_EN_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_MARGINPD_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_MARGINPD_EN_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_MARGINPU_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_MARGINPU_EN_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_MARGINPD_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_MARGINPD_EN_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MARGINPU_SEL );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MARGINPU_SEL_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MARGINPD_SEL );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_MARGINPD_SEL_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_MAIN_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PSEG_MAIN_EN_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_MAIN_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_NSEG_MAIN_EN_LEN );

REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_MODE );
REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_MODE_LEN );
REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN              , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_FFE_BOOST_EN );
REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL     , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_SEG_TEST_LEAKAGE_CTRL );

REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_0   );
REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1                , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_1   );
REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2                , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_2   );
REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3                , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_3   );
REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_4   );
REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5                , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_5   );
REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6                , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_6   );
REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7                , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CTL_SM_7   );

REG64_FLD( OBUS_TX0_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_BIST_DONE_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_PULSE_WIDTH );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN        , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_PULSE_WIDTH_LEN );

REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_FINE_SEL );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN      , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_FINE_SEL_LEN );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL        , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_COARSE_SEL );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_COARSE_SEL_LEN );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_BER_SEL );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN       , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_A_BER_SEL_LEN );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE              , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_ENABLE );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE        , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_CLOCK_ENABLE );

REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_FINE_SEL );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN      , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_FINE_SEL_LEN );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL        , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_COARSE_SEL );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_COARSE_SEL_LEN );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_BER_SEL );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN       , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_B_BER_SEL_LEN );

REG64_FLD( OBUS_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_DAC_CNTL );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_DAC_CNTL_LEN );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL               , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_PHASE_SEL );

REG64_FLD( OBUS_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_PULSE_OFFSET );
REG64_FLD( OBUS_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN        , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TDR_PULSE_OFFSET_LEN );

REG64_FLD( OBUS_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DRV_DATA_PATTERN_GCRMSG );
REG64_FLD( OBUS_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN );

REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLKDIST_PDWN );
REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLKDIST_PDWN_LEN );
REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_BIST_EN                     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BIST_EN    );
REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_EXBIST_MODE                 , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_EXBIST_MODE );

REG64_FLD( OBUS_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ                 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ    );
REG64_FLD( OBUS_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN             , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERR_INJ_LEN );

REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_ERRS                            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS       );
REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_ERRS_LEN                        , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ERRS_LEN   );
REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_PL_ERR                          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_PL_ERR     );

REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL );
REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL );
REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL   , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL );
REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL );
REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL     , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL );
REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL              , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_PL_FIR_ERR_RO_SIGNAL );

REG64_FLD( OBUS_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS                   , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_CLR_PAR_ERRS );
REG64_FLD( OBUS_TX0_TX_FIR_RESET_PG_RESET                          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_RESET      );

REG64_FLD( OBUS_TX0_TX_ID1_PG_BUS_ID                               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BUS_ID     );
REG64_FLD( OBUS_TX0_TX_ID1_PG_BUS_ID_LEN                           , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_BUS_ID_LEN );

REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_0                             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_0          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_1                             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_1          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_2                             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_2          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_3                             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_3          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_4                             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_4          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_5                             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_5          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_6                             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_6          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_7                             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_7          );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_8_9                           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_8_9        );
REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_8_9_LEN                       , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_8_9_LEN    );

REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_TEST_STATUS_RO_SIGNAL        , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_TEST_STATUS_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_TEST_DONE_RO_SIGNAL          , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_TEST_DONE_RO_SIGNAL );

REG64_FLD( OBUS_TX_IMPCAL_NVAL_PB_ZCAL_N                           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_N     );
REG64_FLD( OBUS_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN                       , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_N_LEN );

REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_DONE_RO_SIGNAL                , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_DONE_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_ERROR_RO_SIGNAL               , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_ERROR_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_BUSY_RO_SIGNAL                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_BUSY_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_CMP_OUT_RO_SIGNAL             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_CMP_OUT_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL          , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL );
REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN      , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN );

REG64_FLD( OBUS_TX_IMPCAL_PVAL_PB_ZCAL_P                           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_P     );
REG64_FLD( OBUS_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN                       , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_P_LEN );

REG64_FLD( OBUS_TX_IMPCAL_P_4X_PB_ZCAL                             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL       );
REG64_FLD( OBUS_TX_IMPCAL_P_4X_PB_ZCAL_LEN                         , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_LEN   );

REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_EN                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SWO_EN );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CAL_SEGS                , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SWO_CAL_SEGS );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_INV                 , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SWO_CMP_INV );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_OFFSET              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SWO_CMP_OFFSET );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_RESET               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SWO_CMP_RESET );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_POWERDOWN               , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SWO_POWERDOWN );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_TCOIL                   , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SWO_TCOIL );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_RANGE_CHECK                 , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_RANGE_CHECK );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_CYA_DATA_INV                , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_CYA_DATA_INV );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_2R                 , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_TEST_OVR_2R );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_1R                 , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_TEST_OVR_1R );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_4X_SEG             , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_TEST_OVR_4X_SEG );
REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_CLK_DIV                , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_TEST_CLK_DIV );

REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SM_MIN_VAL );
REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL_LEN              , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SM_MIN_VAL_LEN );
REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL                  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SM_MAX_VAL );
REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL_LEN              , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
           SH_FLD_ZCAL_SM_MAX_VAL_LEN );

#endif
