/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: import/chips/centaur/common/include/cen_gen_scom_fld_template.H $ */
/*                                                                        */
/* OpenPOWER HCODE Project                                                */
/*                                                                        */
/* COPYRIGHT 2016,2017                                                    */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
#ifndef CEN_GEN_SCOM_FLD_TEMPLATE_H
#define CEN_GEN_SCOM_FLD_TEMPLATE_H
static const uint64_t IDX_CEN_TX_CLK_MODE_PG_PDWN = 0;
static const uint64_t IDX_CEN_TX_CLK_MODE_PG_INVERT = 1;
static const uint64_t IDX_CEN_TX_CLK_MODE_PG_QUIESCE_P = 2;
static const uint64_t IDX_CEN_TX_CLK_MODE_PG_QUIESCE_P_LEN = 3;
static const uint64_t IDX_CEN_TX_CLK_MODE_PG_QUIESCE_N = 4;
static const uint64_t IDX_CEN_TX_CLK_MODE_PG_QUIESCE_N_LEN = 5;
static const uint64_t IDX_CEN_TX_CLK_MODE_PG_DDR = 6;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_0 = 7;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_1 = 8;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_2 = 9;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_3 = 10;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_4 = 11;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_5 = 12;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_6 = 13;
static const uint64_t IDX_CEN_TX_SPARE_MODE_PG_7 = 14;
static const uint64_t IDX_CEN_TX_MODE_PG_MAX_BAD_LANES = 15;
static const uint64_t IDX_CEN_TX_MODE_PG_MAX_BAD_LANES_LEN = 16;
static const uint64_t IDX_CEN_TX_MODE_PG_MSBSWAP = 17;
static const uint64_t IDX_CEN_TX_MODE_PG_PDWN_LITE_DISABLE = 18;
static const uint64_t IDX_CEN_TX_RESET_ACT_PG_CLR_PAR_ERRS = 19;
static const uint64_t IDX_CEN_TX_RESET_ACT_PG_FIR = 20;
static const uint64_t IDX_CEN_TX_BIST_STAT_PG_CLK_ERR = 21;
static const uint64_t IDX_CEN_TX_FIR_PG_ERRS = 22;
static const uint64_t IDX_CEN_TX_FIR_PG_ERRS_LEN = 23;
static const uint64_t IDX_CEN_TX_FIR_PG_PL_ERR = 24;
static const uint64_t IDX_CEN_TX_FIR_MASK_PG_ERRS = 25;
static const uint64_t IDX_CEN_TX_FIR_MASK_PG_ERRS_LEN = 26;
static const uint64_t IDX_CEN_TX_FIR_MASK_PG_PL_ERR = 27;
static const uint64_t IDX_CEN_TX_FIR_ERROR_INJECT_PG_PG_ERR_INJ = 28;
static const uint64_t IDX_CEN_TX_FIR_ERROR_INJECT_PG_PG_ERR_INJ_LEN = 29;
static const uint64_t IDX_CEN_TX_ID1_PG_BUS_ID = 30;
static const uint64_t IDX_CEN_TX_ID1_PG_BUS_ID_LEN = 31;
static const uint64_t IDX_CEN_TX_ID1_PG_GROUP_ID = 32;
static const uint64_t IDX_CEN_TX_ID1_PG_GROUP_ID_LEN = 33;
static const uint64_t IDX_CEN_TX_ID2_PG_LAST_GROUP_ID = 34;
static const uint64_t IDX_CEN_TX_ID2_PG_LAST_GROUP_ID_LEN = 35;
static const uint64_t IDX_CEN_TX_ID3_PG_START_LANE_ID = 36;
static const uint64_t IDX_CEN_TX_ID3_PG_START_LANE_ID_LEN = 37;
static const uint64_t IDX_CEN_TX_ID3_PG_END_LANE_ID = 38;
static const uint64_t IDX_CEN_TX_ID3_PG_END_LANE_ID_LEN = 39;
static const uint64_t IDX_CEN_TX_CLK_CNTL_GCRMSG_PG_DRV_PATTERN_GCRMSG = 40;
static const uint64_t IDX_CEN_TX_CLK_CNTL_GCRMSG_PG_DRV_PATTERN_GCRMSG_LEN = 41;
static const uint64_t IDX_CEN_TX_FFE_MODE_PG_TEST = 42;
static const uint64_t IDX_CEN_TX_FFE_MODE_PG_TEST_LEN = 43;
static const uint64_t IDX_CEN_TX_FFE_MODE_PG_TEST_OVERRIDE1R = 44;
static const uint64_t IDX_CEN_TX_FFE_MODE_PG_TEST_OVERRIDE2R = 45;
static const uint64_t IDX_CEN_TX_FFE_MAIN_PG_P_ENC = 46;
static const uint64_t IDX_CEN_TX_FFE_MAIN_PG_P_ENC_LEN = 47;
static const uint64_t IDX_CEN_TX_FFE_MAIN_PG_N_ENC = 48;
static const uint64_t IDX_CEN_TX_FFE_MAIN_PG_N_ENC_LEN = 49;
static const uint64_t IDX_CEN_TX_FFE_POST_PG_P_ENC = 50;
static const uint64_t IDX_CEN_TX_FFE_POST_PG_P_ENC_LEN = 51;
static const uint64_t IDX_CEN_TX_FFE_POST_PG_N_ENC = 52;
static const uint64_t IDX_CEN_TX_FFE_POST_PG_N_ENC_LEN = 53;
static const uint64_t IDX_CEN_TX_FFE_MARGIN_PG_P_ENC = 54;
static const uint64_t IDX_CEN_TX_FFE_MARGIN_PG_P_ENC_LEN = 55;
static const uint64_t IDX_CEN_TX_FFE_MARGIN_PG_N_ENC = 56;
static const uint64_t IDX_CEN_TX_FFE_MARGIN_PG_N_ENC_LEN = 57;
static const uint64_t IDX_CEN_TX_BAD_LANE_ENC_GCRMSG_PG_LANE1_GCRMSG = 58;
static const uint64_t IDX_CEN_TX_BAD_LANE_ENC_GCRMSG_PG_LANE1_GCRMSG_LEN = 59;
static const uint64_t IDX_CEN_TX_BAD_LANE_ENC_GCRMSG_PG_LANE2_GCRMSG = 60;
static const uint64_t IDX_CEN_TX_BAD_LANE_ENC_GCRMSG_PG_LANE2_GCRMSG_LEN = 61;
static const uint64_t IDX_CEN_TX_BAD_LANE_ENC_GCRMSG_PG_CODE_GCRMSG = 62;
static const uint64_t IDX_CEN_TX_BAD_LANE_ENC_GCRMSG_PG_CODE_GCRMSG_LEN = 63;
static const uint64_t IDX_CEN_TX_SLS_LANE_ENC_GCRMSG_PG_GCRMSG = 64;
static const uint64_t IDX_CEN_TX_SLS_LANE_ENC_GCRMSG_PG_GCRMSG_LEN = 65;
static const uint64_t IDX_CEN_TX_SLS_LANE_ENC_GCRMSG_PG_VAL_GCRMSG = 66;
static const uint64_t IDX_CEN_TX_WT_SEG_ENABLE_PG_EN_ALL_CLK_SEGS_GCRMSG = 67;
static const uint64_t IDX_CEN_TX_WT_SEG_ENABLE_PG_EN_ALL_DATA_SEGS_GCRMSG = 68;
static const uint64_t IDX_CEN_TX_LANE_DISABLED_VEC_0_15_PG_15 = 69;
static const uint64_t IDX_CEN_TX_LANE_DISABLED_VEC_0_15_PG_15_LEN = 70;
static const uint64_t IDX_CEN_TX_LANE_DISABLED_VEC_16_31_PG_31 = 71;
static const uint64_t IDX_CEN_TX_LANE_DISABLED_VEC_16_31_PG_31_LEN = 72;
static const uint64_t IDX_CEN_TX_SLS_LANE_MUX_GCRMSG_PG_SHDW_GCRMSG = 73;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_SHDW_REQ_GCRMSG = 74;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_SHDW_RPR_REQ_GCRMSG = 75;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_UNSHDW_REQ_GCRMSG = 76;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_UNSHDW_RPR_REQ_GCRMSG = 77;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_BUS_WIDTH = 78;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_BUS_WIDTH_LEN = 79;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_RPR_REQ_GCRMSG = 80;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_SLS_LANE_SEL_LG_GCRMSG = 81;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_SLS_LANE_UNSEL_LG_GCRMSG = 82;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_SPR_LNS_PDWN_LITE_GCRMSG = 83;
static const uint64_t IDX_CEN_TX_SLV_MV_SLS_LN_REQ_GCRMSG_PG_LGL_RPR_REQ_GCRMSG = 84;
static const uint64_t IDX_CEN_TX_WIRETEST_PP_WT_PATTERN_LENGTH = 85;
static const uint64_t IDX_CEN_TX_WIRETEST_PP_WT_PATTERN_LENGTH_LEN = 86;
static const uint64_t IDX_CEN_TX_MODE_PP_REDUCED_SCRAMBLE = 87;
static const uint64_t IDX_CEN_TX_MODE_PP_REDUCED_SCRAMBLE_LEN = 88;
static const uint64_t IDX_CEN_TX_MODE_PP_PRBS_SCRAMBLE = 89;
static const uint64_t IDX_CEN_TX_MODE_PP_PRBS_SCRAMBLE_LEN = 90;
static const uint64_t IDX_CEN_TX_MODE_PP_FIFO_L2U_DLY = 91;
static const uint64_t IDX_CEN_TX_MODE_PP_FIFO_L2U_DLY_LEN = 92;
static const uint64_t IDX_CEN_TX_SLS_GCRMSG_PP_SND_CMD = 93;
static const uint64_t IDX_CEN_TX_SLS_GCRMSG_PP_DYN_RECAL_TSR_IGNORE_GCRMSG = 94;
static const uint64_t IDX_CEN_TX_SLS_GCRMSG_PP_CMD = 95;
static const uint64_t IDX_CEN_TX_SLS_GCRMSG_PP_CMD_LEN = 96;
static const uint64_t IDX_CEN_TX_SLS_GCRMSG_PP_SND_CMD_PREV = 97;
static const uint64_t IDX_CEN_TX_SLS_GCRMSG_PP_SND_USING_REG_SCRAMBLE = 98;
static const uint64_t IDX_CEN_TX_BER_CNTL_A_PP_ERR_INJ_A_RAND_BEAT_DIS = 99;
static const uint64_t IDX_CEN_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL = 100;
static const uint64_t IDX_CEN_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL_LEN = 101;
static const uint64_t IDX_CEN_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL = 102;
static const uint64_t IDX_CEN_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL_LEN = 103;
static const uint64_t IDX_CEN_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL = 104;
static const uint64_t IDX_CEN_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL_LEN = 105;
static const uint64_t IDX_CEN_TX_BER_CNTL_B_PP_ERR_INJ_B_RAND_BEAT_DIS = 106;
static const uint64_t IDX_CEN_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL = 107;
static const uint64_t IDX_CEN_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL_LEN = 108;
static const uint64_t IDX_CEN_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL = 109;
static const uint64_t IDX_CEN_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL_LEN = 110;
static const uint64_t IDX_CEN_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL = 111;
static const uint64_t IDX_CEN_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL_LEN = 112;
static const uint64_t IDX_CEN_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 113;
static const uint64_t IDX_CEN_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 114;
static const uint64_t IDX_CEN_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 115;
static const uint64_t IDX_CEN_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 116;
static const uint64_t IDX_CEN_TX_BIST_CNTL_PP_EN = 117;
static const uint64_t IDX_CEN_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_MODE = 118;
static const uint64_t IDX_CEN_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_ALL_CMD = 119;
static const uint64_t IDX_CEN_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_RECAL = 120;
static const uint64_t IDX_CEN_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD = 121;
static const uint64_t IDX_CEN_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD_LEN = 122;
static const uint64_t IDX_CEN_TX_CNTL_PP_ENABLE_REDUCED_SCRAMBLE = 123;
static const uint64_t IDX_CEN_TX_RESET_CFG_PP_HLD = 124;
static const uint64_t IDX_CEN_TX_RESET_CFG_PP_HLD_LEN = 125;
static const uint64_t IDX_CEN_TX_TDR_CNTL1_PP_DAC_CNTL = 126;
static const uint64_t IDX_CEN_TX_TDR_CNTL1_PP_DAC_CNTL_LEN = 127;
static const uint64_t IDX_CEN_TX_TDR_CNTL1_PP_PHASE_SEL = 128;
static const uint64_t IDX_CEN_TX_TDR_CNTL2_PP_PULSE_OFFSET = 129;
static const uint64_t IDX_CEN_TX_TDR_CNTL2_PP_PULSE_OFFSET_LEN = 130;
static const uint64_t IDX_CEN_TX_TDR_CNTL3_PP_PULSE_WIDTH = 131;
static const uint64_t IDX_CEN_TX_TDR_CNTL3_PP_PULSE_WIDTH_LEN = 132;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_PL_LANE_PDWN = 133;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_PL_LANE_INVERT = 134;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_PL_LANE_QUIESCE_P = 135;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_PL_LANE_QUIESCE_P_LEN = 136;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_PL_LANE_QUIESCE_N = 137;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_PL_LANE_QUIESCE_N_LEN = 138;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 139;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 140;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_1 = 141;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_2 = 142;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_3 = 143;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_4 = 144;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_5 = 145;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_6 = 146;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_SPARE_MODE_PL_7 = 147;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_BIST_STAT_PL_LANE_ERR = 148;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_PRBS_MODE_PL_TAP_ID = 149;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_PRBS_MODE_PL_TAP_ID_LEN = 150;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 151;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 152;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 153;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_FIR_PL_ERRS = 154;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_FIR_MASK_PL_ERRS = 155;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 156;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 157;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 158;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE0_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 159;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_WIRETEST_PP_WT_PATTERN_LENGTH = 160;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_WIRETEST_PP_WT_PATTERN_LENGTH_LEN = 161;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_MODE_PP_REDUCED_SCRAMBLE = 162;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_MODE_PP_REDUCED_SCRAMBLE_LEN = 163;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_MODE_PP_PRBS_SCRAMBLE = 164;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_MODE_PP_PRBS_SCRAMBLE_LEN = 165;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_MODE_PP_FIFO_L2U_DLY = 166;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_MODE_PP_FIFO_L2U_DLY_LEN = 167;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_SLS_GCRMSG_PP_SND_CMD = 168;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_SLS_GCRMSG_PP_DYN_RECAL_TSR_IGNORE_GCRMSG = 169;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_SLS_GCRMSG_PP_CMD = 170;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_SLS_GCRMSG_PP_CMD_LEN = 171;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_SLS_GCRMSG_PP_SND_CMD_PREV = 172;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_SLS_GCRMSG_PP_SND_USING_REG_SCRAMBLE = 173;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_A_PP_ERR_INJ_A_RAND_BEAT_DIS = 174;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL = 175;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL_LEN = 176;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL = 177;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL_LEN = 178;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL = 179;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL_LEN = 180;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_B_PP_ERR_INJ_B_RAND_BEAT_DIS = 181;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL = 182;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL_LEN = 183;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL = 184;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL_LEN = 185;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL = 186;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL_LEN = 187;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 188;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 189;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 190;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 191;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BIST_CNTL_PP_EN = 192;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_MODE = 193;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_ALL_CMD = 194;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_RECAL = 195;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD = 196;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD_LEN = 197;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_CNTL_PP_ENABLE_REDUCED_SCRAMBLE = 198;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_RESET_CFG_PP_HLD = 199;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_RESET_CFG_PP_HLD_LEN = 200;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_TDR_CNTL1_PP_DAC_CNTL = 201;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_TDR_CNTL1_PP_DAC_CNTL_LEN = 202;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_TDR_CNTL1_PP_PHASE_SEL = 203;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_TDR_CNTL2_PP_PULSE_OFFSET = 204;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_TDR_CNTL2_PP_PULSE_OFFSET_LEN = 205;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_TDR_CNTL3_PP_PULSE_WIDTH = 206;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_TX_TDR_CNTL3_PP_PULSE_WIDTH_LEN = 207;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_PL_LANE_PDWN = 208;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_PL_LANE_INVERT = 209;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_PL_LANE_QUIESCE_P = 210;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_PL_LANE_QUIESCE_P_LEN = 211;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_PL_LANE_QUIESCE_N = 212;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_PL_LANE_QUIESCE_N_LEN = 213;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 214;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 215;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_1 = 216;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_2 = 217;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_3 = 218;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_4 = 219;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_5 = 220;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_6 = 221;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_SPARE_MODE_PL_7 = 222;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_BIST_STAT_PL_LANE_ERR = 223;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_PRBS_MODE_PL_TAP_ID = 224;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_PRBS_MODE_PL_TAP_ID_LEN = 225;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 226;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 227;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 228;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_FIR_PL_ERRS = 229;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_FIR_MASK_PL_ERRS = 230;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 231;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 232;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 233;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE1_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 234;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_PL_LANE_PDWN = 235;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_PL_LANE_INVERT = 236;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_PL_LANE_QUIESCE_P = 237;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_PL_LANE_QUIESCE_P_LEN = 238;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_PL_LANE_QUIESCE_N = 239;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_PL_LANE_QUIESCE_N_LEN = 240;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 241;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 242;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_1 = 243;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_2 = 244;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_3 = 245;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_4 = 246;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_5 = 247;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_6 = 248;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_SPARE_MODE_PL_7 = 249;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_BIST_STAT_PL_LANE_ERR = 250;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_PRBS_MODE_PL_TAP_ID = 251;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_PRBS_MODE_PL_TAP_ID_LEN = 252;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 253;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 254;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 255;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_FIR_PL_ERRS = 256;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_FIR_MASK_PL_ERRS = 257;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 258;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 259;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 260;
static const uint64_t IDX_CEN_TXPACKS0_TXPACK_0_SLICE2_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 261;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_PL_LANE_PDWN = 262;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_PL_LANE_INVERT = 263;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_PL_LANE_QUIESCE_P = 264;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_PL_LANE_QUIESCE_P_LEN = 265;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_PL_LANE_QUIESCE_N = 266;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_PL_LANE_QUIESCE_N_LEN = 267;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 268;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_0 = 269;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 270;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_2 = 271;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_3 = 272;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_4 = 273;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_5 = 274;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_6 = 275;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_SPARE_MODE_PL_7 = 276;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_BIST_STAT_PL_LANE_ERR = 277;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_PRBS_MODE_PL_TAP_ID = 278;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_PRBS_MODE_PL_TAP_ID_LEN = 279;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 280;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 281;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 282;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_FIR_PL_ERRS = 283;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_FIR_MASK_PL_ERRS = 284;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 285;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 286;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 287;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE0_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 288;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_WIRETEST_PP_WT_PATTERN_LENGTH = 289;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_WIRETEST_PP_WT_PATTERN_LENGTH_LEN = 290;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_MODE_PP_REDUCED_SCRAMBLE = 291;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_MODE_PP_REDUCED_SCRAMBLE_LEN = 292;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_MODE_PP_PRBS_SCRAMBLE = 293;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_MODE_PP_PRBS_SCRAMBLE_LEN = 294;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_MODE_PP_FIFO_L2U_DLY = 295;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_MODE_PP_FIFO_L2U_DLY_LEN = 296;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_SLS_GCRMSG_PP_SND_CMD = 297;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_SLS_GCRMSG_PP_DYN_RECAL_TSR_IGNORE_GCRMSG = 298;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_SLS_GCRMSG_PP_CMD = 299;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_SLS_GCRMSG_PP_CMD_LEN = 300;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_SLS_GCRMSG_PP_SND_CMD_PREV = 301;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_SLS_GCRMSG_PP_SND_USING_REG_SCRAMBLE = 302;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_A_PP_ERR_INJ_A_RAND_BEAT_DIS = 303;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL = 304;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL_LEN = 305;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL = 306;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL_LEN = 307;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL = 308;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL_LEN = 309;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_B_PP_ERR_INJ_B_RAND_BEAT_DIS = 310;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL = 311;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL_LEN = 312;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL = 313;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL_LEN = 314;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL = 315;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL_LEN = 316;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 317;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 318;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 319;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 320;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BIST_CNTL_PP_EN = 321;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_MODE = 322;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_ALL_CMD = 323;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_RECAL = 324;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD = 325;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD_LEN = 326;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_CNTL_PP_ENABLE_REDUCED_SCRAMBLE = 327;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_RESET_CFG_PP_HLD = 328;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_RESET_CFG_PP_HLD_LEN = 329;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_TDR_CNTL1_PP_DAC_CNTL = 330;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_TDR_CNTL1_PP_DAC_CNTL_LEN = 331;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_TDR_CNTL1_PP_PHASE_SEL = 332;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_TDR_CNTL2_PP_PULSE_OFFSET = 333;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_TDR_CNTL2_PP_PULSE_OFFSET_LEN = 334;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_TDR_CNTL3_PP_PULSE_WIDTH = 335;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_TX_TDR_CNTL3_PP_PULSE_WIDTH_LEN = 336;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_PL_LANE_PDWN = 337;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_PL_LANE_INVERT = 338;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_PL_LANE_QUIESCE_P = 339;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_PL_LANE_QUIESCE_P_LEN = 340;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_PL_LANE_QUIESCE_N = 341;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_PL_LANE_QUIESCE_N_LEN = 342;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 343;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_0 = 344;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 345;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_2 = 346;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_3 = 347;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_4 = 348;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_5 = 349;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_6 = 350;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_SPARE_MODE_PL_7 = 351;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_BIST_STAT_PL_LANE_ERR = 352;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_PRBS_MODE_PL_TAP_ID = 353;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_PRBS_MODE_PL_TAP_ID_LEN = 354;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 355;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 356;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 357;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_FIR_PL_ERRS = 358;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_FIR_MASK_PL_ERRS = 359;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 360;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 361;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 362;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE1_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 363;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_PL_LANE_PDWN = 364;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_PL_LANE_INVERT = 365;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_PL_LANE_QUIESCE_P = 366;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_PL_LANE_QUIESCE_P_LEN = 367;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_PL_LANE_QUIESCE_N = 368;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_PL_LANE_QUIESCE_N_LEN = 369;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 370;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_0 = 371;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 372;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_2 = 373;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_3 = 374;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_4 = 375;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_5 = 376;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_6 = 377;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_SPARE_MODE_PL_7 = 378;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_BIST_STAT_PL_LANE_ERR = 379;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_PRBS_MODE_PL_TAP_ID = 380;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_PRBS_MODE_PL_TAP_ID_LEN = 381;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 382;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 383;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 384;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_FIR_PL_ERRS = 385;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_FIR_MASK_PL_ERRS = 386;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 387;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 388;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 389;
static const uint64_t IDX_CEN_TXPACKS1_TXPACK_1_SLICE2_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 390;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_PL_LANE_PDWN = 391;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_PL_LANE_INVERT = 392;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_PL_LANE_QUIESCE_P = 393;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_PL_LANE_QUIESCE_P_LEN = 394;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_PL_LANE_QUIESCE_N = 395;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_PL_LANE_QUIESCE_N_LEN = 396;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 397;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_0 = 398;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_1 = 399;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_2 = 400;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_3 = 401;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_4 = 402;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_5 = 403;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_6 = 404;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_SPARE_MODE_PL_7 = 405;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_BIST_STAT_PL_LANE_ERR = 406;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_PRBS_MODE_PL_TAP_ID = 407;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_PRBS_MODE_PL_TAP_ID_LEN = 408;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 409;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 410;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 411;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_FIR_PL_ERRS = 412;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS = 413;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 414;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 415;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 416;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 417;
static const uint64_t IDX_CEN_TXPACKS2_TX_WIRETEST_PP_WT_PATTERN_LENGTH = 418;
static const uint64_t IDX_CEN_TXPACKS2_TX_WIRETEST_PP_WT_PATTERN_LENGTH_LEN = 419;
static const uint64_t IDX_CEN_TXPACKS2_TX_MODE_PP_REDUCED_SCRAMBLE = 420;
static const uint64_t IDX_CEN_TXPACKS2_TX_MODE_PP_REDUCED_SCRAMBLE_LEN = 421;
static const uint64_t IDX_CEN_TXPACKS2_TX_MODE_PP_PRBS_SCRAMBLE = 422;
static const uint64_t IDX_CEN_TXPACKS2_TX_MODE_PP_PRBS_SCRAMBLE_LEN = 423;
static const uint64_t IDX_CEN_TXPACKS2_TX_MODE_PP_FIFO_L2U_DLY = 424;
static const uint64_t IDX_CEN_TXPACKS2_TX_MODE_PP_FIFO_L2U_DLY_LEN = 425;
static const uint64_t IDX_CEN_TXPACKS2_TX_SLS_GCRMSG_PP_SND_CMD = 426;
static const uint64_t IDX_CEN_TXPACKS2_TX_SLS_GCRMSG_PP_DYN_RECAL_TSR_IGNORE_GCRMSG = 427;
static const uint64_t IDX_CEN_TXPACKS2_TX_SLS_GCRMSG_PP_CMD = 428;
static const uint64_t IDX_CEN_TXPACKS2_TX_SLS_GCRMSG_PP_CMD_LEN = 429;
static const uint64_t IDX_CEN_TXPACKS2_TX_SLS_GCRMSG_PP_SND_CMD_PREV = 430;
static const uint64_t IDX_CEN_TXPACKS2_TX_SLS_GCRMSG_PP_SND_USING_REG_SCRAMBLE = 431;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_A_PP_ERR_INJ_A_RAND_BEAT_DIS = 432;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL = 433;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL_LEN = 434;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL = 435;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL_LEN = 436;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL = 437;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL_LEN = 438;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_B_PP_ERR_INJ_B_RAND_BEAT_DIS = 439;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL = 440;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL_LEN = 441;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL = 442;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL_LEN = 443;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL = 444;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL_LEN = 445;
static const uint64_t IDX_CEN_TXPACKS2_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 446;
static const uint64_t IDX_CEN_TXPACKS2_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 447;
static const uint64_t IDX_CEN_TXPACKS2_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 448;
static const uint64_t IDX_CEN_TXPACKS2_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 449;
static const uint64_t IDX_CEN_TXPACKS2_TX_BIST_CNTL_PP_EN = 450;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_MODE = 451;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_ALL_CMD = 452;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_RECAL = 453;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD = 454;
static const uint64_t IDX_CEN_TXPACKS2_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD_LEN = 455;
static const uint64_t IDX_CEN_TXPACKS2_TX_CNTL_PP_ENABLE_REDUCED_SCRAMBLE = 456;
static const uint64_t IDX_CEN_TXPACKS2_TX_RESET_CFG_PP_HLD = 457;
static const uint64_t IDX_CEN_TXPACKS2_TX_RESET_CFG_PP_HLD_LEN = 458;
static const uint64_t IDX_CEN_TXPACKS2_TX_TDR_CNTL1_PP_DAC_CNTL = 459;
static const uint64_t IDX_CEN_TXPACKS2_TX_TDR_CNTL1_PP_DAC_CNTL_LEN = 460;
static const uint64_t IDX_CEN_TXPACKS2_TX_TDR_CNTL1_PP_PHASE_SEL = 461;
static const uint64_t IDX_CEN_TXPACKS2_TX_TDR_CNTL2_PP_PULSE_OFFSET = 462;
static const uint64_t IDX_CEN_TXPACKS2_TX_TDR_CNTL2_PP_PULSE_OFFSET_LEN = 463;
static const uint64_t IDX_CEN_TXPACKS2_TX_TDR_CNTL3_PP_PULSE_WIDTH = 464;
static const uint64_t IDX_CEN_TXPACKS2_TX_TDR_CNTL3_PP_PULSE_WIDTH_LEN = 465;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_PL_LANE_PDWN = 466;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_PL_LANE_INVERT = 467;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_PL_LANE_QUIESCE_P = 468;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_PL_LANE_QUIESCE_P_LEN = 469;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_PL_LANE_QUIESCE_N = 470;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_PL_LANE_QUIESCE_N_LEN = 471;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 472;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_0 = 473;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_1 = 474;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_2 = 475;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_3 = 476;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_4 = 477;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_5 = 478;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_6 = 479;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_SPARE_MODE_PL_7 = 480;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_BIST_STAT_PL_LANE_ERR = 481;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_PRBS_MODE_PL_TAP_ID = 482;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_PRBS_MODE_PL_TAP_ID_LEN = 483;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 484;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 485;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 486;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_FIR_PL_ERRS = 487;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS = 488;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 489;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 490;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 491;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 492;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_PL_LANE_PDWN = 493;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_PL_LANE_INVERT = 494;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_PL_LANE_QUIESCE_P = 495;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_PL_LANE_QUIESCE_P_LEN = 496;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_PL_LANE_QUIESCE_N = 497;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_PL_LANE_QUIESCE_N_LEN = 498;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 499;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_0 = 500;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_1 = 501;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_2 = 502;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_3 = 503;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_4 = 504;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_5 = 505;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_6 = 506;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_SPARE_MODE_PL_7 = 507;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_BIST_STAT_PL_LANE_ERR = 508;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_PRBS_MODE_PL_TAP_ID = 509;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_PRBS_MODE_PL_TAP_ID_LEN = 510;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 511;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 512;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 513;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_FIR_PL_ERRS = 514;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS = 515;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 516;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 517;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 518;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 519;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_PL_LANE_PDWN = 520;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_PL_LANE_INVERT = 521;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_PL_LANE_QUIESCE_P = 522;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_PL_LANE_QUIESCE_P_LEN = 523;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_PL_LANE_QUIESCE_N = 524;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_PL_LANE_QUIESCE_N_LEN = 525;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 526;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_0 = 527;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_1 = 528;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_2 = 529;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_3 = 530;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_4 = 531;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_5 = 532;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_6 = 533;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_SPARE_MODE_PL_7 = 534;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_BIST_STAT_PL_LANE_ERR = 535;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_PRBS_MODE_PL_TAP_ID = 536;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_PRBS_MODE_PL_TAP_ID_LEN = 537;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 538;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 539;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 540;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_FIR_PL_ERRS = 541;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS = 542;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 543;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 544;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 545;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 546;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_PL_LANE_PDWN = 547;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_PL_LANE_INVERT = 548;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_PL_LANE_QUIESCE_P = 549;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_PL_LANE_QUIESCE_P_LEN = 550;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_PL_LANE_QUIESCE_N = 551;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_PL_LANE_QUIESCE_N_LEN = 552;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 553;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_0 = 554;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_1 = 555;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_2 = 556;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_3 = 557;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_4 = 558;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_5 = 559;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_6 = 560;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_SPARE_MODE_PL_7 = 561;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_BIST_STAT_PL_LANE_ERR = 562;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_PRBS_MODE_PL_TAP_ID = 563;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_PRBS_MODE_PL_TAP_ID_LEN = 564;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 565;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 566;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 567;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_FIR_PL_ERRS = 568;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS = 569;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 570;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 571;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 572;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 573;
static const uint64_t IDX_CEN_TXPACKS3_TX_WIRETEST_PP_WT_PATTERN_LENGTH = 574;
static const uint64_t IDX_CEN_TXPACKS3_TX_WIRETEST_PP_WT_PATTERN_LENGTH_LEN = 575;
static const uint64_t IDX_CEN_TXPACKS3_TX_MODE_PP_REDUCED_SCRAMBLE = 576;
static const uint64_t IDX_CEN_TXPACKS3_TX_MODE_PP_REDUCED_SCRAMBLE_LEN = 577;
static const uint64_t IDX_CEN_TXPACKS3_TX_MODE_PP_PRBS_SCRAMBLE = 578;
static const uint64_t IDX_CEN_TXPACKS3_TX_MODE_PP_PRBS_SCRAMBLE_LEN = 579;
static const uint64_t IDX_CEN_TXPACKS3_TX_MODE_PP_FIFO_L2U_DLY = 580;
static const uint64_t IDX_CEN_TXPACKS3_TX_MODE_PP_FIFO_L2U_DLY_LEN = 581;
static const uint64_t IDX_CEN_TXPACKS3_TX_SLS_GCRMSG_PP_SND_CMD = 582;
static const uint64_t IDX_CEN_TXPACKS3_TX_SLS_GCRMSG_PP_DYN_RECAL_TSR_IGNORE_GCRMSG = 583;
static const uint64_t IDX_CEN_TXPACKS3_TX_SLS_GCRMSG_PP_CMD = 584;
static const uint64_t IDX_CEN_TXPACKS3_TX_SLS_GCRMSG_PP_CMD_LEN = 585;
static const uint64_t IDX_CEN_TXPACKS3_TX_SLS_GCRMSG_PP_SND_CMD_PREV = 586;
static const uint64_t IDX_CEN_TXPACKS3_TX_SLS_GCRMSG_PP_SND_USING_REG_SCRAMBLE = 587;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_A_PP_ERR_INJ_A_RAND_BEAT_DIS = 588;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL = 589;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL_LEN = 590;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL = 591;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL_LEN = 592;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL = 593;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL_LEN = 594;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_B_PP_ERR_INJ_B_RAND_BEAT_DIS = 595;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL = 596;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL_LEN = 597;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL = 598;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL_LEN = 599;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL = 600;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL_LEN = 601;
static const uint64_t IDX_CEN_TXPACKS3_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 602;
static const uint64_t IDX_CEN_TXPACKS3_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 603;
static const uint64_t IDX_CEN_TXPACKS3_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 604;
static const uint64_t IDX_CEN_TXPACKS3_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 605;
static const uint64_t IDX_CEN_TXPACKS3_TX_BIST_CNTL_PP_EN = 606;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_MODE = 607;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_ALL_CMD = 608;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_RECAL = 609;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD = 610;
static const uint64_t IDX_CEN_TXPACKS3_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD_LEN = 611;
static const uint64_t IDX_CEN_TXPACKS3_TX_CNTL_PP_ENABLE_REDUCED_SCRAMBLE = 612;
static const uint64_t IDX_CEN_TXPACKS3_TX_RESET_CFG_PP_HLD = 613;
static const uint64_t IDX_CEN_TXPACKS3_TX_RESET_CFG_PP_HLD_LEN = 614;
static const uint64_t IDX_CEN_TXPACKS3_TX_TDR_CNTL1_PP_DAC_CNTL = 615;
static const uint64_t IDX_CEN_TXPACKS3_TX_TDR_CNTL1_PP_DAC_CNTL_LEN = 616;
static const uint64_t IDX_CEN_TXPACKS3_TX_TDR_CNTL1_PP_PHASE_SEL = 617;
static const uint64_t IDX_CEN_TXPACKS3_TX_TDR_CNTL2_PP_PULSE_OFFSET = 618;
static const uint64_t IDX_CEN_TXPACKS3_TX_TDR_CNTL2_PP_PULSE_OFFSET_LEN = 619;
static const uint64_t IDX_CEN_TXPACKS3_TX_TDR_CNTL3_PP_PULSE_WIDTH = 620;
static const uint64_t IDX_CEN_TXPACKS3_TX_TDR_CNTL3_PP_PULSE_WIDTH_LEN = 621;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_PL_LANE_PDWN = 622;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_PL_LANE_INVERT = 623;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_PL_LANE_QUIESCE_P = 624;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_PL_LANE_QUIESCE_P_LEN = 625;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_PL_LANE_QUIESCE_N = 626;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_PL_LANE_QUIESCE_N_LEN = 627;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 628;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_0 = 629;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_1 = 630;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_2 = 631;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_3 = 632;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_4 = 633;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_5 = 634;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_6 = 635;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_SPARE_MODE_PL_7 = 636;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_BIST_STAT_PL_LANE_ERR = 637;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_PRBS_MODE_PL_TAP_ID = 638;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_PRBS_MODE_PL_TAP_ID_LEN = 639;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 640;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 641;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 642;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_FIR_PL_ERRS = 643;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS = 644;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 645;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 646;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 647;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 648;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_PL_LANE_PDWN = 649;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_PL_LANE_INVERT = 650;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_PL_LANE_QUIESCE_P = 651;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_PL_LANE_QUIESCE_P_LEN = 652;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_PL_LANE_QUIESCE_N = 653;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_PL_LANE_QUIESCE_N_LEN = 654;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 655;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_0 = 656;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_1 = 657;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_2 = 658;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_3 = 659;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_4 = 660;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_5 = 661;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_6 = 662;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_SPARE_MODE_PL_7 = 663;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_BIST_STAT_PL_LANE_ERR = 664;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_PRBS_MODE_PL_TAP_ID = 665;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_PRBS_MODE_PL_TAP_ID_LEN = 666;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 667;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 668;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 669;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_FIR_PL_ERRS = 670;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS = 671;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 672;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 673;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 674;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 675;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_PL_LANE_PDWN = 676;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_PL_LANE_INVERT = 677;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_PL_LANE_QUIESCE_P = 678;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_PL_LANE_QUIESCE_P_LEN = 679;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_PL_LANE_QUIESCE_N = 680;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_PL_LANE_QUIESCE_N_LEN = 681;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 682;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_0 = 683;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_1 = 684;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_2 = 685;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_3 = 686;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_4 = 687;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_5 = 688;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_6 = 689;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_SPARE_MODE_PL_7 = 690;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_BIST_STAT_PL_LANE_ERR = 691;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_PRBS_MODE_PL_TAP_ID = 692;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_PRBS_MODE_PL_TAP_ID_LEN = 693;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 694;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 695;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 696;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_FIR_PL_ERRS = 697;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS = 698;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 699;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 700;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 701;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 702;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_PL_LANE_PDWN = 703;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_PL_LANE_INVERT = 704;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_PL_LANE_QUIESCE_P = 705;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_PL_LANE_QUIESCE_P_LEN = 706;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_PL_LANE_QUIESCE_N = 707;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_PL_LANE_QUIESCE_N_LEN = 708;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 709;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_0 = 710;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_1 = 711;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_2 = 712;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_3 = 713;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 714;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_5 = 715;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_6 = 716;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_SPARE_MODE_PL_7 = 717;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_BIST_STAT_PL_LANE_ERR = 718;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_PRBS_MODE_PL_TAP_ID = 719;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_PRBS_MODE_PL_TAP_ID_LEN = 720;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 721;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 722;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 723;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_FIR_PL_ERRS = 724;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_FIR_MASK_PL_ERRS = 725;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 726;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 727;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 728;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE0_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 729;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_WIRETEST_PP_WT_PATTERN_LENGTH = 730;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_WIRETEST_PP_WT_PATTERN_LENGTH_LEN = 731;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_MODE_PP_REDUCED_SCRAMBLE = 732;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_MODE_PP_REDUCED_SCRAMBLE_LEN = 733;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_MODE_PP_PRBS_SCRAMBLE = 734;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_MODE_PP_PRBS_SCRAMBLE_LEN = 735;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_MODE_PP_FIFO_L2U_DLY = 736;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_MODE_PP_FIFO_L2U_DLY_LEN = 737;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_SLS_GCRMSG_PP_SND_CMD = 738;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_SLS_GCRMSG_PP_DYN_RECAL_TSR_IGNORE_GCRMSG = 739;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_SLS_GCRMSG_PP_CMD = 740;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_SLS_GCRMSG_PP_CMD_LEN = 741;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_SLS_GCRMSG_PP_SND_CMD_PREV = 742;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_SLS_GCRMSG_PP_SND_USING_REG_SCRAMBLE = 743;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_A_PP_ERR_INJ_A_RAND_BEAT_DIS = 744;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL = 745;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL_LEN = 746;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL = 747;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL_LEN = 748;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL = 749;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL_LEN = 750;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_B_PP_ERR_INJ_B_RAND_BEAT_DIS = 751;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL = 752;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL_LEN = 753;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL = 754;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL_LEN = 755;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL = 756;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL_LEN = 757;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 758;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 759;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 760;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 761;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BIST_CNTL_PP_EN = 762;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_MODE = 763;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_ALL_CMD = 764;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_RECAL = 765;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD = 766;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD_LEN = 767;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_CNTL_PP_ENABLE_REDUCED_SCRAMBLE = 768;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_RESET_CFG_PP_HLD = 769;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_RESET_CFG_PP_HLD_LEN = 770;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_TDR_CNTL1_PP_DAC_CNTL = 771;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_TDR_CNTL1_PP_DAC_CNTL_LEN = 772;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_TDR_CNTL1_PP_PHASE_SEL = 773;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_TDR_CNTL2_PP_PULSE_OFFSET = 774;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_TDR_CNTL2_PP_PULSE_OFFSET_LEN = 775;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_TDR_CNTL3_PP_PULSE_WIDTH = 776;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_TX_TDR_CNTL3_PP_PULSE_WIDTH_LEN = 777;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_PL_LANE_PDWN = 778;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_PL_LANE_INVERT = 779;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_PL_LANE_QUIESCE_P = 780;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_PL_LANE_QUIESCE_P_LEN = 781;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_PL_LANE_QUIESCE_N = 782;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_PL_LANE_QUIESCE_N_LEN = 783;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 784;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_0 = 785;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_1 = 786;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_2 = 787;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_3 = 788;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 789;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_5 = 790;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_6 = 791;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_SPARE_MODE_PL_7 = 792;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_BIST_STAT_PL_LANE_ERR = 793;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_PRBS_MODE_PL_TAP_ID = 794;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_PRBS_MODE_PL_TAP_ID_LEN = 795;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 796;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 797;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 798;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_FIR_PL_ERRS = 799;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_FIR_MASK_PL_ERRS = 800;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 801;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 802;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 803;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE1_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 804;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_PL_LANE_PDWN = 805;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_PL_LANE_INVERT = 806;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_PL_LANE_QUIESCE_P = 807;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_PL_LANE_QUIESCE_P_LEN = 808;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_PL_LANE_QUIESCE_N = 809;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_PL_LANE_QUIESCE_N_LEN = 810;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 811;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_0 = 812;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_1 = 813;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_2 = 814;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_3 = 815;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 816;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_5 = 817;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_6 = 818;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_SPARE_MODE_PL_7 = 819;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_BIST_STAT_PL_LANE_ERR = 820;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_PRBS_MODE_PL_TAP_ID = 821;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_PRBS_MODE_PL_TAP_ID_LEN = 822;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 823;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 824;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 825;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_FIR_PL_ERRS = 826;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_FIR_MASK_PL_ERRS = 827;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 828;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 829;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 830;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE2_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 831;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_PL_LANE_PDWN = 832;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_PL_LANE_INVERT = 833;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_PL_LANE_QUIESCE_P = 834;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_PL_LANE_QUIESCE_P_LEN = 835;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_PL_LANE_QUIESCE_N = 836;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_PL_LANE_QUIESCE_N_LEN = 837;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 838;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_0 = 839;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_1 = 840;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_2 = 841;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_3 = 842;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 843;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_5 = 844;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_6 = 845;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_SPARE_MODE_PL_7 = 846;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_BIST_STAT_PL_LANE_ERR = 847;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_PRBS_MODE_PL_TAP_ID = 848;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_PRBS_MODE_PL_TAP_ID_LEN = 849;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 850;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 851;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 852;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_FIR_PL_ERRS = 853;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_FIR_MASK_PL_ERRS = 854;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 855;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 856;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 857;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE3_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 858;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_PL_LANE_PDWN = 859;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_PL_LANE_INVERT = 860;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_PL_LANE_QUIESCE_P = 861;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_PL_LANE_QUIESCE_P_LEN = 862;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_PL_LANE_QUIESCE_N = 863;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_PL_LANE_QUIESCE_N_LEN = 864;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 865;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_0 = 866;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_1 = 867;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_2 = 868;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_3 = 869;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 870;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_5 = 871;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_6 = 872;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_SPARE_MODE_PL_7 = 873;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_BIST_STAT_PL_LANE_ERR = 874;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_PRBS_MODE_PL_TAP_ID = 875;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_PRBS_MODE_PL_TAP_ID_LEN = 876;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 877;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 878;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 879;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_FIR_PL_ERRS = 880;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_FIR_MASK_PL_ERRS = 881;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 882;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 883;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 884;
static const uint64_t IDX_CEN_TXPACKS4_TXPACK_4_SLICE4_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 885;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_PL_LANE_PDWN = 886;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_PL_LANE_INVERT = 887;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_PL_LANE_QUIESCE_P = 888;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_PL_LANE_QUIESCE_P_LEN = 889;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_PL_LANE_QUIESCE_N = 890;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_PL_LANE_QUIESCE_N_LEN = 891;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 892;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_0 = 893;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_1 = 894;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_2 = 895;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_3 = 896;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_4 = 897;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 898;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_6 = 899;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_SPARE_MODE_PL_7 = 900;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_BIST_STAT_PL_LANE_ERR = 901;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_PRBS_MODE_PL_TAP_ID = 902;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_PRBS_MODE_PL_TAP_ID_LEN = 903;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 904;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 905;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 906;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_FIR_PL_ERRS = 907;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_FIR_MASK_PL_ERRS = 908;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 909;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 910;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 911;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE0_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 912;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_WIRETEST_PP_WT_PATTERN_LENGTH = 913;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_WIRETEST_PP_WT_PATTERN_LENGTH_LEN = 914;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_MODE_PP_REDUCED_SCRAMBLE = 915;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_MODE_PP_REDUCED_SCRAMBLE_LEN = 916;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_MODE_PP_PRBS_SCRAMBLE = 917;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_MODE_PP_PRBS_SCRAMBLE_LEN = 918;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_MODE_PP_FIFO_L2U_DLY = 919;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_MODE_PP_FIFO_L2U_DLY_LEN = 920;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_SLS_GCRMSG_PP_SND_CMD = 921;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_SLS_GCRMSG_PP_DYN_RECAL_TSR_IGNORE_GCRMSG = 922;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_SLS_GCRMSG_PP_CMD = 923;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_SLS_GCRMSG_PP_CMD_LEN = 924;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_SLS_GCRMSG_PP_SND_CMD_PREV = 925;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_SLS_GCRMSG_PP_SND_USING_REG_SCRAMBLE = 926;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_A_PP_ERR_INJ_A_RAND_BEAT_DIS = 927;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL = 928;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_A_PP_ERR_INJ_A_FINE_SEL_LEN = 929;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL = 930;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_A_PP_ERR_INJ_A_COARSE_SEL_LEN = 931;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL = 932;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_A_PP_ERR_INJ_A_SEL_LEN = 933;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_B_PP_ERR_INJ_B_RAND_BEAT_DIS = 934;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL = 935;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_B_PP_ERR_INJ_B_FINE_SEL_LEN = 936;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL = 937;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_B_PP_ERR_INJ_B_COARSE_SEL_LEN = 938;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL = 939;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_B_PP_ERR_INJ_B_SEL_LEN = 940;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 941;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 942;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 943;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 944;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BIST_CNTL_PP_EN = 945;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_MODE = 946;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_ALL_CMD = 947;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_RECAL = 948;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD = 949;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_BER_CNTL_SLS_PP_ERR_INJ_SLS_CMD_LEN = 950;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_CNTL_PP_ENABLE_REDUCED_SCRAMBLE = 951;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_RESET_CFG_PP_HLD = 952;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_RESET_CFG_PP_HLD_LEN = 953;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_TDR_CNTL1_PP_DAC_CNTL = 954;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_TDR_CNTL1_PP_DAC_CNTL_LEN = 955;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_TDR_CNTL1_PP_PHASE_SEL = 956;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_TDR_CNTL2_PP_PULSE_OFFSET = 957;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_TDR_CNTL2_PP_PULSE_OFFSET_LEN = 958;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_TDR_CNTL3_PP_PULSE_WIDTH = 959;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_TX_TDR_CNTL3_PP_PULSE_WIDTH_LEN = 960;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_PL_LANE_PDWN = 961;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_PL_LANE_INVERT = 962;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_PL_LANE_QUIESCE_P = 963;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_PL_LANE_QUIESCE_P_LEN = 964;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_PL_LANE_QUIESCE_N = 965;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_PL_LANE_QUIESCE_N_LEN = 966;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 967;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_0 = 968;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_1 = 969;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_2 = 970;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_3 = 971;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_4 = 972;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 973;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_6 = 974;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_SPARE_MODE_PL_7 = 975;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_BIST_STAT_PL_LANE_ERR = 976;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_PRBS_MODE_PL_TAP_ID = 977;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_PRBS_MODE_PL_TAP_ID_LEN = 978;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 979;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 980;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 981;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_FIR_PL_ERRS = 982;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_FIR_MASK_PL_ERRS = 983;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 984;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 985;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 986;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE1_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 987;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_PL_LANE_PDWN = 988;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_PL_LANE_INVERT = 989;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_PL_LANE_QUIESCE_P = 990;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_PL_LANE_QUIESCE_P_LEN = 991;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_PL_LANE_QUIESCE_N = 992;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_PL_LANE_QUIESCE_N_LEN = 993;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 994;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_0 = 995;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_1 = 996;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_2 = 997;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_3 = 998;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_4 = 999;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 1000;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_6 = 1001;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_SPARE_MODE_PL_7 = 1002;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_BIST_STAT_PL_LANE_ERR = 1003;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_PRBS_MODE_PL_TAP_ID = 1004;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_PRBS_MODE_PL_TAP_ID_LEN = 1005;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 1006;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 1007;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 1008;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_FIR_PL_ERRS = 1009;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_FIR_MASK_PL_ERRS = 1010;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 1011;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 1012;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 1013;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE2_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 1014;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_PL_LANE_PDWN = 1015;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_PL_LANE_INVERT = 1016;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_PL_LANE_QUIESCE_P = 1017;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_PL_LANE_QUIESCE_P_LEN = 1018;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_PL_LANE_QUIESCE_N = 1019;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_PL_LANE_QUIESCE_N_LEN = 1020;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 1021;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_0 = 1022;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_1 = 1023;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_2 = 1024;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_3 = 1025;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_4 = 1026;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 1027;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_6 = 1028;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_SPARE_MODE_PL_7 = 1029;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_BIST_STAT_PL_LANE_ERR = 1030;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_PRBS_MODE_PL_TAP_ID = 1031;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_PRBS_MODE_PL_TAP_ID_LEN = 1032;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 1033;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 1034;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 1035;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_FIR_PL_ERRS = 1036;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_FIR_MASK_PL_ERRS = 1037;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 1038;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 1039;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 1040;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE3_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 1041;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_PL_LANE_PDWN = 1042;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_PL_LANE_INVERT = 1043;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_PL_LANE_QUIESCE_P = 1044;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_PL_LANE_QUIESCE_P_LEN = 1045;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_PL_LANE_QUIESCE_N = 1046;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_PL_LANE_QUIESCE_N_LEN = 1047;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_PL_LANE_SCRAMBLE_DISABLE = 1048;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_0 = 1049;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_1 = 1050;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_2 = 1051;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_3 = 1052;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_4 = 1053;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_TX_PL_SPARE_MODE = 1054;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_6 = 1055;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_SPARE_MODE_PL_7 = 1056;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_BIST_STAT_PL_LANE_ERR = 1057;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_PRBS_MODE_PL_TAP_ID = 1058;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_PRBS_MODE_PL_TAP_ID_LEN = 1059;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG = 1060;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_DATA_CNTL_GCRMSG_PL_DRV_PATTERN_GCRMSG_LEN = 1061;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_DATA_CNTL_GCRMSG_PL_SLS_LANE_SEL_GCRMSG = 1062;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_FIR_PL_ERRS = 1063;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_FIR_MASK_PL_ERRS = 1064;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 1065;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_FAST_PL_ERR_INJ_A_ENABLE = 1066;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_MODE_FAST_PL_ERR_INJ_B_ENABLE = 1067;
static const uint64_t IDX_CEN_TXPACKS5_TXPACK_5_SLICE4_TX_CNTL_GCRMSG_PL_PDWN_LITE_GCRMSG = 1068;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_BYPASSN = 1069;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_SPEDIV = 1070;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_SPEDIV_LEN = 1071;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CPISEL = 1072;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CPISEL_LEN = 1073;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_DIVSELB = 1074;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_DIVSELB_LEN = 1075;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_PCLKSEL = 1076;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_PCLKSEL_LEN = 1077;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_UNUSED0 = 1078;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_BANDSEL = 1079;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_BANDSEL_LEN = 1080;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE0 = 1081;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE1 = 1082;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE23 = 1083;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE23_LEN = 1084;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE4 = 1085;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE5 = 1086;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE6 = 1087;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE7 = 1088;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE8 = 1089;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE9 = 1090;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ANALOGTUNE10 = 1091;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ATSTSEL = 1092;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_ATSTSEL_LEN = 1093;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_VCOSEL = 1094;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_BGOFFSET = 1095;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_BGOFFSET_LEN = 1096;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CCALBANDSEL = 1097;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CCALBANDSEL_LEN = 1098;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_UNUSED1 = 1099;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_UNUSED1_LEN = 1100;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CCALFMAX = 1101;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CCALFMIN = 1102;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CCALLOAD = 1103;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CCALCVHOLD = 1104;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_DCTEST_DC = 1105;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CCALMETH = 1106;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_UNUSED4 = 1107;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_CMLEN = 1108;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL0_UNUSED5 = 1109;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_CALREQ = 1110;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_CALRECAL = 1111;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_RDIV = 1112;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_RDIV_LEN = 1113;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_UNUSED2 = 1114;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_UNUSED2_LEN = 1115;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_CCALCOMP = 1116;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_CCALERR = 1117;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_SEL = 1118;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_SEL_LEN = 1119;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_EN = 1120;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_VSEL = 1121;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_VSEL_LEN = 1122;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL1_PLLOUTA_DISABLE = 1123;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL2_UNUSED_OUTB_DISABLE = 1124;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL2_UNUSED = 1125;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL2_UNUSED_LEN = 1126;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL2_RESET = 1127;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL2_SPARE = 1128;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL2_SPARE_LEN = 1129;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_BYPASSN = 1130;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_SPEDIV = 1131;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_SPEDIV_LEN = 1132;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CPISEL = 1133;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CPISEL_LEN = 1134;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_DIVSELB = 1135;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_DIVSELB_LEN = 1136;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_PCLKSEL = 1137;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_PCLKSEL_LEN = 1138;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_UNUSED0 = 1139;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_BANDSEL = 1140;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_BANDSEL_LEN = 1141;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_ANALOGTUNE = 1142;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_ANALOGTUNE_LEN = 1143;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_ATSTSEL = 1144;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_ATSTSEL_LEN = 1145;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_VCOSEL = 1146;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_BGOFFSET = 1147;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_BGOFFSET_LEN = 1148;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CCALBANDSEL = 1149;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CCALBANDSEL_LEN = 1150;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_UNUSED1 = 1151;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_UNUSED1_LEN = 1152;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CCALFMAX = 1153;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CCALFMIN = 1154;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CCALLOAD = 1155;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CCALCVHOLD = 1156;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CCALMETH = 1157;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_UNUSED4 = 1158;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_CMLEN = 1159;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP0_SHADOW_UNUSED5 = 1160;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_CALREQ = 1161;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_CALRECAL = 1162;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_RDIV = 1163;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_RDIV_LEN = 1164;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_UNUSED2 = 1165;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_UNUSED2_LEN = 1166;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_CCALCOMP = 1167;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_CCALERR = 1168;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP1_SHADOW_PLLOUTA_DISABLE = 1169;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP2_SHADOW_UNUSED_OUTB_DISABLE = 1170;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP2_SHADOW_UNUSED = 1171;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP2_SHADOW_UNUSED_LEN = 1172;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP2_SHADOW_RESET = 1173;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP2_SHADOW_SPARE = 1174;
static const uint64_t IDX_CEN_DMIPLL_PLL_CNTRL_SETUP2_SHADOW_SPARE_LEN = 1175;
static const uint64_t IDX_CEN_CUPLL_CTL_ANALOGTUNE = 1176;
static const uint64_t IDX_CEN_CUPLL_CTL_ANALOGTUNE_LEN = 1177;
static const uint64_t IDX_CEN_CUPLL_CTL_ATSTSEL = 1178;
static const uint64_t IDX_CEN_CUPLL_CTL_ATSTSEL_LEN = 1179;
static const uint64_t IDX_CEN_CUPLL_CTL_BANDSEL = 1180;
static const uint64_t IDX_CEN_CUPLL_CTL_BANDSEL_LEN = 1181;
static const uint64_t IDX_CEN_CUPLL_CTL_DIVSELFB = 1182;
static const uint64_t IDX_CEN_CUPLL_CTL_DIVSELFB_LEN = 1183;
static const uint64_t IDX_CEN_CUPLL_CTL_BGOFFSET = 1184;
static const uint64_t IDX_CEN_CUPLL_CTL_BGOFFSET_LEN = 1185;
static const uint64_t IDX_CEN_CUPLL_CTL_SPARE = 1186;
static const uint64_t IDX_CEN_CUPLL_CTL_CAPSEL = 1187;
static const uint64_t IDX_CEN_CUPLL_CTL_CPISEL = 1188;
static const uint64_t IDX_CEN_CUPLL_CTL_CPISEL_LEN = 1189;
static const uint64_t IDX_CEN_CUPLL_CTL_ITUNE = 1190;
static const uint64_t IDX_CEN_CUPLL_CTL_ITUNE_LEN = 1191;
static const uint64_t IDX_CEN_CUPLL_CTL_PCLKSEL = 1192;
static const uint64_t IDX_CEN_CUPLL_CTL_PCLKSEL_LEN = 1193;
static const uint64_t IDX_CEN_CUPLL_CTL_PHASEFB = 1194;
static const uint64_t IDX_CEN_CUPLL_CTL_PHASEFB_LEN = 1195;
static const uint64_t IDX_CEN_CUPLL_CTL_RDIV = 1196;
static const uint64_t IDX_CEN_CUPLL_CTL_REFCLKSEL = 1197;
static const uint64_t IDX_CEN_CUPLL_CTL_RESSEL = 1198;
static const uint64_t IDX_CEN_CUPLL_CTL_VREGENABLE_N = 1199;
static const uint64_t IDX_CEN_CUPLL_CTL_VREGBYPASS = 1200;
static const uint64_t IDX_CEN_CUPLL_CTL_PLLLOCK = 1201;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_ANALOGTUNE = 1202;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_ANALOGTUNE_LEN = 1203;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_ATSTSEL = 1204;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_ATSTSEL_LEN = 1205;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_BANDSEL = 1206;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_BANDSEL_LEN = 1207;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_DIVSELFB = 1208;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_DIVSELFB_LEN = 1209;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_BGOFFSET = 1210;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_BGOFFSET_LEN = 1211;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_SPARE = 1212;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_CAPSEL = 1213;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_CPISEL = 1214;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_CPISEL_LEN = 1215;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_ITUNE = 1216;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_ITUNE_LEN = 1217;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_PCLKSEL = 1218;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_PCLKSEL_LEN = 1219;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_PHASEFB = 1220;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_PHASEFB_LEN = 1221;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_RDIV = 1222;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_REFCLKSEL = 1223;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_RESSEL = 1224;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_VREGENABLE_N = 1225;
static const uint64_t IDX_CEN_CUPLL_CTL_SETUP_SHADOW_VREGBYPASS = 1226;
static const uint64_t IDX_CEN_RX_CLK_MODE_PG_PDWN = 1227;
static const uint64_t IDX_CEN_RX_CLK_MODE_PG_INVERT = 1228;
static const uint64_t IDX_CEN_RX_SPARE_MODE_PG_0 = 1229;
static const uint64_t IDX_CEN_RX_SPARE_MODE_PG_1 = 1230;
static const uint64_t IDX_CEN_RX_SPARE_MODE_PG_2 = 1231;
static const uint64_t IDX_CEN_RX_SPARE_MODE_PG_3 = 1232;
static const uint64_t IDX_CEN_RX_SPARE_MODE_PG_4 = 1233;
static const uint64_t IDX_CEN_RX_SPARE_MODE_PG_SLS_EXTEND_SEL = 1234;
static const uint64_t IDX_CEN_RX_SPARE_MODE_PG_SLS_EXTEND_SEL_LEN = 1235;
static const uint64_t IDX_CEN_RX_MODE_PG_MASTER = 1236;
static const uint64_t IDX_CEN_RX_MODE_PG_DISABLE_FENCE_RESET = 1237;
static const uint64_t IDX_CEN_RX_MODE_PG_PDWN_LITE_DISABLE = 1238;
static const uint64_t IDX_CEN_RX_MODE_PG_USE_SLS_AS_SPR = 1239;
static const uint64_t IDX_CEN_RX_MODE_PG_BUMP_BEFORE_PRBS_SYNC = 1240;
static const uint64_t IDX_CEN_RX_RESET_ACT_PG_CLR_PAR_ERRS = 1241;
static const uint64_t IDX_CEN_RX_RESET_ACT_PG_FIR = 1242;
static const uint64_t IDX_CEN_RX_ID1_PG_BUS_ID = 1243;
static const uint64_t IDX_CEN_RX_ID1_PG_BUS_ID_LEN = 1244;
static const uint64_t IDX_CEN_RX_ID1_PG_GROUP_ID = 1245;
static const uint64_t IDX_CEN_RX_ID1_PG_GROUP_ID_LEN = 1246;
static const uint64_t IDX_CEN_RX_ID2_PG_LAST_GROUP_ID = 1247;
static const uint64_t IDX_CEN_RX_ID2_PG_LAST_GROUP_ID_LEN = 1248;
static const uint64_t IDX_CEN_RX_ID3_PG_START_LANE_ID = 1249;
static const uint64_t IDX_CEN_RX_ID3_PG_START_LANE_ID_LEN = 1250;
static const uint64_t IDX_CEN_RX_ID3_PG_END_LANE_ID = 1251;
static const uint64_t IDX_CEN_RX_ID3_PG_END_LANE_ID_LEN = 1252;
static const uint64_t IDX_CEN_RX_MINIKERF_PG_MINIKERF = 1253;
static const uint64_t IDX_CEN_RX_MINIKERF_PG_MINIKERF_LEN = 1254;
static const uint64_t IDX_CEN_RX_DYN_RPR_DEBUG2_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 1255;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_DISABLE = 1256;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_TX_DISABLE = 1257;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_CNTR_TAP_PTS = 1258;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_CNTR_TAP_PTS_LEN = 1259;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_NONSLS_CNTR_TAP_PTS = 1260;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_NONSLS_CNTR_TAP_PTS_LEN = 1261;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_ERR_CHK_RUN = 1262;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_FINAL_NOP_CS = 1263;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_SR_FINAL_NOP_TIMEOUT_SEL = 1264;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_SR_FINAL_NOP_TIMEOUT_SEL_LEN = 1265;
static const uint64_t IDX_CEN_RX_SLS_MODE_PG_EXCEPTION2_CS = 1266;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_WIRETEST = 1267;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_DESKEW = 1268;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_EYE_OPT = 1269;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_REPAIR = 1270;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_FUNC_MODE = 1271;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_BIST = 1272;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_OFFSET_CAL = 1273;
static const uint64_t IDX_CEN_RX_TRAINING_START_PG_START_WT_BYPASS = 1274;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_WIRETEST_DONE = 1275;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_DESKEW_DONE = 1276;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_EYE_OPT_DONE = 1277;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_REPAIR_DONE = 1278;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_FUNC_MODE_DONE = 1279;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_BIST_STARTED = 1280;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_OFFSET_CAL_DONE = 1281;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_WT_BYPASS_DONE = 1282;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_WIRETEST_FAILED = 1283;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_DESKEW_FAILED = 1284;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_EYE_OPT_FAILED = 1285;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_REPAIR_FAILED = 1286;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_START_BIST_FAILED = 1287;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_OFFSET_CAL_FAILED = 1288;
static const uint64_t IDX_CEN_RX_TRAINING_STATUS_PG_WT_BYPASS_FAILED = 1289;
static const uint64_t IDX_CEN_RX_RECAL_STATUS_PG_STATUS = 1290;
static const uint64_t IDX_CEN_RX_RECAL_STATUS_PG_STATUS_LEN = 1291;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_SLS = 1292;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_SLS_LEN = 1293;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_DS_BL = 1294;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_DS_BL_LEN = 1295;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_CL = 1296;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_CL_LEN = 1297;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_WT = 1298;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_WT_LEN = 1299;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_DS = 1300;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL_PG_DS_LEN = 1301;
static const uint64_t IDX_CEN_RX_FIFO_MODE_PG_INITIAL_L2U_DLY = 1302;
static const uint64_t IDX_CEN_RX_FIFO_MODE_PG_INITIAL_L2U_DLY_LEN = 1303;
static const uint64_t IDX_CEN_RX_FIFO_MODE_PG_FINAL_L2U_DLY = 1304;
static const uint64_t IDX_CEN_RX_FIFO_MODE_PG_FINAL_L2U_DLY_LEN = 1305;
static const uint64_t IDX_CEN_RX_FIFO_MODE_PG_FINAL_L2U_MIN_ERR_THRESH = 1306;
static const uint64_t IDX_CEN_RX_FIFO_MODE_PG_FINAL_L2U_MIN_ERR_THRESH_LEN = 1307;
static const uint64_t IDX_CEN_RX_DYN_RPR_MODE_PG_ENC_BAD_DATA_LANE_SHFT_AMT = 1308;
static const uint64_t IDX_CEN_RX_DYN_RPR_MODE_PG_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 1309;
static const uint64_t IDX_CEN_RX_FIR1_PG_ERRS = 1310;
static const uint64_t IDX_CEN_RX_FIR1_PG_ERRS_LEN = 1311;
static const uint64_t IDX_CEN_RX_FIR1_PG_PL_FIR_ERR = 1312;
static const uint64_t IDX_CEN_RX_FIR2_PG_ERRS = 1313;
static const uint64_t IDX_CEN_RX_FIR2_PG_ERRS_LEN = 1314;
static const uint64_t IDX_CEN_RX_FIR1_MASK_PG_ERRS = 1315;
static const uint64_t IDX_CEN_RX_FIR1_MASK_PG_ERRS_LEN = 1316;
static const uint64_t IDX_CEN_RX_FIR1_MASK_PG_PL_FIR_ERR_MASK = 1317;
static const uint64_t IDX_CEN_RX_FIR2_MASK_PG_ERRS = 1318;
static const uint64_t IDX_CEN_RX_FIR2_MASK_PG_ERRS_LEN = 1319;
static const uint64_t IDX_CEN_RX_FIR1_ERROR_INJECT_PG_PG_ERR_INJ = 1320;
static const uint64_t IDX_CEN_RX_FIR1_ERROR_INJECT_PG_PG_ERR_INJ_LEN = 1321;
static const uint64_t IDX_CEN_RX_FIR2_ERROR_INJECT_PG_PG_ERR_INJ = 1322;
static const uint64_t IDX_CEN_RX_FIR2_ERROR_INJECT_PG_PG_ERR_INJ_LEN = 1323;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_ERROR = 1324;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_STATIC_SPARE_DEPLOYED = 1325;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_STATIC_MAX_SPARES_EXCEEDED = 1326;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_DYNAMIC_REPAIR_ERROR = 1327;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_DYNAMIC_SPARE_DEPLOYED = 1328;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 1329;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_RECAL_ERROR = 1330;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_RECAL_SPARE_DEPLOYED = 1331;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_RECAL_MAX_SPARES_EXCEEDED = 1332;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_PG_PG_TOO_MANY_BUS_ERRORS = 1333;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_ERROR = 1334;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_STATIC_SPARE_DEPLOYED_MASK = 1335;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_STATIC_MAX_SPARES_EXCEEDED_MASK = 1336;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_DYNAMIC_REPAIR_ERROR_MASK = 1337;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_DYNAMIC_SPARE_DEPLOYED_MASK = 1338;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_DYNAMIC_MAX_SPARES_EXCEEDED_MASK = 1339;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_RECAL_ERROR_MASK = 1340;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_RECAL_SPARE_DEPLOYED_MASK = 1341;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_RECAL_MAX_SPARES_EXCEEDED_MASK = 1342;
static const uint64_t IDX_CEN_RX_FIR_TRAINING_MASK_PG_PG_TOO_MANY_BUS_ERRORS_MASK = 1343;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_OFFSET_SEL = 1344;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_OFFSET_SEL_LEN = 1345;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_AMP_SEL = 1346;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_AMP_SEL_LEN = 1347;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_CTLE_SEL = 1348;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_CTLE_SEL_LEN = 1349;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_H1AP_SEL = 1350;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_H1AP_SEL_LEN = 1351;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_DDC_SEL = 1352;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_DDC_SEL_LEN = 1353;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL1_PG_EO_FINAL_L2U_SEL = 1354;
static const uint64_t IDX_CEN_RX_LANE_BAD_VEC_0_15_PG_15 = 1355;
static const uint64_t IDX_CEN_RX_LANE_BAD_VEC_0_15_PG_15_LEN = 1356;
static const uint64_t IDX_CEN_RX_LANE_BAD_VEC_16_31_PG_31 = 1357;
static const uint64_t IDX_CEN_RX_LANE_BAD_VEC_16_31_PG_31_LEN = 1358;
static const uint64_t IDX_CEN_RX_LANE_DISABLED_VEC_0_15_PG_15 = 1359;
static const uint64_t IDX_CEN_RX_LANE_DISABLED_VEC_0_15_PG_15_LEN = 1360;
static const uint64_t IDX_CEN_RX_LANE_DISABLED_VEC_16_31_PG_31 = 1361;
static const uint64_t IDX_CEN_RX_LANE_DISABLED_VEC_16_31_PG_31_LEN = 1362;
static const uint64_t IDX_CEN_RX_LANE_SWAPPED_VEC_0_15_PG_15 = 1363;
static const uint64_t IDX_CEN_RX_LANE_SWAPPED_VEC_0_15_PG_15_LEN = 1364;
static const uint64_t IDX_CEN_RX_LANE_SWAPPED_VEC_16_31_PG_31 = 1365;
static const uint64_t IDX_CEN_RX_LANE_SWAPPED_VEC_16_31_PG_31_LEN = 1366;
static const uint64_t IDX_CEN_RX_WIRETEST_LANEINFO_PG_WTR_MAX_BAD_LANES = 1367;
static const uint64_t IDX_CEN_RX_WIRETEST_LANEINFO_PG_WTR_MAX_BAD_LANES_LEN = 1368;
static const uint64_t IDX_CEN_RX_WIRETEST_GCRMSG_PG_WT_PREV_DONE_GCRMSG = 1369;
static const uint64_t IDX_CEN_RX_WIRETEST_GCRMSG_PG_WT_ALL_DONE_GCRMSG = 1370;
static const uint64_t IDX_CEN_RX_WIRETEST_GCRMSG_PG_CD_PREV_DONE_GCRMSG = 1371;
static const uint64_t IDX_CEN_RX_WIRETEST_GCRMSG_PG_CD_ALL_DONE_GCRMSG = 1372;
static const uint64_t IDX_CEN_RX_WIRETEST_GCRMSG_PG_CNTLS_PREV_LDED_GCRMSG = 1373;
static const uint64_t IDX_CEN_RX_DESKEW_GCRMSG_PG_SEQ = 1374;
static const uint64_t IDX_CEN_RX_DESKEW_GCRMSG_PG_SEQ_LEN = 1375;
static const uint64_t IDX_CEN_RX_DESKEW_GCRMSG_PG_SKMIN = 1376;
static const uint64_t IDX_CEN_RX_DESKEW_GCRMSG_PG_SKMIN_LEN = 1377;
static const uint64_t IDX_CEN_RX_DESKEW_GCRMSG_PG_SKMAX = 1378;
static const uint64_t IDX_CEN_RX_DESKEW_GCRMSG_PG_SKMAX_LEN = 1379;
static const uint64_t IDX_CEN_RX_DESKEW_MODE_PG_MAX_LIMIT = 1380;
static const uint64_t IDX_CEN_RX_DESKEW_MODE_PG_MAX_LIMIT_LEN = 1381;
static const uint64_t IDX_CEN_RX_DESKEW_STATUS_PG_MINSKEW_GRP = 1382;
static const uint64_t IDX_CEN_RX_DESKEW_STATUS_PG_MINSKEW_GRP_LEN = 1383;
static const uint64_t IDX_CEN_RX_DESKEW_STATUS_PG_MAXSKEW_GRP = 1384;
static const uint64_t IDX_CEN_RX_DESKEW_STATUS_PG_MAXSKEW_GRP_LEN = 1385;
static const uint64_t IDX_CEN_RX_BAD_LANE_ENC_GCRMSG_PG_LANE1_GCRMSG = 1386;
static const uint64_t IDX_CEN_RX_BAD_LANE_ENC_GCRMSG_PG_LANE1_GCRMSG_LEN = 1387;
static const uint64_t IDX_CEN_RX_BAD_LANE_ENC_GCRMSG_PG_LANE2_GCRMSG = 1388;
static const uint64_t IDX_CEN_RX_BAD_LANE_ENC_GCRMSG_PG_LANE2_GCRMSG_LEN = 1389;
static const uint64_t IDX_CEN_RX_BAD_LANE_ENC_GCRMSG_PG_CODE_GCRMSG = 1390;
static const uint64_t IDX_CEN_RX_BAD_LANE_ENC_GCRMSG_PG_CODE_GCRMSG_LEN = 1391;
static const uint64_t IDX_CEN_RX_TX_BUS_INFO_PG_WIDTH = 1392;
static const uint64_t IDX_CEN_RX_TX_BUS_INFO_PG_WIDTH_LEN = 1393;
static const uint64_t IDX_CEN_RX_TX_BUS_INFO_PG_BUS_WIDTH = 1394;
static const uint64_t IDX_CEN_RX_TX_BUS_INFO_PG_BUS_WIDTH_LEN = 1395;
static const uint64_t IDX_CEN_RX_SLS_LANE_ENC_GCRMSG_PG_GCRMSG = 1396;
static const uint64_t IDX_CEN_RX_SLS_LANE_ENC_GCRMSG_PG_GCRMSG_LEN = 1397;
static const uint64_t IDX_CEN_RX_SLS_LANE_ENC_GCRMSG_PG_VAL_GCRMSG = 1398;
static const uint64_t IDX_CEN_RX_FENCE_PG_FENCE = 1399;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_FUNC_MODE_SEL = 1400;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_FUNC_MODE_SEL_LEN = 1401;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_RC_SLOWDOWN_SEL = 1402;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_RC_SLOWDOWN_SEL_LEN = 1403;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_PUP_LITE_WAIT_SEL = 1404;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_PUP_LITE_WAIT_SEL_LEN = 1405;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_EO_L2U_WD_SEL = 1406;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_EO_L2U_WD_SEL_LEN = 1407;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_EO_VGA_WD_SEL = 1408;
static const uint64_t IDX_CEN_RX_TIMEOUT_SEL2_PG_EO_VGA_WD_SEL_LEN = 1409;
static const uint64_t IDX_CEN_RX_MISC_ANALOG_PG_C4_SEL = 1410;
static const uint64_t IDX_CEN_RX_MISC_ANALOG_PG_C4_SEL_LEN = 1411;
static const uint64_t IDX_CEN_RX_MISC_ANALOG_PG_NEGZ_EN = 1412;
static const uint64_t IDX_CEN_RX_MISC_ANALOG_PG_PROT_SPEED_SLCT = 1413;
static const uint64_t IDX_CEN_RX_MISC_ANALOG_PG_IREF_BC = 1414;
static const uint64_t IDX_CEN_RX_MISC_ANALOG_PG_IREF_BC_LEN = 1415;
static const uint64_t IDX_CEN_RX_DYN_RPR_GCRMSG_PG_REQ = 1416;
static const uint64_t IDX_CEN_RX_DYN_RPR_GCRMSG_PG_LANE2RPR = 1417;
static const uint64_t IDX_CEN_RX_DYN_RPR_GCRMSG_PG_LANE2RPR_LEN = 1418;
static const uint64_t IDX_CEN_RX_DYN_RPR_GCRMSG_PG_IP = 1419;
static const uint64_t IDX_CEN_RX_DYN_RPR_GCRMSG_PG_COMPLETE = 1420;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_BAD_LANE_MAX = 1421;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_BAD_LANE_MAX_LEN = 1422;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_CNTR1_DURATION = 1423;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_CNTR1_DURATION_LEN = 1424;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_CLR_CNTR1 = 1425;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_DISABLE = 1426;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_ENC_BAD_DATA_LANE_WIDTH = 1427;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING1_PG_ENC_BAD_DATA_LANE_WIDTH_LEN = 1428;
static const uint64_t IDX_CEN_RX_EO_FINAL_L2U_GCRMSG_PG_DLY_SEQ = 1429;
static const uint64_t IDX_CEN_RX_EO_FINAL_L2U_GCRMSG_PG_DLY_SEQ_LEN = 1430;
static const uint64_t IDX_CEN_RX_EO_FINAL_L2U_GCRMSG_PG_DLY_MAXCHG = 1431;
static const uint64_t IDX_CEN_RX_EO_FINAL_L2U_GCRMSG_PG_DLY_MAXCHG_LEN = 1432;
static const uint64_t IDX_CEN_RX_DYN_RECAL_PG_SERVO_RECAL_IP = 1433;
static const uint64_t IDX_CEN_RX_WT_CLK_STATUS_PG_LANE_INVERTED = 1434;
static const uint64_t IDX_CEN_RX_WT_CLK_STATUS_PG_LANE_BAD_CODE = 1435;
static const uint64_t IDX_CEN_RX_WT_CLK_STATUS_PG_LANE_BAD_CODE_LEN = 1436;
static const uint64_t IDX_CEN_RX_DYN_RECAL_CONFIG_PG_OVERALL_TIMEOUT_SEL = 1437;
static const uint64_t IDX_CEN_RX_DYN_RECAL_CONFIG_PG_OVERALL_TIMEOUT_SEL_LEN = 1438;
static const uint64_t IDX_CEN_RX_DYN_RECAL_CONFIG_PG_SUSPEND = 1439;
static const uint64_t IDX_CEN_RX_DYN_RECAL_GCRMSG_PG_IP = 1440;
static const uint64_t IDX_CEN_RX_DYN_RECAL_GCRMSG_PG_FAILED = 1441;
static const uint64_t IDX_CEN_RX_DYN_RECAL_GCRMSG_PG_RIPPLE = 1442;
static const uint64_t IDX_CEN_RX_DYN_RECAL_GCRMSG_PG_TIMEOUT = 1443;
static const uint64_t IDX_CEN_RX_WIRETEST_PLL_CNTL_PG_WT_CU_PLL_PGOOD = 1444;
static const uint64_t IDX_CEN_RX_WIRETEST_PLL_CNTL_PG_WT_CU_PLL_RESET = 1445;
static const uint64_t IDX_CEN_RX_WIRETEST_PLL_CNTL_PG_WT_CU_PLL_PGOODDLY = 1446;
static const uint64_t IDX_CEN_RX_WIRETEST_PLL_CNTL_PG_WT_CU_PLL_PGOODDLY_LEN = 1447;
static const uint64_t IDX_CEN_RX_WIRETEST_PLL_CNTL_PG_WT_PLL_REFCLKSEL = 1448;
static const uint64_t IDX_CEN_RX_WIRETEST_PLL_CNTL_PG_PLL_REFCLKSEL_SCOM_EN = 1449;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_LATCH_OFFSET_CAL = 1450;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_CTLE_CAL = 1451;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_VGA_CAL = 1452;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_DFE_H1_CAL = 1453;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_H1AP_TWEAK = 1454;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_DDC = 1455;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_FINAL_L2U_ADJ = 1456;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_BER_TEST = 1457;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_RESULT_CHECK = 1458;
static const uint64_t IDX_CEN_RX_EO_STEP_CNTL_PG_ENABLE_CTLE_EDGE_TRACK_ONLY = 1459;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_LATCH_OFFSET_DONE = 1460;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_CTLE_DONE = 1461;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_VGA_DONE = 1462;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_H1AP_TWEAK_DONE = 1463;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_DDC_DONE = 1464;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_FINAL_L2U_ADJ_DONE = 1465;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_DFE_FLAG = 1466;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_BER_TEST_DONE = 1467;
static const uint64_t IDX_CEN_RX_EO_STEP_STAT_PG_RESULT_CHECK_DONE = 1468;
static const uint64_t IDX_CEN_RX_AP_PG_EVEN_WORK = 1469;
static const uint64_t IDX_CEN_RX_AP_PG_EVEN_WORK_LEN = 1470;
static const uint64_t IDX_CEN_RX_AP_PG_ODD_WORK = 1471;
static const uint64_t IDX_CEN_RX_AP_PG_ODD_WORK_LEN = 1472;
static const uint64_t IDX_CEN_RX_AN_PG_EVEN_WORK = 1473;
static const uint64_t IDX_CEN_RX_AN_PG_EVEN_WORK_LEN = 1474;
static const uint64_t IDX_CEN_RX_AN_PG_ODD_WORK = 1475;
static const uint64_t IDX_CEN_RX_AN_PG_ODD_WORK_LEN = 1476;
static const uint64_t IDX_CEN_RX_AMIN_PG_EVEN_WORK = 1477;
static const uint64_t IDX_CEN_RX_AMIN_PG_EVEN_WORK_LEN = 1478;
static const uint64_t IDX_CEN_RX_AMIN_PG_ODD_WORK = 1479;
static const uint64_t IDX_CEN_RX_AMIN_PG_ODD_WORK_LEN = 1480;
static const uint64_t IDX_CEN_RX_AMAX_PG_HIGH = 1481;
static const uint64_t IDX_CEN_RX_AMAX_PG_HIGH_LEN = 1482;
static const uint64_t IDX_CEN_RX_AMAX_PG_LOW = 1483;
static const uint64_t IDX_CEN_RX_AMAX_PG_LOW_LEN = 1484;
static const uint64_t IDX_CEN_RX_AMP_VAL_PG_PEAK_WORK = 1485;
static const uint64_t IDX_CEN_RX_AMP_VAL_PG_PEAK_WORK_LEN = 1486;
static const uint64_t IDX_CEN_RX_AMP_VAL_PG_GAIN_WORK = 1487;
static const uint64_t IDX_CEN_RX_AMP_VAL_PG_GAIN_WORK_LEN = 1488;
static const uint64_t IDX_CEN_RX_AMP_VAL_PG_OFFSET_WORK = 1489;
static const uint64_t IDX_CEN_RX_AMP_VAL_PG_OFFSET_WORK_LEN = 1490;
static const uint64_t IDX_CEN_RX_AMP_OFFSET_PG_MAX = 1491;
static const uint64_t IDX_CEN_RX_AMP_OFFSET_PG_MAX_LEN = 1492;
static const uint64_t IDX_CEN_RX_AMP_OFFSET_PG_MIN = 1493;
static const uint64_t IDX_CEN_RX_AMP_OFFSET_PG_MIN_LEN = 1494;
static const uint64_t IDX_CEN_RX_EO_CONVERGENCE_PG_CONVERGED_COUNT = 1495;
static const uint64_t IDX_CEN_RX_EO_CONVERGENCE_PG_CONVERGED_COUNT_LEN = 1496;
static const uint64_t IDX_CEN_RX_EO_CONVERGENCE_PG_CONVERGED_END_COUNT = 1497;
static const uint64_t IDX_CEN_RX_EO_CONVERGENCE_PG_CONVERGED_END_COUNT_LEN = 1498;
static const uint64_t IDX_CEN_RX_SLS_RCVY_PG_DISABLE = 1499;
static const uint64_t IDX_CEN_RX_SLS_RCVY_GCRMSG_PG_REQ = 1500;
static const uint64_t IDX_CEN_RX_SLS_RCVY_GCRMSG_PG_IP = 1501;
static const uint64_t IDX_CEN_RX_SLS_RCVY_GCRMSG_PG_DONE = 1502;
static const uint64_t IDX_CEN_RX_TX_LANE_INFO_GCRMSG_PG_BAD_CNTR_GCRMSG = 1503;
static const uint64_t IDX_CEN_RX_TX_LANE_INFO_GCRMSG_PG_BAD_CNTR_GCRMSG_LEN = 1504;
static const uint64_t IDX_CEN_RX_ERR_TALLYING_GCRMSG_PG_DIS_SYND_TALLYING_GCRMSG = 1505;
static const uint64_t IDX_CEN_RX_TRACE_PG_TRC_MODE = 1506;
static const uint64_t IDX_CEN_RX_TRACE_PG_TRC_MODE_LEN = 1507;
static const uint64_t IDX_CEN_RX_TRACE_PG_TRC_GRP = 1508;
static const uint64_t IDX_CEN_RX_TRACE_PG_TRC_GRP_LEN = 1509;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_LATCH_OFFSET_CAL = 1510;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_CTLE_CAL = 1511;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_VGA_CAL = 1512;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_DFE_H1_CAL = 1513;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_H1AP_TWEAK = 1514;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_DDC = 1515;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_BER_TEST = 1516;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_RESULT_CHECK = 1517;
static const uint64_t IDX_CEN_RX_RC_STEP_CNTL_PG_ENABLE_CTLE_EDGE_TRACK_ONLY = 1518;
static const uint64_t IDX_CEN_RX_SERVO_BER_COUNT_PG_WORK = 1519;
static const uint64_t IDX_CEN_RX_SERVO_BER_COUNT_PG_WORK_LEN = 1520;
static const uint64_t IDX_CEN_RX_DYN_RPR_DEBUG_PG_ENC_BAD_DATA_LANE = 1521;
static const uint64_t IDX_CEN_RX_DYN_RPR_DEBUG_PG_ENC_BAD_DATA_LANE_LEN = 1522;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING2_PG_BAD_BUS_MAX = 1523;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING2_PG_BAD_BUS_MAX_LEN = 1524;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING2_PG_CNTR2_DURATION = 1525;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING2_PG_CNTR2_DURATION_LEN = 1526;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING2_PG_CLR_CNTR2 = 1527;
static const uint64_t IDX_CEN_RX_DYN_RPR_ERR_TALLYING2_PG_DISABLE2 = 1528;
static const uint64_t IDX_CEN_RX_RESULT_CHK_PG_MIN_EYE_WIDTH = 1529;
static const uint64_t IDX_CEN_RX_RESULT_CHK_PG_MIN_EYE_WIDTH_LEN = 1530;
static const uint64_t IDX_CEN_RX_RESULT_CHK_PG_MIN_EYE_HEIGHT = 1531;
static const uint64_t IDX_CEN_RX_RESULT_CHK_PG_MIN_EYE_HEIGHT_LEN = 1532;
static const uint64_t IDX_CEN_RX_BER_CHK_PG_MAX_CHECK_COUNT = 1533;
static const uint64_t IDX_CEN_RX_BER_CHK_PG_MAX_CHECK_COUNT_LEN = 1534;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_SHDW_DONE_FIN_GCRMSG = 1535;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_SHDW_NOP_FIN_GCRMSG = 1536;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_SHDW_RPR_DONE_FIN_GCRMSG = 1537;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_SHDW_RPR_NOP_FIN_GCRMSG = 1538;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_UNSHDW_DONE_FIN_GCRMSG = 1539;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_UNSHDW_NOP_FIN_GCRMSG = 1540;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG = 1541;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG = 1542;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_RECAL_DONE_NOP_FIN_GCRMSG = 1543;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_RECAL_FAIL_NOP_FIN_GCRMSG = 1544;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_RECAL_FRESULTS_FIN_GCRMSG = 1545;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_RECAL_ABORT_ACK_FIN_GCRMSG = 1546;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG = 1547;
static const uint64_t IDX_CEN_RX_SLS_RCVY_FIN_GCRMSG_PG_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG = 1548;
static const uint64_t IDX_CEN_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE = 1549;
static const uint64_t IDX_CEN_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE_LEN = 1550;
static const uint64_t IDX_CEN_RX_MODE1_PP_PRBS_SCRAMBLE_MODE = 1551;
static const uint64_t IDX_CEN_RX_MODE1_PP_PRBS_SCRAMBLE_MODE_LEN = 1552;
static const uint64_t IDX_CEN_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL = 1553;
static const uint64_t IDX_CEN_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL_LEN = 1554;
static const uint64_t IDX_CEN_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL = 1555;
static const uint64_t IDX_CEN_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL_LEN = 1556;
static const uint64_t IDX_CEN_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL = 1557;
static const uint64_t IDX_CEN_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL_LEN = 1558;
static const uint64_t IDX_CEN_RX_MODE1_PP_ENABLE_DFE_V1 = 1559;
static const uint64_t IDX_CEN_RX_MODE1_PP_AMIN_ALL = 1560;
static const uint64_t IDX_CEN_RX_CNTL_FAST_PP_PRBS_CHECK_SYNC = 1561;
static const uint64_t IDX_CEN_RX_CNTL_FAST_PP_ENABLE_REDUCED_SCRAMBLE = 1562;
static const uint64_t IDX_CEN_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 1563;
static const uint64_t IDX_CEN_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 1564;
static const uint64_t IDX_CEN_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 1565;
static const uint64_t IDX_CEN_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 1566;
static const uint64_t IDX_CEN_RX_BER_CNTL_PP_EN = 1567;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_TIMER_FREEZE_EN = 1568;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_COUNT_FREEZE_EN = 1569;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_COUNT_SEL = 1570;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_COUNT_SEL_LEN = 1571;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_TIMER_SEL = 1572;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_TIMER_SEL_LEN = 1573;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_CLR_COUNT_ON_READ_EN = 1574;
static const uint64_t IDX_CEN_RX_BER_MODE_PP_CLR_TIMER_ON_READ_EN = 1575;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_A = 1576;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_A_LEN = 1577;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_B = 1578;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_B_LEN = 1579;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_C = 1580;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_C_LEN = 1581;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_D = 1582;
static const uint64_t IDX_CEN_RX_SERVO_TO1_PP_TIMEOUT_SEL_D_LEN = 1583;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_E = 1584;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_E_LEN = 1585;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_F = 1586;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_F_LEN = 1587;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_G = 1588;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_G_LEN = 1589;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_H = 1590;
static const uint64_t IDX_CEN_RX_SERVO_TO2_PP_TIMEOUT_SEL_H_LEN = 1591;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_I = 1592;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_I_LEN = 1593;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_J = 1594;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_J_LEN = 1595;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_K = 1596;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_K_LEN = 1597;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_L = 1598;
static const uint64_t IDX_CEN_RX_SERVO_TO3_PP_TIMEOUT_SEL_L_LEN = 1599;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_PEAK_CFG = 1600;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_PEAK_CFG_LEN = 1601;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_AMIN_CFG = 1602;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_AMIN_CFG_LEN = 1603;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_ANAP_CFG = 1604;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_ANAP_CFG_LEN = 1605;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_H1_CFG = 1606;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_H1_CFG_LEN = 1607;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_H1AP_CFG = 1608;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_H1AP_CFG_LEN = 1609;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_CA_CFG = 1610;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_CA_CFG_LEN = 1611;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_SPMUX_CFG = 1612;
static const uint64_t IDX_CEN_RX_DFE_CONFIG_PP_SPMUX_CFG_LEN = 1613;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_INIT_TMR_CFG = 1614;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_INIT_TMR_CFG_LEN = 1615;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_BER_CFG = 1616;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_BER_CFG_LEN = 1617;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_FIFO_DLY_CFG = 1618;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_FIFO_DLY_CFG_LEN = 1619;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_DDC_CFG = 1620;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_DDC_CFG_LEN = 1621;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_DAC_BO_CFG = 1622;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_DAC_BO_CFG_LEN = 1623;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_PROT_CFG = 1624;
static const uint64_t IDX_CEN_RX_DFE_TIMERS_PP_PROT_CFG_LEN = 1625;
static const uint64_t IDX_CEN_RX_RESET_CFG_PP_HLD = 1626;
static const uint64_t IDX_CEN_RX_RESET_CFG_PP_HLD_LEN = 1627;
static const uint64_t IDX_CEN_RX_RECAL_TO1_PP_TIMEOUT_SEL_A = 1628;
static const uint64_t IDX_CEN_RX_RECAL_TO1_PP_TIMEOUT_SEL_A_LEN = 1629;
static const uint64_t IDX_CEN_RX_RECAL_TO1_PP_TIMEOUT_SEL_B = 1630;
static const uint64_t IDX_CEN_RX_RECAL_TO1_PP_TIMEOUT_SEL_B_LEN = 1631;
static const uint64_t IDX_CEN_RX_RECAL_TO2_PP_TIMEOUT_SEL_E = 1632;
static const uint64_t IDX_CEN_RX_RECAL_TO2_PP_TIMEOUT_SEL_E_LEN = 1633;
static const uint64_t IDX_CEN_RX_RECAL_TO2_PP_TIMEOUT_SEL_G = 1634;
static const uint64_t IDX_CEN_RX_RECAL_TO2_PP_TIMEOUT_SEL_G_LEN = 1635;
static const uint64_t IDX_CEN_RX_RECAL_TO2_PP_TIMEOUT_SEL_H = 1636;
static const uint64_t IDX_CEN_RX_RECAL_TO2_PP_TIMEOUT_SEL_H_LEN = 1637;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_I = 1638;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_I_LEN = 1639;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_J = 1640;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_J_LEN = 1641;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_K = 1642;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_K_LEN = 1643;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_L = 1644;
static const uint64_t IDX_CEN_RX_RECAL_TO3_PP_TIMEOUT_SEL_L_LEN = 1645;
static const uint64_t IDX_CEN_RX_MODE2_PP_PP_TRC_EN = 1646;
static const uint64_t IDX_CEN_RX_MODE2_PP_PP_TRC_MODE = 1647;
static const uint64_t IDX_CEN_RX_MODE2_PP_PP_TRC_MODE_LEN = 1648;
static const uint64_t IDX_CEN_RX_MODE2_PP_BIST_JITTER_PULSE_SEL = 1649;
static const uint64_t IDX_CEN_RX_MODE2_PP_BIST_JITTER_PULSE_SEL_LEN = 1650;
static const uint64_t IDX_CEN_RX_MODE2_PP_BIST_MIN_EYE_WIDTH = 1651;
static const uint64_t IDX_CEN_RX_MODE2_PP_BIST_MIN_EYE_WIDTH_LEN = 1652;
static const uint64_t IDX_CEN_RX_MODE2_PP_WT_PATTERN_LENGTH = 1653;
static const uint64_t IDX_CEN_RX_MODE2_PP_WT_PATTERN_LENGTH_LEN = 1654;
static const uint64_t IDX_CEN_RX_BIST_GCRMSG_PP_EN = 1655;
static const uint64_t IDX_CEN_RX_SCOPE_CNTL_PP_CONTROL = 1656;
static const uint64_t IDX_CEN_RX_SCOPE_CNTL_PP_CONTROL_LEN = 1657;
static const uint64_t IDX_CEN_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG = 1658;
static const uint64_t IDX_CEN_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG_LEN = 1659;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_STEP_INTERVAL_EN = 1660;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_STEP_INTERVAL = 1661;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_STEP_INTERVAL_LEN = 1662;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_PHASEROT_OFFSET_EN = 1663;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_PHASEROT_OFFSET = 1664;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_PHASEROT_OFFSET_LEN = 1665;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_BUFFER_SEL = 1666;
static const uint64_t IDX_CEN_RX_MODE3_PP_BIST_BUFFER_SEL_LEN = 1667;
static const uint64_t IDX_CEN_RX_STOP_CNTL_STAT_PG_STATE_ENABLE = 1668;
static const uint64_t IDX_CEN_RX_STOP_CNTL_STAT_PG_ADDR_MSB = 1669;
static const uint64_t IDX_CEN_RX_STOP_CNTL_STAT_PG_ADDR_MSB_LEN = 1670;
static const uint64_t IDX_CEN_RX_STOP_CNTL_STAT_PG_MASK_MSB = 1671;
static const uint64_t IDX_CEN_RX_STOP_CNTL_STAT_PG_MASK_MSB_LEN = 1672;
static const uint64_t IDX_CEN_RX_STOP_ADDR_LSB_PG_LSB = 1673;
static const uint64_t IDX_CEN_RX_STOP_ADDR_LSB_PG_LSB_LEN = 1674;
static const uint64_t IDX_CEN_RX_STOP_MASK_LSB_PG_LSB = 1675;
static const uint64_t IDX_CEN_RX_STOP_MASK_LSB_PG_LSB_LEN = 1676;
static const uint64_t IDX_CEN_RX_WT_CONFIG_PG_CHECK_COUNT = 1677;
static const uint64_t IDX_CEN_RX_WT_CONFIG_PG_CHECK_COUNT_LEN = 1678;
static const uint64_t IDX_CEN_RX_WT_CONFIG_PG_CHECK_LANES = 1679;
static const uint64_t IDX_CEN_RX_WT_CONFIG_PG_CHECK_LANES_LEN = 1680;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE = 1681;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE_LEN = 1682;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_PRBS_SCRAMBLE_MODE = 1683;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_PRBS_SCRAMBLE_MODE_LEN = 1684;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL = 1685;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL_LEN = 1686;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL = 1687;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL_LEN = 1688;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL = 1689;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL_LEN = 1690;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_ENABLE_DFE_V1 = 1691;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE1_PP_AMIN_ALL = 1692;
static const uint64_t IDX_CEN_TXPACKS0_RX_CNTL_FAST_PP_PRBS_CHECK_SYNC = 1693;
static const uint64_t IDX_CEN_TXPACKS0_RX_CNTL_FAST_PP_ENABLE_REDUCED_SCRAMBLE = 1694;
static const uint64_t IDX_CEN_TXPACKS0_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 1695;
static const uint64_t IDX_CEN_TXPACKS0_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 1696;
static const uint64_t IDX_CEN_TXPACKS0_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 1697;
static const uint64_t IDX_CEN_TXPACKS0_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 1698;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_CNTL_PP_EN = 1699;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_TIMER_FREEZE_EN = 1700;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_COUNT_FREEZE_EN = 1701;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_COUNT_SEL = 1702;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_COUNT_SEL_LEN = 1703;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_TIMER_SEL = 1704;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_TIMER_SEL_LEN = 1705;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_CLR_COUNT_ON_READ_EN = 1706;
static const uint64_t IDX_CEN_TXPACKS0_RX_BER_MODE_PP_CLR_TIMER_ON_READ_EN = 1707;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_A = 1708;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_A_LEN = 1709;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_B = 1710;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_B_LEN = 1711;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_C = 1712;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_C_LEN = 1713;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_D = 1714;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO1_PP_TIMEOUT_SEL_D_LEN = 1715;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_E = 1716;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_E_LEN = 1717;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_F = 1718;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_F_LEN = 1719;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_G = 1720;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_G_LEN = 1721;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_H = 1722;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO2_PP_TIMEOUT_SEL_H_LEN = 1723;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_I = 1724;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_I_LEN = 1725;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_J = 1726;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_J_LEN = 1727;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_K = 1728;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_K_LEN = 1729;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_L = 1730;
static const uint64_t IDX_CEN_TXPACKS0_RX_SERVO_TO3_PP_TIMEOUT_SEL_L_LEN = 1731;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_PEAK_CFG = 1732;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_PEAK_CFG_LEN = 1733;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_AMIN_CFG = 1734;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_AMIN_CFG_LEN = 1735;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_ANAP_CFG = 1736;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_ANAP_CFG_LEN = 1737;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_H1_CFG = 1738;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_H1_CFG_LEN = 1739;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_H1AP_CFG = 1740;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_H1AP_CFG_LEN = 1741;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_CA_CFG = 1742;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_CA_CFG_LEN = 1743;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_SPMUX_CFG = 1744;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_CONFIG_PP_SPMUX_CFG_LEN = 1745;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_INIT_TMR_CFG = 1746;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_INIT_TMR_CFG_LEN = 1747;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_BER_CFG = 1748;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_BER_CFG_LEN = 1749;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_FIFO_DLY_CFG = 1750;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_FIFO_DLY_CFG_LEN = 1751;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_DDC_CFG = 1752;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_DDC_CFG_LEN = 1753;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_DAC_BO_CFG = 1754;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_DAC_BO_CFG_LEN = 1755;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_PROT_CFG = 1756;
static const uint64_t IDX_CEN_TXPACKS0_RX_DFE_TIMERS_PP_PROT_CFG_LEN = 1757;
static const uint64_t IDX_CEN_TXPACKS0_RX_RESET_CFG_PP_HLD = 1758;
static const uint64_t IDX_CEN_TXPACKS0_RX_RESET_CFG_PP_HLD_LEN = 1759;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO1_PP_TIMEOUT_SEL_A = 1760;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO1_PP_TIMEOUT_SEL_A_LEN = 1761;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO1_PP_TIMEOUT_SEL_B = 1762;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO1_PP_TIMEOUT_SEL_B_LEN = 1763;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO2_PP_TIMEOUT_SEL_E = 1764;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO2_PP_TIMEOUT_SEL_E_LEN = 1765;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO2_PP_TIMEOUT_SEL_G = 1766;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO2_PP_TIMEOUT_SEL_G_LEN = 1767;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO2_PP_TIMEOUT_SEL_H = 1768;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO2_PP_TIMEOUT_SEL_H_LEN = 1769;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_I = 1770;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_I_LEN = 1771;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_J = 1772;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_J_LEN = 1773;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_K = 1774;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_K_LEN = 1775;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_L = 1776;
static const uint64_t IDX_CEN_TXPACKS0_RX_RECAL_TO3_PP_TIMEOUT_SEL_L_LEN = 1777;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_PP_TRC_EN = 1778;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_PP_TRC_MODE = 1779;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_PP_TRC_MODE_LEN = 1780;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_BIST_JITTER_PULSE_SEL = 1781;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_BIST_JITTER_PULSE_SEL_LEN = 1782;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_BIST_MIN_EYE_WIDTH = 1783;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_BIST_MIN_EYE_WIDTH_LEN = 1784;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_WT_PATTERN_LENGTH = 1785;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE2_PP_WT_PATTERN_LENGTH_LEN = 1786;
static const uint64_t IDX_CEN_TXPACKS0_RX_BIST_GCRMSG_PP_EN = 1787;
static const uint64_t IDX_CEN_TXPACKS0_RX_SCOPE_CNTL_PP_CONTROL = 1788;
static const uint64_t IDX_CEN_TXPACKS0_RX_SCOPE_CNTL_PP_CONTROL_LEN = 1789;
static const uint64_t IDX_CEN_TXPACKS0_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG = 1790;
static const uint64_t IDX_CEN_TXPACKS0_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG_LEN = 1791;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_STEP_INTERVAL_EN = 1792;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_STEP_INTERVAL = 1793;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_STEP_INTERVAL_LEN = 1794;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_PHASEROT_OFFSET_EN = 1795;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_PHASEROT_OFFSET = 1796;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_PHASEROT_OFFSET_LEN = 1797;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_BUFFER_SEL = 1798;
static const uint64_t IDX_CEN_TXPACKS0_RX_MODE3_PP_BIST_BUFFER_SEL_LEN = 1799;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_MODE_PL_LANE_PDWN = 1800;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 1801;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_CNTL_PL_BLOCK_LOCK_LANE = 1802;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_CNTL_PL_CHECK_SKEW_LANE = 1803;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_CNTL_PL_PDWN_LITE = 1804;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_CNTL_PL_OFFCAL_MODE = 1805;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 = 1806;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 = 1807;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_2 = 1808;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_3 = 1809;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_4 = 1810;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_5 = 1811;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 = 1812;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 = 1813;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_BIST_STAT_PL_ERR = 1814;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_EVEN_PL_SAMP1 = 1815;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_EVEN_PL_SAMP1_LEN = 1816;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_EVEN_PL_SAMP0 = 1817;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_EVEN_PL_SAMP0_LEN = 1818;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_ODD_PL_SAMP1 = 1819;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_ODD_PL_SAMP1_LEN = 1820;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_ODD_PL_SAMP0 = 1821;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_OFFSET_ODD_PL_SAMP0_LEN = 1822;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMP_VAL_PL_PEAK = 1823;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMP_VAL_PL_PEAK_LEN = 1824;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMP_VAL_PL_GAIN = 1825;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMP_VAL_PL_GAIN_LEN = 1826;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMP_VAL_PL_OFFSET = 1827;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMP_VAL_PL_OFFSET_LEN = 1828;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMP_CNTL_PL_ADJ_DONE = 1829;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET = 1830;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 1831;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIFO_STAT_PL_L2U_DLY = 1832;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIFO_STAT_PL_L2U_DLY_LEN = 1833;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AP_PL_EVEN_SAMP = 1834;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AP_PL_EVEN_SAMP_LEN = 1835;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AP_PL_ODD_SAMP = 1836;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AP_PL_ODD_SAMP_LEN = 1837;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AN_PL_EVEN_SAMP = 1838;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AN_PL_EVEN_SAMP_LEN = 1839;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AN_PL_ODD_SAMP = 1840;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AN_PL_ODD_SAMP_LEN = 1841;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMIN_PL_EVEN = 1842;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMIN_PL_EVEN_LEN = 1843;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMIN_PL_ODD = 1844;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_AMIN_PL_ODD_LEN = 1845;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_EVEN_PL_SAMP1 = 1846;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_EVEN_PL_SAMP1_LEN = 1847;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_EVEN_PL_SAMP0 = 1848;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_EVEN_PL_SAMP0_LEN = 1849;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_ODD_PL_SAMP1 = 1850;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_ODD_PL_SAMP1_LEN = 1851;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_ODD_PL_SAMP0 = 1852;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_H1_ODD_PL_SAMP0_LEN = 1853;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_PRBS_MODE_PL_TAP_ID = 1854;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_PRBS_MODE_PL_TAP_ID_LEN = 1855;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 1856;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_DESKEW_STAT_PL_BAD_SKEW = 1857;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_DESKEW_STAT_PL_BAD = 1858;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIR_PL_ERRS = 1859;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIR_PL_ERRS_LEN = 1860;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS = 1861;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 1862;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 1863;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 1864;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SLS_PL_LANE_SEL = 1865;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SLS_PL_9TH_PATTERN_EN = 1866;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_WT_STATUS_PL_LANE_DISABLED = 1867;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_WT_STATUS_PL_LANE_INVERTED = 1868;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE = 1869;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 1870;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SERVO_CNTL_PL_OP_DONE = 1871;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SERVO_CNTL_PL_OP = 1872;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_SERVO_CNTL_PL_OP_LEN = 1873;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ = 1874;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 1875;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_TRACE_PL_LN_TRC_EN = 1876;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_EYE_OPT_STAT_PL_BAD_BER = 1877;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 1878;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 1879;
static const uint64_t IDX_CEN_TXPACKS0_SLICE0_RX_EYE_OPT_STAT_PL_BAD_DDC = 1880;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_MODE_PL_LANE_PDWN = 1881;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 1882;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_CNTL_PL_BLOCK_LOCK_LANE = 1883;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_CNTL_PL_CHECK_SKEW_LANE = 1884;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_CNTL_PL_PDWN_LITE = 1885;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_CNTL_PL_OFFCAL_MODE = 1886;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 = 1887;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 = 1888;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_2 = 1889;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_3 = 1890;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_4 = 1891;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_5 = 1892;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 = 1893;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 = 1894;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_BIST_STAT_PL_ERR = 1895;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_EVEN_PL_SAMP1 = 1896;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_EVEN_PL_SAMP1_LEN = 1897;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_EVEN_PL_SAMP0 = 1898;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_EVEN_PL_SAMP0_LEN = 1899;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_ODD_PL_SAMP1 = 1900;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_ODD_PL_SAMP1_LEN = 1901;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_ODD_PL_SAMP0 = 1902;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_OFFSET_ODD_PL_SAMP0_LEN = 1903;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMP_VAL_PL_PEAK = 1904;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMP_VAL_PL_PEAK_LEN = 1905;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMP_VAL_PL_GAIN = 1906;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMP_VAL_PL_GAIN_LEN = 1907;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMP_VAL_PL_OFFSET = 1908;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMP_VAL_PL_OFFSET_LEN = 1909;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMP_CNTL_PL_ADJ_DONE = 1910;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET = 1911;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 1912;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIFO_STAT_PL_L2U_DLY = 1913;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIFO_STAT_PL_L2U_DLY_LEN = 1914;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AP_PL_EVEN_SAMP = 1915;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AP_PL_EVEN_SAMP_LEN = 1916;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AP_PL_ODD_SAMP = 1917;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AP_PL_ODD_SAMP_LEN = 1918;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AN_PL_EVEN_SAMP = 1919;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AN_PL_EVEN_SAMP_LEN = 1920;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AN_PL_ODD_SAMP = 1921;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AN_PL_ODD_SAMP_LEN = 1922;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMIN_PL_EVEN = 1923;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMIN_PL_EVEN_LEN = 1924;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMIN_PL_ODD = 1925;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_AMIN_PL_ODD_LEN = 1926;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_EVEN_PL_SAMP1 = 1927;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_EVEN_PL_SAMP1_LEN = 1928;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_EVEN_PL_SAMP0 = 1929;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_EVEN_PL_SAMP0_LEN = 1930;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_ODD_PL_SAMP1 = 1931;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_ODD_PL_SAMP1_LEN = 1932;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_ODD_PL_SAMP0 = 1933;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_H1_ODD_PL_SAMP0_LEN = 1934;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_PRBS_MODE_PL_TAP_ID = 1935;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_PRBS_MODE_PL_TAP_ID_LEN = 1936;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 1937;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_DESKEW_STAT_PL_BAD_SKEW = 1938;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_DESKEW_STAT_PL_BAD = 1939;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIR_PL_ERRS = 1940;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIR_PL_ERRS_LEN = 1941;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS = 1942;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 1943;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 1944;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 1945;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SLS_PL_LANE_SEL = 1946;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SLS_PL_9TH_PATTERN_EN = 1947;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_WT_STATUS_PL_LANE_DISABLED = 1948;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_WT_STATUS_PL_LANE_INVERTED = 1949;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE = 1950;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 1951;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SERVO_CNTL_PL_OP_DONE = 1952;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SERVO_CNTL_PL_OP = 1953;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_SERVO_CNTL_PL_OP_LEN = 1954;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ = 1955;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 1956;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_TRACE_PL_LN_TRC_EN = 1957;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_EYE_OPT_STAT_PL_BAD_BER = 1958;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 1959;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 1960;
static const uint64_t IDX_CEN_TXPACKS0_SLICE1_RX_EYE_OPT_STAT_PL_BAD_DDC = 1961;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_MODE_PL_LANE_PDWN = 1962;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 1963;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_CNTL_PL_BLOCK_LOCK_LANE = 1964;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_CNTL_PL_CHECK_SKEW_LANE = 1965;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_CNTL_PL_PDWN_LITE = 1966;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_CNTL_PL_OFFCAL_MODE = 1967;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 = 1968;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 = 1969;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_2 = 1970;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_3 = 1971;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_4 = 1972;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_5 = 1973;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 = 1974;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 = 1975;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_BIST_STAT_PL_ERR = 1976;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_EVEN_PL_SAMP1 = 1977;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_EVEN_PL_SAMP1_LEN = 1978;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_EVEN_PL_SAMP0 = 1979;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_EVEN_PL_SAMP0_LEN = 1980;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_ODD_PL_SAMP1 = 1981;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_ODD_PL_SAMP1_LEN = 1982;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_ODD_PL_SAMP0 = 1983;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_OFFSET_ODD_PL_SAMP0_LEN = 1984;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMP_VAL_PL_PEAK = 1985;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMP_VAL_PL_PEAK_LEN = 1986;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMP_VAL_PL_GAIN = 1987;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMP_VAL_PL_GAIN_LEN = 1988;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMP_VAL_PL_OFFSET = 1989;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMP_VAL_PL_OFFSET_LEN = 1990;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMP_CNTL_PL_ADJ_DONE = 1991;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET = 1992;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 1993;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIFO_STAT_PL_L2U_DLY = 1994;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIFO_STAT_PL_L2U_DLY_LEN = 1995;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AP_PL_EVEN_SAMP = 1996;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AP_PL_EVEN_SAMP_LEN = 1997;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AP_PL_ODD_SAMP = 1998;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AP_PL_ODD_SAMP_LEN = 1999;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AN_PL_EVEN_SAMP = 2000;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AN_PL_EVEN_SAMP_LEN = 2001;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AN_PL_ODD_SAMP = 2002;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AN_PL_ODD_SAMP_LEN = 2003;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMIN_PL_EVEN = 2004;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMIN_PL_EVEN_LEN = 2005;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMIN_PL_ODD = 2006;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_AMIN_PL_ODD_LEN = 2007;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_EVEN_PL_SAMP1 = 2008;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_EVEN_PL_SAMP1_LEN = 2009;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_EVEN_PL_SAMP0 = 2010;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_EVEN_PL_SAMP0_LEN = 2011;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_ODD_PL_SAMP1 = 2012;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_ODD_PL_SAMP1_LEN = 2013;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_ODD_PL_SAMP0 = 2014;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_H1_ODD_PL_SAMP0_LEN = 2015;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_PRBS_MODE_PL_TAP_ID = 2016;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_PRBS_MODE_PL_TAP_ID_LEN = 2017;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2018;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_DESKEW_STAT_PL_BAD_SKEW = 2019;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_DESKEW_STAT_PL_BAD = 2020;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIR_PL_ERRS = 2021;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIR_PL_ERRS_LEN = 2022;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS = 2023;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 2024;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2025;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2026;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SLS_PL_LANE_SEL = 2027;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SLS_PL_9TH_PATTERN_EN = 2028;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_WT_STATUS_PL_LANE_DISABLED = 2029;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_WT_STATUS_PL_LANE_INVERTED = 2030;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE = 2031;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2032;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SERVO_CNTL_PL_OP_DONE = 2033;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SERVO_CNTL_PL_OP = 2034;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_SERVO_CNTL_PL_OP_LEN = 2035;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ = 2036;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2037;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_TRACE_PL_LN_TRC_EN = 2038;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_EYE_OPT_STAT_PL_BAD_BER = 2039;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2040;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2041;
static const uint64_t IDX_CEN_TXPACKS0_SLICE2_RX_EYE_OPT_STAT_PL_BAD_DDC = 2042;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_MODE_PL_LANE_PDWN = 2043;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2044;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_CNTL_PL_BLOCK_LOCK_LANE = 2045;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_CNTL_PL_CHECK_SKEW_LANE = 2046;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_CNTL_PL_PDWN_LITE = 2047;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_CNTL_PL_OFFCAL_MODE = 2048;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 = 2049;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 = 2050;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_2 = 2051;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_3 = 2052;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_4 = 2053;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_5 = 2054;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 = 2055;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 = 2056;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_BIST_STAT_PL_ERR = 2057;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_EVEN_PL_SAMP1 = 2058;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2059;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_EVEN_PL_SAMP0 = 2060;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2061;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_ODD_PL_SAMP1 = 2062;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_ODD_PL_SAMP1_LEN = 2063;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_ODD_PL_SAMP0 = 2064;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_OFFSET_ODD_PL_SAMP0_LEN = 2065;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMP_VAL_PL_PEAK = 2066;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMP_VAL_PL_PEAK_LEN = 2067;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMP_VAL_PL_GAIN = 2068;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMP_VAL_PL_GAIN_LEN = 2069;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMP_VAL_PL_OFFSET = 2070;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMP_VAL_PL_OFFSET_LEN = 2071;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMP_CNTL_PL_ADJ_DONE = 2072;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2073;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2074;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIFO_STAT_PL_L2U_DLY = 2075;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2076;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AP_PL_EVEN_SAMP = 2077;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AP_PL_EVEN_SAMP_LEN = 2078;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AP_PL_ODD_SAMP = 2079;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AP_PL_ODD_SAMP_LEN = 2080;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AN_PL_EVEN_SAMP = 2081;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AN_PL_EVEN_SAMP_LEN = 2082;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AN_PL_ODD_SAMP = 2083;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AN_PL_ODD_SAMP_LEN = 2084;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMIN_PL_EVEN = 2085;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMIN_PL_EVEN_LEN = 2086;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMIN_PL_ODD = 2087;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_AMIN_PL_ODD_LEN = 2088;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_EVEN_PL_SAMP1 = 2089;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_EVEN_PL_SAMP1_LEN = 2090;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_EVEN_PL_SAMP0 = 2091;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_EVEN_PL_SAMP0_LEN = 2092;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_ODD_PL_SAMP1 = 2093;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_ODD_PL_SAMP1_LEN = 2094;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_ODD_PL_SAMP0 = 2095;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_H1_ODD_PL_SAMP0_LEN = 2096;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_PRBS_MODE_PL_TAP_ID = 2097;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_PRBS_MODE_PL_TAP_ID_LEN = 2098;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2099;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_DESKEW_STAT_PL_BAD_SKEW = 2100;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_DESKEW_STAT_PL_BAD = 2101;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIR_PL_ERRS = 2102;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIR_PL_ERRS_LEN = 2103;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS = 2104;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 2105;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2106;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2107;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SLS_PL_LANE_SEL = 2108;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SLS_PL_9TH_PATTERN_EN = 2109;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_WT_STATUS_PL_LANE_DISABLED = 2110;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_WT_STATUS_PL_LANE_INVERTED = 2111;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE = 2112;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2113;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SERVO_CNTL_PL_OP_DONE = 2114;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SERVO_CNTL_PL_OP = 2115;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_SERVO_CNTL_PL_OP_LEN = 2116;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ = 2117;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2118;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_TRACE_PL_LN_TRC_EN = 2119;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_EYE_OPT_STAT_PL_BAD_BER = 2120;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2121;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2122;
static const uint64_t IDX_CEN_TXPACKS0_SLICE3_RX_EYE_OPT_STAT_PL_BAD_DDC = 2123;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE = 2124;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE_LEN = 2125;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_PRBS_SCRAMBLE_MODE = 2126;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_PRBS_SCRAMBLE_MODE_LEN = 2127;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL = 2128;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL_LEN = 2129;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL = 2130;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL_LEN = 2131;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL = 2132;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL_LEN = 2133;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_ENABLE_DFE_V1 = 2134;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE1_PP_AMIN_ALL = 2135;
static const uint64_t IDX_CEN_TXPACKS1_RX_CNTL_FAST_PP_PRBS_CHECK_SYNC = 2136;
static const uint64_t IDX_CEN_TXPACKS1_RX_CNTL_FAST_PP_ENABLE_REDUCED_SCRAMBLE = 2137;
static const uint64_t IDX_CEN_TXPACKS1_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 2138;
static const uint64_t IDX_CEN_TXPACKS1_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 2139;
static const uint64_t IDX_CEN_TXPACKS1_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 2140;
static const uint64_t IDX_CEN_TXPACKS1_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 2141;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_CNTL_PP_EN = 2142;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_TIMER_FREEZE_EN = 2143;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_COUNT_FREEZE_EN = 2144;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_COUNT_SEL = 2145;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_COUNT_SEL_LEN = 2146;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_TIMER_SEL = 2147;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_TIMER_SEL_LEN = 2148;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_CLR_COUNT_ON_READ_EN = 2149;
static const uint64_t IDX_CEN_TXPACKS1_RX_BER_MODE_PP_CLR_TIMER_ON_READ_EN = 2150;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_A = 2151;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_A_LEN = 2152;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_B = 2153;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_B_LEN = 2154;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_C = 2155;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_C_LEN = 2156;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_D = 2157;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO1_PP_TIMEOUT_SEL_D_LEN = 2158;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_E = 2159;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_E_LEN = 2160;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_F = 2161;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_F_LEN = 2162;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_G = 2163;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_G_LEN = 2164;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_H = 2165;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO2_PP_TIMEOUT_SEL_H_LEN = 2166;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_I = 2167;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_I_LEN = 2168;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_J = 2169;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_J_LEN = 2170;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_K = 2171;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_K_LEN = 2172;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_L = 2173;
static const uint64_t IDX_CEN_TXPACKS1_RX_SERVO_TO3_PP_TIMEOUT_SEL_L_LEN = 2174;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_PEAK_CFG = 2175;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_PEAK_CFG_LEN = 2176;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_AMIN_CFG = 2177;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_AMIN_CFG_LEN = 2178;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_ANAP_CFG = 2179;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_ANAP_CFG_LEN = 2180;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_H1_CFG = 2181;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_H1_CFG_LEN = 2182;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_H1AP_CFG = 2183;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_H1AP_CFG_LEN = 2184;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_CA_CFG = 2185;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_CA_CFG_LEN = 2186;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_SPMUX_CFG = 2187;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_CONFIG_PP_SPMUX_CFG_LEN = 2188;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_INIT_TMR_CFG = 2189;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_INIT_TMR_CFG_LEN = 2190;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_BER_CFG = 2191;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_BER_CFG_LEN = 2192;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_FIFO_DLY_CFG = 2193;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_FIFO_DLY_CFG_LEN = 2194;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_DDC_CFG = 2195;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_DDC_CFG_LEN = 2196;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_DAC_BO_CFG = 2197;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_DAC_BO_CFG_LEN = 2198;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_PROT_CFG = 2199;
static const uint64_t IDX_CEN_TXPACKS1_RX_DFE_TIMERS_PP_PROT_CFG_LEN = 2200;
static const uint64_t IDX_CEN_TXPACKS1_RX_RESET_CFG_PP_HLD = 2201;
static const uint64_t IDX_CEN_TXPACKS1_RX_RESET_CFG_PP_HLD_LEN = 2202;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO1_PP_TIMEOUT_SEL_A = 2203;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO1_PP_TIMEOUT_SEL_A_LEN = 2204;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO1_PP_TIMEOUT_SEL_B = 2205;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO1_PP_TIMEOUT_SEL_B_LEN = 2206;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO2_PP_TIMEOUT_SEL_E = 2207;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO2_PP_TIMEOUT_SEL_E_LEN = 2208;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO2_PP_TIMEOUT_SEL_G = 2209;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO2_PP_TIMEOUT_SEL_G_LEN = 2210;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO2_PP_TIMEOUT_SEL_H = 2211;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO2_PP_TIMEOUT_SEL_H_LEN = 2212;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_I = 2213;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_I_LEN = 2214;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_J = 2215;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_J_LEN = 2216;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_K = 2217;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_K_LEN = 2218;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_L = 2219;
static const uint64_t IDX_CEN_TXPACKS1_RX_RECAL_TO3_PP_TIMEOUT_SEL_L_LEN = 2220;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_PP_TRC_EN = 2221;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_PP_TRC_MODE = 2222;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_PP_TRC_MODE_LEN = 2223;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_BIST_JITTER_PULSE_SEL = 2224;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_BIST_JITTER_PULSE_SEL_LEN = 2225;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_BIST_MIN_EYE_WIDTH = 2226;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_BIST_MIN_EYE_WIDTH_LEN = 2227;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_WT_PATTERN_LENGTH = 2228;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE2_PP_WT_PATTERN_LENGTH_LEN = 2229;
static const uint64_t IDX_CEN_TXPACKS1_RX_BIST_GCRMSG_PP_EN = 2230;
static const uint64_t IDX_CEN_TXPACKS1_RX_SCOPE_CNTL_PP_CONTROL = 2231;
static const uint64_t IDX_CEN_TXPACKS1_RX_SCOPE_CNTL_PP_CONTROL_LEN = 2232;
static const uint64_t IDX_CEN_TXPACKS1_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG = 2233;
static const uint64_t IDX_CEN_TXPACKS1_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG_LEN = 2234;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_STEP_INTERVAL_EN = 2235;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_STEP_INTERVAL = 2236;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_STEP_INTERVAL_LEN = 2237;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_PHASEROT_OFFSET_EN = 2238;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_PHASEROT_OFFSET = 2239;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_PHASEROT_OFFSET_LEN = 2240;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_BUFFER_SEL = 2241;
static const uint64_t IDX_CEN_TXPACKS1_RX_MODE3_PP_BIST_BUFFER_SEL_LEN = 2242;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_MODE_PL_LANE_PDWN = 2243;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2244;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_CNTL_PL_BLOCK_LOCK_LANE = 2245;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_CNTL_PL_CHECK_SKEW_LANE = 2246;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_CNTL_PL_PDWN_LITE = 2247;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_CNTL_PL_OFFCAL_MODE = 2248;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 = 2249;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 = 2250;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_2 = 2251;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_3 = 2252;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_4 = 2253;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_5 = 2254;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 = 2255;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 = 2256;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_BIST_STAT_PL_ERR = 2257;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_EVEN_PL_SAMP1 = 2258;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2259;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_EVEN_PL_SAMP0 = 2260;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2261;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_ODD_PL_SAMP1 = 2262;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_ODD_PL_SAMP1_LEN = 2263;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_ODD_PL_SAMP0 = 2264;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_OFFSET_ODD_PL_SAMP0_LEN = 2265;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMP_VAL_PL_PEAK = 2266;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMP_VAL_PL_PEAK_LEN = 2267;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMP_VAL_PL_GAIN = 2268;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMP_VAL_PL_GAIN_LEN = 2269;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMP_VAL_PL_OFFSET = 2270;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMP_VAL_PL_OFFSET_LEN = 2271;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMP_CNTL_PL_ADJ_DONE = 2272;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2273;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2274;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIFO_STAT_PL_L2U_DLY = 2275;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2276;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AP_PL_EVEN_SAMP = 2277;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AP_PL_EVEN_SAMP_LEN = 2278;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AP_PL_ODD_SAMP = 2279;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AP_PL_ODD_SAMP_LEN = 2280;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AN_PL_EVEN_SAMP = 2281;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AN_PL_EVEN_SAMP_LEN = 2282;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AN_PL_ODD_SAMP = 2283;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AN_PL_ODD_SAMP_LEN = 2284;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMIN_PL_EVEN = 2285;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMIN_PL_EVEN_LEN = 2286;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMIN_PL_ODD = 2287;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_AMIN_PL_ODD_LEN = 2288;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_EVEN_PL_SAMP1 = 2289;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_EVEN_PL_SAMP1_LEN = 2290;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_EVEN_PL_SAMP0 = 2291;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_EVEN_PL_SAMP0_LEN = 2292;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_ODD_PL_SAMP1 = 2293;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_ODD_PL_SAMP1_LEN = 2294;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_ODD_PL_SAMP0 = 2295;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_H1_ODD_PL_SAMP0_LEN = 2296;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_PRBS_MODE_PL_TAP_ID = 2297;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_PRBS_MODE_PL_TAP_ID_LEN = 2298;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2299;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_DESKEW_STAT_PL_BAD_SKEW = 2300;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_DESKEW_STAT_PL_BAD = 2301;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIR_PL_ERRS = 2302;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIR_PL_ERRS_LEN = 2303;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS = 2304;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 2305;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2306;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2307;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SLS_PL_LANE_SEL = 2308;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SLS_PL_9TH_PATTERN_EN = 2309;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_WT_STATUS_PL_LANE_DISABLED = 2310;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_WT_STATUS_PL_LANE_INVERTED = 2311;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE = 2312;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2313;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SERVO_CNTL_PL_OP_DONE = 2314;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SERVO_CNTL_PL_OP = 2315;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_SERVO_CNTL_PL_OP_LEN = 2316;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ = 2317;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2318;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_TRACE_PL_LN_TRC_EN = 2319;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_EYE_OPT_STAT_PL_BAD_BER = 2320;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2321;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2322;
static const uint64_t IDX_CEN_TXPACKS1_SLICE0_RX_EYE_OPT_STAT_PL_BAD_DDC = 2323;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_MODE_PL_LANE_PDWN = 2324;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2325;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_CNTL_PL_BLOCK_LOCK_LANE = 2326;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_CNTL_PL_CHECK_SKEW_LANE = 2327;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_CNTL_PL_PDWN_LITE = 2328;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_CNTL_PL_OFFCAL_MODE = 2329;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 = 2330;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 = 2331;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_2 = 2332;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_3 = 2333;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_4 = 2334;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_5 = 2335;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 = 2336;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 = 2337;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_BIST_STAT_PL_ERR = 2338;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_EVEN_PL_SAMP1 = 2339;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2340;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_EVEN_PL_SAMP0 = 2341;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2342;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_ODD_PL_SAMP1 = 2343;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_ODD_PL_SAMP1_LEN = 2344;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_ODD_PL_SAMP0 = 2345;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_OFFSET_ODD_PL_SAMP0_LEN = 2346;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMP_VAL_PL_PEAK = 2347;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMP_VAL_PL_PEAK_LEN = 2348;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMP_VAL_PL_GAIN = 2349;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMP_VAL_PL_GAIN_LEN = 2350;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMP_VAL_PL_OFFSET = 2351;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMP_VAL_PL_OFFSET_LEN = 2352;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMP_CNTL_PL_ADJ_DONE = 2353;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2354;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2355;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIFO_STAT_PL_L2U_DLY = 2356;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2357;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AP_PL_EVEN_SAMP = 2358;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AP_PL_EVEN_SAMP_LEN = 2359;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AP_PL_ODD_SAMP = 2360;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AP_PL_ODD_SAMP_LEN = 2361;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AN_PL_EVEN_SAMP = 2362;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AN_PL_EVEN_SAMP_LEN = 2363;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AN_PL_ODD_SAMP = 2364;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AN_PL_ODD_SAMP_LEN = 2365;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMIN_PL_EVEN = 2366;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMIN_PL_EVEN_LEN = 2367;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMIN_PL_ODD = 2368;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_AMIN_PL_ODD_LEN = 2369;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_EVEN_PL_SAMP1 = 2370;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_EVEN_PL_SAMP1_LEN = 2371;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_EVEN_PL_SAMP0 = 2372;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_EVEN_PL_SAMP0_LEN = 2373;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_ODD_PL_SAMP1 = 2374;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_ODD_PL_SAMP1_LEN = 2375;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_ODD_PL_SAMP0 = 2376;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_H1_ODD_PL_SAMP0_LEN = 2377;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_PRBS_MODE_PL_TAP_ID = 2378;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_PRBS_MODE_PL_TAP_ID_LEN = 2379;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2380;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_DESKEW_STAT_PL_BAD_SKEW = 2381;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_DESKEW_STAT_PL_BAD = 2382;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIR_PL_ERRS = 2383;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIR_PL_ERRS_LEN = 2384;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS = 2385;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 2386;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2387;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2388;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SLS_PL_LANE_SEL = 2389;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SLS_PL_9TH_PATTERN_EN = 2390;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_WT_STATUS_PL_LANE_DISABLED = 2391;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_WT_STATUS_PL_LANE_INVERTED = 2392;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE = 2393;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2394;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SERVO_CNTL_PL_OP_DONE = 2395;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SERVO_CNTL_PL_OP = 2396;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_SERVO_CNTL_PL_OP_LEN = 2397;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ = 2398;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2399;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_TRACE_PL_LN_TRC_EN = 2400;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_EYE_OPT_STAT_PL_BAD_BER = 2401;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2402;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2403;
static const uint64_t IDX_CEN_TXPACKS1_SLICE1_RX_EYE_OPT_STAT_PL_BAD_DDC = 2404;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_MODE_PL_LANE_PDWN = 2405;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2406;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_CNTL_PL_BLOCK_LOCK_LANE = 2407;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_CNTL_PL_CHECK_SKEW_LANE = 2408;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_CNTL_PL_PDWN_LITE = 2409;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_CNTL_PL_OFFCAL_MODE = 2410;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 = 2411;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 = 2412;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_2 = 2413;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_3 = 2414;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_4 = 2415;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_5 = 2416;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 = 2417;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 = 2418;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_BIST_STAT_PL_ERR = 2419;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_EVEN_PL_SAMP1 = 2420;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2421;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_EVEN_PL_SAMP0 = 2422;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2423;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_ODD_PL_SAMP1 = 2424;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_ODD_PL_SAMP1_LEN = 2425;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_ODD_PL_SAMP0 = 2426;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_OFFSET_ODD_PL_SAMP0_LEN = 2427;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMP_VAL_PL_PEAK = 2428;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMP_VAL_PL_PEAK_LEN = 2429;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMP_VAL_PL_GAIN = 2430;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMP_VAL_PL_GAIN_LEN = 2431;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMP_VAL_PL_OFFSET = 2432;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMP_VAL_PL_OFFSET_LEN = 2433;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMP_CNTL_PL_ADJ_DONE = 2434;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2435;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2436;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIFO_STAT_PL_L2U_DLY = 2437;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2438;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AP_PL_EVEN_SAMP = 2439;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AP_PL_EVEN_SAMP_LEN = 2440;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AP_PL_ODD_SAMP = 2441;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AP_PL_ODD_SAMP_LEN = 2442;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AN_PL_EVEN_SAMP = 2443;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AN_PL_EVEN_SAMP_LEN = 2444;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AN_PL_ODD_SAMP = 2445;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AN_PL_ODD_SAMP_LEN = 2446;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMIN_PL_EVEN = 2447;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMIN_PL_EVEN_LEN = 2448;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMIN_PL_ODD = 2449;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_AMIN_PL_ODD_LEN = 2450;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_EVEN_PL_SAMP1 = 2451;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_EVEN_PL_SAMP1_LEN = 2452;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_EVEN_PL_SAMP0 = 2453;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_EVEN_PL_SAMP0_LEN = 2454;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_ODD_PL_SAMP1 = 2455;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_ODD_PL_SAMP1_LEN = 2456;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_ODD_PL_SAMP0 = 2457;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_H1_ODD_PL_SAMP0_LEN = 2458;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_PRBS_MODE_PL_TAP_ID = 2459;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_PRBS_MODE_PL_TAP_ID_LEN = 2460;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2461;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_DESKEW_STAT_PL_BAD_SKEW = 2462;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_DESKEW_STAT_PL_BAD = 2463;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIR_PL_ERRS = 2464;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIR_PL_ERRS_LEN = 2465;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS = 2466;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 2467;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2468;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2469;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SLS_PL_LANE_SEL = 2470;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SLS_PL_9TH_PATTERN_EN = 2471;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_WT_STATUS_PL_LANE_DISABLED = 2472;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_WT_STATUS_PL_LANE_INVERTED = 2473;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE = 2474;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2475;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SERVO_CNTL_PL_OP_DONE = 2476;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SERVO_CNTL_PL_OP = 2477;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_SERVO_CNTL_PL_OP_LEN = 2478;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ = 2479;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2480;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_TRACE_PL_LN_TRC_EN = 2481;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_EYE_OPT_STAT_PL_BAD_BER = 2482;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2483;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2484;
static const uint64_t IDX_CEN_TXPACKS1_SLICE2_RX_EYE_OPT_STAT_PL_BAD_DDC = 2485;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_MODE_PL_LANE_PDWN = 2486;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2487;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_CNTL_PL_BLOCK_LOCK_LANE = 2488;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_CNTL_PL_CHECK_SKEW_LANE = 2489;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_CNTL_PL_PDWN_LITE = 2490;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_CNTL_PL_OFFCAL_MODE = 2491;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 = 2492;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 = 2493;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_2 = 2494;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_3 = 2495;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_4 = 2496;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_5 = 2497;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 = 2498;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 = 2499;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_BIST_STAT_PL_ERR = 2500;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_EVEN_PL_SAMP1 = 2501;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2502;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_EVEN_PL_SAMP0 = 2503;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2504;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_ODD_PL_SAMP1 = 2505;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_ODD_PL_SAMP1_LEN = 2506;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_ODD_PL_SAMP0 = 2507;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_OFFSET_ODD_PL_SAMP0_LEN = 2508;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMP_VAL_PL_PEAK = 2509;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMP_VAL_PL_PEAK_LEN = 2510;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMP_VAL_PL_GAIN = 2511;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMP_VAL_PL_GAIN_LEN = 2512;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMP_VAL_PL_OFFSET = 2513;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMP_VAL_PL_OFFSET_LEN = 2514;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMP_CNTL_PL_ADJ_DONE = 2515;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2516;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2517;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIFO_STAT_PL_L2U_DLY = 2518;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2519;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AP_PL_EVEN_SAMP = 2520;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AP_PL_EVEN_SAMP_LEN = 2521;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AP_PL_ODD_SAMP = 2522;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AP_PL_ODD_SAMP_LEN = 2523;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AN_PL_EVEN_SAMP = 2524;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AN_PL_EVEN_SAMP_LEN = 2525;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AN_PL_ODD_SAMP = 2526;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AN_PL_ODD_SAMP_LEN = 2527;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMIN_PL_EVEN = 2528;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMIN_PL_EVEN_LEN = 2529;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMIN_PL_ODD = 2530;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_AMIN_PL_ODD_LEN = 2531;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_EVEN_PL_SAMP1 = 2532;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_EVEN_PL_SAMP1_LEN = 2533;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_EVEN_PL_SAMP0 = 2534;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_EVEN_PL_SAMP0_LEN = 2535;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_ODD_PL_SAMP1 = 2536;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_ODD_PL_SAMP1_LEN = 2537;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_ODD_PL_SAMP0 = 2538;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_H1_ODD_PL_SAMP0_LEN = 2539;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_PRBS_MODE_PL_TAP_ID = 2540;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_PRBS_MODE_PL_TAP_ID_LEN = 2541;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2542;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_DESKEW_STAT_PL_BAD_SKEW = 2543;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_DESKEW_STAT_PL_BAD = 2544;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIR_PL_ERRS = 2545;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIR_PL_ERRS_LEN = 2546;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS = 2547;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 2548;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2549;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2550;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SLS_PL_LANE_SEL = 2551;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SLS_PL_9TH_PATTERN_EN = 2552;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_WT_STATUS_PL_LANE_DISABLED = 2553;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_WT_STATUS_PL_LANE_INVERTED = 2554;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE = 2555;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2556;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SERVO_CNTL_PL_OP_DONE = 2557;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SERVO_CNTL_PL_OP = 2558;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_SERVO_CNTL_PL_OP_LEN = 2559;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ = 2560;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2561;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_TRACE_PL_LN_TRC_EN = 2562;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_EYE_OPT_STAT_PL_BAD_BER = 2563;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2564;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2565;
static const uint64_t IDX_CEN_TXPACKS1_SLICE3_RX_EYE_OPT_STAT_PL_BAD_DDC = 2566;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE = 2567;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE_LEN = 2568;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_PRBS_SCRAMBLE_MODE = 2569;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_PRBS_SCRAMBLE_MODE_LEN = 2570;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL = 2571;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL_LEN = 2572;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL = 2573;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL_LEN = 2574;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL = 2575;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL_LEN = 2576;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_ENABLE_DFE_V1 = 2577;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE1_PP_AMIN_ALL = 2578;
static const uint64_t IDX_CEN_TXPACKS2_RX_CNTL_FAST_PP_PRBS_CHECK_SYNC = 2579;
static const uint64_t IDX_CEN_TXPACKS2_RX_CNTL_FAST_PP_ENABLE_REDUCED_SCRAMBLE = 2580;
static const uint64_t IDX_CEN_TXPACKS2_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 2581;
static const uint64_t IDX_CEN_TXPACKS2_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 2582;
static const uint64_t IDX_CEN_TXPACKS2_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 2583;
static const uint64_t IDX_CEN_TXPACKS2_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 2584;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_CNTL_PP_EN = 2585;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_TIMER_FREEZE_EN = 2586;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_COUNT_FREEZE_EN = 2587;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_COUNT_SEL = 2588;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_COUNT_SEL_LEN = 2589;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_TIMER_SEL = 2590;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_TIMER_SEL_LEN = 2591;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_CLR_COUNT_ON_READ_EN = 2592;
static const uint64_t IDX_CEN_TXPACKS2_RX_BER_MODE_PP_CLR_TIMER_ON_READ_EN = 2593;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_A = 2594;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_A_LEN = 2595;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_B = 2596;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_B_LEN = 2597;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_C = 2598;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_C_LEN = 2599;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_D = 2600;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO1_PP_TIMEOUT_SEL_D_LEN = 2601;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_E = 2602;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_E_LEN = 2603;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_F = 2604;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_F_LEN = 2605;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_G = 2606;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_G_LEN = 2607;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_H = 2608;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO2_PP_TIMEOUT_SEL_H_LEN = 2609;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_I = 2610;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_I_LEN = 2611;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_J = 2612;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_J_LEN = 2613;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_K = 2614;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_K_LEN = 2615;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_L = 2616;
static const uint64_t IDX_CEN_TXPACKS2_RX_SERVO_TO3_PP_TIMEOUT_SEL_L_LEN = 2617;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_PEAK_CFG = 2618;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_PEAK_CFG_LEN = 2619;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_AMIN_CFG = 2620;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_AMIN_CFG_LEN = 2621;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_ANAP_CFG = 2622;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_ANAP_CFG_LEN = 2623;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_H1_CFG = 2624;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_H1_CFG_LEN = 2625;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_H1AP_CFG = 2626;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_H1AP_CFG_LEN = 2627;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_CA_CFG = 2628;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_CA_CFG_LEN = 2629;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_SPMUX_CFG = 2630;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_CONFIG_PP_SPMUX_CFG_LEN = 2631;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_INIT_TMR_CFG = 2632;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_INIT_TMR_CFG_LEN = 2633;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_BER_CFG = 2634;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_BER_CFG_LEN = 2635;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_FIFO_DLY_CFG = 2636;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_FIFO_DLY_CFG_LEN = 2637;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_DDC_CFG = 2638;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_DDC_CFG_LEN = 2639;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_DAC_BO_CFG = 2640;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_DAC_BO_CFG_LEN = 2641;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_PROT_CFG = 2642;
static const uint64_t IDX_CEN_TXPACKS2_RX_DFE_TIMERS_PP_PROT_CFG_LEN = 2643;
static const uint64_t IDX_CEN_TXPACKS2_RX_RESET_CFG_PP_HLD = 2644;
static const uint64_t IDX_CEN_TXPACKS2_RX_RESET_CFG_PP_HLD_LEN = 2645;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO1_PP_TIMEOUT_SEL_A = 2646;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO1_PP_TIMEOUT_SEL_A_LEN = 2647;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO1_PP_TIMEOUT_SEL_B = 2648;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO1_PP_TIMEOUT_SEL_B_LEN = 2649;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO2_PP_TIMEOUT_SEL_E = 2650;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO2_PP_TIMEOUT_SEL_E_LEN = 2651;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO2_PP_TIMEOUT_SEL_G = 2652;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO2_PP_TIMEOUT_SEL_G_LEN = 2653;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO2_PP_TIMEOUT_SEL_H = 2654;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO2_PP_TIMEOUT_SEL_H_LEN = 2655;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_I = 2656;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_I_LEN = 2657;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_J = 2658;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_J_LEN = 2659;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_K = 2660;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_K_LEN = 2661;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_L = 2662;
static const uint64_t IDX_CEN_TXPACKS2_RX_RECAL_TO3_PP_TIMEOUT_SEL_L_LEN = 2663;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_PP_TRC_EN = 2664;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_PP_TRC_MODE = 2665;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_PP_TRC_MODE_LEN = 2666;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_BIST_JITTER_PULSE_SEL = 2667;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_BIST_JITTER_PULSE_SEL_LEN = 2668;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_BIST_MIN_EYE_WIDTH = 2669;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_BIST_MIN_EYE_WIDTH_LEN = 2670;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_WT_PATTERN_LENGTH = 2671;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE2_PP_WT_PATTERN_LENGTH_LEN = 2672;
static const uint64_t IDX_CEN_TXPACKS2_RX_BIST_GCRMSG_PP_EN = 2673;
static const uint64_t IDX_CEN_TXPACKS2_RX_SCOPE_CNTL_PP_CONTROL = 2674;
static const uint64_t IDX_CEN_TXPACKS2_RX_SCOPE_CNTL_PP_CONTROL_LEN = 2675;
static const uint64_t IDX_CEN_TXPACKS2_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG = 2676;
static const uint64_t IDX_CEN_TXPACKS2_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG_LEN = 2677;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_STEP_INTERVAL_EN = 2678;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_STEP_INTERVAL = 2679;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_STEP_INTERVAL_LEN = 2680;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_PHASEROT_OFFSET_EN = 2681;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_PHASEROT_OFFSET = 2682;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_PHASEROT_OFFSET_LEN = 2683;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_BUFFER_SEL = 2684;
static const uint64_t IDX_CEN_TXPACKS2_RX_MODE3_PP_BIST_BUFFER_SEL_LEN = 2685;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_MODE_PL_LANE_PDWN = 2686;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2687;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_CNTL_PL_BLOCK_LOCK_LANE = 2688;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_CNTL_PL_CHECK_SKEW_LANE = 2689;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_CNTL_PL_PDWN_LITE = 2690;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_CNTL_PL_OFFCAL_MODE = 2691;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 = 2692;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 = 2693;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_2 = 2694;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_3 = 2695;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_4 = 2696;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_5 = 2697;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 = 2698;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 = 2699;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_BIST_STAT_PL_ERR = 2700;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_EVEN_PL_SAMP1 = 2701;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2702;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_EVEN_PL_SAMP0 = 2703;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2704;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_ODD_PL_SAMP1 = 2705;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_ODD_PL_SAMP1_LEN = 2706;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_ODD_PL_SAMP0 = 2707;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_OFFSET_ODD_PL_SAMP0_LEN = 2708;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMP_VAL_PL_PEAK = 2709;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMP_VAL_PL_PEAK_LEN = 2710;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMP_VAL_PL_GAIN = 2711;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMP_VAL_PL_GAIN_LEN = 2712;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMP_VAL_PL_OFFSET = 2713;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMP_VAL_PL_OFFSET_LEN = 2714;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMP_CNTL_PL_ADJ_DONE = 2715;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2716;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2717;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIFO_STAT_PL_L2U_DLY = 2718;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2719;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AP_PL_EVEN_SAMP = 2720;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AP_PL_EVEN_SAMP_LEN = 2721;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AP_PL_ODD_SAMP = 2722;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AP_PL_ODD_SAMP_LEN = 2723;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AN_PL_EVEN_SAMP = 2724;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AN_PL_EVEN_SAMP_LEN = 2725;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AN_PL_ODD_SAMP = 2726;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AN_PL_ODD_SAMP_LEN = 2727;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMIN_PL_EVEN = 2728;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMIN_PL_EVEN_LEN = 2729;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMIN_PL_ODD = 2730;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_AMIN_PL_ODD_LEN = 2731;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_EVEN_PL_SAMP1 = 2732;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_EVEN_PL_SAMP1_LEN = 2733;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_EVEN_PL_SAMP0 = 2734;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_EVEN_PL_SAMP0_LEN = 2735;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_ODD_PL_SAMP1 = 2736;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_ODD_PL_SAMP1_LEN = 2737;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_ODD_PL_SAMP0 = 2738;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_H1_ODD_PL_SAMP0_LEN = 2739;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_PRBS_MODE_PL_TAP_ID = 2740;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_PRBS_MODE_PL_TAP_ID_LEN = 2741;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2742;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_DESKEW_STAT_PL_BAD_SKEW = 2743;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_DESKEW_STAT_PL_BAD = 2744;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIR_PL_ERRS = 2745;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIR_PL_ERRS_LEN = 2746;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS = 2747;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 2748;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2749;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2750;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SLS_PL_LANE_SEL = 2751;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SLS_PL_9TH_PATTERN_EN = 2752;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_WT_STATUS_PL_LANE_DISABLED = 2753;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_WT_STATUS_PL_LANE_INVERTED = 2754;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE = 2755;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2756;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SERVO_CNTL_PL_OP_DONE = 2757;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SERVO_CNTL_PL_OP = 2758;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_SERVO_CNTL_PL_OP_LEN = 2759;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ = 2760;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2761;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_TRACE_PL_LN_TRC_EN = 2762;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_EYE_OPT_STAT_PL_BAD_BER = 2763;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2764;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2765;
static const uint64_t IDX_CEN_TXPACKS2_SLICE0_RX_EYE_OPT_STAT_PL_BAD_DDC = 2766;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_MODE_PL_LANE_PDWN = 2767;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2768;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_CNTL_PL_BLOCK_LOCK_LANE = 2769;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_CNTL_PL_CHECK_SKEW_LANE = 2770;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_CNTL_PL_PDWN_LITE = 2771;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_CNTL_PL_OFFCAL_MODE = 2772;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 = 2773;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 = 2774;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_2 = 2775;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_3 = 2776;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_4 = 2777;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_5 = 2778;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 = 2779;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 = 2780;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_BIST_STAT_PL_ERR = 2781;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_EVEN_PL_SAMP1 = 2782;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2783;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_EVEN_PL_SAMP0 = 2784;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2785;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_ODD_PL_SAMP1 = 2786;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_ODD_PL_SAMP1_LEN = 2787;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_ODD_PL_SAMP0 = 2788;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_OFFSET_ODD_PL_SAMP0_LEN = 2789;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMP_VAL_PL_PEAK = 2790;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMP_VAL_PL_PEAK_LEN = 2791;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMP_VAL_PL_GAIN = 2792;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMP_VAL_PL_GAIN_LEN = 2793;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMP_VAL_PL_OFFSET = 2794;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMP_VAL_PL_OFFSET_LEN = 2795;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMP_CNTL_PL_ADJ_DONE = 2796;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2797;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2798;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIFO_STAT_PL_L2U_DLY = 2799;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2800;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AP_PL_EVEN_SAMP = 2801;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AP_PL_EVEN_SAMP_LEN = 2802;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AP_PL_ODD_SAMP = 2803;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AP_PL_ODD_SAMP_LEN = 2804;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AN_PL_EVEN_SAMP = 2805;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AN_PL_EVEN_SAMP_LEN = 2806;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AN_PL_ODD_SAMP = 2807;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AN_PL_ODD_SAMP_LEN = 2808;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMIN_PL_EVEN = 2809;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMIN_PL_EVEN_LEN = 2810;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMIN_PL_ODD = 2811;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_AMIN_PL_ODD_LEN = 2812;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_EVEN_PL_SAMP1 = 2813;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_EVEN_PL_SAMP1_LEN = 2814;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_EVEN_PL_SAMP0 = 2815;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_EVEN_PL_SAMP0_LEN = 2816;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_ODD_PL_SAMP1 = 2817;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_ODD_PL_SAMP1_LEN = 2818;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_ODD_PL_SAMP0 = 2819;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_H1_ODD_PL_SAMP0_LEN = 2820;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_PRBS_MODE_PL_TAP_ID = 2821;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_PRBS_MODE_PL_TAP_ID_LEN = 2822;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2823;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_DESKEW_STAT_PL_BAD_SKEW = 2824;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_DESKEW_STAT_PL_BAD = 2825;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIR_PL_ERRS = 2826;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIR_PL_ERRS_LEN = 2827;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS = 2828;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 2829;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2830;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2831;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SLS_PL_LANE_SEL = 2832;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SLS_PL_9TH_PATTERN_EN = 2833;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_WT_STATUS_PL_LANE_DISABLED = 2834;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_WT_STATUS_PL_LANE_INVERTED = 2835;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE = 2836;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2837;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SERVO_CNTL_PL_OP_DONE = 2838;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SERVO_CNTL_PL_OP = 2839;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_SERVO_CNTL_PL_OP_LEN = 2840;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ = 2841;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2842;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_TRACE_PL_LN_TRC_EN = 2843;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_EYE_OPT_STAT_PL_BAD_BER = 2844;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2845;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2846;
static const uint64_t IDX_CEN_TXPACKS2_SLICE1_RX_EYE_OPT_STAT_PL_BAD_DDC = 2847;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_MODE_PL_LANE_PDWN = 2848;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2849;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_CNTL_PL_BLOCK_LOCK_LANE = 2850;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_CNTL_PL_CHECK_SKEW_LANE = 2851;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_CNTL_PL_PDWN_LITE = 2852;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_CNTL_PL_OFFCAL_MODE = 2853;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 = 2854;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 = 2855;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_2 = 2856;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_3 = 2857;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_4 = 2858;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_5 = 2859;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 = 2860;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 = 2861;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_BIST_STAT_PL_ERR = 2862;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_EVEN_PL_SAMP1 = 2863;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2864;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_EVEN_PL_SAMP0 = 2865;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2866;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_ODD_PL_SAMP1 = 2867;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_ODD_PL_SAMP1_LEN = 2868;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_ODD_PL_SAMP0 = 2869;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_OFFSET_ODD_PL_SAMP0_LEN = 2870;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMP_VAL_PL_PEAK = 2871;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMP_VAL_PL_PEAK_LEN = 2872;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMP_VAL_PL_GAIN = 2873;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMP_VAL_PL_GAIN_LEN = 2874;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMP_VAL_PL_OFFSET = 2875;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMP_VAL_PL_OFFSET_LEN = 2876;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMP_CNTL_PL_ADJ_DONE = 2877;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2878;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2879;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIFO_STAT_PL_L2U_DLY = 2880;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2881;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AP_PL_EVEN_SAMP = 2882;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AP_PL_EVEN_SAMP_LEN = 2883;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AP_PL_ODD_SAMP = 2884;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AP_PL_ODD_SAMP_LEN = 2885;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AN_PL_EVEN_SAMP = 2886;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AN_PL_EVEN_SAMP_LEN = 2887;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AN_PL_ODD_SAMP = 2888;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AN_PL_ODD_SAMP_LEN = 2889;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMIN_PL_EVEN = 2890;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMIN_PL_EVEN_LEN = 2891;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMIN_PL_ODD = 2892;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_AMIN_PL_ODD_LEN = 2893;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_EVEN_PL_SAMP1 = 2894;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_EVEN_PL_SAMP1_LEN = 2895;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_EVEN_PL_SAMP0 = 2896;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_EVEN_PL_SAMP0_LEN = 2897;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_ODD_PL_SAMP1 = 2898;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_ODD_PL_SAMP1_LEN = 2899;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_ODD_PL_SAMP0 = 2900;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_H1_ODD_PL_SAMP0_LEN = 2901;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_PRBS_MODE_PL_TAP_ID = 2902;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_PRBS_MODE_PL_TAP_ID_LEN = 2903;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2904;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_DESKEW_STAT_PL_BAD_SKEW = 2905;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_DESKEW_STAT_PL_BAD = 2906;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIR_PL_ERRS = 2907;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIR_PL_ERRS_LEN = 2908;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS = 2909;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 2910;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2911;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2912;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SLS_PL_LANE_SEL = 2913;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SLS_PL_9TH_PATTERN_EN = 2914;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_WT_STATUS_PL_LANE_DISABLED = 2915;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_WT_STATUS_PL_LANE_INVERTED = 2916;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE = 2917;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2918;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SERVO_CNTL_PL_OP_DONE = 2919;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SERVO_CNTL_PL_OP = 2920;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_SERVO_CNTL_PL_OP_LEN = 2921;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ = 2922;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 2923;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_TRACE_PL_LN_TRC_EN = 2924;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_EYE_OPT_STAT_PL_BAD_BER = 2925;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 2926;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 2927;
static const uint64_t IDX_CEN_TXPACKS2_SLICE2_RX_EYE_OPT_STAT_PL_BAD_DDC = 2928;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_MODE_PL_LANE_PDWN = 2929;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 2930;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_CNTL_PL_BLOCK_LOCK_LANE = 2931;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_CNTL_PL_CHECK_SKEW_LANE = 2932;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_CNTL_PL_PDWN_LITE = 2933;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_CNTL_PL_OFFCAL_MODE = 2934;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 = 2935;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 = 2936;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_2 = 2937;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_3 = 2938;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_4 = 2939;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_5 = 2940;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 = 2941;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 = 2942;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_BIST_STAT_PL_ERR = 2943;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_EVEN_PL_SAMP1 = 2944;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_EVEN_PL_SAMP1_LEN = 2945;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_EVEN_PL_SAMP0 = 2946;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_EVEN_PL_SAMP0_LEN = 2947;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_ODD_PL_SAMP1 = 2948;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_ODD_PL_SAMP1_LEN = 2949;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_ODD_PL_SAMP0 = 2950;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_OFFSET_ODD_PL_SAMP0_LEN = 2951;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMP_VAL_PL_PEAK = 2952;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMP_VAL_PL_PEAK_LEN = 2953;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMP_VAL_PL_GAIN = 2954;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMP_VAL_PL_GAIN_LEN = 2955;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMP_VAL_PL_OFFSET = 2956;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMP_VAL_PL_OFFSET_LEN = 2957;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMP_CNTL_PL_ADJ_DONE = 2958;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET = 2959;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 2960;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIFO_STAT_PL_L2U_DLY = 2961;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIFO_STAT_PL_L2U_DLY_LEN = 2962;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AP_PL_EVEN_SAMP = 2963;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AP_PL_EVEN_SAMP_LEN = 2964;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AP_PL_ODD_SAMP = 2965;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AP_PL_ODD_SAMP_LEN = 2966;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AN_PL_EVEN_SAMP = 2967;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AN_PL_EVEN_SAMP_LEN = 2968;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AN_PL_ODD_SAMP = 2969;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AN_PL_ODD_SAMP_LEN = 2970;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMIN_PL_EVEN = 2971;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMIN_PL_EVEN_LEN = 2972;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMIN_PL_ODD = 2973;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_AMIN_PL_ODD_LEN = 2974;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_EVEN_PL_SAMP1 = 2975;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_EVEN_PL_SAMP1_LEN = 2976;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_EVEN_PL_SAMP0 = 2977;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_EVEN_PL_SAMP0_LEN = 2978;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_ODD_PL_SAMP1 = 2979;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_ODD_PL_SAMP1_LEN = 2980;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_ODD_PL_SAMP0 = 2981;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_H1_ODD_PL_SAMP0_LEN = 2982;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_PRBS_MODE_PL_TAP_ID = 2983;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_PRBS_MODE_PL_TAP_ID_LEN = 2984;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 2985;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_DESKEW_STAT_PL_BAD_SKEW = 2986;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_DESKEW_STAT_PL_BAD = 2987;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIR_PL_ERRS = 2988;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIR_PL_ERRS_LEN = 2989;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS = 2990;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 2991;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 2992;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 2993;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SLS_PL_LANE_SEL = 2994;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SLS_PL_9TH_PATTERN_EN = 2995;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_WT_STATUS_PL_LANE_DISABLED = 2996;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_WT_STATUS_PL_LANE_INVERTED = 2997;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE = 2998;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 2999;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SERVO_CNTL_PL_OP_DONE = 3000;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SERVO_CNTL_PL_OP = 3001;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_SERVO_CNTL_PL_OP_LEN = 3002;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ = 3003;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 3004;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_TRACE_PL_LN_TRC_EN = 3005;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_EYE_OPT_STAT_PL_BAD_BER = 3006;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 3007;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 3008;
static const uint64_t IDX_CEN_TXPACKS2_SLICE3_RX_EYE_OPT_STAT_PL_BAD_DDC = 3009;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE = 3010;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE_LEN = 3011;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_PRBS_SCRAMBLE_MODE = 3012;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_PRBS_SCRAMBLE_MODE_LEN = 3013;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL = 3014;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL_LEN = 3015;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL = 3016;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL_LEN = 3017;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL = 3018;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL_LEN = 3019;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_ENABLE_DFE_V1 = 3020;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE1_PP_AMIN_ALL = 3021;
static const uint64_t IDX_CEN_TXPACKS3_RX_CNTL_FAST_PP_PRBS_CHECK_SYNC = 3022;
static const uint64_t IDX_CEN_TXPACKS3_RX_CNTL_FAST_PP_ENABLE_REDUCED_SCRAMBLE = 3023;
static const uint64_t IDX_CEN_TXPACKS3_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 3024;
static const uint64_t IDX_CEN_TXPACKS3_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 3025;
static const uint64_t IDX_CEN_TXPACKS3_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 3026;
static const uint64_t IDX_CEN_TXPACKS3_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 3027;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_CNTL_PP_EN = 3028;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_TIMER_FREEZE_EN = 3029;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_COUNT_FREEZE_EN = 3030;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_COUNT_SEL = 3031;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_COUNT_SEL_LEN = 3032;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_TIMER_SEL = 3033;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_TIMER_SEL_LEN = 3034;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_CLR_COUNT_ON_READ_EN = 3035;
static const uint64_t IDX_CEN_TXPACKS3_RX_BER_MODE_PP_CLR_TIMER_ON_READ_EN = 3036;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_A = 3037;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_A_LEN = 3038;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_B = 3039;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_B_LEN = 3040;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_C = 3041;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_C_LEN = 3042;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_D = 3043;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO1_PP_TIMEOUT_SEL_D_LEN = 3044;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_E = 3045;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_E_LEN = 3046;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_F = 3047;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_F_LEN = 3048;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_G = 3049;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_G_LEN = 3050;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_H = 3051;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO2_PP_TIMEOUT_SEL_H_LEN = 3052;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_I = 3053;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_I_LEN = 3054;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_J = 3055;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_J_LEN = 3056;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_K = 3057;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_K_LEN = 3058;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_L = 3059;
static const uint64_t IDX_CEN_TXPACKS3_RX_SERVO_TO3_PP_TIMEOUT_SEL_L_LEN = 3060;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_PEAK_CFG = 3061;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_PEAK_CFG_LEN = 3062;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_AMIN_CFG = 3063;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_AMIN_CFG_LEN = 3064;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_ANAP_CFG = 3065;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_ANAP_CFG_LEN = 3066;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_H1_CFG = 3067;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_H1_CFG_LEN = 3068;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_H1AP_CFG = 3069;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_H1AP_CFG_LEN = 3070;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_CA_CFG = 3071;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_CA_CFG_LEN = 3072;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_SPMUX_CFG = 3073;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_CONFIG_PP_SPMUX_CFG_LEN = 3074;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_INIT_TMR_CFG = 3075;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_INIT_TMR_CFG_LEN = 3076;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_BER_CFG = 3077;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_BER_CFG_LEN = 3078;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_FIFO_DLY_CFG = 3079;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_FIFO_DLY_CFG_LEN = 3080;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_DDC_CFG = 3081;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_DDC_CFG_LEN = 3082;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_DAC_BO_CFG = 3083;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_DAC_BO_CFG_LEN = 3084;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_PROT_CFG = 3085;
static const uint64_t IDX_CEN_TXPACKS3_RX_DFE_TIMERS_PP_PROT_CFG_LEN = 3086;
static const uint64_t IDX_CEN_TXPACKS3_RX_RESET_CFG_PP_HLD = 3087;
static const uint64_t IDX_CEN_TXPACKS3_RX_RESET_CFG_PP_HLD_LEN = 3088;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO1_PP_TIMEOUT_SEL_A = 3089;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO1_PP_TIMEOUT_SEL_A_LEN = 3090;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO1_PP_TIMEOUT_SEL_B = 3091;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO1_PP_TIMEOUT_SEL_B_LEN = 3092;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO2_PP_TIMEOUT_SEL_E = 3093;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO2_PP_TIMEOUT_SEL_E_LEN = 3094;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO2_PP_TIMEOUT_SEL_G = 3095;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO2_PP_TIMEOUT_SEL_G_LEN = 3096;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO2_PP_TIMEOUT_SEL_H = 3097;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO2_PP_TIMEOUT_SEL_H_LEN = 3098;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_I = 3099;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_I_LEN = 3100;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_J = 3101;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_J_LEN = 3102;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_K = 3103;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_K_LEN = 3104;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_L = 3105;
static const uint64_t IDX_CEN_TXPACKS3_RX_RECAL_TO3_PP_TIMEOUT_SEL_L_LEN = 3106;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_PP_TRC_EN = 3107;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_PP_TRC_MODE = 3108;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_PP_TRC_MODE_LEN = 3109;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_BIST_JITTER_PULSE_SEL = 3110;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_BIST_JITTER_PULSE_SEL_LEN = 3111;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_BIST_MIN_EYE_WIDTH = 3112;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_BIST_MIN_EYE_WIDTH_LEN = 3113;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_WT_PATTERN_LENGTH = 3114;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE2_PP_WT_PATTERN_LENGTH_LEN = 3115;
static const uint64_t IDX_CEN_TXPACKS3_RX_BIST_GCRMSG_PP_EN = 3116;
static const uint64_t IDX_CEN_TXPACKS3_RX_SCOPE_CNTL_PP_CONTROL = 3117;
static const uint64_t IDX_CEN_TXPACKS3_RX_SCOPE_CNTL_PP_CONTROL_LEN = 3118;
static const uint64_t IDX_CEN_TXPACKS3_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG = 3119;
static const uint64_t IDX_CEN_TXPACKS3_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG_LEN = 3120;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_STEP_INTERVAL_EN = 3121;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_STEP_INTERVAL = 3122;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_STEP_INTERVAL_LEN = 3123;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_PHASEROT_OFFSET_EN = 3124;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_PHASEROT_OFFSET = 3125;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_PHASEROT_OFFSET_LEN = 3126;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_BUFFER_SEL = 3127;
static const uint64_t IDX_CEN_TXPACKS3_RX_MODE3_PP_BIST_BUFFER_SEL_LEN = 3128;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_MODE_PL_LANE_PDWN = 3129;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 3130;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_CNTL_PL_BLOCK_LOCK_LANE = 3131;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_CNTL_PL_CHECK_SKEW_LANE = 3132;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_CNTL_PL_PDWN_LITE = 3133;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_CNTL_PL_OFFCAL_MODE = 3134;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 = 3135;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 = 3136;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_2 = 3137;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_3 = 3138;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_4 = 3139;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_5 = 3140;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 = 3141;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 = 3142;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_BIST_STAT_PL_ERR = 3143;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_EVEN_PL_SAMP1 = 3144;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_EVEN_PL_SAMP1_LEN = 3145;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_EVEN_PL_SAMP0 = 3146;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_EVEN_PL_SAMP0_LEN = 3147;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_ODD_PL_SAMP1 = 3148;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_ODD_PL_SAMP1_LEN = 3149;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_ODD_PL_SAMP0 = 3150;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_OFFSET_ODD_PL_SAMP0_LEN = 3151;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMP_VAL_PL_PEAK = 3152;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMP_VAL_PL_PEAK_LEN = 3153;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMP_VAL_PL_GAIN = 3154;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMP_VAL_PL_GAIN_LEN = 3155;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMP_VAL_PL_OFFSET = 3156;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMP_VAL_PL_OFFSET_LEN = 3157;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMP_CNTL_PL_ADJ_DONE = 3158;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET = 3159;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 3160;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIFO_STAT_PL_L2U_DLY = 3161;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIFO_STAT_PL_L2U_DLY_LEN = 3162;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AP_PL_EVEN_SAMP = 3163;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AP_PL_EVEN_SAMP_LEN = 3164;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AP_PL_ODD_SAMP = 3165;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AP_PL_ODD_SAMP_LEN = 3166;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AN_PL_EVEN_SAMP = 3167;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AN_PL_EVEN_SAMP_LEN = 3168;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AN_PL_ODD_SAMP = 3169;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AN_PL_ODD_SAMP_LEN = 3170;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMIN_PL_EVEN = 3171;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMIN_PL_EVEN_LEN = 3172;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMIN_PL_ODD = 3173;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_AMIN_PL_ODD_LEN = 3174;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_EVEN_PL_SAMP1 = 3175;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_EVEN_PL_SAMP1_LEN = 3176;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_EVEN_PL_SAMP0 = 3177;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_EVEN_PL_SAMP0_LEN = 3178;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_ODD_PL_SAMP1 = 3179;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_ODD_PL_SAMP1_LEN = 3180;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_ODD_PL_SAMP0 = 3181;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_H1_ODD_PL_SAMP0_LEN = 3182;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_PRBS_MODE_PL_TAP_ID = 3183;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_PRBS_MODE_PL_TAP_ID_LEN = 3184;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 3185;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_DESKEW_STAT_PL_BAD_SKEW = 3186;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_DESKEW_STAT_PL_BAD = 3187;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIR_PL_ERRS = 3188;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIR_PL_ERRS_LEN = 3189;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS = 3190;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3191;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 3192;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 3193;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SLS_PL_LANE_SEL = 3194;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SLS_PL_9TH_PATTERN_EN = 3195;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_WT_STATUS_PL_LANE_DISABLED = 3196;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_WT_STATUS_PL_LANE_INVERTED = 3197;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE = 3198;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 3199;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SERVO_CNTL_PL_OP_DONE = 3200;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SERVO_CNTL_PL_OP = 3201;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_SERVO_CNTL_PL_OP_LEN = 3202;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ = 3203;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 3204;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_TRACE_PL_LN_TRC_EN = 3205;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_EYE_OPT_STAT_PL_BAD_BER = 3206;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 3207;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 3208;
static const uint64_t IDX_CEN_TXPACKS3_SLICE0_RX_EYE_OPT_STAT_PL_BAD_DDC = 3209;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_MODE_PL_LANE_PDWN = 3210;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 3211;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_CNTL_PL_BLOCK_LOCK_LANE = 3212;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_CNTL_PL_CHECK_SKEW_LANE = 3213;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_CNTL_PL_PDWN_LITE = 3214;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_CNTL_PL_OFFCAL_MODE = 3215;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 = 3216;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 = 3217;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_2 = 3218;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_3 = 3219;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_4 = 3220;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_5 = 3221;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 = 3222;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 = 3223;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_BIST_STAT_PL_ERR = 3224;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_EVEN_PL_SAMP1 = 3225;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_EVEN_PL_SAMP1_LEN = 3226;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_EVEN_PL_SAMP0 = 3227;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_EVEN_PL_SAMP0_LEN = 3228;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_ODD_PL_SAMP1 = 3229;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_ODD_PL_SAMP1_LEN = 3230;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_ODD_PL_SAMP0 = 3231;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_OFFSET_ODD_PL_SAMP0_LEN = 3232;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMP_VAL_PL_PEAK = 3233;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMP_VAL_PL_PEAK_LEN = 3234;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMP_VAL_PL_GAIN = 3235;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMP_VAL_PL_GAIN_LEN = 3236;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMP_VAL_PL_OFFSET = 3237;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMP_VAL_PL_OFFSET_LEN = 3238;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMP_CNTL_PL_ADJ_DONE = 3239;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET = 3240;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 3241;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIFO_STAT_PL_L2U_DLY = 3242;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIFO_STAT_PL_L2U_DLY_LEN = 3243;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AP_PL_EVEN_SAMP = 3244;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AP_PL_EVEN_SAMP_LEN = 3245;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AP_PL_ODD_SAMP = 3246;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AP_PL_ODD_SAMP_LEN = 3247;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AN_PL_EVEN_SAMP = 3248;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AN_PL_EVEN_SAMP_LEN = 3249;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AN_PL_ODD_SAMP = 3250;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AN_PL_ODD_SAMP_LEN = 3251;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMIN_PL_EVEN = 3252;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMIN_PL_EVEN_LEN = 3253;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMIN_PL_ODD = 3254;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_AMIN_PL_ODD_LEN = 3255;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_EVEN_PL_SAMP1 = 3256;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_EVEN_PL_SAMP1_LEN = 3257;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_EVEN_PL_SAMP0 = 3258;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_EVEN_PL_SAMP0_LEN = 3259;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_ODD_PL_SAMP1 = 3260;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_ODD_PL_SAMP1_LEN = 3261;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_ODD_PL_SAMP0 = 3262;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_H1_ODD_PL_SAMP0_LEN = 3263;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_PRBS_MODE_PL_TAP_ID = 3264;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_PRBS_MODE_PL_TAP_ID_LEN = 3265;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 3266;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_DESKEW_STAT_PL_BAD_SKEW = 3267;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_DESKEW_STAT_PL_BAD = 3268;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIR_PL_ERRS = 3269;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIR_PL_ERRS_LEN = 3270;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS = 3271;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3272;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 3273;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 3274;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SLS_PL_LANE_SEL = 3275;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SLS_PL_9TH_PATTERN_EN = 3276;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_WT_STATUS_PL_LANE_DISABLED = 3277;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_WT_STATUS_PL_LANE_INVERTED = 3278;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE = 3279;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 3280;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SERVO_CNTL_PL_OP_DONE = 3281;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SERVO_CNTL_PL_OP = 3282;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_SERVO_CNTL_PL_OP_LEN = 3283;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ = 3284;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 3285;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_TRACE_PL_LN_TRC_EN = 3286;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_EYE_OPT_STAT_PL_BAD_BER = 3287;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 3288;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 3289;
static const uint64_t IDX_CEN_TXPACKS3_SLICE1_RX_EYE_OPT_STAT_PL_BAD_DDC = 3290;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_MODE_PL_LANE_PDWN = 3291;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 3292;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_CNTL_PL_BLOCK_LOCK_LANE = 3293;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_CNTL_PL_CHECK_SKEW_LANE = 3294;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_CNTL_PL_PDWN_LITE = 3295;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_CNTL_PL_OFFCAL_MODE = 3296;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 = 3297;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 = 3298;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_2 = 3299;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_3 = 3300;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_4 = 3301;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_5 = 3302;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 = 3303;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 = 3304;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_BIST_STAT_PL_ERR = 3305;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_EVEN_PL_SAMP1 = 3306;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_EVEN_PL_SAMP1_LEN = 3307;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_EVEN_PL_SAMP0 = 3308;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_EVEN_PL_SAMP0_LEN = 3309;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_ODD_PL_SAMP1 = 3310;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_ODD_PL_SAMP1_LEN = 3311;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_ODD_PL_SAMP0 = 3312;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_OFFSET_ODD_PL_SAMP0_LEN = 3313;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMP_VAL_PL_PEAK = 3314;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMP_VAL_PL_PEAK_LEN = 3315;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMP_VAL_PL_GAIN = 3316;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMP_VAL_PL_GAIN_LEN = 3317;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMP_VAL_PL_OFFSET = 3318;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMP_VAL_PL_OFFSET_LEN = 3319;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMP_CNTL_PL_ADJ_DONE = 3320;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET = 3321;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 3322;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIFO_STAT_PL_L2U_DLY = 3323;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIFO_STAT_PL_L2U_DLY_LEN = 3324;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AP_PL_EVEN_SAMP = 3325;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AP_PL_EVEN_SAMP_LEN = 3326;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AP_PL_ODD_SAMP = 3327;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AP_PL_ODD_SAMP_LEN = 3328;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AN_PL_EVEN_SAMP = 3329;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AN_PL_EVEN_SAMP_LEN = 3330;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AN_PL_ODD_SAMP = 3331;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AN_PL_ODD_SAMP_LEN = 3332;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMIN_PL_EVEN = 3333;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMIN_PL_EVEN_LEN = 3334;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMIN_PL_ODD = 3335;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_AMIN_PL_ODD_LEN = 3336;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_EVEN_PL_SAMP1 = 3337;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_EVEN_PL_SAMP1_LEN = 3338;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_EVEN_PL_SAMP0 = 3339;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_EVEN_PL_SAMP0_LEN = 3340;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_ODD_PL_SAMP1 = 3341;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_ODD_PL_SAMP1_LEN = 3342;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_ODD_PL_SAMP0 = 3343;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_H1_ODD_PL_SAMP0_LEN = 3344;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_PRBS_MODE_PL_TAP_ID = 3345;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_PRBS_MODE_PL_TAP_ID_LEN = 3346;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 3347;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_DESKEW_STAT_PL_BAD_SKEW = 3348;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_DESKEW_STAT_PL_BAD = 3349;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIR_PL_ERRS = 3350;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIR_PL_ERRS_LEN = 3351;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS = 3352;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3353;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 3354;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 3355;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SLS_PL_LANE_SEL = 3356;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SLS_PL_9TH_PATTERN_EN = 3357;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_WT_STATUS_PL_LANE_DISABLED = 3358;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_WT_STATUS_PL_LANE_INVERTED = 3359;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE = 3360;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 3361;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SERVO_CNTL_PL_OP_DONE = 3362;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SERVO_CNTL_PL_OP = 3363;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_SERVO_CNTL_PL_OP_LEN = 3364;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ = 3365;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 3366;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_TRACE_PL_LN_TRC_EN = 3367;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_EYE_OPT_STAT_PL_BAD_BER = 3368;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 3369;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 3370;
static const uint64_t IDX_CEN_TXPACKS3_SLICE2_RX_EYE_OPT_STAT_PL_BAD_DDC = 3371;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_MODE_PL_LANE_PDWN = 3372;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 3373;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_CNTL_PL_BLOCK_LOCK_LANE = 3374;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_CNTL_PL_CHECK_SKEW_LANE = 3375;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_CNTL_PL_PDWN_LITE = 3376;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_CNTL_PL_OFFCAL_MODE = 3377;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 = 3378;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 = 3379;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_2 = 3380;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_3 = 3381;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_4 = 3382;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_5 = 3383;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 = 3384;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 = 3385;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_BIST_STAT_PL_ERR = 3386;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_EVEN_PL_SAMP1 = 3387;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_EVEN_PL_SAMP1_LEN = 3388;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_EVEN_PL_SAMP0 = 3389;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_EVEN_PL_SAMP0_LEN = 3390;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_ODD_PL_SAMP1 = 3391;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_ODD_PL_SAMP1_LEN = 3392;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_ODD_PL_SAMP0 = 3393;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_OFFSET_ODD_PL_SAMP0_LEN = 3394;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMP_VAL_PL_PEAK = 3395;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMP_VAL_PL_PEAK_LEN = 3396;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMP_VAL_PL_GAIN = 3397;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMP_VAL_PL_GAIN_LEN = 3398;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMP_VAL_PL_OFFSET = 3399;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMP_VAL_PL_OFFSET_LEN = 3400;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMP_CNTL_PL_ADJ_DONE = 3401;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET = 3402;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 3403;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIFO_STAT_PL_L2U_DLY = 3404;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIFO_STAT_PL_L2U_DLY_LEN = 3405;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AP_PL_EVEN_SAMP = 3406;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AP_PL_EVEN_SAMP_LEN = 3407;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AP_PL_ODD_SAMP = 3408;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AP_PL_ODD_SAMP_LEN = 3409;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AN_PL_EVEN_SAMP = 3410;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AN_PL_EVEN_SAMP_LEN = 3411;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AN_PL_ODD_SAMP = 3412;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AN_PL_ODD_SAMP_LEN = 3413;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMIN_PL_EVEN = 3414;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMIN_PL_EVEN_LEN = 3415;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMIN_PL_ODD = 3416;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_AMIN_PL_ODD_LEN = 3417;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_EVEN_PL_SAMP1 = 3418;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_EVEN_PL_SAMP1_LEN = 3419;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_EVEN_PL_SAMP0 = 3420;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_EVEN_PL_SAMP0_LEN = 3421;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_ODD_PL_SAMP1 = 3422;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_ODD_PL_SAMP1_LEN = 3423;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_ODD_PL_SAMP0 = 3424;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_H1_ODD_PL_SAMP0_LEN = 3425;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_PRBS_MODE_PL_TAP_ID = 3426;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_PRBS_MODE_PL_TAP_ID_LEN = 3427;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 3428;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_DESKEW_STAT_PL_BAD_SKEW = 3429;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_DESKEW_STAT_PL_BAD = 3430;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIR_PL_ERRS = 3431;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIR_PL_ERRS_LEN = 3432;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS = 3433;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3434;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 3435;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 3436;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SLS_PL_LANE_SEL = 3437;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SLS_PL_9TH_PATTERN_EN = 3438;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_WT_STATUS_PL_LANE_DISABLED = 3439;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_WT_STATUS_PL_LANE_INVERTED = 3440;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE = 3441;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 3442;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SERVO_CNTL_PL_OP_DONE = 3443;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SERVO_CNTL_PL_OP = 3444;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_SERVO_CNTL_PL_OP_LEN = 3445;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ = 3446;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 3447;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_TRACE_PL_LN_TRC_EN = 3448;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_EYE_OPT_STAT_PL_BAD_BER = 3449;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 3450;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 3451;
static const uint64_t IDX_CEN_TXPACKS3_SLICE3_RX_EYE_OPT_STAT_PL_BAD_DDC = 3452;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE = 3453;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_REDUCED_SCRAMBLE_MODE_LEN = 3454;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_PRBS_SCRAMBLE_MODE = 3455;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_PRBS_SCRAMBLE_MODE_LEN = 3456;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL = 3457;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_ACT_CHECK_TIMEOUT_SEL_LEN = 3458;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL = 3459;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_BLOCK_LOCK_TIMEOUT_SEL_LEN = 3460;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL = 3461;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_BIT_LOCK_TIMEOUT_SEL_LEN = 3462;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_ENABLE_DFE_V1 = 3463;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE1_PP_AMIN_ALL = 3464;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_CNTL_FAST_PP_PRBS_CHECK_SYNC = 3465;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_CNTL_FAST_PP_ENABLE_REDUCED_SCRAMBLE = 3466;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL = 3467;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DYN_RECAL_TIMEOUTS_PP_INTERVAL_TIMEOUT_SEL_LEN = 3468;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL = 3469;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DYN_RECAL_TIMEOUTS_PP_STATUS_RPT_TIMEOUT_SEL_LEN = 3470;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_CNTL_PP_EN = 3471;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_TIMER_FREEZE_EN = 3472;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_COUNT_FREEZE_EN = 3473;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_COUNT_SEL = 3474;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_COUNT_SEL_LEN = 3475;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_TIMER_SEL = 3476;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_TIMER_SEL_LEN = 3477;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_CLR_COUNT_ON_READ_EN = 3478;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BER_MODE_PP_CLR_TIMER_ON_READ_EN = 3479;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_A = 3480;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_A_LEN = 3481;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_B = 3482;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_B_LEN = 3483;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_C = 3484;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_C_LEN = 3485;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_D = 3486;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO1_PP_TIMEOUT_SEL_D_LEN = 3487;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_E = 3488;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_E_LEN = 3489;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_F = 3490;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_F_LEN = 3491;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_G = 3492;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_G_LEN = 3493;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_H = 3494;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO2_PP_TIMEOUT_SEL_H_LEN = 3495;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_I = 3496;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_I_LEN = 3497;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_J = 3498;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_J_LEN = 3499;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_K = 3500;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_K_LEN = 3501;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_L = 3502;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SERVO_TO3_PP_TIMEOUT_SEL_L_LEN = 3503;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_PEAK_CFG = 3504;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_PEAK_CFG_LEN = 3505;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_AMIN_CFG = 3506;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_AMIN_CFG_LEN = 3507;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_ANAP_CFG = 3508;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_ANAP_CFG_LEN = 3509;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_H1_CFG = 3510;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_H1_CFG_LEN = 3511;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_H1AP_CFG = 3512;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_H1AP_CFG_LEN = 3513;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_CA_CFG = 3514;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_CA_CFG_LEN = 3515;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_SPMUX_CFG = 3516;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_CONFIG_PP_SPMUX_CFG_LEN = 3517;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_INIT_TMR_CFG = 3518;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_INIT_TMR_CFG_LEN = 3519;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_BER_CFG = 3520;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_BER_CFG_LEN = 3521;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_FIFO_DLY_CFG = 3522;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_FIFO_DLY_CFG_LEN = 3523;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_DDC_CFG = 3524;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_DDC_CFG_LEN = 3525;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_DAC_BO_CFG = 3526;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_DAC_BO_CFG_LEN = 3527;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_PROT_CFG = 3528;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_DFE_TIMERS_PP_PROT_CFG_LEN = 3529;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RESET_CFG_PP_HLD = 3530;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RESET_CFG_PP_HLD_LEN = 3531;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO1_PP_TIMEOUT_SEL_A = 3532;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO1_PP_TIMEOUT_SEL_A_LEN = 3533;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO1_PP_TIMEOUT_SEL_B = 3534;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO1_PP_TIMEOUT_SEL_B_LEN = 3535;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO2_PP_TIMEOUT_SEL_E = 3536;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO2_PP_TIMEOUT_SEL_E_LEN = 3537;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO2_PP_TIMEOUT_SEL_G = 3538;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO2_PP_TIMEOUT_SEL_G_LEN = 3539;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO2_PP_TIMEOUT_SEL_H = 3540;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO2_PP_TIMEOUT_SEL_H_LEN = 3541;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_I = 3542;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_I_LEN = 3543;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_J = 3544;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_J_LEN = 3545;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_K = 3546;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_K_LEN = 3547;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_L = 3548;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_RECAL_TO3_PP_TIMEOUT_SEL_L_LEN = 3549;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_PP_TRC_EN = 3550;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_PP_TRC_MODE = 3551;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_PP_TRC_MODE_LEN = 3552;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_BIST_JITTER_PULSE_SEL = 3553;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_BIST_JITTER_PULSE_SEL_LEN = 3554;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_BIST_MIN_EYE_WIDTH = 3555;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_BIST_MIN_EYE_WIDTH_LEN = 3556;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_WT_PATTERN_LENGTH = 3557;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE2_PP_WT_PATTERN_LENGTH_LEN = 3558;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_BIST_GCRMSG_PP_EN = 3559;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SCOPE_CNTL_PP_CONTROL = 3560;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SCOPE_CNTL_PP_CONTROL_LEN = 3561;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG = 3562;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_SCOPE_CNTL_PP_H1_CLKADJ_CFG_LEN = 3563;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_STEP_INTERVAL_EN = 3564;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_STEP_INTERVAL = 3565;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_STEP_INTERVAL_LEN = 3566;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_PHASEROT_OFFSET_EN = 3567;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_PHASEROT_OFFSET = 3568;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_PHASEROT_OFFSET_LEN = 3569;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_BUFFER_SEL = 3570;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_RX_MODE3_PP_BIST_BUFFER_SEL_LEN = 3571;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_MODE_PL_LANE_PDWN = 3572;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 3573;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_CNTL_PL_BLOCK_LOCK_LANE = 3574;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_CNTL_PL_CHECK_SKEW_LANE = 3575;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_CNTL_PL_PDWN_LITE = 3576;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_CNTL_PL_OFFCAL_MODE = 3577;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_0 = 3578;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_1 = 3579;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_2 = 3580;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_3 = 3581;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_RX_PL_SPARE_MODE = 3582;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_5 = 3583;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_6 = 3584;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SPARE_MODE_PL_7 = 3585;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_BIST_STAT_PL_ERR = 3586;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_EVEN_PL_SAMP1 = 3587;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_EVEN_PL_SAMP1_LEN = 3588;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_EVEN_PL_SAMP0 = 3589;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_EVEN_PL_SAMP0_LEN = 3590;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_ODD_PL_SAMP1 = 3591;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_ODD_PL_SAMP1_LEN = 3592;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_ODD_PL_SAMP0 = 3593;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_OFFSET_ODD_PL_SAMP0_LEN = 3594;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMP_VAL_PL_PEAK = 3595;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMP_VAL_PL_PEAK_LEN = 3596;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMP_VAL_PL_GAIN = 3597;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMP_VAL_PL_GAIN_LEN = 3598;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMP_VAL_PL_OFFSET = 3599;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMP_VAL_PL_OFFSET_LEN = 3600;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMP_CNTL_PL_ADJ_DONE = 3601;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET = 3602;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 3603;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIFO_STAT_PL_L2U_DLY = 3604;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIFO_STAT_PL_L2U_DLY_LEN = 3605;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AP_PL_EVEN_SAMP = 3606;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AP_PL_EVEN_SAMP_LEN = 3607;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AP_PL_ODD_SAMP = 3608;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AP_PL_ODD_SAMP_LEN = 3609;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AN_PL_EVEN_SAMP = 3610;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AN_PL_EVEN_SAMP_LEN = 3611;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AN_PL_ODD_SAMP = 3612;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AN_PL_ODD_SAMP_LEN = 3613;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMIN_PL_EVEN = 3614;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMIN_PL_EVEN_LEN = 3615;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMIN_PL_ODD = 3616;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_AMIN_PL_ODD_LEN = 3617;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_EVEN_PL_SAMP1 = 3618;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_EVEN_PL_SAMP1_LEN = 3619;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_EVEN_PL_SAMP0 = 3620;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_EVEN_PL_SAMP0_LEN = 3621;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_ODD_PL_SAMP1 = 3622;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_ODD_PL_SAMP1_LEN = 3623;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_ODD_PL_SAMP0 = 3624;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_H1_ODD_PL_SAMP0_LEN = 3625;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_PRBS_MODE_PL_TAP_ID = 3626;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_PRBS_MODE_PL_TAP_ID_LEN = 3627;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 3628;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_DESKEW_STAT_PL_BAD_SKEW = 3629;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_DESKEW_STAT_PL_BAD = 3630;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIR_PL_ERRS = 3631;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIR_PL_ERRS_LEN = 3632;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIR_MASK_PL_ERRS = 3633;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3634;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 3635;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 3636;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SLS_PL_LANE_SEL = 3637;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SLS_PL_9TH_PATTERN_EN = 3638;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_WT_STATUS_PL_LANE_DISABLED = 3639;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_WT_STATUS_PL_LANE_INVERTED = 3640;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE = 3641;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 3642;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SERVO_CNTL_PL_OP_DONE = 3643;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SERVO_CNTL_PL_OP = 3644;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_SERVO_CNTL_PL_OP_LEN = 3645;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ = 3646;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 3647;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_TRACE_PL_LN_TRC_EN = 3648;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_EYE_OPT_STAT_PL_BAD_BER = 3649;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 3650;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 3651;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE0_RX_EYE_OPT_STAT_PL_BAD_DDC = 3652;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_MODE_PL_LANE_PDWN = 3653;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_MODE_PL_LANE_SCRAMBLE_DISABLE = 3654;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_CNTL_PL_BLOCK_LOCK_LANE = 3655;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_CNTL_PL_CHECK_SKEW_LANE = 3656;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_CNTL_PL_PDWN_LITE = 3657;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_CNTL_PL_OFFCAL_MODE = 3658;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_0 = 3659;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_1 = 3660;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_2 = 3661;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_3 = 3662;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_RX_PL_SPARE_MODE = 3663;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_5 = 3664;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_6 = 3665;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SPARE_MODE_PL_7 = 3666;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_BIST_STAT_PL_ERR = 3667;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_EVEN_PL_SAMP1 = 3668;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_EVEN_PL_SAMP1_LEN = 3669;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_EVEN_PL_SAMP0 = 3670;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_EVEN_PL_SAMP0_LEN = 3671;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_ODD_PL_SAMP1 = 3672;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_ODD_PL_SAMP1_LEN = 3673;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_ODD_PL_SAMP0 = 3674;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_OFFSET_ODD_PL_SAMP0_LEN = 3675;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMP_VAL_PL_PEAK = 3676;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMP_VAL_PL_PEAK_LEN = 3677;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMP_VAL_PL_GAIN = 3678;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMP_VAL_PL_GAIN_LEN = 3679;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMP_VAL_PL_OFFSET = 3680;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMP_VAL_PL_OFFSET_LEN = 3681;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMP_CNTL_PL_ADJ_DONE = 3682;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET = 3683;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_PROT_MODE_PL_PHASEROT_OFFSET_LEN = 3684;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIFO_STAT_PL_L2U_DLY = 3685;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIFO_STAT_PL_L2U_DLY_LEN = 3686;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AP_PL_EVEN_SAMP = 3687;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AP_PL_EVEN_SAMP_LEN = 3688;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AP_PL_ODD_SAMP = 3689;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AP_PL_ODD_SAMP_LEN = 3690;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AN_PL_EVEN_SAMP = 3691;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AN_PL_EVEN_SAMP_LEN = 3692;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AN_PL_ODD_SAMP = 3693;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AN_PL_ODD_SAMP_LEN = 3694;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMIN_PL_EVEN = 3695;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMIN_PL_EVEN_LEN = 3696;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMIN_PL_ODD = 3697;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_AMIN_PL_ODD_LEN = 3698;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_EVEN_PL_SAMP1 = 3699;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_EVEN_PL_SAMP1_LEN = 3700;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_EVEN_PL_SAMP0 = 3701;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_EVEN_PL_SAMP0_LEN = 3702;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_ODD_PL_SAMP1 = 3703;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_ODD_PL_SAMP1_LEN = 3704;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_ODD_PL_SAMP0 = 3705;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_H1_ODD_PL_SAMP0_LEN = 3706;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_PRBS_MODE_PL_TAP_ID = 3707;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_PRBS_MODE_PL_TAP_ID_LEN = 3708;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_DESKEW_STAT_PL_BAD_BLOCK_LOCK = 3709;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_DESKEW_STAT_PL_BAD_SKEW = 3710;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_DESKEW_STAT_PL_BAD = 3711;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIR_PL_ERRS = 3712;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIR_PL_ERRS_LEN = 3713;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIR_MASK_PL_ERRS = 3714;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3715;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ = 3716;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_FIR_ERROR_INJECT_PL_PL_ERR_INJ_LEN = 3717;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SLS_PL_LANE_SEL = 3718;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SLS_PL_9TH_PATTERN_EN = 3719;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_WT_STATUS_PL_LANE_DISABLED = 3720;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_WT_STATUS_PL_LANE_INVERTED = 3721;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE = 3722;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_WT_STATUS_PL_LANE_BAD_CODE_LEN = 3723;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SERVO_CNTL_PL_OP_DONE = 3724;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SERVO_CNTL_PL_OP = 3725;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_SERVO_CNTL_PL_OP_LEN = 3726;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ = 3727;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_DFE_CLKADJ_PL_CLKADJ_LEN = 3728;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_TRACE_PL_LN_TRC_EN = 3729;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_EYE_OPT_STAT_PL_BAD_BER = 3730;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_EYE_OPT_STAT_PL_BAD_WIDTH = 3731;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_EYE_OPT_STAT_PL_BAD_HEIGHT = 3732;
static const uint64_t IDX_CEN_TXPACKS4_RXPACK_4_SLICE1_RX_EYE_OPT_STAT_PL_BAD_DDC = 3733;
static const uint64_t IDX_CEN_SCOM_MODE_PB_GCR_TEST = 3734;
static const uint64_t IDX_CEN_SCOM_MODE_PB_ENABLE_GCR_OFL_BUFF = 3735;
static const uint64_t IDX_CEN_SCOM_MODE_PB_IORESET_HARD_BUS0 = 3736;
static const uint64_t IDX_CEN_SCOM_MODE_PB_IORESET_HARD_BUS0_LEN = 3737;
static const uint64_t IDX_CEN_SCOM_MODE_PB_GCR_HANG_DET_SEL = 3738;
static const uint64_t IDX_CEN_SCOM_MODE_PB_GCR_HANG_DET_SEL_LEN = 3739;
static const uint64_t IDX_CEN_SCOM_MODE_PB_GCR_BUFFER_ENABLED_RO_SIGNAL = 3740;
static const uint64_t IDX_CEN_SCOM_MODE_PB_GCR_HANG_ERROR_MASK = 3741;
static const uint64_t IDX_CEN_SCOM_MODE_PB_GCR_HANG_ERROR_INJ = 3742;
static const uint64_t IDX_CEN_SCOM_MODE_PB_SPARES = 3743;
static const uint64_t IDX_CEN_SCOM_MODE_PB_SPARES_LEN = 3744;
static const uint64_t IDX_CEN_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 3745;
static const uint64_t IDX_CEN_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 3746;
static const uint64_t IDX_CEN_FIR_REG_GCR_HANG_ERROR = 3747;
static const uint64_t IDX_CEN_FIR_REG_RESERVED3_7 = 3748;
static const uint64_t IDX_CEN_FIR_REG_RESERVED3_7_LEN = 3749;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS0_TRAINING_ERROR = 3750;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS0_SPARE_DEPLOYED = 3751;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS0_MAX_SPARES_EXCEEDED = 3752;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR = 3753;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS0_TOO_MANY_BUS_ERRORS = 3754;
static const uint64_t IDX_CEN_FIR_REG_RESERVED13_15 = 3755;
static const uint64_t IDX_CEN_FIR_REG_RESERVED13_15_LEN = 3756;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS1_TRAINING_ERROR = 3757;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS1_SPARE_DEPLOYED = 3758;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS1_MAX_SPARES_EXCEEDED = 3759;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR = 3760;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS1_TOO_MANY_BUS_ERRORS = 3761;
static const uint64_t IDX_CEN_FIR_REG_RESERVED21_23 = 3762;
static const uint64_t IDX_CEN_FIR_REG_RESERVED21_23_LEN = 3763;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS2_TRAINING_ERROR = 3764;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS2_SPARE_DEPLOYED = 3765;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS2_MAX_SPARES_EXCEEDED = 3766;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR = 3767;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS2_TOO_MANY_BUS_ERRORS = 3768;
static const uint64_t IDX_CEN_FIR_REG_RESERVED29_31 = 3769;
static const uint64_t IDX_CEN_FIR_REG_RESERVED29_31_LEN = 3770;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS3_TRAINING_ERROR = 3771;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS3_SPARE_DEPLOYED = 3772;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS3_MAX_SPARES_EXCEEDED = 3773;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR = 3774;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS3_TOO_MANY_BUS_ERRORS = 3775;
static const uint64_t IDX_CEN_FIR_REG_RESERVED37_39 = 3776;
static const uint64_t IDX_CEN_FIR_REG_RESERVED37_39_LEN = 3777;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS4_TRAINING_ERROR = 3778;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS4_SPARE_DEPLOYED = 3779;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS4_MAX_SPARES_EXCEEDED = 3780;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR = 3781;
static const uint64_t IDX_CEN_FIR_REG_RX_BUS4_TOO_MANY_BUS_ERRORS = 3782;
static const uint64_t IDX_CEN_FIR_REG_RESERVED45_47 = 3783;
static const uint64_t IDX_CEN_FIR_REG_RESERVED45_47_LEN = 3784;
static const uint64_t IDX_CEN_FIR_REG_SCOMFIR_ERROR = 3785;
static const uint64_t IDX_CEN_FIR_REG_SCOMFIR_ERROR_CLONE = 3786;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 3787;
static const uint64_t IDX_CEN_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 3788;
static const uint64_t IDX_CEN_FIR_MASK_REG_GCR_HANG_ERROR = 3789;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED3_7 = 3790;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED3_7_LEN = 3791;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS0_TRAINING_ERROR = 3792;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS0_SPARE_DEPLOYED = 3793;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS0_MAX_SPARES_EXCEEDED = 3794;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR = 3795;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS0_TOO_MANY_BUS_ERRORS = 3796;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED13_15 = 3797;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED13_15_LEN = 3798;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS1_TRAINING_ERROR = 3799;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS1_SPARE_DEPLOYED = 3800;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS1_MAX_SPARES_EXCEEDED = 3801;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR = 3802;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS1_TOO_MANY_BUS_ERRORS = 3803;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED21_23 = 3804;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED21_23_LEN = 3805;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS2_TRAINING_ERROR = 3806;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS2_SPARE_DEPLOYED = 3807;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS2_MAX_SPARES_EXCEEDED = 3808;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR = 3809;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS2_TOO_MANY_BUS_ERRORS = 3810;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED29_31 = 3811;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED29_31_LEN = 3812;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS3_TRAINING_ERROR = 3813;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS3_SPARE_DEPLOYED = 3814;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS3_MAX_SPARES_EXCEEDED = 3815;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR = 3816;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS3_TOO_MANY_BUS_ERRORS = 3817;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED37_39 = 3818;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED37_39_LEN = 3819;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS4_TRAINING_ERROR = 3820;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS4_SPARE_DEPLOYED = 3821;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS4_MAX_SPARES_EXCEEDED = 3822;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR = 3823;
static const uint64_t IDX_CEN_FIR_MASK_REG_RX_BUS4_TOO_MANY_BUS_ERRORS = 3824;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED45_47 = 3825;
static const uint64_t IDX_CEN_FIR_MASK_REG_RESERVED45_47_LEN = 3826;
static const uint64_t IDX_CEN_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 3827;
static const uint64_t IDX_CEN_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 3828;
static const uint64_t IDX_CEN_FIR_ACTION0_REG_ACTION0 = 3829;
static const uint64_t IDX_CEN_FIR_ACTION0_REG_ACTION0_LEN = 3830;
static const uint64_t IDX_CEN_FIR_ACTION1_REG_ACTION1 = 3831;
static const uint64_t IDX_CEN_FIR_ACTION1_REG_ACTION1_LEN = 3832;
static const uint64_t IDX_CEN_TX_IMPCAL_NVAL_PB_ZCAL_N = 3833;
static const uint64_t IDX_CEN_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN = 3834;
static const uint64_t IDX_CEN_TX_IMPCAL_PVAL_PB_ZCAL_P = 3835;
static const uint64_t IDX_CEN_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN = 3836;
static const uint64_t IDX_CEN_TX_IMPCAL_P_4X_PB_ZCAL_P_4X = 3837;
static const uint64_t IDX_CEN_TX_IMPCAL_P_4X_PB_ZCAL_P_4X_LEN = 3838;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_SWO_EN = 3839;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CAL_SEGS = 3840;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_INV = 3841;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_OFFSET = 3842;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_RESET = 3843;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_SWO_POWERDOWN = 3844;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_CYA_DATA_INV = 3845;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_2R = 3846;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_DEBUG_MODE = 3847;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO1_PB_ZCAL_DEBUG_MODE_LEN = 3848;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL = 3849;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL_LEN = 3850;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL = 3851;
static const uint64_t IDX_CEN_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL_LEN = 3852;
static const uint64_t IDX_CEN_TX_ANALOG_IREF_PB_IREF_BC = 3853;
static const uint64_t IDX_CEN_TX_ANALOG_IREF_PB_IREF_BC_LEN = 3854;
static const uint64_t IDX_CEN_TX_MINIKERF_PB_MINIKERF = 3855;
static const uint64_t IDX_CEN_TX_MINIKERF_PB_MINIKERF_LEN = 3856;
static const uint64_t IDX_CEN_TX_INIT_VERSION_PB_VERSION = 3857;
static const uint64_t IDX_CEN_TX_INIT_VERSION_PB_VERSION_LEN = 3858;
static const uint64_t IDX_CEN_TX_SCRATCH_REG_PB_REG = 3859;
static const uint64_t IDX_CEN_TX_SCRATCH_REG_PB_REG_LEN = 3860;
static const uint64_t IDX_CEN_RX_FIR_RESET_PB_PB_CLR_PAR_ERRS = 3861;
static const uint64_t IDX_CEN_RX_FIR_RESET_PB_RESET = 3862;
static const uint64_t IDX_CEN_RX_FIR_PB_ERRS = 3863;
static const uint64_t IDX_CEN_RX_FIR_PB_ERRS_LEN = 3864;
static const uint64_t IDX_CEN_RX_FIR_MASK_PB_ERRS = 3865;
static const uint64_t IDX_CEN_RX_FIR_MASK_PB_ERRS_LEN = 3866;
static const uint64_t IDX_CEN_RX_FIR_ERROR_INJECT_PB_PB_ERRS_INJ = 3867;
static const uint64_t IDX_CEN_RX_FIR_ERROR_INJECT_PB_PB_ERRS_INJ_LEN = 3868;
static const uint64_t IDX_CEN_MBCCFGQ_CACHE_ENABLE = 3869;
static const uint64_t IDX_CEN_MBCCFGQ_CFG_DYN_WHAP_EN = 3870;
static const uint64_t IDX_CEN_MBCCFGQ_CLEANER_ENABLE = 3871;
static const uint64_t IDX_CEN_MBCCFGQ_CACHE_ONLY_ENABLE = 3872;
static const uint64_t IDX_CEN_MBCCFGQ_LRU_DMAP_EN = 3873;
static const uint64_t IDX_CEN_MBCCFGQ_LRU_RANDOM_EN = 3874;
static const uint64_t IDX_CEN_MBCCFGQ_LRU_SINGLE_MEM_EN = 3875;
static const uint64_t IDX_CEN_MBCCFGQ_CFG_SRW_DELETE_UE_EN = 3876;
static const uint64_t IDX_CEN_MBCCFGQ_SRW_LINE_DELETE_NEXT_CE_EN = 3877;
static const uint64_t IDX_CEN_MBCCFGQ_ONLY_LOG_ECC_UE = 3878;
static const uint64_t IDX_CEN_MBCCFGQ_ONLY_LOG_ECC_CE = 3879;
static const uint64_t IDX_CEN_MBCCFGQ_SRW_PREFETCH_DIS = 3880;
static const uint64_t IDX_CEN_MBCCFGQ_PRQ_PREFETCH_DIS = 3881;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_PAGE_MODE_BUNDLE_MAX_CNT_0_3 = 3882;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_PAGE_MODE_BUNDLE_MAX_CNT_0_3_LEN = 3883;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WRQ_TGT_ALLOC_0_5 = 3884;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WRQ_TGT_ALLOC_0_5_LEN = 3885;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_WRQ_HWMARK_0_5 = 3886;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_WRQ_HWMARK_0_5_LEN = 3887;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_WRQ_LWMARK_0_5 = 3888;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_WRQ_LWMARK_0_5_LEN = 3889;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_DV_HWMARK_0_13 = 3890;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_DV_HWMARK_0_13_LEN = 3891;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_DV_LWMARK_0_13 = 3892;
static const uint64_t IDX_CEN_MBCCFGQ_CLN_WR_PRIORITY_DV_LWMARK_0_13_LEN = 3893;
static const uint64_t IDX_CEN_MBCCFGQ_MBS_WAT_TRIGGER = 3894;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD0_CP_UTIL_EN_DC = 3895;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD0_CP_UTIL_SEL_DC_0_1 = 3896;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD0_CP_UTIL_SEL_DC_0_1_LEN = 3897;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD0_CP_UTIL_EXT_SEL_0_2 = 3898;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD0_CP_UTIL_EXT_SEL_0_2_LEN = 3899;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD0_CP_UTIL_MON_BITS_0_5 = 3900;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD0_CP_UTIL_MON_BITS_0_5_LEN = 3901;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD1_CP_UTIL_EN_DC = 3902;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD1_CP_UTIL_SEL_DC_0_1 = 3903;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD1_CP_UTIL_SEL_DC_0_1_LEN = 3904;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD1_CP_UTIL_EXT_SEL_0_2 = 3905;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD1_CP_UTIL_EXT_SEL_0_2_LEN = 3906;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD1_CP_UTIL_MON_BITS_0_5 = 3907;
static const uint64_t IDX_CEN_MBCDCPMQ_MBCD1_CP_UTIL_MON_BITS_0_5_LEN = 3908;
static const uint64_t IDX_CEN_MBCELOGQ_VALID_ECC_ERR = 3909;
static const uint64_t IDX_CEN_MBCELOGQ_CE = 3910;
static const uint64_t IDX_CEN_MBCELOGQ_UE = 3911;
static const uint64_t IDX_CEN_MBCELOGQ_SUE = 3912;
static const uint64_t IDX_CEN_MBCELOGQ_MBCD_READ_PORT = 3913;
static const uint64_t IDX_CEN_MBCELOGQ_ECC_SYNDROME = 3914;
static const uint64_t IDX_CEN_MBCELOGQ_ECC_SYNDROME_LEN = 3915;
static const uint64_t IDX_CEN_MBCELOGQ_CEUE_PERSISTENT = 3916;
static const uint64_t IDX_CEN_MBCELOGQ_CEUE_WINDOW_CLEAR = 3917;
static const uint64_t IDX_CEN_MBCELOGQ_RSVD = 3918;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_BNK_3 = 3919;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_CA_0_2 = 3920;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_CA_0_2_LEN = 3921;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_RA_2_9 = 3922;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_RA_2_9_LEN = 3923;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_RA_0_1 = 3924;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_RA_0_1_LEN = 3925;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_BNK_0_2 = 3926;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_BNK_0_2_LEN = 3927;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_DW = 3928;
static const uint64_t IDX_CEN_MBCELOGQ_EDRAM_DW_LEN = 3929;
static const uint64_t IDX_CEN_MBCPGQ_CFG_MBC_MEMBER_DIS = 3930;
static const uint64_t IDX_CEN_MBCPGQ_CFG_MBC_MEMBER_DIS_LEN = 3931;
static const uint64_t IDX_CEN_MBCPGQ_CFG_MBC_PARTIAL_GOOD_DIS = 3932;
static const uint64_t IDX_CEN_MBCPGQ_EVEN_DIS = 3933;
static const uint64_t IDX_CEN_MBCPGQ_ODD_DIS = 3934;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_ENTIRE_CACHE = 3935;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_RANGE = 3936;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_SINGLE_MEMBER_AND_INVALIDATE = 3937;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_SINGLE_MEMBER_AND_DELETE = 3938;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_START_MEMBER = 3939;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_START_MEMBER_LEN = 3940;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_START_CGC = 3941;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_START_CGC_LEN = 3942;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_END_MEMBER = 3943;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_END_MEMBER_LEN = 3944;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_END_CGC = 3945;
static const uint64_t IDX_CEN_MBCPRGQ_PURGE_CACHE_END_CGC_LEN = 3946;
static const uint64_t IDX_CEN_MBCPRGSQ_MAX_DELETED_MEMBERS = 3947;
static const uint64_t IDX_CEN_MBCPRGSQ_MAX_DELETED_MEMBERS_LEN = 3948;
static const uint64_t IDX_CEN_MBCPRGSQ_PURGE_ENGINE_IS_BUSY = 3949;
static const uint64_t IDX_CEN_MBCPRGSQ_PURGE_CMD_ERROR = 3950;
static const uint64_t IDX_CEN_MBCPRGSQ_PURGE_CACHE_ADDRESS_16_32 = 3951;
static const uint64_t IDX_CEN_MBCPRGSQ_PURGE_CACHE_ADDRESS_16_32_LEN = 3952;
static const uint64_t IDX_CEN_MBCPRGSQ_RSVD = 3953;
static const uint64_t IDX_CEN_MBSACUMQ_HCA_DECAY_UPDATE_EVENDW = 3954;
static const uint64_t IDX_CEN_MBSACUMQ_HCA_DECAY_UPDATE_EVENDW_LEN = 3955;
static const uint64_t IDX_CEN_MBSACUMQ_HCA_DECAY_UPDATE_ODDDW = 3956;
static const uint64_t IDX_CEN_MBSACUMQ_HCA_DECAY_UPDATE_ODDDW_LEN = 3957;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD0_RP0_CE = 3958;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD0_RP0_UE = 3959;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD0_RP0_SUE = 3960;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD1_RP0_CE = 3961;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD1_RP0_UE = 3962;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD1_RP0_SUE = 3963;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD0_RP1_CE = 3964;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD0_RP1_UE = 3965;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD0_RP1_SUE = 3966;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD1_RP1_CE = 3967;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD1_RP1_UE = 3968;
static const uint64_t IDX_CEN_MBSCERR1Q_MBCD1_RP1_SUE = 3969;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP0_EVEN_CE = 3970;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP0_EVEN_UE = 3971;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP0_EVEN_SUE = 3972;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP0_ODD_CE = 3973;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP0_ODD_UE = 3974;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP0_ODD_SUE = 3975;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP1_EVEN_CE = 3976;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP1_EVEN_UE = 3977;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP1_EVEN_SUE = 3978;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP1_ODD_CE = 3979;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP1_ODD_UE = 3980;
static const uint64_t IDX_CEN_MBSCERR1Q_SRB_RP1_ODD_SUE = 3981;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB0_CE = 3982;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB0_UE = 3983;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB0_SUE = 3984;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB1_CE = 3985;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB1_UE = 3986;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB1_SUE = 3987;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB2_CE = 3988;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB2_UE = 3989;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB2_SUE = 3990;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB3_CE = 3991;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB3_UE = 3992;
static const uint64_t IDX_CEN_MBSCERR1Q_PFB3_SUE = 3993;
static const uint64_t IDX_CEN_MBSCERR1Q_WRQA01_PE = 3994;
static const uint64_t IDX_CEN_MBSCERR1Q_WRQA23_PE = 3995;
static const uint64_t IDX_CEN_MBSCERR1Q_SRWADD_PE = 3996;
static const uint64_t IDX_CEN_MBSCERR1Q_DADDP_PE = 3997;
static const uint64_t IDX_CEN_MBSCERR1Q_SWPAB_PE = 3998;
static const uint64_t IDX_CEN_MBSCERR1Q_SWB_EVEN_CE = 3999;
static const uint64_t IDX_CEN_MBSCERR1Q_SWB_EVEN_UE = 4000;
static const uint64_t IDX_CEN_MBSCERR1Q_SWB_EVEN_SUE = 4001;
static const uint64_t IDX_CEN_MBSCERR1Q_SWB_ODD_CE = 4002;
static const uint64_t IDX_CEN_MBSCERR1Q_SWB_ODD_UE = 4003;
static const uint64_t IDX_CEN_MBSCERR1Q_SWB_ODD_SUE = 4004;
static const uint64_t IDX_CEN_MBSCERR1Q_SRW_PWRT_SIZE_ERR = 4005;
static const uint64_t IDX_CEN_MBSCERR1Q_WBMGR_WRQ01_IDX_ERR = 4006;
static const uint64_t IDX_CEN_MBSCERR1Q_WBMGR_WRQ23_IDX_ERR = 4007;
static const uint64_t IDX_CEN_MBSCERR1Q_CLNFSM_TIMEOUT_ERR = 4008;
static const uint64_t IDX_CEN_MBSCERR1Q_COADD_ADDR_ERR = 4009;
static const uint64_t IDX_CEN_MBSCERR1Q_DIR_ADDR_PARITY_ERR = 4010;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_INVALID_DS_CMD_ERR = 4011;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_INVALID_ADDR_ERR = 4012;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_INVALID_CAC_ONLY_ERR = 4013;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_LRU_ID_ERR = 4014;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_RRQ01_CNT_PARITY_ERR = 4015;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_RRQ23_CNT_PARITY_ERR = 4016;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_RRQ01_OVERFLOW_ERR = 4017;
static const uint64_t IDX_CEN_MBSCERR1Q_DISP_RRQ23_OVERFLOW_ERR = 4018;
static const uint64_t IDX_CEN_MBSCERR1Q_RESERVED_61_63 = 4019;
static const uint64_t IDX_CEN_MBSCERR1Q_RESERVED_61_63_LEN = 4020;
static const uint64_t IDX_CEN_MBSCERR2Q_PFFSM_TIMEOUT = 4021;
static const uint64_t IDX_CEN_MBSCERR2Q_PRQ_PROTOCOL_ERR = 4022;
static const uint64_t IDX_CEN_MBSCERR2Q_PFFSM_PROTOCOL_ERR = 4023;
static const uint64_t IDX_CEN_MBSCERR2Q_PFARB_PROTOCOL_ERR = 4024;
static const uint64_t IDX_CEN_MBSCERR2Q_SRWFSM_UNEXPECTED_DS_CRESP = 4025;
static const uint64_t IDX_CEN_MBSCERR2Q_SRWFSM_UNEXPECTED_DS_CMD = 4026;
static const uint64_t IDX_CEN_MBSCERR2Q_SRWFSM_EXT_TIMOUT = 4027;
static const uint64_t IDX_CEN_MBSCERR2Q_SRWFSM_INT_TIMEOUT = 4028;
static const uint64_t IDX_CEN_MBSCERR2Q_SRWFSM_PURGE_LINE_DEL = 4029;
static const uint64_t IDX_CEN_MBSCERR2Q_SRWFSM_PURGE_CLEAN_UE = 4030;
static const uint64_t IDX_CEN_MBSCERR2Q_SRWFSM_PURGE_DIRTY_UE = 4031;
static const uint64_t IDX_CEN_MBSCERR2Q_SWDONE_WDONE_P_ERR = 4032;
static const uint64_t IDX_CEN_MBSCERR2Q_SWPAB_DS_TSIZE_ERR_HOLD = 4033;
static const uint64_t IDX_CEN_MBSCERR2Q_SWB_DS_WDATA_ERR0_HOLD = 4034;
static const uint64_t IDX_CEN_MBSCERR2Q_SWB_DS_WDATA_ERR1_HOLD = 4035;
static const uint64_t IDX_CEN_MBSCERR2Q_MBX_MBS_RDTAG_PERR = 4036;
static const uint64_t IDX_CEN_MBSCERR2Q_RDTAG_FIFO_PERR = 4037;
static const uint64_t IDX_CEN_MBSCERR2Q_DS_FRAME_SEG_ERR = 4038;
static const uint64_t IDX_CEN_MBSCERR2Q_DS_INVALID_DATA_SUE_ERR = 4039;
static const uint64_t IDX_CEN_MBSCERR2Q_US_READ_DATA_PERR = 4040;
static const uint64_t IDX_CEN_MBSCERR2Q_US_READ_DATA_INFO_PERR = 4041;
static const uint64_t IDX_CEN_MBSCERR2Q_IBB_CE = 4042;
static const uint64_t IDX_CEN_MBSCERR2Q_IBB_UE = 4043;
static const uint64_t IDX_CEN_MBSCERR2Q_IBB_SUE = 4044;
static const uint64_t IDX_CEN_MBSCERR2Q_IBB_DS_CE = 4045;
static const uint64_t IDX_CEN_MBSCERR2Q_IBB_DS_PROTOCOL_ERR = 4046;
static const uint64_t IDX_CEN_MBSCERR2Q_CLNFSM_SCOMFIR_CERR_HOLD = 4047;
static const uint64_t IDX_CEN_MBSCERR2Q_SPARE = 4048;
static const uint64_t IDX_CEN_MBSCERR2Q_RXLT_SIR_PERR = 4049;
static const uint64_t IDX_CEN_MBSCERR2Q_CACTL_ADDRESS_ERR = 4050;
static const uint64_t IDX_CEN_MBSCERR2Q_EMER_THROTTLE_CERR = 4051;
static const uint64_t IDX_CEN_MBSCERR2Q_MAX_LINE_DEL_ERR = 4052;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD0_DW02_13BNK_DRAM_ERR = 4053;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD0_DW46_57BNK_ERR = 4054;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD0_DW8A_9BBNK_ERR = 4055;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD0_DWCE_DFBNK_ERR = 4056;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD1_DW02_13BNK_ERR = 4057;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD1_DW46_57BNK_ERR = 4058;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD1_DW8A_9BBNK_ERR = 4059;
static const uint64_t IDX_CEN_MBSCERR2Q_MBCD1_DWCE_DFBNK_ERR = 4060;
static const uint64_t IDX_CEN_MBSCERR2Q_RXLAT_PERR = 4061;
static const uint64_t IDX_CEN_MBSCERR2Q_CLNADD_PERR = 4062;
static const uint64_t IDX_CEN_MBSCERR2Q_COADDR_PERR = 4063;
static const uint64_t IDX_CEN_MBSCERR2Q_PFADDR_PERR = 4064;
static const uint64_t IDX_CEN_MBSCERR2Q_PRQADDR_PERR = 4065;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SWB_DW0_CE = 4066;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SWB_DW0_UE = 4067;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SWB_DW0_SUE = 4068;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SWB_DW1_CE = 4069;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SWB_DW1_UE = 4070;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SWB_DW1_SUE = 4071;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SRB_DW0_CE = 4072;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SRB_DW0_UE = 4073;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SRB_DW0_SUE = 4074;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SRB_DW1_CE = 4075;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SRB_DW1_UE = 4076;
static const uint64_t IDX_CEN_MBSCERR2Q_WDF_SRB_DW1_SUE = 4077;
static const uint64_t IDX_CEN_MBSCERR2Q_US_DTAG_PERR = 4078;
static const uint64_t IDX_CEN_MBSCERR2Q_US_DONE_PERR = 4079;
static const uint64_t IDX_CEN_MBSCERR2Q_DS_WDAT0_PERR = 4080;
static const uint64_t IDX_CEN_MBSCERR2Q_DS_WDAT1_PERR = 4081;
static const uint64_t IDX_CEN_MBSCERR2Q_DIR_DCECK_PERR = 4082;
static const uint64_t IDX_CEN_MBSCERR2Q_SRB_INFO_PERR = 4083;
static const uint64_t IDX_CEN_MBSCERR2Q_RESERVED_63 = 4084;
static const uint64_t IDX_CEN_MBSCFGQ_ECCBP_EXIT_SEL = 4085;
static const uint64_t IDX_CEN_MBSCFGQ_DRAM_ECC_BYPASS_DIS = 4086;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_SCOM_WAT_TRIGGER = 4087;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_PRQ_REF_AVOIDANCE_EN = 4088;
static const uint64_t IDX_CEN_MBSCFGQ_RSV4_6 = 4089;
static const uint64_t IDX_CEN_MBSCFGQ_RSV4_6_LEN = 4090;
static const uint64_t IDX_CEN_MBSCFGQ_OCC_DEADMAN_TIMER_SEL = 4091;
static const uint64_t IDX_CEN_MBSCFGQ_OCC_DEADMAN_TIMER_SEL_LEN = 4092;
static const uint64_t IDX_CEN_MBSCFGQ_SYNC_FSYNC_MBA_STROBE_EN = 4093;
static const uint64_t IDX_CEN_MBSCFGQ_HCA_TIMEBASE_OP_MODE = 4094;
static const uint64_t IDX_CEN_MBSCFGQ_HCA_LOCAL_TIMER_INC_SELECT = 4095;
static const uint64_t IDX_CEN_MBSCFGQ_HCA_LOCAL_TIMER_INC_SELECT_LEN = 4096;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_01_RDTAG_DELAY = 4097;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_01_RDTAG_DELAY_LEN = 4098;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_01_RDTAG_FORCE_DEAD_CYCLE = 4099;
static const uint64_t IDX_CEN_MBSCFGQ_SYNC_LAT_POL_01 = 4100;
static const uint64_t IDX_CEN_MBSCFGQ_SYNC_LAT_ADJ_01 = 4101;
static const uint64_t IDX_CEN_MBSCFGQ_SYNC_LAT_ADJ_01_LEN = 4102;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_23_RDTAG_DELAY = 4103;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_23_RDTAG_DELAY_LEN = 4104;
static const uint64_t IDX_CEN_MBSCFGQ_MBS_23_RDTAG_FORCE_DEAD_CYCLE = 4105;
static const uint64_t IDX_CEN_MBSCFGQ_SYNC_LAT_POL_23 = 4106;
static const uint64_t IDX_CEN_MBSCFGQ_SYNC_LAT_ADJ_23 = 4107;
static const uint64_t IDX_CEN_MBSCFGQ_SYNC_LAT_ADJ_23_LEN = 4108;
static const uint64_t IDX_CEN_MBSDBG0CTLQ_DEBUG_SOURCE = 4109;
static const uint64_t IDX_CEN_MBSDBG0CTLQ_DEBUG_SOURCE_LEN = 4110;
static const uint64_t IDX_CEN_MBSDBG0CTLQ_PENDING_SEL = 4111;
static const uint64_t IDX_CEN_MBSDBG0CTLQ_PENDING_SEL_LEN = 4112;
static const uint64_t IDX_CEN_MBSDBG0CTLQ_DEBUG_ENABLE = 4113;
static const uint64_t IDX_CEN_MBSDBG0DATQ_DEBUG_DATA = 4114;
static const uint64_t IDX_CEN_MBSDBG0DATQ_DEBUG_DATA_LEN = 4115;
static const uint64_t IDX_CEN_MBSDBG1CTLQ_DEBUG_SOURCE = 4116;
static const uint64_t IDX_CEN_MBSDBG1CTLQ_DEBUG_SOURCE_LEN = 4117;
static const uint64_t IDX_CEN_MBSDBG1DATQ_DEBUG_DATA = 4118;
static const uint64_t IDX_CEN_MBSDBG1DATQ_DEBUG_DATA_LEN = 4119;
static const uint64_t IDX_CEN_MBSDBGXDATQ_DEBUG0_EXTENDED = 4120;
static const uint64_t IDX_CEN_MBSDBGXDATQ_DEBUG0_EXTENDED_LEN = 4121;
static const uint64_t IDX_CEN_MBSDBGXDATQ_DEBUG1_EXTENDED = 4122;
static const uint64_t IDX_CEN_MBSDBGXDATQ_DEBUG1_EXTENDED_LEN = 4123;
static const uint64_t IDX_CEN_MBSEINJQ_CACHE_WP0_ERR_INJECT_MODE = 4124;
static const uint64_t IDX_CEN_MBSEINJQ_CACHE_WP0_ERR_INJECT_CE = 4125;
static const uint64_t IDX_CEN_MBSEINJQ_CACHE_WP0_ERR_INJECT_UE = 4126;
static const uint64_t IDX_CEN_MBSEINJQ_CACHE_WP0_ERR_INJECT_SUE = 4127;
static const uint64_t IDX_CEN_MBSEINJQ_DIRECTORY_ERR_INJECT_MODE = 4128;
static const uint64_t IDX_CEN_MBSEINJQ_DIRECTORY_ERR_INJECT_CE = 4129;
static const uint64_t IDX_CEN_MBSEINJQ_DIRECTORY_ERR_INJECT_UE = 4130;
static const uint64_t IDX_CEN_MBSEINJQ_SWB_ERR_INJECT_MODE = 4131;
static const uint64_t IDX_CEN_MBSEINJQ_SWB_ERR_INJECT_CE = 4132;
static const uint64_t IDX_CEN_MBSEINJQ_SWB_ERR_INJECT_UE = 4133;
static const uint64_t IDX_CEN_MBSEINJQ_SRB_RP0_ERR_INJECT_MODE = 4134;
static const uint64_t IDX_CEN_MBSEINJQ_SRB_RP0_ERR_INJECT_CE = 4135;
static const uint64_t IDX_CEN_MBSEINJQ_SRB_RP0_ERR_INJECT_UE = 4136;
static const uint64_t IDX_CEN_MBSEINJQ_SRB_RP1_ERROR_INJECT_MODE = 4137;
static const uint64_t IDX_CEN_MBSEINJQ_SRB_RP1_ERROR_INJECT_CE = 4138;
static const uint64_t IDX_CEN_MBSEINJQ_SRB_RP1_ERROR_INJECT_UE = 4139;
static const uint64_t IDX_CEN_MBSEINJQ_PFB_ERR_INJECT_MODE = 4140;
static const uint64_t IDX_CEN_MBSEINJQ_PFB_ERR_INJECT_CE = 4141;
static const uint64_t IDX_CEN_MBSEINJQ_PFB_ERR_INJECT_UE = 4142;
static const uint64_t IDX_CEN_MBSEINJQ_SPWA_ERR_INJECT_MODE = 4143;
static const uint64_t IDX_CEN_MBSEINJQ_SPWA_ERR_INJECT_PERR = 4144;
static const uint64_t IDX_CEN_MBSEINJQ_CO_ERR_INJECT_MODE = 4145;
static const uint64_t IDX_CEN_MBSEINJQ_CO_ERR_INJECT_CE = 4146;
static const uint64_t IDX_CEN_MBSEINJQ_CO_ERR_INJECT_UE = 4147;
static const uint64_t IDX_CEN_MBSEINJQ_INT_RESET_KEEPER = 4148;
static const uint64_t IDX_CEN_MBSEINJQ_RESERVED_25 = 4149;
static const uint64_t IDX_CEN_MBSEINJQ_RESERVED_26 = 4150;
static const uint64_t IDX_CEN_MBSEINJQ_IB_BFR_ERR_INJECT_MODE = 4151;
static const uint64_t IDX_CEN_MBSEINJQ_IB_BFR_ERR_INJECT_CE = 4152;
static const uint64_t IDX_CEN_MBSEINJQ_IB_BFR_ERR_INJECT_UE = 4153;
static const uint64_t IDX_CEN_MBSEINJQ_DIRECTORY_ERR_INJECT_ADDR_PERR = 4154;
static const uint64_t IDX_CEN_MBSEINJQ_RRQ_POP_INJECT = 4155;
static const uint64_t IDX_CEN_MBSEINJQ_RRQ_POP_INJECT_PERR = 4156;
static const uint64_t IDX_CEN_MBSEINJQ_SHORT_HANG_TIMER = 4157;
static const uint64_t IDX_CEN_MBSEINJQ_LRU_ERR_INJ = 4158;
static const uint64_t IDX_CEN_MBSEMERTHROQ_EMERGENCY_THROTTLE_IN_PROGRESS = 4159;
static const uint64_t IDX_CEN_MBSIBERR0Q_IB_HOST_ADDRESS = 4160;
static const uint64_t IDX_CEN_MBSIBERR0Q_IB_HOST_ADDRESS_LEN = 4161;
static const uint64_t IDX_CEN_MBSIBERR0Q_IB_HOST_ERROR_VALID = 4162;
static const uint64_t IDX_CEN_MBSIBERR0Q_IB_HOST_ERROR_STATUS = 4163;
static const uint64_t IDX_CEN_MBSIBERR0Q_IB_HOST_ERROR_STATUS_LEN = 4164;
static const uint64_t IDX_CEN_MBSIBERR0Q_IB_HOST_WRITE_NOT_READ = 4165;
static const uint64_t IDX_CEN_MBSIBERR1Q_OCC_IB_ADDRESS = 4166;
static const uint64_t IDX_CEN_MBSIBERR1Q_OCC_IB_ADDRESS_LEN = 4167;
static const uint64_t IDX_CEN_MBSIBERR1Q_OCC_IB_ERROR_VALID = 4168;
static const uint64_t IDX_CEN_MBSIBERR1Q_OCC_IB_ERROR_STATUS = 4169;
static const uint64_t IDX_CEN_MBSIBERR1Q_OCC_IB_ERROR_STATUS_LEN = 4170;
static const uint64_t IDX_CEN_MBSIBERR1Q_OCC_IB_WRITE_NOT_READ = 4171;
static const uint64_t IDX_CEN_MBSIBWRSTATQ_SPARE0 = 4172;
static const uint64_t IDX_CEN_MBSIBWRSTATQ_SPARE0_LEN = 4173;
static const uint64_t IDX_CEN_MBSOCC01HQ_OCC_01_RD_HIT = 4174;
static const uint64_t IDX_CEN_MBSOCC01HQ_OCC_01_RD_HIT_LEN = 4175;
static const uint64_t IDX_CEN_MBSOCC01HQ_OCC_01_WR_HIT = 4176;
static const uint64_t IDX_CEN_MBSOCC01HQ_OCC_01_WR_HIT_LEN = 4177;
static const uint64_t IDX_CEN_MBSOCC23HQ_OCC_23_RD_HIT = 4178;
static const uint64_t IDX_CEN_MBSOCC23HQ_OCC_23_RD_HIT_LEN = 4179;
static const uint64_t IDX_CEN_MBSOCC23HQ_OCC_23_WR_HIT = 4180;
static const uint64_t IDX_CEN_MBSOCC23HQ_OCC_23_WR_HIT_LEN = 4181;
static const uint64_t IDX_CEN_MBSOCCITCQ_OCC_CENT_IDLE_TH_CNT = 4182;
static const uint64_t IDX_CEN_MBSOCCITCQ_OCC_CENT_IDLE_TH_CNT_LEN = 4183;
static const uint64_t IDX_CEN_MBSOCCSCANQ_OCC_01_SPEC_CAN = 4184;
static const uint64_t IDX_CEN_MBSOCCSCANQ_OCC_01_SPEC_CAN_LEN = 4185;
static const uint64_t IDX_CEN_MBSOCCSCANQ_OCC_23_SPEC_CAN = 4186;
static const uint64_t IDX_CEN_MBSOCCSCANQ_OCC_23_SPEC_CAN_LEN = 4187;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER0_ENABLE = 4188;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER1_ENABLE = 4189;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER2_ENABLE = 4190;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER3_ENABLE = 4191;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_PRESCALER_SEL = 4192;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_PRESCALER_SEL_LEN = 4193;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER_FREEZE_MODE = 4194;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER_RESET_MODE = 4195;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER0_EVENT_SEL = 4196;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER0_EVENT_SEL_LEN = 4197;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER0_POSEDGE_SEL = 4198;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER0_BIT_PAIR_SEL = 4199;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER0_BIT_PAIR_SEL_LEN = 4200;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER1_EVENT_SEL = 4201;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER1_EVENT_SEL_LEN = 4202;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER1_POSEDGE_SEL = 4203;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER1_BIT_PAIR_SEL = 4204;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER1_BIT_PAIR_SEL_LEN = 4205;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER2_EVENT_SEL = 4206;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER2_EVENT_SEL_LEN = 4207;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER2_POSEDGE_SEL = 4208;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER2_BIT_PAIR_SEL = 4209;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER2_BIT_PAIR_SEL_LEN = 4210;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER3_EVENT_SEL = 4211;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER3_EVENT_SEL_LEN = 4212;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER3_POSEDGE_SEL = 4213;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER3_BIT_PAIR_SEL = 4214;
static const uint64_t IDX_CEN_MBSPMU0CFGQ_PMU0_COUNTER3_BIT_PAIR_SEL_LEN = 4215;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT0 = 4216;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT0_LEN = 4217;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT1 = 4218;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT1_LEN = 4219;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT2 = 4220;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT2_LEN = 4221;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT3 = 4222;
static const uint64_t IDX_CEN_MBSPMU0CNTQ_PMU0_CNT3_LEN = 4223;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT0_IN_SEL = 4224;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT0_IN_SEL_LEN = 4225;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT1_IN_SEL = 4226;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT1_IN_SEL_LEN = 4227;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT2_IN_SEL = 4228;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT2_IN_SEL_LEN = 4229;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT3_IN_SEL = 4230;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT3_IN_SEL_LEN = 4231;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT4_IN_SEL = 4232;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT4_IN_SEL_LEN = 4233;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT5_SIN_EL = 4234;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT5_SIN_EL_LEN = 4235;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT6_IN_SEL = 4236;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT6_IN_SEL_LEN = 4237;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT7_IN_SEL = 4238;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_EVENT7_IN_SEL_LEN = 4239;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_RANK_FILTER_EN = 4240;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_RANK_FILTER = 4241;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_RANK_FILTER_LEN = 4242;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_SPARE = 4243;
static const uint64_t IDX_CEN_MBSPMUSELQ_PMU_SPARE_LEN = 4244;
static const uint64_t IDX_CEN_MBSSQ_ALL_QUEUES_EMPTY = 4245;
static const uint64_t IDX_CEN_MBSSQ_ECCBP_EXIT1_SELECTED = 4246;
static const uint64_t IDX_CEN_MBSSQ_IML_COMPLETE = 4247;
static const uint64_t IDX_CEN_MBS_FIR_ACTION0_REG_ACTION0 = 4248;
static const uint64_t IDX_CEN_MBS_FIR_ACTION0_REG_ACTION0_LEN = 4249;
static const uint64_t IDX_CEN_MBS_FIR_ACTION1_REG_ACTION1 = 4250;
static const uint64_t IDX_CEN_MBS_FIR_ACTION1_REG_ACTION1_LEN = 4251;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_HOST_PROTOCOL_ERROR = 4252;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INT_PROTOCOL_ERROR = 4253;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INVALID_ADDRESS_ERROR = 4254;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_EXTERNAL_TIMEOUT = 4255;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INTERNAL_TIMEOUT = 4256;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INT_BUFFER_CE = 4257;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INT_BUFFER_UE = 4258;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INT_BUFFER_SUE = 4259;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INT_PARITY_ERROR = 4260;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_CACHE_SRW_CE = 4261;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_CACHE_SRW_UE = 4262;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_CACHE_SRW_SUE = 4263;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_CACHE_CO_CE = 4264;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_CACHE_CO_UE = 4265;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_CACHE_CO_SUE = 4266;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_DIR_CE = 4267;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_DIR_UE = 4268;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_DIR_MEMBER_DELETED = 4269;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_DIR_ALL_MEMBERS_DELETED = 4270;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_LRU_ERROR = 4271;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_EDRAM_ERROR = 4272;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_EMERGENCY_THROTTLE_SET = 4273;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_HOST_INBAND_READ_ERROR = 4274;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_HOST_INBAND_WRITE_ERROR = 4275;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_OCC_INBAND_READ_ERROR = 4276;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_OCC_INBAND_WRITE_ERROR = 4277;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_SRB_BUFFER_CE = 4278;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_SRB_BUFFER_UE = 4279;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_SRB_BUFFER_SUE = 4280;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_DIR_PURGE_CE = 4281;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_PROXIMAL_CE_UE = 4282;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_SPARE_FIR31 = 4283;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_SPARE_FIR32 = 4284;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 4285;
static const uint64_t IDX_CEN_MBS_FIR_MASK_REG_INTERNAL_SCOM_ERROR_COPY = 4286;
static const uint64_t IDX_CEN_MBS_FIR_REG_HOST_PROTOCOL_ERROR = 4287;
static const uint64_t IDX_CEN_MBS_FIR_REG_INT_PROTOCOL_ERROR = 4288;
static const uint64_t IDX_CEN_MBS_FIR_REG_INVALID_ADDRESS_ERROR = 4289;
static const uint64_t IDX_CEN_MBS_FIR_REG_EXTERNAL_TIMEOUT = 4290;
static const uint64_t IDX_CEN_MBS_FIR_REG_INTERNAL_TIMEOUT = 4291;
static const uint64_t IDX_CEN_MBS_FIR_REG_INT_BUFFER_CE = 4292;
static const uint64_t IDX_CEN_MBS_FIR_REG_INT_BUFFER_UE = 4293;
static const uint64_t IDX_CEN_MBS_FIR_REG_INT_BUFFER_SUE = 4294;
static const uint64_t IDX_CEN_MBS_FIR_REG_INT_PARITY_ERROR = 4295;
static const uint64_t IDX_CEN_MBS_FIR_REG_CACHE_SRW_CE = 4296;
static const uint64_t IDX_CEN_MBS_FIR_REG_CACHE_SRW_UE = 4297;
static const uint64_t IDX_CEN_MBS_FIR_REG_CACHE_SRW_SUE = 4298;
static const uint64_t IDX_CEN_MBS_FIR_REG_CACHE_CO_CE = 4299;
static const uint64_t IDX_CEN_MBS_FIR_REG_CACHE_CO_UE = 4300;
static const uint64_t IDX_CEN_MBS_FIR_REG_CACHE_CO_SUE = 4301;
static const uint64_t IDX_CEN_MBS_FIR_REG_DIR_CE = 4302;
static const uint64_t IDX_CEN_MBS_FIR_REG_DIR_UE = 4303;
static const uint64_t IDX_CEN_MBS_FIR_REG_DIR_MEMBER_DELETED = 4304;
static const uint64_t IDX_CEN_MBS_FIR_REG_DIR_ALL_MEMBERS_DELETED = 4305;
static const uint64_t IDX_CEN_MBS_FIR_REG_LRU_ERROR = 4306;
static const uint64_t IDX_CEN_MBS_FIR_REG_EDRAM_ERROR = 4307;
static const uint64_t IDX_CEN_MBS_FIR_REG_EMERGENCY_THROTTLE_SET = 4308;
static const uint64_t IDX_CEN_MBS_FIR_REG_HOST_INBAND_READ_ERROR = 4309;
static const uint64_t IDX_CEN_MBS_FIR_REG_HOST_INBAND_WRITE_ERROR = 4310;
static const uint64_t IDX_CEN_MBS_FIR_REG_OCC_INBAND_READ_ERROR = 4311;
static const uint64_t IDX_CEN_MBS_FIR_REG_OCC_INBAND_WRITE_ERROR = 4312;
static const uint64_t IDX_CEN_MBS_FIR_REG_SRB_BUFFER_CE = 4313;
static const uint64_t IDX_CEN_MBS_FIR_REG_SRB_BUFFER_UE = 4314;
static const uint64_t IDX_CEN_MBS_FIR_REG_SRB_BUFFER_SUE = 4315;
static const uint64_t IDX_CEN_MBS_FIR_REG_DIR_PURGE_CE = 4316;
static const uint64_t IDX_CEN_MBS_FIR_REG_PROXIMAL_CE_UE = 4317;
static const uint64_t IDX_CEN_MBS_FIR_REG_SPARE_FIR31 = 4318;
static const uint64_t IDX_CEN_MBS_FIR_REG_SPARE_FIR32 = 4319;
static const uint64_t IDX_CEN_MBS_FIR_REG_INTERNAL_SCOM_ERROR = 4320;
static const uint64_t IDX_CEN_MBS_FIR_REG_INTERNAL_SCOM_ERROR_COPY = 4321;
static const uint64_t IDX_CEN_MBS_FIR_WOF_WOF = 4322;
static const uint64_t IDX_CEN_MBS_FIR_WOF_WOF_LEN = 4323;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_CONFIG_TYPE = 4324;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_CONFIG_TYPE_LEN = 4325;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_CONFIG_SUBTYPE = 4326;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_CONFIG_SUBTYPE_LEN = 4327;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_DRAM_SIZE = 4328;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_DRAM_SIZE_LEN = 4329;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_CONFIGURATION = 4330;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_DRAM_WIDTH = 4331;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_HASH_MODE = 4332;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_HASH_MODE_LEN = 4333;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_INTERLEAVE_MODE = 4334;
static const uint64_t IDX_CEN_MBAXCR01Q_MBA01_SLOT1_ONLY = 4335;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_CONFIG_TYPE = 4336;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_CONFIG_TYPE_LEN = 4337;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_CONFIG_SUBTYPE = 4338;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_CONFIG_SUBTYPE_LEN = 4339;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_DRAM_SIZE = 4340;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_DRAM_SIZE_LEN = 4341;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_CONFIGURATION = 4342;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_DRAM_WIDTH = 4343;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_HASH_MODE = 4344;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_HASH_MODE_LEN = 4345;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_INTERLEAVE_MODE = 4346;
static const uint64_t IDX_CEN_MBAXCR23Q_MBA23_SLOT1_ONLY = 4347;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_MASTER_RANK_0_SELECT = 4348;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_MASTER_RANK_0_SELECT_LEN = 4349;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_MASTER_RANK_1_SELECT = 4350;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_MASTER_RANK_1_SELECT_LEN = 4351;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_MASTER_RANK_2_SELECT = 4352;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_MASTER_RANK_2_SELECT_LEN = 4353;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_SLAVE_RANK_0_SELECT = 4354;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_SLAVE_RANK_0_SELECT_LEN = 4355;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_SLAVE_RANK_1_SELECT = 4356;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_SLAVE_RANK_1_SELECT_LEN = 4357;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_SLAVE_RANK_2_SELECT = 4358;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_SLAVE_RANK_2_SELECT_LEN = 4359;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_B2_DDR3_B0_DDR4_SELECT = 4360;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_B2_DDR3_B0_DDR4_SELECT_LEN = 4361;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_B0_DDR3_B1_DDR4_SELECT = 4362;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA01_B0_DDR3_B1_DDR4_SELECT_LEN = 4363;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_MASTER_RANK_0_SELECT = 4364;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_MASTER_RANK_0_SELECT_LEN = 4365;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_MASTER_RANK_1_SELECT = 4366;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_MASTER_RANK_1_SELECT_LEN = 4367;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_MASTER_RANK_2_SELECT = 4368;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_MASTER_RANK_2_SELECT_LEN = 4369;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_SLAVE_RANK_0_SELECT = 4370;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_SLAVE_RANK_0_SELECT_LEN = 4371;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_SLAVE_RANK_1_SELECT = 4372;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_SLAVE_RANK_1_SELECT_LEN = 4373;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_SLAVE_RANK_2_SELECT = 4374;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_SLAVE_RANK_2_SELECT_LEN = 4375;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_B2_DDR3_B0_DDR4_SELECT = 4376;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_B2_DDR3_B0_DDR4_SELECT_LEN = 4377;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_B0_DDR3_B1_DDR4_SELECT = 4378;
static const uint64_t IDX_CEN_MBAXCRMSQ_MBA23_B0_DDR3_B1_DDR4_SELECT_LEN = 4379;
static const uint64_t IDX_CEN_MBSSIRACT0_ACTION_0 = 4380;
static const uint64_t IDX_CEN_MBSSIRACT0_ACTION_0_LEN = 4381;
static const uint64_t IDX_CEN_MBSSIRACT1_ACTION_1 = 4382;
static const uint64_t IDX_CEN_MBSSIRACT1_ACTION_1_LEN = 4383;
static const uint64_t IDX_CEN_MBSSIRMASK_INVALID_MBSXCR_ACCESS = 4384;
static const uint64_t IDX_CEN_MBSSIRMASK_INVALID_MBAXCR01_ACCESS = 4385;
static const uint64_t IDX_CEN_MBSSIRMASK_INVALID_MBAXCR23_ACCESS = 4386;
static const uint64_t IDX_CEN_MBSSIRMASK_INVALID_MBAXCRMS_ACCRESS = 4387;
static const uint64_t IDX_CEN_MBSSIRMASK_SPARE = 4388;
static const uint64_t IDX_CEN_MBSSIRMASK_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS = 4389;
static const uint64_t IDX_CEN_MBSSIRQ_INVALID_MBSXCR_ACCESS = 4390;
static const uint64_t IDX_CEN_MBSSIRQ_INVALID_MBAXCR01_ACCESS = 4391;
static const uint64_t IDX_CEN_MBSSIRQ_INVALID_MBAXCR23_ACCESS = 4392;
static const uint64_t IDX_CEN_MBSSIRQ_INVALID_MBAXCRMS_ACCRESS = 4393;
static const uint64_t IDX_CEN_MBSSIRQ_SPARE = 4394;
static const uint64_t IDX_CEN_MBSSIRQ_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS = 4395;
static const uint64_t IDX_CEN_MBSXCRQ_MBA_ADDRESS_INTERLEAVE_MODE = 4396;
static const uint64_t IDX_CEN_MBSXCRQ_MBA_ADDRESS_INTERLEAVE_MODE_LEN = 4397;
static const uint64_t IDX_CEN_MBSXCRQ_Z_MODE_CENTAUR_ADDR4_SELECT = 4398;
static const uint64_t IDX_CEN_MBSXCRQ_USE_ALT_CLEANER_CONFIG = 4399;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_CLEANER_RANK_TYPE = 4400;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_CLEANER_RANK_TYPE_LEN = 4401;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_CLEANER_MRANK0 = 4402;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_CLEANER_MRANK0_LEN = 4403;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_CLEANER_MRANK1 = 4404;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_CLEANER_MRANK1_LEN = 4405;
static const uint64_t IDX_CEN_MBSXCRQ_USE_ALT_PREFETCH_CONFIG = 4406;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_PREFETCH_RANK_LOCATION = 4407;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_PREFETCH_RANK_LOCATION_LEN = 4408;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_PREFETCH_RANK_TYPE = 4409;
static const uint64_t IDX_CEN_MBSXCRQ_ALT_PREFETCH_RANK_TYPE_LEN = 4410;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_0 = 4411;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_1 = 4412;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_2 = 4413;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_3 = 4414;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_4 = 4415;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_5 = 4416;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_6 = 4417;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_22 = 4418;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDRESS_MASK_30 = 4419;
static const uint64_t IDX_CEN_MBSXCRQ_RESERVED_30_31 = 4420;
static const uint64_t IDX_CEN_MBSXCRQ_RESERVED_30_31_LEN = 4421;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR2_SELECT = 4422;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR2_SELECT_LEN = 4423;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR3_SELECT = 4424;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR3_SELECT_LEN = 4425;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR4_SELECT = 4426;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR4_SELECT_LEN = 4427;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR5_SELECT = 4428;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR5_SELECT_LEN = 4429;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR6_SELECT = 4430;
static const uint64_t IDX_CEN_MBSXCRQ_CENTAUR_ADDR6_SELECT_LEN = 4431;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_MASTER_RANK0 = 4432;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_DIMM_SELECT = 4433;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_MASTER_RANK1 = 4434;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_MASTER_RANK2 = 4435;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_SLAVE_RANK = 4436;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_SLAVE_RANK_LEN = 4437;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_BANK = 4438;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_BANK_LEN = 4439;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_ROW = 4440;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_ROW_LEN = 4441;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_COL = 4442;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_COL_LEN = 4443;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_ERR_OCCURRED_AFTER_UE_RETRY = 4444;
static const uint64_t IDX_CEN_MCBISTS01_MBMPERQ_RD_MPE_ROW17 = 4445;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_MASTER_RANK0 = 4446;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_DIMM_SELECT = 4447;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_MASTER_RANK1 = 4448;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_MASTER_RANK2 = 4449;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_SLAVE_RANK = 4450;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_SLAVE_RANK_LEN = 4451;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_BANK = 4452;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_BANK_LEN = 4453;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_ROW = 4454;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_ROW_LEN = 4455;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_COL = 4456;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_COL_LEN = 4457;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_ERR_OCCURRED__AFTER_UE_RETRY = 4458;
static const uint64_t IDX_CEN_MCBISTS01_MBNCERQ_RD_NCE_ROW17 = 4459;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_MASTER_RANK0 = 4460;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_DIMM_SELECT = 4461;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_MASTER_RANK1 = 4462;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_MASTER_RANK2 = 4463;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_SLAVE_RANK = 4464;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_SLAVE_RANK_LEN = 4465;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_BANK = 4466;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_BANK_LEN = 4467;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_ROW = 4468;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_ROW_LEN = 4469;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_COL = 4470;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_COL_LEN = 4471;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_ERR_OCCURRED_AFTER_UE_RETRY = 4472;
static const uint64_t IDX_CEN_MCBISTS01_MBRCERQ_RD_RCE_ROW17 = 4473;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_SOFT_CE_COUNT = 4474;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_SOFT_CE_COUNT_LEN = 4475;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_INTERMITTENT_CE_COUNT = 4476;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN = 4477;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_HARD_CE_COUNT = 4478;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_HARD_CE_COUNT_LEN = 4479;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_SCE_COUNT = 4480;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_SCE_COUNT_LEN = 4481;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_MCE_COUNT = 4482;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC0Q_MCE_COUNT_LEN = 4483;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC1Q_RCE_COUNT = 4484;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC1Q_RCE_COUNT_LEN = 4485;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC1Q_MPE_COUNT = 4486;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC1Q_MPE_COUNT_LEN = 4487;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC1Q_UE_COUNT = 4488;
static const uint64_t IDX_CEN_MCBISTS01_MBSEC1Q_UE_COUNT_LEN = 4489;
static const uint64_t IDX_CEN_MCBISTS01_MBSEVRQ_ERR_VECTOR0 = 4490;
static const uint64_t IDX_CEN_MCBISTS01_MBSEVRQ_ERR_VECTOR0_LEN = 4491;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT0_SCOM_PAR_ERRORS = 4492;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT0_MBX_PAR_ERRORS = 4493;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT0_RESERVED_2_14 = 4494;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT0_RESERVED_2_14_LEN = 4495;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT0_INTERNAL_SCOM_ERROR = 4496;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT0_INTERNAL_SCOM_ERROR_CLONE = 4497;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT1_SCOM_PAR_ERRORS = 4498;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT1_MBX_PAR_ERRORS = 4499;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT1_RESERVED_2_14 = 4500;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT1_RESERVED_2_14_LEN = 4501;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT1_INTERNAL_SCOM_ERROR = 4502;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRACT1_INTERNAL_SCOM_ERROR_CLONE = 4503;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRMASK_SCOM_PAR_ERRORS = 4504;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRMASK_MBX_PAR_ERRORS = 4505;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRMASK_RESERVED_2_14 = 4506;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRMASK_RESERVED_2_14_LEN = 4507;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRMASK_INTERNAL_SCOM_ERROR = 4508;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRMASK_INTERNAL_SCOM_ERROR_CLONE = 4509;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_SCOM_PAR_ERRORS = 4510;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_MBX_PAR_ERRORS = 4511;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_DRAM_EVENTN_BIT0 = 4512;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_DRAM_EVENTN_BIT1 = 4513;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_RESERVED_4_14 = 4514;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_RESERVED_4_14_LEN = 4515;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_INTERNAL_SCOM_ERROR = 4516;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE = 4517;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRWOF_SCOM_PAR_ERRORS = 4518;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRWOF_MBX_PAR_ERRORS = 4519;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRWOF_RESERVED_2_14 = 4520;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRWOF_RESERVED_2_14_LEN = 4521;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRWOF_INTERNAL_SCOM_ERROR = 4522;
static const uint64_t IDX_CEN_MCBISTS01_MBSFIRWOF_INTERNAL_SCOM_ERROR_CLONE = 4523;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_0_ERROR_COUNT = 4524;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_0_ERROR_COUNT_LEN = 4525;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_1_ERROR_COUNT = 4526;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_1_ERROR_COUNT_LEN = 4527;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_2_ERROR_COUNT = 4528;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_2_ERROR_COUNT_LEN = 4529;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_3_ERROR_COUNT = 4530;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_3_ERROR_COUNT_LEN = 4531;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_4_ERROR_COUNT = 4532;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_4_ERROR_COUNT_LEN = 4533;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_5_ERROR_COUNT = 4534;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_5_ERROR_COUNT_LEN = 4535;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_6_ERROR_COUNT = 4536;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_6_ERROR_COUNT_LEN = 4537;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_7_ERROR_COUNT = 4538;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC0Q_SYMBOL_7_ERROR_COUNT_LEN = 4539;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_8_ERROR_COUNT = 4540;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_8_ERROR_COUNT_LEN = 4541;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_9_ERROR_COUNT = 4542;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_9_ERROR_COUNT_LEN = 4543;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_10_ERROR_COUNT = 4544;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_10_ERROR_COUNT_LEN = 4545;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_11_ERROR_COUNT = 4546;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_11_ERROR_COUNT_LEN = 4547;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_12_ERROR_COUNT = 4548;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_12_ERROR_COUNT_LEN = 4549;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_13_ERROR_COUNT = 4550;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_13_ERROR_COUNT_LEN = 4551;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_14_ERROR_COUNT = 4552;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_14_ERROR_COUNT_LEN = 4553;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_15_ERROR_COUNT = 4554;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC1Q_SYMBOL_15_ERROR_COUNT_LEN = 4555;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_16_ERROR_COUNT = 4556;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_16_ERROR_COUNT_LEN = 4557;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_17_ERROR_COUNT = 4558;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_17_ERROR_COUNT_LEN = 4559;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_18_ERROR_COUNT = 4560;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_18_ERROR_COUNT_LEN = 4561;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_19_ERROR_COUNT = 4562;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_19_ERROR_COUNT_LEN = 4563;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_20_ERROR_COUNT = 4564;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_20_ERROR_COUNT_LEN = 4565;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_21_ERROR_COUNT = 4566;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_21_ERROR_COUNT_LEN = 4567;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_22_ERROR_COUNT = 4568;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_22_ERROR_COUNT_LEN = 4569;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_23_ERROR_COUNT = 4570;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC2Q_SYMBOL_23_ERROR_COUNT_LEN = 4571;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_24_ERROR_COUNT = 4572;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_24_ERROR_COUNT_LEN = 4573;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_25_ERROR_COUNT = 4574;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_25_ERROR_COUNT_LEN = 4575;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_26_ERROR_COUNT = 4576;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_26_ERROR_COUNT_LEN = 4577;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_27_ERROR_COUNT = 4578;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_27_ERROR_COUNT_LEN = 4579;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_28_ERROR_COUNT = 4580;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_28_ERROR_COUNT_LEN = 4581;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_29_ERROR_COUNT = 4582;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_29_ERROR_COUNT_LEN = 4583;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_30_ERROR_COUNT = 4584;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_30_ERROR_COUNT_LEN = 4585;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_31_ERROR_COUNT = 4586;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC3Q_SYMBOL_31_ERROR_COUNT_LEN = 4587;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_32_ERROR_COUNT = 4588;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_32_ERROR_COUNT_LEN = 4589;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_33_ERROR_COUNT = 4590;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_33_ERROR_COUNT_LEN = 4591;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_34_ERROR_COUNT = 4592;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_34_ERROR_COUNT_LEN = 4593;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_35_ERROR_COUNT = 4594;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_35_ERROR_COUNT_LEN = 4595;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_36_ERROR_COUNT = 4596;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_36_ERROR_COUNT_LEN = 4597;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_37_ERROR_COUNT = 4598;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_37_ERROR_COUNT_LEN = 4599;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_38ERROR_COUNT = 4600;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_38ERROR_COUNT_LEN = 4601;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_39_ERROR_COUNT = 4602;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC4Q_SYMBOL_39_ERROR_COUNT_LEN = 4603;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_40_ERROR_COUNT = 4604;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_40_ERROR_COUNT_LEN = 4605;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_41_ERROR_COUNT = 4606;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_41_ERROR_COUNT_LEN = 4607;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_42_ERROR_COUNT = 4608;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_42_ERROR_COUNT_LEN = 4609;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_43_ERROR_COUNT = 4610;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_43_ERROR_COUNT_LEN = 4611;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_44_ERROR_COUNT = 4612;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_44_ERROR_COUNT_LEN = 4613;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_45_ERROR_COUNT = 4614;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_45_ERROR_COUNT_LEN = 4615;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_46_ERROR_COUNT = 4616;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_46_ERROR_COUNT_LEN = 4617;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_47_ERROR_COUNT = 4618;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC5Q_SYMBOL_47_ERROR_COUNT_LEN = 4619;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_48_ERROR_COUNT = 4620;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_48_ERROR_COUNT_LEN = 4621;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_49_ERROR_COUNT = 4622;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_49_ERROR_COUNT_LEN = 4623;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_50_ERROR_COUNT = 4624;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_50_ERROR_COUNT_LEN = 4625;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_51_ERROR_COUNT = 4626;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_51_ERROR_COUNT_LEN = 4627;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_52_ERROR_COUNT = 4628;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_52_ERROR_COUNT_LEN = 4629;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_53_ERROR_COUNT = 4630;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_53_ERROR_COUNT_LEN = 4631;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_54_ERROR_COUNT = 4632;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_54_ERROR_COUNT_LEN = 4633;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_55_ERROR_COUNT = 4634;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC6Q_SYMBOL_55_ERROR_COUNT_LEN = 4635;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_56_ERROR_COUNT = 4636;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_56_ERROR_COUNT_LEN = 4637;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_57_ERROR_COUNT = 4638;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_57_ERROR_COUNT_LEN = 4639;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_58_ERROR_COUNT = 4640;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_58_ERROR_COUNT_LEN = 4641;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_59_ERROR_COUNT = 4642;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_59_ERROR_COUNT_LEN = 4643;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_60_ERROR_COUNT = 4644;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_60_ERROR_COUNT_LEN = 4645;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_61_ERROR_COUNT = 4646;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_61_ERROR_COUNT_LEN = 4647;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_62_ERROR_COUNT = 4648;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_62_ERROR_COUNT_LEN = 4649;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_63_ERROR_COUNT = 4650;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC7Q_SYMBOL_63_ERROR_COUNT_LEN = 4651;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_64_ERROR_COUNT = 4652;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_64_ERROR_COUNT_LEN = 4653;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_65_ERROR_COUNT = 4654;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_65_ERROR_COUNT_LEN = 4655;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_66_ERROR_COUNT = 4656;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_66_ERROR_COUNT_LEN = 4657;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_67_ERROR_COUNT = 4658;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_67_ERROR_COUNT_LEN = 4659;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_68_ERROR_COUNT = 4660;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_68_ERROR_COUNT_LEN = 4661;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_69_ERROR_COUNT = 4662;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_69_ERROR_COUNT_LEN = 4663;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_70_ERROR_COUNT = 4664;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_70_ERROR_COUNT_LEN = 4665;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_71_ERROR_COUNT = 4666;
static const uint64_t IDX_CEN_MCBISTS01_MBSSYMEC8Q_SYMBOL_71_ERROR_COUNT_LEN = 4667;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_SOFT_CE_COUNT_THRESHOLD_ATTN_STOP = 4668;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_INTERMITTENT_CE_COUNT_THRESHOLD_ATTN_STOP = 4669;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_HARD_CE_COUNT_THRESHOLD_ATTN_STOP = 4670;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_RCE_COUNT_THRESHOLD_ATTN_STOP = 4671;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_SOFT_CE_COUNT_THRESHOLD = 4672;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_SOFT_CE_COUNT_THRESHOLD_LEN = 4673;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_INTERMITTENT_CE_COUNT_THRESHOLD = 4674;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_INTERMITTENT_CE_COUNT_THRESHOLD_LEN = 4675;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_HARD_CE_COUNT_THRESHOLD = 4676;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_HARD_CE_COUNT_THRESHOLD_LEN = 4677;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_RETRY_CE_COUNT_THRESHOLD = 4678;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_RETRY_CE_COUNT_THRESHOLD_LEN = 4679;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_RESET_KEEPER = 4680;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_RESET_ALL_ERROR_COUNT_REGISTERS = 4681;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_DISABLE_RESET_ERROR_REG_RANK_END = 4682;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_SOFT_CE_INCR_SYMBOL_COUNT = 4683;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_INTERMIT_INCR_SYMBOL_COUNT = 4684;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_HARD_CE_INCR_SYMBOL_COUNT = 4685;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_MCE_INCR_SYMBOL_COUNT = 4686;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_UE_TRAP = 4687;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_CFG_MAINT_RCE_WITH_CE = 4688;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_RESERVED_61 = 4689;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_INTERMITTENT_NCE_INJECT = 4690;
static const uint64_t IDX_CEN_MCBISTS01_MBSTRQ_RESERVED_63 = 4691;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_CFG_DATA_ROT = 4692;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_CFG_DATA_ROT_LEN = 4693;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_CFG_DATA_ROT_SEED = 4694;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN = 4695;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_CFG_INVERT_DATA = 4696;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_DD2_HW234828_ROUTE_NONMAINT_DATA_TO_MAINTBUFF_EN = 4697;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_RESERVED_22_63 = 4698;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRCRQ_RESERVED_22_63_LEN = 4699;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRSRQ_CFG_DATA_ROT_SEED = 4700;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN = 4701;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD0Q_CFG_FIXED_SEED = 4702;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD0Q_CFG_FIXED_SEED_LEN = 4703;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD1Q_CFG_FIXED_SEED = 4704;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD1Q_CFG_FIXED_SEED_LEN = 4705;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD2Q_CFG_FIXED_SEED = 4706;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD2Q_CFG_FIXED_SEED_LEN = 4707;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD3Q_CFG_FIXED_SEED = 4708;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD3Q_CFG_FIXED_SEED_LEN = 4709;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD4Q_CFG_FIXED_SEED = 4710;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD4Q_CFG_FIXED_SEED_LEN = 4711;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD5Q_CFG_FIXED_SEED = 4712;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD5Q_CFG_FIXED_SEED_LEN = 4713;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD6Q_CFG_FIXED_SEED = 4714;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD6Q_CFG_FIXED_SEED_LEN = 4715;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD7Q_CFG_FIXED_SEED = 4716;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFD7Q_CFG_FIXED_SEED_LEN = 4717;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED1 = 4718;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED1_LEN = 4719;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED2 = 4720;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED2_LEN = 4721;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED3 = 4722;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED3_LEN = 4723;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED4 = 4724;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED4_LEN = 4725;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED5 = 4726;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED5_LEN = 4727;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED6 = 4728;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED6_LEN = 4729;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED7 = 4730;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED7_LEN = 4731;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED8 = 4732;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDQ_CFG_FIXED_SEED8_LEN = 4733;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED1 = 4734;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED1_LEN = 4735;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED2 = 4736;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED2_LEN = 4737;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED3 = 4738;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED3_LEN = 4739;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED4 = 4740;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED4_LEN = 4741;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED5 = 4742;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED5_LEN = 4743;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED6 = 4744;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED6_LEN = 4745;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED7 = 4746;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED7_LEN = 4747;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED8 = 4748;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBFDSPQ_CFG_FIXED_SEED8_LEN = 4749;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED0 = 4750;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED0_LEN = 4751;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED1 = 4752;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED1_LEN = 4753;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED2 = 4754;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED2_LEN = 4755;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED3 = 4756;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED3_LEN = 4757;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED4 = 4758;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED4_LEN = 4759;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED5 = 4760;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED5_LEN = 4761;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED6 = 4762;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED6_LEN = 4763;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED7 = 4764;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS0Q_DGEN_RNDD_SEED7_LEN = 4765;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED0 = 4766;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED0_LEN = 4767;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED1 = 4768;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED1_LEN = 4769;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED2 = 4770;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED2_LEN = 4771;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED3 = 4772;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED3_LEN = 4773;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED4 = 4774;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED4_LEN = 4775;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED5 = 4776;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED5_LEN = 4777;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED6 = 4778;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED6_LEN = 4779;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED7 = 4780;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS1Q_DGEN_RNDD_SEED7_LEN = 4781;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED0 = 4782;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED0_LEN = 4783;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED1 = 4784;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED1_LEN = 4785;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED2 = 4786;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED2_LEN = 4787;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED3 = 4788;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED3_LEN = 4789;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED4 = 4790;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED4_LEN = 4791;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED5 = 4792;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED5_LEN = 4793;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED6 = 4794;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED6_LEN = 4795;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED7 = 4796;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS2Q_DGEN_RNDD_SEED7_LEN = 4797;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED0 = 4798;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED0_LEN = 4799;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED1 = 4800;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED1_LEN = 4801;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED2 = 4802;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED2_LEN = 4803;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED3 = 4804;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED3_LEN = 4805;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED4 = 4806;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED4_LEN = 4807;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED5 = 4808;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED5_LEN = 4809;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED6 = 4810;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED6_LEN = 4811;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED7 = 4812;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS3Q_DGEN_RNDD_SEED7_LEN = 4813;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED0 = 4814;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED0_LEN = 4815;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED1 = 4816;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED1_LEN = 4817;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED2 = 4818;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED2_LEN = 4819;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED3 = 4820;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED3_LEN = 4821;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED4 = 4822;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED4_LEN = 4823;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED5 = 4824;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED5_LEN = 4825;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED6 = 4826;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED6_LEN = 4827;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED7 = 4828;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS4Q_DGEN_RNDD_SEED7_LEN = 4829;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED0 = 4830;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED0_LEN = 4831;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED1 = 4832;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED1_LEN = 4833;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED2 = 4834;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED2_LEN = 4835;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED3 = 4836;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED3_LEN = 4837;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED4 = 4838;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED4_LEN = 4839;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED5 = 4840;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED5_LEN = 4841;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED6 = 4842;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED6_LEN = 4843;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED7 = 4844;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS5Q_DGEN_RNDD_SEED7_LEN = 4845;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED0 = 4846;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED0_LEN = 4847;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED1 = 4848;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED1_LEN = 4849;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED2 = 4850;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED2_LEN = 4851;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED3 = 4852;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED3_LEN = 4853;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED4 = 4854;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED4_LEN = 4855;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED5 = 4856;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED5_LEN = 4857;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED6 = 4858;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED6_LEN = 4859;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED7 = 4860;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS6Q_DGEN_RNDD_SEED7_LEN = 4861;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED0 = 4862;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED0_LEN = 4863;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED1 = 4864;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED1_LEN = 4865;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED2 = 4866;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED2_LEN = 4867;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED3 = 4868;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED3_LEN = 4869;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED4 = 4870;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED4_LEN = 4871;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED5 = 4872;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED5_LEN = 4873;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED6 = 4874;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED6_LEN = 4875;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED7 = 4876;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS7Q_DGEN_RNDD_SEED7_LEN = 4877;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED0 = 4878;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED0_LEN = 4879;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED1 = 4880;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED1_LEN = 4881;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED2 = 4882;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED2_LEN = 4883;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED3 = 4884;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED3_LEN = 4885;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED4 = 4886;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED4_LEN = 4887;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED5 = 4888;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED5_LEN = 4889;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED6 = 4890;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED6_LEN = 4891;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED7 = 4892;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDS8Q_DGEN_RNDD_SEED7_LEN = 4893;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED0 = 4894;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED0_LEN = 4895;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED1 = 4896;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED1_LEN = 4897;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED2 = 4898;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED2_LEN = 4899;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED3 = 4900;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED3_LEN = 4901;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED4 = 4902;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED4_LEN = 4903;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED5 = 4904;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED5_LEN = 4905;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED6 = 4906;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED6_LEN = 4907;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED7 = 4908;
static const uint64_t IDX_CEN_MCBISTS01_MBS_MCBRDSSPQ_DGEN_RNDD_SEED7_LEN = 4909;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_MASTER_RANK0 = 4910;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_DIMM_SELECT = 4911;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_MASTER_RANK1 = 4912;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_MASTER_RANK2 = 4913;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_SLAVE_RANK = 4914;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_SLAVE_RANK_LEN = 4915;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_BANK = 4916;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_BANK_LEN = 4917;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_ROW = 4918;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_ROW_LEN = 4919;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_COL = 4920;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_COL_LEN = 4921;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RESERVED_40 = 4922;
static const uint64_t IDX_CEN_MCBISTS01_MBUERQ_RD_UE_ROW17 = 4923;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_RCMD_ERR_INJ_MODE = 4924;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_RCMD_ERR_INJ = 4925;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_WRD_CE_ERR_INJ_MODE = 4926;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_WRD_CE_ERR_INJ = 4927;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_WRD_UE_ERR_INJ_MODE = 4928;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_WRD_UE_ERR_INJ = 4929;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_MAINT_CE_ERR_INJ_MODE = 4930;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_MAINT_CE_ERR_INJ = 4931;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_MAINT_UE_ERR_INJ_MODE = 4932;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_MAINT_UE_ERR_INJ = 4933;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_SCOM_PE_ERR_INJ_MODE = 4934;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_SCOM_PE_ERR_INJ = 4935;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_RESERVED_12_63 = 4936;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRINJQ_RESERVED_12_63_LEN = 4937;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRSTATQ_WDONE_PAR_ERROR = 4938;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRSTATQ_RDTAG_RDCHECK_ERROR = 4939;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRSTATQ_RDTAG_PAR_ERROR = 4940;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRSTATQ_RDTAG_PAR_RC_ERROR = 4941;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRSTATQ_RESERVED_4_63 = 4942;
static const uint64_t IDX_CEN_MCBISTS01_MBXERRSTATQ_RESERVED_4_63_LEN = 4943;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMA1Q_COMPARE_MASK_A = 4944;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMA1Q_COMPARE_MASK_A_LEN = 4945;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_COMPARE_MASK_A = 4946;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_COMPARE_MASK_A_LEN = 4947;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_COMPARE_MASK_B = 4948;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_COMPARE_MASK_B_LEN = 4949;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_CFG_STORE_FAIL = 4950;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_MCBIST_ENABLE_CE_TRAP = 4951;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_MCBIST_ENABLE_MPE_TRAP = 4952;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_ENABLE_UE_TRAP = 4953;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_MCBIST_STOP_ON_NTH_FAIL = 4954;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_ARRAY_READ_ENABLE = 4955;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_RESERVED_38_63 = 4956;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMABQ_RESERVED_38_63_LEN = 4957;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMB1Q_COMPARE_MASK_B = 4958;
static const uint64_t IDX_CEN_MCBISTS01_MCBCMB1Q_COMPARE_MASK_B_LEN = 4959;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_ERROR_MAP_PORTA_RNK0 = 4960;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_ERROR_MAP_PORTA_RNK0_LEN = 4961;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_ERROR_MAP_PORTA_RNK1 = 4962;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_ERROR_MAP_PORTA_RNK1_LEN = 4963;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_ERROR_MAP_PORTA_RNK2 = 4964;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_ERROR_MAP_PORTA_RNK2_LEN = 4965;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_RESERVED_60_63 = 4966;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA1Q_RESERVED_60_63_LEN = 4967;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_ERROR_MAP_PORTA_RNK3 = 4968;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_ERROR_MAP_PORTA_RNK3_LEN = 4969;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_ERROR_MAP_PORTA_RNK4 = 4970;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_ERROR_MAP_PORTA_RNK4_LEN = 4971;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_ERROR_MAP_PORTA_RNK5 = 4972;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_ERROR_MAP_PORTA_RNK5_LEN = 4973;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_RESERVED_60_63 = 4974;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA2Q_RESERVED_60_63_LEN = 4975;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA3Q_ERROR_MAP_PORTA_RNK6 = 4976;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA3Q_ERROR_MAP_PORTA_RNK6_LEN = 4977;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA3Q_ERROR_MAP_PORTA_RNK7 = 4978;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA3Q_ERROR_MAP_PORTA_RNK7_LEN = 4979;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA3Q_RESERVED_40_63 = 4980;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMA3Q_RESERVED_40_63_LEN = 4981;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_ERROR_MAP_PORTB_RNK0 = 4982;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_ERROR_MAP_PORTB_RNK0_LEN = 4983;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_ERROR_MAP_PORTB_RNK1 = 4984;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_ERROR_MAP_PORTB_RNK1_LEN = 4985;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_ERROR_MAP_PORTB_RNK2 = 4986;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_ERROR_MAP_PORTB_RNK2_LEN = 4987;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_RESERVED_60_63 = 4988;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB1Q_RESERVED_60_63_LEN = 4989;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_ERROR_MAP_PORTB_RNK3 = 4990;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_ERROR_MAP_PORTB_RNK3_LEN = 4991;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_ERROR_MAP_PORTB_RNK4 = 4992;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_ERROR_MAP_PORTB_RNK4_LEN = 4993;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_ERROR_MAP_PORTB_RNK5 = 4994;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_ERROR_MAP_PORTB_RNK5_LEN = 4995;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_RESERVED_60_63 = 4996;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB2Q_RESERVED_60_63_LEN = 4997;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB3Q_ERROR_MAP_PORTB_RNK6 = 4998;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB3Q_ERROR_MAP_PORTB_RNK6_LEN = 4999;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB3Q_ERROR_MAP_PORTB_RNK7 = 5000;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB3Q_ERROR_MAP_PORTB_RNK7_LEN = 5001;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB3Q_RESERVED_40_63 = 5002;
static const uint64_t IDX_CEN_MCBISTS01_MCBEMB3Q_RESERVED_40_63_LEN = 5003;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_PORTA_CE_ERR = 5004;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_PORTA_UE_ERR = 5005;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_PORTA_ERR_TRAP_OVERFLOW = 5006;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_PORTA_CNTL_TRAP_SUBTST_NUM = 5007;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_PORTA_CNTL_TRAP_SUBTST_NUM_LEN = 5008;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_PORTA_ERR_LOG_PTR = 5009;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_PORTA_ERR_LOG_PTR_LEN = 5010;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_RESERVED_11_23 = 5011;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATAQ_RESERVED_11_23_LEN = 5012;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_PORTB_CE_ERR = 5013;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_PORTB_UE_ERR = 5014;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_PORTB_ERR_TRAP_OVERFLOW = 5015;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_PORTB_CNTL_TRAP_SUBTST_NUM = 5016;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_PORTB_CNTL_TRAP_SUBTST_NUM_LEN = 5017;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_PORTB_ERR_LOG_PTR = 5018;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_PORTB_ERR_LOG_PTR_LEN = 5019;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_RESERVED_11_23 = 5020;
static const uint64_t IDX_CEN_MCBISTS01_MCBSTATBQ_RESERVED_11_23_LEN = 5021;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR0 = 5022;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR0_LEN = 5023;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR1 = 5024;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR1_LEN = 5025;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR2 = 5026;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR2_LEN = 5027;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR3 = 5028;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR3_LEN = 5029;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR4 = 5030;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR4_LEN = 5031;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR5 = 5032;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR5_LEN = 5033;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR6 = 5034;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR6_LEN = 5035;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR7 = 5036;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR7_LEN = 5037;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR8 = 5038;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR8_LEN = 5039;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA1Q_RESERVED_63 = 5040;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR9 = 5041;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR9_LEN = 5042;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR10 = 5043;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR10_LEN = 5044;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR11 = 5045;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR11_LEN = 5046;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR12 = 5047;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR12_LEN = 5048;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR13 = 5049;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR13_LEN = 5050;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR14 = 5051;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR14_LEN = 5052;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR15 = 5053;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR15_LEN = 5054;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR16 = 5055;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR16_LEN = 5056;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR17 = 5057;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR17_LEN = 5058;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA2Q_ERR_CNTR_OVERFLOW = 5059;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR18 = 5060;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR18_LEN = 5061;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR19 = 5062;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR19_LEN = 5063;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA3Q_RESERVED_14_63 = 5064;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTA3Q_RESERVED_14_63_LEN = 5065;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR0 = 5066;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR0_LEN = 5067;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR1 = 5068;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR1_LEN = 5069;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR2 = 5070;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR2_LEN = 5071;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR3 = 5072;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR3_LEN = 5073;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR4 = 5074;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR4_LEN = 5075;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR5 = 5076;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR5_LEN = 5077;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR6 = 5078;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR6_LEN = 5079;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR7 = 5080;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR7_LEN = 5081;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR8 = 5082;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR8_LEN = 5083;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB1Q_RESERVED_63 = 5084;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR9 = 5085;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR9_LEN = 5086;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR10 = 5087;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR10_LEN = 5088;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR11 = 5089;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR11_LEN = 5090;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR12 = 5091;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR12_LEN = 5092;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR13 = 5093;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR13_LEN = 5094;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR14 = 5095;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR14_LEN = 5096;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR15 = 5097;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR15_LEN = 5098;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR16 = 5099;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR16_LEN = 5100;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR17 = 5101;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR17_LEN = 5102;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB2Q_ERR_CNTR_OVERFLOW = 5103;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR18 = 5104;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR18_LEN = 5105;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR19 = 5106;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR19_LEN = 5107;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB3Q_RESERVED_14_63 = 5108;
static const uint64_t IDX_CEN_MCBISTS01_MCB_ERRCNTB3Q_RESERVED_14_63_LEN = 5109;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG = 5110;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG_LEN = 5111;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG = 5112;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG_LEN = 5113;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG = 5114;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG_LEN = 5115;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG = 5116;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG_LEN = 5117;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG = 5118;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG_LEN = 5119;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG = 5120;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG_LEN = 5121;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG = 5122;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG_LEN = 5123;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG = 5124;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG_LEN = 5125;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG = 5126;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG_LEN = 5127;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG = 5128;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG_LEN = 5129;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG = 5130;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG_LEN = 5131;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG = 5132;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG_LEN = 5133;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG = 5134;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG_LEN = 5135;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG = 5136;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG_LEN = 5137;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG = 5138;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG_LEN = 5139;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG = 5140;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG_LEN = 5141;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS = 5142;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS_LEN = 5143;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS = 5144;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS_LEN = 5145;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS = 5146;
static const uint64_t IDX_CEN_IBB_PIBMST_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS_LEN = 5147;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MEMORY_MPE_RANK_0_7 = 5148;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MEMORY_MPE_RANK_0_7_LEN = 5149;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_RESERVED_8_15 = 5150;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_RESERVED_8_15_LEN = 5151;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MEMORY_NCE = 5152;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MEMORY_RCE = 5153;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MEMORY_SUE = 5154;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MEMORY_UE = 5155;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINT_MPE_RANK_0_7 = 5156;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINT_MPE_RANK_0_7_LEN = 5157;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_RESERVED_28_35 = 5158;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_RESERVED_28_35_LEN = 5159;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINTENANCE_NCE = 5160;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINTENANCE_SCE = 5161;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINTENANCE_MCE = 5162;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINTENANCE_RCE = 5163;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINTENANCE_SUE = 5164;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINTENANCE_UE = 5165;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE = 5166;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_PREFETCH_MEMORY_UE = 5167;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MEMORY_RCD_PARITY_ERROR = 5168;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR = 5169;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR = 5170;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR = 5171;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR = 5172;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_ECC_DATAPATH_PARITY_ERROR = 5173;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_INTERNAL_SCOM_ERROR = 5174;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_INTERNAL_SCOM_ERROR_COPY = 5175;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_ACTION0_FIR = 5176;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_ACTION0_FIR_LEN = 5177;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_ACTION1_FIR = 5178;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_ACTION1_FIR_LEN = 5179;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MASK_FIR = 5180;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_MASK_FIR_LEN = 5181;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_WOF_FIR = 5182;
static const uint64_t IDX_CEN_ECC01_MBECCFIR_WOF_FIR_LEN = 5183;
static const uint64_t IDX_CEN_ECC01_MBMMRQ_SYMBOL_MAINTENANCE_MARK_VALUE = 5184;
static const uint64_t IDX_CEN_ECC01_MBMMRQ_SYMBOL_MAINTENANCE_MARK_VALUE_LEN = 5185;
static const uint64_t IDX_CEN_ECC01_MBMMRQ_CHIP_MAINTENANCE_MARK_VALUE = 5186;
static const uint64_t IDX_CEN_ECC01_MBMMRQ_CHIP_MAINTENANCE_MARK_VALUE_LEN = 5187;
static const uint64_t IDX_CEN_ECC01_MBMS0_SYMBOL_MARK_VALUE_FOR_RANKX = 5188;
static const uint64_t IDX_CEN_ECC01_MBMS0_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5189;
static const uint64_t IDX_CEN_ECC01_MBMS0_CHIP_MARK_VALUE_FOR_RANKX = 5190;
static const uint64_t IDX_CEN_ECC01_MBMS0_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5191;
static const uint64_t IDX_CEN_ECC01_MBMS1_SYMBOL_MARK_VALUE_FOR_RANKX = 5192;
static const uint64_t IDX_CEN_ECC01_MBMS1_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5193;
static const uint64_t IDX_CEN_ECC01_MBMS1_CHIP_MARK_VALUE_FOR_RANKX = 5194;
static const uint64_t IDX_CEN_ECC01_MBMS1_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5195;
static const uint64_t IDX_CEN_ECC01_MBMS2_SYMBOL_MARK_VALUE_FOR_RANKX = 5196;
static const uint64_t IDX_CEN_ECC01_MBMS2_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5197;
static const uint64_t IDX_CEN_ECC01_MBMS2_CHIP_MARK_VALUE_FOR_RANKX = 5198;
static const uint64_t IDX_CEN_ECC01_MBMS2_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5199;
static const uint64_t IDX_CEN_ECC01_MBMS3_SYMBOL_MARK_VALUE_FOR_RANKX = 5200;
static const uint64_t IDX_CEN_ECC01_MBMS3_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5201;
static const uint64_t IDX_CEN_ECC01_MBMS3_CHIP_MARK_VALUE_FOR_RANKX = 5202;
static const uint64_t IDX_CEN_ECC01_MBMS3_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5203;
static const uint64_t IDX_CEN_ECC01_MBMS4_SYMBOL_MARK_VALUE_FOR_RANKX = 5204;
static const uint64_t IDX_CEN_ECC01_MBMS4_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5205;
static const uint64_t IDX_CEN_ECC01_MBMS4_CHIP_MARK_VALUE_FOR_RANKX = 5206;
static const uint64_t IDX_CEN_ECC01_MBMS4_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5207;
static const uint64_t IDX_CEN_ECC01_MBMS5_SYMBOL_MARK_VALUE_FOR_RANKX = 5208;
static const uint64_t IDX_CEN_ECC01_MBMS5_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5209;
static const uint64_t IDX_CEN_ECC01_MBMS5_CHIP_MARK_VALUE_FOR_RANKX = 5210;
static const uint64_t IDX_CEN_ECC01_MBMS5_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5211;
static const uint64_t IDX_CEN_ECC01_MBMS6_SYMBOL_MARK_VALUE_FOR_RANKX = 5212;
static const uint64_t IDX_CEN_ECC01_MBMS6_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5213;
static const uint64_t IDX_CEN_ECC01_MBMS6_CHIP_MARK_VALUE_FOR_RANKX = 5214;
static const uint64_t IDX_CEN_ECC01_MBMS6_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5215;
static const uint64_t IDX_CEN_ECC01_MBMS7_SYMBOL_MARK_VALUE_FOR_RANKX = 5216;
static const uint64_t IDX_CEN_ECC01_MBMS7_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5217;
static const uint64_t IDX_CEN_ECC01_MBMS7_CHIP_MARK_VALUE_FOR_RANKX = 5218;
static const uint64_t IDX_CEN_ECC01_MBMS7_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5219;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_ADDRESS = 5220;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_ADDRESS_LEN = 5221;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_ENABLE_RCE_INJECT = 5222;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_ENABLE_SCRUB_INJECT = 5223;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_READ1_ERROR_TYPE = 5224;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_READ1_ERROR_TYPE_LEN = 5225;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_READ2_ERROR_TYPE = 5226;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_READ2_ERROR_TYPE_LEN = 5227;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_READ3_ERROR_TYPE = 5228;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_READ3_ERROR_TYPE_LEN = 5229;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_BANK_MASK_SELECT = 5230;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_BANK_MASK_SELECT_LEN = 5231;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_ROW_MASK_SELECT = 5232;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_ROW_MASK_SELECT_LEN = 5233;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_COLUMN_MASK_SELECT = 5234;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_COLUMN_MASK_SELECT_LEN = 5235;
static const uint64_t IDX_CEN_ECC01_MBRCEICRQ_ROW17_ADDRESS = 5236;
static const uint64_t IDX_CEN_ECC01_MBSBS0_READ_BIT_STEER_MUX_SELECT_0 = 5237;
static const uint64_t IDX_CEN_ECC01_MBSBS0_READ_BIT_STEER_MUX_SELECT_0_LEN = 5238;
static const uint64_t IDX_CEN_ECC01_MBSBS0_READ_BIT_STEER_MUX_SELECT_1 = 5239;
static const uint64_t IDX_CEN_ECC01_MBSBS0_READ_BIT_STEER_MUX_SELECT_1_LEN = 5240;
static const uint64_t IDX_CEN_ECC01_MBSBS0_READ_BIT_STEER_MUX_SELECT_2 = 5241;
static const uint64_t IDX_CEN_ECC01_MBSBS0_READ_BIT_STEER_MUX_SELECT_2_LEN = 5242;
static const uint64_t IDX_CEN_ECC01_MBSBS1_READ_BIT_STEER_MUX_SELECT_0 = 5243;
static const uint64_t IDX_CEN_ECC01_MBSBS1_READ_BIT_STEER_MUX_SELECT_0_LEN = 5244;
static const uint64_t IDX_CEN_ECC01_MBSBS1_READ_BIT_STEER_MUX_SELECT_1 = 5245;
static const uint64_t IDX_CEN_ECC01_MBSBS1_READ_BIT_STEER_MUX_SELECT_1_LEN = 5246;
static const uint64_t IDX_CEN_ECC01_MBSBS1_READ_BIT_STEER_MUX_SELECT_2 = 5247;
static const uint64_t IDX_CEN_ECC01_MBSBS1_READ_BIT_STEER_MUX_SELECT_2_LEN = 5248;
static const uint64_t IDX_CEN_ECC01_MBSBS2_READ_BIT_STEER_MUX_SELECT_0 = 5249;
static const uint64_t IDX_CEN_ECC01_MBSBS2_READ_BIT_STEER_MUX_SELECT_0_LEN = 5250;
static const uint64_t IDX_CEN_ECC01_MBSBS2_READ_BIT_STEER_MUX_SELECT_1 = 5251;
static const uint64_t IDX_CEN_ECC01_MBSBS2_READ_BIT_STEER_MUX_SELECT_1_LEN = 5252;
static const uint64_t IDX_CEN_ECC01_MBSBS2_READ_BIT_STEER_MUX_SELECT_2 = 5253;
static const uint64_t IDX_CEN_ECC01_MBSBS2_READ_BIT_STEER_MUX_SELECT_2_LEN = 5254;
static const uint64_t IDX_CEN_ECC01_MBSBS3_READ_BIT_STEER_MUX_SELECT_0 = 5255;
static const uint64_t IDX_CEN_ECC01_MBSBS3_READ_BIT_STEER_MUX_SELECT_0_LEN = 5256;
static const uint64_t IDX_CEN_ECC01_MBSBS3_READ_BIT_STEER_MUX_SELECT_1 = 5257;
static const uint64_t IDX_CEN_ECC01_MBSBS3_READ_BIT_STEER_MUX_SELECT_1_LEN = 5258;
static const uint64_t IDX_CEN_ECC01_MBSBS3_READ_BIT_STEER_MUX_SELECT_2 = 5259;
static const uint64_t IDX_CEN_ECC01_MBSBS3_READ_BIT_STEER_MUX_SELECT_2_LEN = 5260;
static const uint64_t IDX_CEN_ECC01_MBSBS4_READ_BIT_STEER_MUX_SELECT_0 = 5261;
static const uint64_t IDX_CEN_ECC01_MBSBS4_READ_BIT_STEER_MUX_SELECT_0_LEN = 5262;
static const uint64_t IDX_CEN_ECC01_MBSBS4_READ_BIT_STEER_MUX_SELECT_1 = 5263;
static const uint64_t IDX_CEN_ECC01_MBSBS4_READ_BIT_STEER_MUX_SELECT_1_LEN = 5264;
static const uint64_t IDX_CEN_ECC01_MBSBS4_READ_BIT_STEER_MUX_SELECT_2 = 5265;
static const uint64_t IDX_CEN_ECC01_MBSBS4_READ_BIT_STEER_MUX_SELECT_2_LEN = 5266;
static const uint64_t IDX_CEN_ECC01_MBSBS5_READ_BIT_STEER_MUX_SELECT_0 = 5267;
static const uint64_t IDX_CEN_ECC01_MBSBS5_READ_BIT_STEER_MUX_SELECT_0_LEN = 5268;
static const uint64_t IDX_CEN_ECC01_MBSBS5_READ_BIT_STEER_MUX_SELECT_1 = 5269;
static const uint64_t IDX_CEN_ECC01_MBSBS5_READ_BIT_STEER_MUX_SELECT_1_LEN = 5270;
static const uint64_t IDX_CEN_ECC01_MBSBS5_READ_BIT_STEER_MUX_SELECT_2 = 5271;
static const uint64_t IDX_CEN_ECC01_MBSBS5_READ_BIT_STEER_MUX_SELECT_2_LEN = 5272;
static const uint64_t IDX_CEN_ECC01_MBSBS6_READ_BIT_STEER_MUX_SELECT_0 = 5273;
static const uint64_t IDX_CEN_ECC01_MBSBS6_READ_BIT_STEER_MUX_SELECT_0_LEN = 5274;
static const uint64_t IDX_CEN_ECC01_MBSBS6_READ_BIT_STEER_MUX_SELECT_1 = 5275;
static const uint64_t IDX_CEN_ECC01_MBSBS6_READ_BIT_STEER_MUX_SELECT_1_LEN = 5276;
static const uint64_t IDX_CEN_ECC01_MBSBS6_READ_BIT_STEER_MUX_SELECT_2 = 5277;
static const uint64_t IDX_CEN_ECC01_MBSBS6_READ_BIT_STEER_MUX_SELECT_2_LEN = 5278;
static const uint64_t IDX_CEN_ECC01_MBSBS7_READ_BIT_STEER_MUX_SELECT_0 = 5279;
static const uint64_t IDX_CEN_ECC01_MBSBS7_READ_BIT_STEER_MUX_SELECT_0_LEN = 5280;
static const uint64_t IDX_CEN_ECC01_MBSBS7_READ_BIT_STEER_MUX_SELECT_1 = 5281;
static const uint64_t IDX_CEN_ECC01_MBSBS7_READ_BIT_STEER_MUX_SELECT_1_LEN = 5282;
static const uint64_t IDX_CEN_ECC01_MBSBS7_READ_BIT_STEER_MUX_SELECT_2 = 5283;
static const uint64_t IDX_CEN_ECC01_MBSBS7_READ_BIT_STEER_MUX_SELECT_2_LEN = 5284;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS0_CHIP_PARITY = 5285;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS0_SYMBOL_PARITY = 5286;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS0_PARITY = 5287;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS1_CHIP_PARITY = 5288;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS1_SYMBOL_PARITY = 5289;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS1_PARITY = 5290;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS2_CHIP_PARITY = 5291;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS2_SYMBOL_PARITY = 5292;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS2_PARITY = 5293;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS3_CHIP_PARITY = 5294;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS3_SYMBOL_PARITY = 5295;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS3_PARITY = 5296;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS4_CHIP_PARITY = 5297;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS4_SYMBOL_PARITY = 5298;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS4_PARITY = 5299;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS5_CHIP_PARITY = 5300;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS5_SYMBOL_PARITY = 5301;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS5_PARITY = 5302;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS6_CHIP_PARITY = 5303;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS6_SYMBOL_PARITY = 5304;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS6_PARITY = 5305;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS7_CHIP_PARITY = 5306;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS7_SYMBOL_PARITY = 5307;
static const uint64_t IDX_CEN_ECC01_MBSECCERR0_MBMS7_PARITY = 5308;
static const uint64_t IDX_CEN_ECC01_MBSECCERR1_MEMORY_BIT_STEER_PARITY = 5309;
static const uint64_t IDX_CEN_ECC01_MBSECCERR1_MEMORY_BIT_STEER_PARITY_LEN = 5310;
static const uint64_t IDX_CEN_ECC01_MBSECCERR1_MBMMR_PARITY = 5311;
static const uint64_t IDX_CEN_ECC01_MBSECCERR1_MBRCEICR_PARITY = 5312;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 5313;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 5314;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_RESERVED_2 = 5315;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_ENABLE_64BYTE_DATA_CHECKBIT_INVERSION = 5316;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_USE_MAINTENANCE_MARK = 5317;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_DISABLE_MARK_STORE_WRITE = 5318;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_ENABLE_FIRST_SHADOW_READ_UE = 5319;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_ECC_METADATA_MODE = 5320;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_ECC_METADATA_MODE_LEN = 5321;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_SINGLE_WIRE_MODE = 5322;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_INT_RESET_KEEPER = 5323;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_INJECT_SCOM_PARITY_ERROR = 5324;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_INJECT_MARK_STORE_SYMBOL_PARITY_ERROR = 5325;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_INJECT_MARK_STORE_CHIP_PARITY_ERROR = 5326;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_MBRCEICRQ_DATAPATH_PARITY_ERROR_INJECT = 5327;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_REPORT_RCE_ON_CORRECTIONS = 5328;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_RESERVED_17_23 = 5329;
static const uint64_t IDX_CEN_ECC01_MBSECCQ_RESERVED_17_23_LEN = 5330;
static const uint64_t IDX_CEN_ECC01_MBSMSRQ_MARK_VALUE = 5331;
static const uint64_t IDX_CEN_ECC01_MBSMSRQ_MARK_VALUE_LEN = 5332;
static const uint64_t IDX_CEN_ECC01_MBSMSRQ_MARK_SHADOW_RANK = 5333;
static const uint64_t IDX_CEN_ECC01_MBSMSRQ_MARK_SHADOW_RANK_LEN = 5334;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MEMORY_MPE_RANK_0_7 = 5335;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MEMORY_MPE_RANK_0_7_LEN = 5336;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_RESERVED_8_15 = 5337;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_RESERVED_8_15_LEN = 5338;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MEMORY_NCE = 5339;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MEMORY_RCE = 5340;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MEMORY_SUE = 5341;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MEMORY_UE = 5342;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINT_MPE_RANK_0_7 = 5343;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINT_MPE_RANK_0_7_LEN = 5344;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_RESERVED_28_35 = 5345;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_RESERVED_28_35_LEN = 5346;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINTENANCE_NCE = 5347;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINTENANCE_SCE = 5348;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINTENANCE_MCE = 5349;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINTENANCE_RCE = 5350;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINTENANCE_SUE = 5351;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINTENANCE_UE = 5352;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE = 5353;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_PREFETCH_MEMORY_UE = 5354;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MEMORY_RCD_PARITY_ERROR = 5355;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR = 5356;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR = 5357;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR = 5358;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR = 5359;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_ECC_DATAPATH_PARITY_ERROR = 5360;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_INTERNAL_SCOM_ERROR = 5361;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_INTERNAL_SCOM_ERROR_COPY = 5362;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_ACTION0_FIR = 5363;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_ACTION0_FIR_LEN = 5364;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_ACTION1_FIR = 5365;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_ACTION1_FIR_LEN = 5366;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MASK_FIR = 5367;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_MASK_FIR_LEN = 5368;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_WOF_FIR = 5369;
static const uint64_t IDX_CEN_ECC23_MBECCFIR_WOF_FIR_LEN = 5370;
static const uint64_t IDX_CEN_ECC23_MBMMRQ_SYMBOL_MAINTENANCE_MARK_VALUE = 5371;
static const uint64_t IDX_CEN_ECC23_MBMMRQ_SYMBOL_MAINTENANCE_MARK_VALUE_LEN = 5372;
static const uint64_t IDX_CEN_ECC23_MBMMRQ_CHIP_MAINTENANCE_MARK_VALUE = 5373;
static const uint64_t IDX_CEN_ECC23_MBMMRQ_CHIP_MAINTENANCE_MARK_VALUE_LEN = 5374;
static const uint64_t IDX_CEN_ECC23_MBMS0_SYMBOL_MARK_VALUE_FOR_RANKX = 5375;
static const uint64_t IDX_CEN_ECC23_MBMS0_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5376;
static const uint64_t IDX_CEN_ECC23_MBMS0_CHIP_MARK_VALUE_FOR_RANKX = 5377;
static const uint64_t IDX_CEN_ECC23_MBMS0_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5378;
static const uint64_t IDX_CEN_ECC23_MBMS1_SYMBOL_MARK_VALUE_FOR_RANKX = 5379;
static const uint64_t IDX_CEN_ECC23_MBMS1_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5380;
static const uint64_t IDX_CEN_ECC23_MBMS1_CHIP_MARK_VALUE_FOR_RANKX = 5381;
static const uint64_t IDX_CEN_ECC23_MBMS1_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5382;
static const uint64_t IDX_CEN_ECC23_MBMS2_SYMBOL_MARK_VALUE_FOR_RANKX = 5383;
static const uint64_t IDX_CEN_ECC23_MBMS2_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5384;
static const uint64_t IDX_CEN_ECC23_MBMS2_CHIP_MARK_VALUE_FOR_RANKX = 5385;
static const uint64_t IDX_CEN_ECC23_MBMS2_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5386;
static const uint64_t IDX_CEN_ECC23_MBMS3_SYMBOL_MARK_VALUE_FOR_RANKX = 5387;
static const uint64_t IDX_CEN_ECC23_MBMS3_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5388;
static const uint64_t IDX_CEN_ECC23_MBMS3_CHIP_MARK_VALUE_FOR_RANKX = 5389;
static const uint64_t IDX_CEN_ECC23_MBMS3_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5390;
static const uint64_t IDX_CEN_ECC23_MBMS4_SYMBOL_MARK_VALUE_FOR_RANKX = 5391;
static const uint64_t IDX_CEN_ECC23_MBMS4_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5392;
static const uint64_t IDX_CEN_ECC23_MBMS4_CHIP_MARK_VALUE_FOR_RANKX = 5393;
static const uint64_t IDX_CEN_ECC23_MBMS4_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5394;
static const uint64_t IDX_CEN_ECC23_MBMS5_SYMBOL_MARK_VALUE_FOR_RANKX = 5395;
static const uint64_t IDX_CEN_ECC23_MBMS5_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5396;
static const uint64_t IDX_CEN_ECC23_MBMS5_CHIP_MARK_VALUE_FOR_RANKX = 5397;
static const uint64_t IDX_CEN_ECC23_MBMS5_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5398;
static const uint64_t IDX_CEN_ECC23_MBMS6_SYMBOL_MARK_VALUE_FOR_RANKX = 5399;
static const uint64_t IDX_CEN_ECC23_MBMS6_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5400;
static const uint64_t IDX_CEN_ECC23_MBMS6_CHIP_MARK_VALUE_FOR_RANKX = 5401;
static const uint64_t IDX_CEN_ECC23_MBMS6_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5402;
static const uint64_t IDX_CEN_ECC23_MBMS7_SYMBOL_MARK_VALUE_FOR_RANKX = 5403;
static const uint64_t IDX_CEN_ECC23_MBMS7_SYMBOL_MARK_VALUE_FOR_RANKX_LEN = 5404;
static const uint64_t IDX_CEN_ECC23_MBMS7_CHIP_MARK_VALUE_FOR_RANKX = 5405;
static const uint64_t IDX_CEN_ECC23_MBMS7_CHIP_MARK_VALUE_FOR_RANKX_LEN = 5406;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_ADDRESS = 5407;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_ADDRESS_LEN = 5408;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_ENABLE_RCE_INJECT = 5409;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_ENABLE_SCRUB_INJECT = 5410;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_READ1_ERROR_TYPE = 5411;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_READ1_ERROR_TYPE_LEN = 5412;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_READ2_ERROR_TYPE = 5413;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_READ2_ERROR_TYPE_LEN = 5414;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_READ3_ERROR_TYPE = 5415;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_READ3_ERROR_TYPE_LEN = 5416;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_BANK_MASK_SELECT = 5417;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_BANK_MASK_SELECT_LEN = 5418;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_ROW_MASK_SELECT = 5419;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_ROW_MASK_SELECT_LEN = 5420;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_COLUMN_MASK_SELECT = 5421;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_COLUMN_MASK_SELECT_LEN = 5422;
static const uint64_t IDX_CEN_ECC23_MBRCEICRQ_ROW17_ADDRESS = 5423;
static const uint64_t IDX_CEN_ECC23_MBSBS0_READ_BIT_STEER_MUX_SELECT_0 = 5424;
static const uint64_t IDX_CEN_ECC23_MBSBS0_READ_BIT_STEER_MUX_SELECT_0_LEN = 5425;
static const uint64_t IDX_CEN_ECC23_MBSBS0_READ_BIT_STEER_MUX_SELECT_1 = 5426;
static const uint64_t IDX_CEN_ECC23_MBSBS0_READ_BIT_STEER_MUX_SELECT_1_LEN = 5427;
static const uint64_t IDX_CEN_ECC23_MBSBS0_READ_BIT_STEER_MUX_SELECT_2 = 5428;
static const uint64_t IDX_CEN_ECC23_MBSBS0_READ_BIT_STEER_MUX_SELECT_2_LEN = 5429;
static const uint64_t IDX_CEN_ECC23_MBSBS1_READ_BIT_STEER_MUX_SELECT_0 = 5430;
static const uint64_t IDX_CEN_ECC23_MBSBS1_READ_BIT_STEER_MUX_SELECT_0_LEN = 5431;
static const uint64_t IDX_CEN_ECC23_MBSBS1_READ_BIT_STEER_MUX_SELECT_1 = 5432;
static const uint64_t IDX_CEN_ECC23_MBSBS1_READ_BIT_STEER_MUX_SELECT_1_LEN = 5433;
static const uint64_t IDX_CEN_ECC23_MBSBS1_READ_BIT_STEER_MUX_SELECT_2 = 5434;
static const uint64_t IDX_CEN_ECC23_MBSBS1_READ_BIT_STEER_MUX_SELECT_2_LEN = 5435;
static const uint64_t IDX_CEN_ECC23_MBSBS2_READ_BIT_STEER_MUX_SELECT_0 = 5436;
static const uint64_t IDX_CEN_ECC23_MBSBS2_READ_BIT_STEER_MUX_SELECT_0_LEN = 5437;
static const uint64_t IDX_CEN_ECC23_MBSBS2_READ_BIT_STEER_MUX_SELECT_1 = 5438;
static const uint64_t IDX_CEN_ECC23_MBSBS2_READ_BIT_STEER_MUX_SELECT_1_LEN = 5439;
static const uint64_t IDX_CEN_ECC23_MBSBS2_READ_BIT_STEER_MUX_SELECT_2 = 5440;
static const uint64_t IDX_CEN_ECC23_MBSBS2_READ_BIT_STEER_MUX_SELECT_2_LEN = 5441;
static const uint64_t IDX_CEN_ECC23_MBSBS3_READ_BIT_STEER_MUX_SELECT_0 = 5442;
static const uint64_t IDX_CEN_ECC23_MBSBS3_READ_BIT_STEER_MUX_SELECT_0_LEN = 5443;
static const uint64_t IDX_CEN_ECC23_MBSBS3_READ_BIT_STEER_MUX_SELECT_1 = 5444;
static const uint64_t IDX_CEN_ECC23_MBSBS3_READ_BIT_STEER_MUX_SELECT_1_LEN = 5445;
static const uint64_t IDX_CEN_ECC23_MBSBS3_READ_BIT_STEER_MUX_SELECT_2 = 5446;
static const uint64_t IDX_CEN_ECC23_MBSBS3_READ_BIT_STEER_MUX_SELECT_2_LEN = 5447;
static const uint64_t IDX_CEN_ECC23_MBSBS4_READ_BIT_STEER_MUX_SELECT_0 = 5448;
static const uint64_t IDX_CEN_ECC23_MBSBS4_READ_BIT_STEER_MUX_SELECT_0_LEN = 5449;
static const uint64_t IDX_CEN_ECC23_MBSBS4_READ_BIT_STEER_MUX_SELECT_1 = 5450;
static const uint64_t IDX_CEN_ECC23_MBSBS4_READ_BIT_STEER_MUX_SELECT_1_LEN = 5451;
static const uint64_t IDX_CEN_ECC23_MBSBS4_READ_BIT_STEER_MUX_SELECT_2 = 5452;
static const uint64_t IDX_CEN_ECC23_MBSBS4_READ_BIT_STEER_MUX_SELECT_2_LEN = 5453;
static const uint64_t IDX_CEN_ECC23_MBSBS5_READ_BIT_STEER_MUX_SELECT_0 = 5454;
static const uint64_t IDX_CEN_ECC23_MBSBS5_READ_BIT_STEER_MUX_SELECT_0_LEN = 5455;
static const uint64_t IDX_CEN_ECC23_MBSBS5_READ_BIT_STEER_MUX_SELECT_1 = 5456;
static const uint64_t IDX_CEN_ECC23_MBSBS5_READ_BIT_STEER_MUX_SELECT_1_LEN = 5457;
static const uint64_t IDX_CEN_ECC23_MBSBS5_READ_BIT_STEER_MUX_SELECT_2 = 5458;
static const uint64_t IDX_CEN_ECC23_MBSBS5_READ_BIT_STEER_MUX_SELECT_2_LEN = 5459;
static const uint64_t IDX_CEN_ECC23_MBSBS6_READ_BIT_STEER_MUX_SELECT_0 = 5460;
static const uint64_t IDX_CEN_ECC23_MBSBS6_READ_BIT_STEER_MUX_SELECT_0_LEN = 5461;
static const uint64_t IDX_CEN_ECC23_MBSBS6_READ_BIT_STEER_MUX_SELECT_1 = 5462;
static const uint64_t IDX_CEN_ECC23_MBSBS6_READ_BIT_STEER_MUX_SELECT_1_LEN = 5463;
static const uint64_t IDX_CEN_ECC23_MBSBS6_READ_BIT_STEER_MUX_SELECT_2 = 5464;
static const uint64_t IDX_CEN_ECC23_MBSBS6_READ_BIT_STEER_MUX_SELECT_2_LEN = 5465;
static const uint64_t IDX_CEN_ECC23_MBSBS7_READ_BIT_STEER_MUX_SELECT_0 = 5466;
static const uint64_t IDX_CEN_ECC23_MBSBS7_READ_BIT_STEER_MUX_SELECT_0_LEN = 5467;
static const uint64_t IDX_CEN_ECC23_MBSBS7_READ_BIT_STEER_MUX_SELECT_1 = 5468;
static const uint64_t IDX_CEN_ECC23_MBSBS7_READ_BIT_STEER_MUX_SELECT_1_LEN = 5469;
static const uint64_t IDX_CEN_ECC23_MBSBS7_READ_BIT_STEER_MUX_SELECT_2 = 5470;
static const uint64_t IDX_CEN_ECC23_MBSBS7_READ_BIT_STEER_MUX_SELECT_2_LEN = 5471;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS0_CHIP_PARITY = 5472;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS0_SYMBOL_PARITY = 5473;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS0_PARITY = 5474;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS1_CHIP_PARITY = 5475;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS1_SYMBOL_PARITY = 5476;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS1_PARITY = 5477;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS2_CHIP_PARITY = 5478;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS2_SYMBOL_PARITY = 5479;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS2_PARITY = 5480;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS3_CHIP_PARITY = 5481;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS3_SYMBOL_PARITY = 5482;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS3_PARITY = 5483;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS4_CHIP_PARITY = 5484;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS4_SYMBOL_PARITY = 5485;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS4_PARITY = 5486;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS5_CHIP_PARITY = 5487;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS5_SYMBOL_PARITY = 5488;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS5_PARITY = 5489;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS6_CHIP_PARITY = 5490;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS6_SYMBOL_PARITY = 5491;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS6_PARITY = 5492;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS7_CHIP_PARITY = 5493;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS7_SYMBOL_PARITY = 5494;
static const uint64_t IDX_CEN_ECC23_MBSECCERR0_MBMS7_PARITY = 5495;
static const uint64_t IDX_CEN_ECC23_MBSECCERR1_MEMORY_BIT_STEER_PARITY = 5496;
static const uint64_t IDX_CEN_ECC23_MBSECCERR1_MEMORY_BIT_STEER_PARITY_LEN = 5497;
static const uint64_t IDX_CEN_ECC23_MBSECCERR1_MBMMR_PARITY = 5498;
static const uint64_t IDX_CEN_ECC23_MBSECCERR1_MBRCEICR_PARITY = 5499;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 5500;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 5501;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_RESERVED_2 = 5502;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_ENABLE_64BYTE_DATA_CHECKBIT_INVERSION = 5503;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_USE_MAINTENANCE_MARK = 5504;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_DISABLE_MARK_STORE_WRITE = 5505;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_ENABLE_FIRST_SHADOW_READ_UE = 5506;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_ECC_METADATA_MODE = 5507;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_ECC_METADATA_MODE_LEN = 5508;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_SINGLE_WIRE_MODE = 5509;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_INT_RESET_KEEPER = 5510;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_INJECT_SCOM_PARITY_ERROR = 5511;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_INJECT_MARK_STORE_SYMBOL_PARITY_ERROR = 5512;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_INJECT_MARK_STORE_CHIP_PARITY_ERROR = 5513;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_MBRCEICRQ_DATAPATH_PARITY_ERROR_INJECT = 5514;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_REPORT_RCE_ON_CORRECTIONS = 5515;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_RESERVED_17_23 = 5516;
static const uint64_t IDX_CEN_ECC23_MBSECCQ_RESERVED_17_23_LEN = 5517;
static const uint64_t IDX_CEN_ECC23_MBSMSRQ_MARK_VALUE = 5518;
static const uint64_t IDX_CEN_ECC23_MBSMSRQ_MARK_VALUE_LEN = 5519;
static const uint64_t IDX_CEN_ECC23_MBSMSRQ_MARK_SHADOW_RANK = 5520;
static const uint64_t IDX_CEN_ECC23_MBSMSRQ_MARK_SHADOW_RANK_LEN = 5521;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_MASTER_RANK0 = 5522;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_DIMM_SELECT = 5523;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_MASTER_RANK1 = 5524;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_MASTER_RANK2 = 5525;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_SLAVE_RANK = 5526;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_SLAVE_RANK_LEN = 5527;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_BANK = 5528;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_BANK_LEN = 5529;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_ROW = 5530;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_ROW_LEN = 5531;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_COL = 5532;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_COL_LEN = 5533;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_ERR_OCCURRED_AFTER_UE_RETRY = 5534;
static const uint64_t IDX_CEN_MCBISTS23_MBMPERQ_RD_MPE_ROW17 = 5535;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_MASTER_RANK0 = 5536;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_DIMM_SELECT = 5537;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_MASTER_RANK1 = 5538;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_MASTER_RANK2 = 5539;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_SLAVE_RANK = 5540;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_SLAVE_RANK_LEN = 5541;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_BANK = 5542;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_BANK_LEN = 5543;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_ROW = 5544;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_ROW_LEN = 5545;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_COL = 5546;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_COL_LEN = 5547;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_ERR_OCCURRED__AFTER_UE_RETRY = 5548;
static const uint64_t IDX_CEN_MCBISTS23_MBNCERQ_RD_NCE_ROW17 = 5549;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_MASTER_RANK0 = 5550;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_DIMM_SELECT = 5551;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_MASTER_RANK1 = 5552;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_MASTER_RANK2 = 5553;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_SLAVE_RANK = 5554;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_SLAVE_RANK_LEN = 5555;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_BANK = 5556;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_BANK_LEN = 5557;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_ROW = 5558;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_ROW_LEN = 5559;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_COL = 5560;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_COL_LEN = 5561;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_ERR_OCCURRED_AFTER_UE_RETRY = 5562;
static const uint64_t IDX_CEN_MCBISTS23_MBRCERQ_RD_RCE_ROW17 = 5563;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_SOFT_CE_COUNT = 5564;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_SOFT_CE_COUNT_LEN = 5565;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_INTERMITTENT_CE_COUNT = 5566;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN = 5567;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_HARD_CE_COUNT = 5568;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_HARD_CE_COUNT_LEN = 5569;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_SCE_COUNT = 5570;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_SCE_COUNT_LEN = 5571;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_MCE_COUNT = 5572;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC0Q_MCE_COUNT_LEN = 5573;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC1Q_RCE_COUNT = 5574;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC1Q_RCE_COUNT_LEN = 5575;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC1Q_MPE_COUNT = 5576;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC1Q_MPE_COUNT_LEN = 5577;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC1Q_UE_COUNT = 5578;
static const uint64_t IDX_CEN_MCBISTS23_MBSEC1Q_UE_COUNT_LEN = 5579;
static const uint64_t IDX_CEN_MCBISTS23_MBSEVRQ_ERR_VECTOR0 = 5580;
static const uint64_t IDX_CEN_MCBISTS23_MBSEVRQ_ERR_VECTOR0_LEN = 5581;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT0_SCOM_PAR_ERRORS = 5582;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT0_MBX_PAR_ERRORS = 5583;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT0_RESERVED_2_14 = 5584;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT0_RESERVED_2_14_LEN = 5585;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT0_INTERNAL_SCOM_ERROR = 5586;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT0_INTERNAL_SCOM_ERROR_CLONE = 5587;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT1_SCOM_PAR_ERRORS = 5588;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT1_MBX_PAR_ERRORS = 5589;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT1_RESERVED_2_14 = 5590;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT1_RESERVED_2_14_LEN = 5591;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT1_INTERNAL_SCOM_ERROR = 5592;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRACT1_INTERNAL_SCOM_ERROR_CLONE = 5593;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRMASK_SCOM_PAR_ERRORS = 5594;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRMASK_MBX_PAR_ERRORS = 5595;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRMASK_RESERVED_2_14 = 5596;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRMASK_RESERVED_2_14_LEN = 5597;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRMASK_INTERNAL_SCOM_ERROR = 5598;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRMASK_INTERNAL_SCOM_ERROR_CLONE = 5599;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_SCOM_PAR_ERRORS = 5600;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_MBX_PAR_ERRORS = 5601;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_DRAM_EVENTN_BIT0 = 5602;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_DRAM_EVENTN_BIT1 = 5603;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_RESERVED_4_14 = 5604;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_RESERVED_4_14_LEN = 5605;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_INTERNAL_SCOM_ERROR = 5606;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE = 5607;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRWOF_SCOM_PAR_ERRORS = 5608;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRWOF_MBX_PAR_ERRORS = 5609;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRWOF_RESERVED_2_14 = 5610;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRWOF_RESERVED_2_14_LEN = 5611;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRWOF_INTERNAL_SCOM_ERROR = 5612;
static const uint64_t IDX_CEN_MCBISTS23_MBSFIRWOF_INTERNAL_SCOM_ERROR_CLONE = 5613;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_0_ERROR_COUNT = 5614;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_0_ERROR_COUNT_LEN = 5615;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_1_ERROR_COUNT = 5616;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_1_ERROR_COUNT_LEN = 5617;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_2_ERROR_COUNT = 5618;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_2_ERROR_COUNT_LEN = 5619;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_3_ERROR_COUNT = 5620;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_3_ERROR_COUNT_LEN = 5621;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_4_ERROR_COUNT = 5622;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_4_ERROR_COUNT_LEN = 5623;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_5_ERROR_COUNT = 5624;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_5_ERROR_COUNT_LEN = 5625;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_6_ERROR_COUNT = 5626;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_6_ERROR_COUNT_LEN = 5627;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_7_ERROR_COUNT = 5628;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC0Q_SYMBOL_7_ERROR_COUNT_LEN = 5629;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_8_ERROR_COUNT = 5630;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_8_ERROR_COUNT_LEN = 5631;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_9_ERROR_COUNT = 5632;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_9_ERROR_COUNT_LEN = 5633;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_10_ERROR_COUNT = 5634;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_10_ERROR_COUNT_LEN = 5635;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_11_ERROR_COUNT = 5636;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_11_ERROR_COUNT_LEN = 5637;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_12_ERROR_COUNT = 5638;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_12_ERROR_COUNT_LEN = 5639;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_13_ERROR_COUNT = 5640;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_13_ERROR_COUNT_LEN = 5641;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_14_ERROR_COUNT = 5642;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_14_ERROR_COUNT_LEN = 5643;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_15_ERROR_COUNT = 5644;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC1Q_SYMBOL_15_ERROR_COUNT_LEN = 5645;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_16_ERROR_COUNT = 5646;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_16_ERROR_COUNT_LEN = 5647;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_17_ERROR_COUNT = 5648;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_17_ERROR_COUNT_LEN = 5649;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_18_ERROR_COUNT = 5650;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_18_ERROR_COUNT_LEN = 5651;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_19_ERROR_COUNT = 5652;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_19_ERROR_COUNT_LEN = 5653;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_20_ERROR_COUNT = 5654;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_20_ERROR_COUNT_LEN = 5655;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_21_ERROR_COUNT = 5656;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_21_ERROR_COUNT_LEN = 5657;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_22_ERROR_COUNT = 5658;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_22_ERROR_COUNT_LEN = 5659;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_23_ERROR_COUNT = 5660;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC2Q_SYMBOL_23_ERROR_COUNT_LEN = 5661;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_24_ERROR_COUNT = 5662;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_24_ERROR_COUNT_LEN = 5663;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_25_ERROR_COUNT = 5664;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_25_ERROR_COUNT_LEN = 5665;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_26_ERROR_COUNT = 5666;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_26_ERROR_COUNT_LEN = 5667;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_27_ERROR_COUNT = 5668;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_27_ERROR_COUNT_LEN = 5669;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_28_ERROR_COUNT = 5670;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_28_ERROR_COUNT_LEN = 5671;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_29_ERROR_COUNT = 5672;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_29_ERROR_COUNT_LEN = 5673;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_30_ERROR_COUNT = 5674;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_30_ERROR_COUNT_LEN = 5675;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_31_ERROR_COUNT = 5676;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC3Q_SYMBOL_31_ERROR_COUNT_LEN = 5677;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_32_ERROR_COUNT = 5678;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_32_ERROR_COUNT_LEN = 5679;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_33_ERROR_COUNT = 5680;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_33_ERROR_COUNT_LEN = 5681;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_34_ERROR_COUNT = 5682;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_34_ERROR_COUNT_LEN = 5683;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_35_ERROR_COUNT = 5684;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_35_ERROR_COUNT_LEN = 5685;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_36_ERROR_COUNT = 5686;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_36_ERROR_COUNT_LEN = 5687;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_37_ERROR_COUNT = 5688;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_37_ERROR_COUNT_LEN = 5689;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_38ERROR_COUNT = 5690;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_38ERROR_COUNT_LEN = 5691;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_39_ERROR_COUNT = 5692;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC4Q_SYMBOL_39_ERROR_COUNT_LEN = 5693;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_40_ERROR_COUNT = 5694;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_40_ERROR_COUNT_LEN = 5695;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_41_ERROR_COUNT = 5696;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_41_ERROR_COUNT_LEN = 5697;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_42_ERROR_COUNT = 5698;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_42_ERROR_COUNT_LEN = 5699;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_43_ERROR_COUNT = 5700;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_43_ERROR_COUNT_LEN = 5701;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_44_ERROR_COUNT = 5702;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_44_ERROR_COUNT_LEN = 5703;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_45_ERROR_COUNT = 5704;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_45_ERROR_COUNT_LEN = 5705;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_46_ERROR_COUNT = 5706;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_46_ERROR_COUNT_LEN = 5707;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_47_ERROR_COUNT = 5708;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC5Q_SYMBOL_47_ERROR_COUNT_LEN = 5709;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_48_ERROR_COUNT = 5710;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_48_ERROR_COUNT_LEN = 5711;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_49_ERROR_COUNT = 5712;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_49_ERROR_COUNT_LEN = 5713;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_50_ERROR_COUNT = 5714;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_50_ERROR_COUNT_LEN = 5715;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_51_ERROR_COUNT = 5716;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_51_ERROR_COUNT_LEN = 5717;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_52_ERROR_COUNT = 5718;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_52_ERROR_COUNT_LEN = 5719;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_53_ERROR_COUNT = 5720;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_53_ERROR_COUNT_LEN = 5721;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_54_ERROR_COUNT = 5722;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_54_ERROR_COUNT_LEN = 5723;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_55_ERROR_COUNT = 5724;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC6Q_SYMBOL_55_ERROR_COUNT_LEN = 5725;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_56_ERROR_COUNT = 5726;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_56_ERROR_COUNT_LEN = 5727;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_57_ERROR_COUNT = 5728;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_57_ERROR_COUNT_LEN = 5729;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_58_ERROR_COUNT = 5730;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_58_ERROR_COUNT_LEN = 5731;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_59_ERROR_COUNT = 5732;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_59_ERROR_COUNT_LEN = 5733;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_60_ERROR_COUNT = 5734;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_60_ERROR_COUNT_LEN = 5735;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_61_ERROR_COUNT = 5736;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_61_ERROR_COUNT_LEN = 5737;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_62_ERROR_COUNT = 5738;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_62_ERROR_COUNT_LEN = 5739;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_63_ERROR_COUNT = 5740;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC7Q_SYMBOL_63_ERROR_COUNT_LEN = 5741;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_64_ERROR_COUNT = 5742;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_64_ERROR_COUNT_LEN = 5743;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_65_ERROR_COUNT = 5744;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_65_ERROR_COUNT_LEN = 5745;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_66_ERROR_COUNT = 5746;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_66_ERROR_COUNT_LEN = 5747;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_67_ERROR_COUNT = 5748;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_67_ERROR_COUNT_LEN = 5749;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_68_ERROR_COUNT = 5750;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_68_ERROR_COUNT_LEN = 5751;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_69_ERROR_COUNT = 5752;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_69_ERROR_COUNT_LEN = 5753;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_70_ERROR_COUNT = 5754;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_70_ERROR_COUNT_LEN = 5755;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_71_ERROR_COUNT = 5756;
static const uint64_t IDX_CEN_MCBISTS23_MBSSYMEC8Q_SYMBOL_71_ERROR_COUNT_LEN = 5757;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_SOFT_CE_COUNT_THRESHOLD_ATTN_STOP = 5758;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_INTERMITTENT_CE_COUNT_THRESHOLD_ATTN_STOP = 5759;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_HARD_CE_COUNT_THRESHOLD_ATTN_STOP = 5760;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_RCE_COUNT_THRESHOLD_ATTN_STOP = 5761;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_SOFT_CE_COUNT_THRESHOLD = 5762;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_SOFT_CE_COUNT_THRESHOLD_LEN = 5763;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_INTERMITTENT_CE_COUNT_THRESHOLD = 5764;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_INTERMITTENT_CE_COUNT_THRESHOLD_LEN = 5765;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_HARD_CE_COUNT_THRESHOLD = 5766;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_HARD_CE_COUNT_THRESHOLD_LEN = 5767;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_RETRY_CE_COUNT_THRESHOLD = 5768;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_RETRY_CE_COUNT_THRESHOLD_LEN = 5769;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_RESET_KEEPER = 5770;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_RESET_ALL_ERROR_COUNT_REGISTERS = 5771;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_DISABLE_RESET_ERROR_REG_RANK_END = 5772;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_SOFT_CE_INCR_SYMBOL_COUNT = 5773;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_INTERMIT_INCR_SYMBOL_COUNT = 5774;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_HARD_CE_INCR_SYMBOL_COUNT = 5775;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_MCE_INCR_SYMBOL_COUNT = 5776;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_UE_TRAP = 5777;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_CFG_MAINT_RCE_WITH_CE = 5778;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_RESERVED_61 = 5779;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_INTERMITTENT_NCE_INJECT = 5780;
static const uint64_t IDX_CEN_MCBISTS23_MBSTRQ_RESERVED_63 = 5781;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_CFG_DATA_ROT = 5782;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_CFG_DATA_ROT_LEN = 5783;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_CFG_DATA_ROT_SEED = 5784;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN = 5785;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_CFG_INVERT_DATA = 5786;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_DD2_HW234828_ROUTE_NONMAINT_DATA_TO_MAINTBUFF_EN = 5787;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_RESERVED_22_63 = 5788;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRCRQ_RESERVED_22_63_LEN = 5789;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRSRQ_CFG_DATA_ROT_SEED = 5790;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN = 5791;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD0Q_CFG_FIXED_SEED = 5792;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD0Q_CFG_FIXED_SEED_LEN = 5793;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD1Q_CFG_FIXED_SEED = 5794;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD1Q_CFG_FIXED_SEED_LEN = 5795;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD2Q_CFG_FIXED_SEED = 5796;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD2Q_CFG_FIXED_SEED_LEN = 5797;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD3Q_CFG_FIXED_SEED = 5798;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD3Q_CFG_FIXED_SEED_LEN = 5799;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD4Q_CFG_FIXED_SEED = 5800;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD4Q_CFG_FIXED_SEED_LEN = 5801;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD5Q_CFG_FIXED_SEED = 5802;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD5Q_CFG_FIXED_SEED_LEN = 5803;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD6Q_CFG_FIXED_SEED = 5804;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD6Q_CFG_FIXED_SEED_LEN = 5805;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD7Q_CFG_FIXED_SEED = 5806;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFD7Q_CFG_FIXED_SEED_LEN = 5807;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED1 = 5808;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED1_LEN = 5809;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED2 = 5810;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED2_LEN = 5811;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED3 = 5812;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED3_LEN = 5813;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED4 = 5814;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED4_LEN = 5815;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED5 = 5816;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED5_LEN = 5817;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED6 = 5818;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED6_LEN = 5819;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED7 = 5820;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED7_LEN = 5821;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED8 = 5822;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDQ_CFG_FIXED_SEED8_LEN = 5823;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED1 = 5824;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED1_LEN = 5825;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED2 = 5826;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED2_LEN = 5827;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED3 = 5828;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED3_LEN = 5829;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED4 = 5830;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED4_LEN = 5831;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED5 = 5832;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED5_LEN = 5833;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED6 = 5834;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED6_LEN = 5835;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED7 = 5836;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED7_LEN = 5837;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED8 = 5838;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBFDSPQ_CFG_FIXED_SEED8_LEN = 5839;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED0 = 5840;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED0_LEN = 5841;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED1 = 5842;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED1_LEN = 5843;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED2 = 5844;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED2_LEN = 5845;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED3 = 5846;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED3_LEN = 5847;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED4 = 5848;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED4_LEN = 5849;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED5 = 5850;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED5_LEN = 5851;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED6 = 5852;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED6_LEN = 5853;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED7 = 5854;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS0Q_DGEN_RNDD_SEED7_LEN = 5855;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED0 = 5856;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED0_LEN = 5857;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED1 = 5858;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED1_LEN = 5859;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED2 = 5860;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED2_LEN = 5861;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED3 = 5862;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED3_LEN = 5863;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED4 = 5864;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED4_LEN = 5865;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED5 = 5866;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED5_LEN = 5867;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED6 = 5868;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED6_LEN = 5869;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED7 = 5870;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS1Q_DGEN_RNDD_SEED7_LEN = 5871;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED0 = 5872;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED0_LEN = 5873;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED1 = 5874;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED1_LEN = 5875;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED2 = 5876;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED2_LEN = 5877;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED3 = 5878;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED3_LEN = 5879;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED4 = 5880;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED4_LEN = 5881;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED5 = 5882;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED5_LEN = 5883;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED6 = 5884;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED6_LEN = 5885;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED7 = 5886;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS2Q_DGEN_RNDD_SEED7_LEN = 5887;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED0 = 5888;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED0_LEN = 5889;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED1 = 5890;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED1_LEN = 5891;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED2 = 5892;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED2_LEN = 5893;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED3 = 5894;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED3_LEN = 5895;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED4 = 5896;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED4_LEN = 5897;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED5 = 5898;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED5_LEN = 5899;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED6 = 5900;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED6_LEN = 5901;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED7 = 5902;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS3Q_DGEN_RNDD_SEED7_LEN = 5903;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED0 = 5904;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED0_LEN = 5905;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED1 = 5906;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED1_LEN = 5907;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED2 = 5908;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED2_LEN = 5909;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED3 = 5910;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED3_LEN = 5911;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED4 = 5912;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED4_LEN = 5913;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED5 = 5914;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED5_LEN = 5915;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED6 = 5916;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED6_LEN = 5917;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED7 = 5918;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS4Q_DGEN_RNDD_SEED7_LEN = 5919;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED0 = 5920;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED0_LEN = 5921;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED1 = 5922;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED1_LEN = 5923;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED2 = 5924;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED2_LEN = 5925;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED3 = 5926;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED3_LEN = 5927;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED4 = 5928;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED4_LEN = 5929;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED5 = 5930;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED5_LEN = 5931;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED6 = 5932;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED6_LEN = 5933;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED7 = 5934;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS5Q_DGEN_RNDD_SEED7_LEN = 5935;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED0 = 5936;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED0_LEN = 5937;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED1 = 5938;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED1_LEN = 5939;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED2 = 5940;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED2_LEN = 5941;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED3 = 5942;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED3_LEN = 5943;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED4 = 5944;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED4_LEN = 5945;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED5 = 5946;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED5_LEN = 5947;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED6 = 5948;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED6_LEN = 5949;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED7 = 5950;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS6Q_DGEN_RNDD_SEED7_LEN = 5951;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED0 = 5952;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED0_LEN = 5953;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED1 = 5954;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED1_LEN = 5955;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED2 = 5956;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED2_LEN = 5957;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED3 = 5958;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED3_LEN = 5959;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED4 = 5960;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED4_LEN = 5961;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED5 = 5962;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED5_LEN = 5963;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED6 = 5964;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED6_LEN = 5965;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED7 = 5966;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS7Q_DGEN_RNDD_SEED7_LEN = 5967;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED0 = 5968;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED0_LEN = 5969;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED1 = 5970;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED1_LEN = 5971;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED2 = 5972;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED2_LEN = 5973;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED3 = 5974;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED3_LEN = 5975;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED4 = 5976;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED4_LEN = 5977;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED5 = 5978;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED5_LEN = 5979;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED6 = 5980;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED6_LEN = 5981;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED7 = 5982;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDS8Q_DGEN_RNDD_SEED7_LEN = 5983;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED0 = 5984;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED0_LEN = 5985;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED1 = 5986;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED1_LEN = 5987;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED2 = 5988;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED2_LEN = 5989;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED3 = 5990;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED3_LEN = 5991;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED4 = 5992;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED4_LEN = 5993;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED5 = 5994;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED5_LEN = 5995;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED6 = 5996;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED6_LEN = 5997;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED7 = 5998;
static const uint64_t IDX_CEN_MCBISTS23_MBS_MCBRDSSPQ_DGEN_RNDD_SEED7_LEN = 5999;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_MASTER_RANK0 = 6000;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_DIMM_SELECT = 6001;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_MASTER_RANK1 = 6002;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_MASTER_RANK2 = 6003;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_SLAVE_RANK = 6004;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_SLAVE_RANK_LEN = 6005;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_BANK = 6006;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_BANK_LEN = 6007;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_ROW = 6008;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_ROW_LEN = 6009;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_COL = 6010;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_COL_LEN = 6011;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RESERVED_40 = 6012;
static const uint64_t IDX_CEN_MCBISTS23_MBUERQ_RD_UE_ROW17 = 6013;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_RCMD_ERR_INJ_MODE = 6014;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_RCMD_ERR_INJ = 6015;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_WRD_CE_ERR_INJ_MODE = 6016;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_WRD_CE_ERR_INJ = 6017;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_WRD_UE_ERR_INJ_MODE = 6018;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_WRD_UE_ERR_INJ = 6019;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_MAINT_CE_ERR_INJ_MODE = 6020;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_MAINT_CE_ERR_INJ = 6021;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_MAINT_UE_ERR_INJ_MODE = 6022;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_MAINT_UE_ERR_INJ = 6023;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_SCOM_PE_ERR_INJ_MODE = 6024;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_SCOM_PE_ERR_INJ = 6025;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_RESERVED_12_63 = 6026;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRINJQ_RESERVED_12_63_LEN = 6027;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRSTATQ_WDONE_PAR_ERROR = 6028;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRSTATQ_RDTAG_RDCHECK_ERROR = 6029;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRSTATQ_RDTAG_PAR_ERROR = 6030;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRSTATQ_RDTAG_PAR_RC_ERROR = 6031;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRSTATQ_RESERVED_4_63 = 6032;
static const uint64_t IDX_CEN_MCBISTS23_MBXERRSTATQ_RESERVED_4_63_LEN = 6033;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMA1Q_COMPARE_MASK_A = 6034;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMA1Q_COMPARE_MASK_A_LEN = 6035;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_COMPARE_MASK_A = 6036;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_COMPARE_MASK_A_LEN = 6037;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_COMPARE_MASK_B = 6038;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_COMPARE_MASK_B_LEN = 6039;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_CFG_STORE_FAIL = 6040;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_MCBIST_ENABLE_CE_TRAP = 6041;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_MCBIST_ENABLE_MPE_TRAP = 6042;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_ENABLE_UE_TRAP = 6043;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_MCBIST_STOP_ON_NTH_FAIL = 6044;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_ARRAY_READ_ENABLE = 6045;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_RESERVED_38_63 = 6046;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMABQ_RESERVED_38_63_LEN = 6047;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMB1Q_COMPARE_MASK_B = 6048;
static const uint64_t IDX_CEN_MCBISTS23_MCBCMB1Q_COMPARE_MASK_B_LEN = 6049;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_ERROR_MAP_PORTA_RNK0 = 6050;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_ERROR_MAP_PORTA_RNK0_LEN = 6051;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_ERROR_MAP_PORTA_RNK1 = 6052;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_ERROR_MAP_PORTA_RNK1_LEN = 6053;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_ERROR_MAP_PORTA_RNK2 = 6054;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_ERROR_MAP_PORTA_RNK2_LEN = 6055;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_RESERVED_60_63 = 6056;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA1Q_RESERVED_60_63_LEN = 6057;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_ERROR_MAP_PORTA_RNK3 = 6058;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_ERROR_MAP_PORTA_RNK3_LEN = 6059;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_ERROR_MAP_PORTA_RNK4 = 6060;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_ERROR_MAP_PORTA_RNK4_LEN = 6061;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_ERROR_MAP_PORTA_RNK5 = 6062;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_ERROR_MAP_PORTA_RNK5_LEN = 6063;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_RESERVED_60_63 = 6064;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA2Q_RESERVED_60_63_LEN = 6065;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA3Q_ERROR_MAP_PORTA_RNK6 = 6066;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA3Q_ERROR_MAP_PORTA_RNK6_LEN = 6067;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA3Q_ERROR_MAP_PORTA_RNK7 = 6068;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA3Q_ERROR_MAP_PORTA_RNK7_LEN = 6069;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA3Q_RESERVED_40_63 = 6070;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMA3Q_RESERVED_40_63_LEN = 6071;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_ERROR_MAP_PORTB_RNK0 = 6072;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_ERROR_MAP_PORTB_RNK0_LEN = 6073;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_ERROR_MAP_PORTB_RNK1 = 6074;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_ERROR_MAP_PORTB_RNK1_LEN = 6075;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_ERROR_MAP_PORTB_RNK2 = 6076;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_ERROR_MAP_PORTB_RNK2_LEN = 6077;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_RESERVED_60_63 = 6078;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB1Q_RESERVED_60_63_LEN = 6079;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_ERROR_MAP_PORTB_RNK3 = 6080;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_ERROR_MAP_PORTB_RNK3_LEN = 6081;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_ERROR_MAP_PORTB_RNK4 = 6082;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_ERROR_MAP_PORTB_RNK4_LEN = 6083;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_ERROR_MAP_PORTB_RNK5 = 6084;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_ERROR_MAP_PORTB_RNK5_LEN = 6085;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_RESERVED_60_63 = 6086;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB2Q_RESERVED_60_63_LEN = 6087;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB3Q_ERROR_MAP_PORTB_RNK6 = 6088;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB3Q_ERROR_MAP_PORTB_RNK6_LEN = 6089;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB3Q_ERROR_MAP_PORTB_RNK7 = 6090;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB3Q_ERROR_MAP_PORTB_RNK7_LEN = 6091;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB3Q_RESERVED_40_63 = 6092;
static const uint64_t IDX_CEN_MCBISTS23_MCBEMB3Q_RESERVED_40_63_LEN = 6093;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_PORTA_CE_ERR = 6094;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_PORTA_UE_ERR = 6095;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_PORTA_ERR_TRAP_OVERFLOW = 6096;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_PORTA_CNTL_TRAP_SUBTST_NUM = 6097;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_PORTA_CNTL_TRAP_SUBTST_NUM_LEN = 6098;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_PORTA_ERR_LOG_PTR = 6099;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_PORTA_ERR_LOG_PTR_LEN = 6100;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_RESERVED_11_23 = 6101;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATAQ_RESERVED_11_23_LEN = 6102;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_PORTB_CE_ERR = 6103;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_PORTB_UE_ERR = 6104;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_PORTB_ERR_TRAP_OVERFLOW = 6105;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_PORTB_CNTL_TRAP_SUBTST_NUM = 6106;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_PORTB_CNTL_TRAP_SUBTST_NUM_LEN = 6107;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_PORTB_ERR_LOG_PTR = 6108;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_PORTB_ERR_LOG_PTR_LEN = 6109;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_RESERVED_11_23 = 6110;
static const uint64_t IDX_CEN_MCBISTS23_MCBSTATBQ_RESERVED_11_23_LEN = 6111;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR0 = 6112;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR0_LEN = 6113;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR1 = 6114;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR1_LEN = 6115;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR2 = 6116;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR2_LEN = 6117;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR3 = 6118;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR3_LEN = 6119;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR4 = 6120;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR4_LEN = 6121;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR5 = 6122;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR5_LEN = 6123;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR6 = 6124;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR6_LEN = 6125;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR7 = 6126;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR7_LEN = 6127;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR8 = 6128;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_NIBBLE_ERR_PORTA_CNTR8_LEN = 6129;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA1Q_RESERVED_63 = 6130;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR9 = 6131;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR9_LEN = 6132;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR10 = 6133;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR10_LEN = 6134;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR11 = 6135;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR11_LEN = 6136;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR12 = 6137;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR12_LEN = 6138;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR13 = 6139;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR13_LEN = 6140;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR14 = 6141;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR14_LEN = 6142;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR15 = 6143;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR15_LEN = 6144;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR16 = 6145;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR16_LEN = 6146;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR17 = 6147;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_NIBBLE_ERR_PORTA_CNTR17_LEN = 6148;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA2Q_ERR_CNTR_OVERFLOW = 6149;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR18 = 6150;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR18_LEN = 6151;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR19 = 6152;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA3Q_NIBBLE_ERR_PORTA_CNTR19_LEN = 6153;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA3Q_RESERVED_14_63 = 6154;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTA3Q_RESERVED_14_63_LEN = 6155;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR0 = 6156;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR0_LEN = 6157;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR1 = 6158;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR1_LEN = 6159;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR2 = 6160;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR2_LEN = 6161;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR3 = 6162;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR3_LEN = 6163;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR4 = 6164;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR4_LEN = 6165;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR5 = 6166;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR5_LEN = 6167;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR6 = 6168;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR6_LEN = 6169;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR7 = 6170;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR7_LEN = 6171;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR8 = 6172;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_NIBBLE_ERR_PORTB_CNTR8_LEN = 6173;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB1Q_RESERVED_63 = 6174;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR9 = 6175;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR9_LEN = 6176;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR10 = 6177;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR10_LEN = 6178;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR11 = 6179;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR11_LEN = 6180;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR12 = 6181;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR12_LEN = 6182;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR13 = 6183;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR13_LEN = 6184;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR14 = 6185;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR14_LEN = 6186;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR15 = 6187;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR15_LEN = 6188;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR16 = 6189;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR16_LEN = 6190;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR17 = 6191;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_NIBBLE_ERR_PORTB_CNTR17_LEN = 6192;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB2Q_ERR_CNTR_OVERFLOW = 6193;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR18 = 6194;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR18_LEN = 6195;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR19 = 6196;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB3Q_NIBBLE_ERR_PORTB_CNTR19_LEN = 6197;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB3Q_RESERVED_14_63 = 6198;
static const uint64_t IDX_CEN_MCBISTS23_MCB_ERRCNTB3Q_RESERVED_14_63_LEN = 6199;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA0_DATA = 6200;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA0_DATA_LEN = 6201;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA1_DATA = 6202;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA1_DATA_LEN = 6203;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA2_DATA = 6204;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA2_DATA_LEN = 6205;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA3_DATA = 6206;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA3_DATA_LEN = 6207;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA4_DATA = 6208;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA4_DATA_LEN = 6209;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA5_DATA = 6210;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA5_DATA_LEN = 6211;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA6_DATA = 6212;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA6_DATA_LEN = 6213;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA7_DATA = 6214;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF0_DATA7_DATA_LEN = 6215;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA0_DATA = 6216;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA0_DATA_LEN = 6217;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA1_DATA = 6218;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA1_DATA_LEN = 6219;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA2_DATA = 6220;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA2_DATA_LEN = 6221;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA3_DATA = 6222;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA3_DATA_LEN = 6223;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA4_DATA = 6224;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA4_DATA_LEN = 6225;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA5_DATA = 6226;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA5_DATA_LEN = 6227;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA6_DATA = 6228;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA6_DATA_LEN = 6229;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA7_DATA = 6230;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF1_DATA7_DATA_LEN = 6231;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA0_DATA = 6232;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA0_DATA_LEN = 6233;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA1_DATA = 6234;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA1_DATA_LEN = 6235;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA2_DATA = 6236;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA2_DATA_LEN = 6237;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA3_DATA = 6238;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA3_DATA_LEN = 6239;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA4_DATA = 6240;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA4_DATA_LEN = 6241;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA5_DATA = 6242;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA5_DATA_LEN = 6243;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA6_DATA = 6244;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA6_DATA_LEN = 6245;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA7_DATA = 6246;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF2_DATA7_DATA_LEN = 6247;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA0_DATA = 6248;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA0_DATA_LEN = 6249;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA1_DATA = 6250;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA1_DATA_LEN = 6251;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA2_DATA = 6252;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA2_DATA_LEN = 6253;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA3_DATA = 6254;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA3_DATA_LEN = 6255;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA4_DATA = 6256;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA4_DATA_LEN = 6257;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA5_DATA = 6258;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA5_DATA_LEN = 6259;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA6_DATA = 6260;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA6_DATA_LEN = 6261;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA7_DATA = 6262;
static const uint64_t IDX_CEN_MBS01_SRB_BUFF3_DATA7_DATA_LEN = 6263;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA0_DATA = 6264;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA0_DATA_LEN = 6265;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA1_DATA = 6266;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA1_DATA_LEN = 6267;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA2_DATA = 6268;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA2_DATA_LEN = 6269;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA3_DATA = 6270;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA3_DATA_LEN = 6271;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA4_DATA = 6272;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA4_DATA_LEN = 6273;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA5_DATA = 6274;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA5_DATA_LEN = 6275;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA6_DATA = 6276;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA6_DATA_LEN = 6277;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA7_DATA = 6278;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF0_DATA7_DATA_LEN = 6279;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA0_DATA = 6280;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA0_DATA_LEN = 6281;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA1_DATA = 6282;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA1_DATA_LEN = 6283;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA2_DATA = 6284;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA2_DATA_LEN = 6285;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA3_DATA = 6286;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA3_DATA_LEN = 6287;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA4_DATA = 6288;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA4_DATA_LEN = 6289;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA5_DATA = 6290;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA5_DATA_LEN = 6291;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA6_DATA = 6292;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA6_DATA_LEN = 6293;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA7_DATA = 6294;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF1_DATA7_DATA_LEN = 6295;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA0_DATA = 6296;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA0_DATA_LEN = 6297;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA1_DATA = 6298;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA1_DATA_LEN = 6299;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA2_DATA = 6300;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA2_DATA_LEN = 6301;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA3_DATA = 6302;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA3_DATA_LEN = 6303;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA4_DATA = 6304;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA4_DATA_LEN = 6305;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA5_DATA = 6306;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA5_DATA_LEN = 6307;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA6_DATA = 6308;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA6_DATA_LEN = 6309;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA7_DATA = 6310;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF2_DATA7_DATA_LEN = 6311;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA0_DATA = 6312;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA0_DATA_LEN = 6313;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA1_DATA = 6314;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA1_DATA_LEN = 6315;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA2_DATA = 6316;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA2_DATA_LEN = 6317;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA3_DATA = 6318;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA3_DATA_LEN = 6319;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA4_DATA = 6320;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA4_DATA_LEN = 6321;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA5_DATA = 6322;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA5_DATA_LEN = 6323;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA6_DATA = 6324;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA6_DATA_LEN = 6325;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA7_DATA = 6326;
static const uint64_t IDX_CEN_MBS23_SRB_BUFF3_DATA7_DATA_LEN = 6327;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA0_DATA = 6328;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA0_DATA_LEN = 6329;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA1_DATA = 6330;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA1_DATA_LEN = 6331;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA2_DATA = 6332;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA2_DATA_LEN = 6333;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA3_DATA = 6334;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA3_DATA_LEN = 6335;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA4_DATA = 6336;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA4_DATA_LEN = 6337;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA5_DATA = 6338;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA5_DATA_LEN = 6339;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA6_DATA = 6340;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA6_DATA_LEN = 6341;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA7_DATA = 6342;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF0_DATA7_DATA_LEN = 6343;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA0_DATA = 6344;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA0_DATA_LEN = 6345;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA1_DATA = 6346;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA1_DATA_LEN = 6347;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA2_DATA = 6348;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA2_DATA_LEN = 6349;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA3_DATA = 6350;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA3_DATA_LEN = 6351;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA4_DATA = 6352;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA4_DATA_LEN = 6353;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA5_DATA = 6354;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA5_DATA_LEN = 6355;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA6_DATA = 6356;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA6_DATA_LEN = 6357;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA7_DATA = 6358;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF1_DATA7_DATA_LEN = 6359;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA0_DATA = 6360;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA0_DATA_LEN = 6361;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA1_DATA = 6362;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA1_DATA_LEN = 6363;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA2_DATA = 6364;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA2_DATA_LEN = 6365;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA3_DATA = 6366;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA3_DATA_LEN = 6367;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA4_DATA = 6368;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA4_DATA_LEN = 6369;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA5_DATA = 6370;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA5_DATA_LEN = 6371;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA6_DATA = 6372;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA6_DATA_LEN = 6373;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA7_DATA = 6374;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF2_DATA7_DATA_LEN = 6375;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA0_DATA = 6376;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA0_DATA_LEN = 6377;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA1_DATA = 6378;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA1_DATA_LEN = 6379;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA2_DATA = 6380;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA2_DATA_LEN = 6381;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA3_DATA = 6382;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA3_DATA_LEN = 6383;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA4_DATA = 6384;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA4_DATA_LEN = 6385;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA5_DATA = 6386;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA5_DATA_LEN = 6387;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA6_DATA = 6388;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA6_DATA_LEN = 6389;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA7_DATA = 6390;
static const uint64_t IDX_CEN_MBS01_PFB_BUFF3_DATA7_DATA_LEN = 6391;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA0_DATA = 6392;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA0_DATA_LEN = 6393;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA1_DATA = 6394;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA1_DATA_LEN = 6395;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA2_DATA = 6396;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA2_DATA_LEN = 6397;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA3_DATA = 6398;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA3_DATA_LEN = 6399;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA4_DATA = 6400;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA4_DATA_LEN = 6401;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA5_DATA = 6402;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA5_DATA_LEN = 6403;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA6_DATA = 6404;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA6_DATA_LEN = 6405;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA7_DATA = 6406;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF0_DATA7_DATA_LEN = 6407;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA0_DATA = 6408;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA0_DATA_LEN = 6409;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA1_DATA = 6410;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA1_DATA_LEN = 6411;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA2_DATA = 6412;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA2_DATA_LEN = 6413;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA3_DATA = 6414;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA3_DATA_LEN = 6415;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA4_DATA = 6416;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA4_DATA_LEN = 6417;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA5_DATA = 6418;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA5_DATA_LEN = 6419;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA6_DATA = 6420;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA6_DATA_LEN = 6421;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA7_DATA = 6422;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF1_DATA7_DATA_LEN = 6423;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA0_DATA = 6424;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA0_DATA_LEN = 6425;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA1_DATA = 6426;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA1_DATA_LEN = 6427;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA2_DATA = 6428;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA2_DATA_LEN = 6429;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA3_DATA = 6430;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA3_DATA_LEN = 6431;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA4_DATA = 6432;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA4_DATA_LEN = 6433;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA5_DATA = 6434;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA5_DATA_LEN = 6435;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA6_DATA = 6436;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA6_DATA_LEN = 6437;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA7_DATA = 6438;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF2_DATA7_DATA_LEN = 6439;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA0_DATA = 6440;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA0_DATA_LEN = 6441;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA1_DATA = 6442;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA1_DATA_LEN = 6443;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA2_DATA = 6444;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA2_DATA_LEN = 6445;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA3_DATA = 6446;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA3_DATA_LEN = 6447;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA4_DATA = 6448;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA4_DATA_LEN = 6449;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA5_DATA = 6450;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA5_DATA_LEN = 6451;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA6_DATA = 6452;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA6_DATA_LEN = 6453;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA7_DATA = 6454;
static const uint64_t IDX_CEN_MBS23_PFB_BUFF3_DATA7_DATA_LEN = 6455;
static const uint64_t IDX_CEN_MBIERPT0_MBISTAT_PARITY_ERROR = 6456;
static const uint64_t IDX_CEN_MBIERPT0_MBICRCSYN_PARITY_ERROR = 6457;
static const uint64_t IDX_CEN_MBIERPT0_MBIERRINJ_PARITY_ERROR = 6458;
static const uint64_t IDX_CEN_MBIERPT0_MBIFPGAINTR_PARITY_ERROR = 6459;
static const uint64_t IDX_CEN_MBIERPT0_CRCG_DATAFLOW_PARITY_ERROR = 6460;
static const uint64_t IDX_CEN_MBIERPT0_ECCG_DATAFLOW_PARITY_ERROR = 6461;
static const uint64_t IDX_CEN_MBIERPT0_US_CHINIT_READY_TIMEOUT_ERROR = 6462;
static const uint64_t IDX_CEN_MBIERPT0_DS_FRAME_START_TIMEOUT_ERROR = 6463;
static const uint64_t IDX_CEN_MBIERPT0_DS_NULL_PACKET_TIMEOUT_ERROR = 6464;
static const uint64_t IDX_CEN_MBIERPT0_DS_ACK_PACKET_TIMEOUT_ERROR = 6465;
static const uint64_t IDX_CEN_MBIERPT0_FRTL_SM_PARITY_ERROR = 6466;
static const uint64_t IDX_CEN_MBIERPT0_FL_SM_PARITY_ERROR = 6467;
static const uint64_t IDX_CEN_MBIERPT0_GLOBAL_SM_PARITY_ERROR = 6468;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY0_SM_PARITY_ERROR = 6469;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY1_SM_PARITY_ERROR = 6470;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY2_SM_PARITY_ERROR = 6471;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY3_SM_PARITY_ERROR = 6472;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY4_SM_PARITY_ERROR = 6473;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY5_SM_PARITY_ERROR = 6474;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY6_SM_PARITY_ERROR = 6475;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY7_SM_PARITY_ERROR = 6476;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY8_SM_PARITY_ERROR = 6477;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY9_SM_PARITY_ERROR = 6478;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY10_SM_PARITY_ERROR = 6479;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY11_SM_PARITY_ERROR = 6480;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY12_SM_PARITY_ERROR = 6481;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY13_SM_PARITY_ERROR = 6482;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY14_SM_PARITY_ERROR = 6483;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY15_SM_PARITY_ERROR = 6484;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY16_SM_PARITY_ERROR = 6485;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY17_SM_PARITY_ERROR = 6486;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY18_SM_PARITY_ERROR = 6487;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY19_SM_PARITY_ERROR = 6488;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY20_SM_PARITY_ERROR = 6489;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY21_SM_PARITY_ERROR = 6490;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY22_SM_PARITY_ERROR = 6491;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY23_SM_PARITY_ERROR = 6492;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY24_SM_PARITY_ERROR = 6493;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY25_SM_PARITY_ERROR = 6494;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY26_SM_PARITY_ERROR = 6495;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY27_SM_PARITY_ERROR = 6496;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY28_SM_PARITY_ERROR = 6497;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY29_SM_PARITY_ERROR = 6498;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY30_SM_PARITY_ERROR = 6499;
static const uint64_t IDX_CEN_MBIERPT0_REPLAY31_SM_PARITY_ERROR = 6500;
static const uint64_t IDX_CEN_MBICFGQ_FORCE_CHANNEL_FAIL = 6501;
static const uint64_t IDX_CEN_MBICFGQ_REPLAY_CRC_DISABLE = 6502;
static const uint64_t IDX_CEN_MBICFGQ_REPLAY_NOACK_DISABLE = 6503;
static const uint64_t IDX_CEN_MBICFGQ_REPLAY_OUTOFORDER_DISABLE = 6504;
static const uint64_t IDX_CEN_MBICFGQ_FORCE_LFSR_REPLAY = 6505;
static const uint64_t IDX_CEN_MBICFGQ_CRC_CHECK_DISABLE = 6506;
static const uint64_t IDX_CEN_MBICFGQ_ECC_CHECK_DISABLE = 6507;
static const uint64_t IDX_CEN_MBICFGQ_FORCE_FRAME_LOCK = 6508;
static const uint64_t IDX_CEN_MBICFGQ_FORCE_FRTL = 6509;
static const uint64_t IDX_CEN_MBICFGQ_AUTO_FRTL_DISABLE = 6510;
static const uint64_t IDX_CEN_MBICFGQ_MANUAL_FRTL_VALUE = 6511;
static const uint64_t IDX_CEN_MBICFGQ_MANUAL_FRTL_VALUE_LEN = 6512;
static const uint64_t IDX_CEN_MBICFGQ_MANUAL_FRTL_DONE = 6513;
static const uint64_t IDX_CEN_MBICFGQ_ECC_CORRECT_DISABLE = 6514;
static const uint64_t IDX_CEN_MBICFGQ_SPARE1 = 6515;
static const uint64_t IDX_CEN_MBICFGQ_LANE_VOTING_BYPASS = 6516;
static const uint64_t IDX_CEN_MBICFGQ_BAD_LANE_VALUE = 6517;
static const uint64_t IDX_CEN_MBICFGQ_BAD_LANE_VALUE_LEN = 6518;
static const uint64_t IDX_CEN_MBICFGQ_BAD_LANE_VOTING_DISABLE = 6519;
static const uint64_t IDX_CEN_MBICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE = 6520;
static const uint64_t IDX_CEN_MBICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE_LEN = 6521;
static const uint64_t IDX_CEN_MBICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT = 6522;
static const uint64_t IDX_CEN_MBICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT_LEN = 6523;
static const uint64_t IDX_CEN_MBICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE = 6524;
static const uint64_t IDX_CEN_MBICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE_LEN = 6525;
static const uint64_t IDX_CEN_MBICFGQ_MBI_RESET_KEEPER = 6526;
static const uint64_t IDX_CEN_MBICFGQ_FAULT_LINE_ERROR_ENABLE = 6527;
static const uint64_t IDX_CEN_MBICFGQ_DEBUG_BUS_WAT_CONTROL = 6528;
static const uint64_t IDX_CEN_MBICFGQ_SPARE3 = 6529;
static const uint64_t IDX_CEN_MBICFGQ_SPARE3_LEN = 6530;
static const uint64_t IDX_CEN_MBICRCSYNQ_VALID = 6531;
static const uint64_t IDX_CEN_MBICRCSYNQ_FIRST = 6532;
static const uint64_t IDX_CEN_MBICRCSYNQ_AUTO_RESET_DISABLE = 6533;
static const uint64_t IDX_CEN_MBICRCSYNQ_DS_SYNDROME = 6534;
static const uint64_t IDX_CEN_MBICRCSYNQ_DS_SYNDROME_LEN = 6535;
static const uint64_t IDX_CEN_MBIERRINJQ_FRAME_CRC_ERROR_INJECT_MODE = 6536;
static const uint64_t IDX_CEN_MBIERRINJQ_FRAME_CRC_ERROR_INJECT = 6537;
static const uint64_t IDX_CEN_MBIERRINJQ_REPLAY_BUFFER_ERROR_INJECT_MODE = 6538;
static const uint64_t IDX_CEN_MBIERRINJQ_REPLAY_BUFFER_ECC_CE_INJECT = 6539;
static const uint64_t IDX_CEN_MBIERRINJQ_REPLAY_BUFFER_ECC_UE_INJECT = 6540;
static const uint64_t IDX_CEN_MBIERRINJQ_DATA_FLOW_PARITY_ERROR_INJECT_MODE = 6541;
static const uint64_t IDX_CEN_MBIERRINJQ_DATA_FLOW_PARITY_ERROR_INJECT = 6542;
static const uint64_t IDX_CEN_MBIERRINJQ_DEAD_FRAME_CRC_ERROR_INJECT = 6543;
static const uint64_t IDX_CEN_MBIFIRACT0_ACTION_0 = 6544;
static const uint64_t IDX_CEN_MBIFIRACT0_ACTION_0_LEN = 6545;
static const uint64_t IDX_CEN_MBIFIRACT1_ACTION_1 = 6546;
static const uint64_t IDX_CEN_MBIFIRACT1_ACTION_1_LEN = 6547;
static const uint64_t IDX_CEN_MBIFIRMASK_REPLAY_TIMEOUT = 6548;
static const uint64_t IDX_CEN_MBIFIRMASK_CHANNEL_FAIL = 6549;
static const uint64_t IDX_CEN_MBIFIRMASK_CRC_ERROR = 6550;
static const uint64_t IDX_CEN_MBIFIRMASK_FRAME_NOACK = 6551;
static const uint64_t IDX_CEN_MBIFIRMASK_SEQID_OUT_OF_ORDER = 6552;
static const uint64_t IDX_CEN_MBIFIRMASK_REPLAY_BUFFER_ECC_CE = 6553;
static const uint64_t IDX_CEN_MBIFIRMASK_REPLAY_BUFFER_ECC_UE = 6554;
static const uint64_t IDX_CEN_MBIFIRMASK_MBI_CHINIT_STATE_MACHINE_TIMEOUT = 6555;
static const uint64_t IDX_CEN_MBIFIRMASK_MBI_INTERNAL_CONTROL_PARITY_ERROR = 6556;
static const uint64_t IDX_CEN_MBIFIRMASK_MBI_DATA_FLOW_PARITY_ERROR = 6557;
static const uint64_t IDX_CEN_MBIFIRMASK_CRC_PERFORMANCE_DEGRADATION = 6558;
static const uint64_t IDX_CEN_MBIFIRMASK_HOST_MC_CHECKSTOP = 6559;
static const uint64_t IDX_CEN_MBIFIRMASK_HOST_MC_TRACESTOP = 6560;
static const uint64_t IDX_CEN_MBIFIRMASK_CHANNEL_INTERLOCK_FAIL = 6561;
static const uint64_t IDX_CEN_MBIFIRMASK_HOST_MC_LOCAL_CHECKSTOP = 6562;
static const uint64_t IDX_CEN_MBIFIRMASK_FRTL_COUNTER_OVERFLOW = 6563;
static const uint64_t IDX_CEN_MBIFIRMASK_SCOM_REGISTER_PARITY_ERROR = 6564;
static const uint64_t IDX_CEN_MBIFIRMASK_IO_FAULT = 6565;
static const uint64_t IDX_CEN_MBIFIRMASK_MULTIPLE_REPLAY = 6566;
static const uint64_t IDX_CEN_MBIFIRMASK_MBICFG_PARITY_SCOM_ERROR = 6567;
static const uint64_t IDX_CEN_MBIFIRMASK_BUFFER_OVERRUN_ERROR = 6568;
static const uint64_t IDX_CEN_MBIFIRMASK_WAT_EVENT = 6569;
static const uint64_t IDX_CEN_MBIFIRMASK_RESERVED_2 = 6570;
static const uint64_t IDX_CEN_MBIFIRMASK_RESERVED_3 = 6571;
static const uint64_t IDX_CEN_MBIFIRMASK_RESERVED_4 = 6572;
static const uint64_t IDX_CEN_MBIFIRMASK_INTERNAL_SCOM_ERROR_CLONE = 6573;
static const uint64_t IDX_CEN_MBIFIRMASK_INTERNAL_SCOM_ERROR_CLONE_COPY = 6574;
static const uint64_t IDX_CEN_MBIFIRQ_REPLAY_TIMEOUT = 6575;
static const uint64_t IDX_CEN_MBIFIRQ_CHANNEL_FAIL = 6576;
static const uint64_t IDX_CEN_MBIFIRQ_CRC_ERROR = 6577;
static const uint64_t IDX_CEN_MBIFIRQ_FRAME_NOACK = 6578;
static const uint64_t IDX_CEN_MBIFIRQ_SEQID_OUT_OF_ORDER = 6579;
static const uint64_t IDX_CEN_MBIFIRQ_REPLAY_BUFFER_ECC_CE = 6580;
static const uint64_t IDX_CEN_MBIFIRQ_REPLAY_BUFFER_ECC_UE = 6581;
static const uint64_t IDX_CEN_MBIFIRQ_MBI_STATE_MACHINE_TIMEOUT = 6582;
static const uint64_t IDX_CEN_MBIFIRQ_MBI_INTERNAL_CONTROL_PARITY_ERROR = 6583;
static const uint64_t IDX_CEN_MBIFIRQ_MBI_DATA_FLOW_PARITY_ERROR = 6584;
static const uint64_t IDX_CEN_MBIFIRQ_CRC_PERFORMANCE_DEGRADATION = 6585;
static const uint64_t IDX_CEN_MBIFIRQ_HOST_MC_GLOBAL_CHECKSTOP = 6586;
static const uint64_t IDX_CEN_MBIFIRQ_HOST_MC_TRACESTOP = 6587;
static const uint64_t IDX_CEN_MBIFIRQ_CHANNEL_INTERLOCK_FAIL = 6588;
static const uint64_t IDX_CEN_MBIFIRQ_HOST_MC_LOCAL_CHECKSTOP = 6589;
static const uint64_t IDX_CEN_MBIFIRQ_FRTL_CONTER_OVERFLOW = 6590;
static const uint64_t IDX_CEN_MBIFIRQ_SCOM_REGISTER_PARITY_ERROR = 6591;
static const uint64_t IDX_CEN_MBIFIRQ_IO_FAULT = 6592;
static const uint64_t IDX_CEN_MBIFIRQ_MULTIPLE_REPLAY = 6593;
static const uint64_t IDX_CEN_MBIFIRQ_MBICFG_PARITY_SCOM_ERROR = 6594;
static const uint64_t IDX_CEN_MBIFIRQ_BUFFER_OVERRUN_ERROR = 6595;
static const uint64_t IDX_CEN_MBIFIRQ_WAT_EVENT = 6596;
static const uint64_t IDX_CEN_MBIFIRQ_RESERVED_2 = 6597;
static const uint64_t IDX_CEN_MBIFIRQ_RESERVED_3 = 6598;
static const uint64_t IDX_CEN_MBIFIRQ_RESERVED_4 = 6599;
static const uint64_t IDX_CEN_MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE = 6600;
static const uint64_t IDX_CEN_MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE_COPY = 6601;
static const uint64_t IDX_CEN_MBIFPGAINTRQ_FPGA_INTERRUPT_ENABLE = 6602;
static const uint64_t IDX_CEN_MBIFPGAINTRQ_FPGA_INTERRUPT_TRIGGER = 6603;
static const uint64_t IDX_CEN_MBIFPGAINTRQ_FPGA_INTERRUPT_FENCE_DISABLE = 6604;
static const uint64_t IDX_CEN_MBISTATQ_FRAME_LOCK_PASS = 6605;
static const uint64_t IDX_CEN_MBISTATQ_FRAME_LOCK_FAIL = 6606;
static const uint64_t IDX_CEN_MBISTATQ_FRTL_PASS = 6607;
static const uint64_t IDX_CEN_MBISTATQ_FRTL_FAIL = 6608;
static const uint64_t IDX_CEN_MBISTATQ_REPLAY_IN_PROGRESS = 6609;
static const uint64_t IDX_CEN_MBISTATQ_OPERATING_FRTL_VALUE = 6610;
static const uint64_t IDX_CEN_MBISTATQ_OPERATING_FRTL_VALUE_LEN = 6611;
static const uint64_t IDX_CEN_MBISTATQ_DMI_EDI_FENCE = 6612;
static const uint64_t IDX_CEN_MBISTATQ_CHAN_INTERLOCK_PASS = 6613;
static const uint64_t IDX_CEN_MBISTATQ_CHAN_INTERLOCK_FAIL = 6614;
static const uint64_t IDX_CEN_MBISTATQ_SPARE0 = 6615;
static const uint64_t IDX_CEN_MBIFIRWOF_REPLAY_TIMEOUT = 6616;
static const uint64_t IDX_CEN_MBIFIRWOF_CHANNEL_FAIL = 6617;
static const uint64_t IDX_CEN_MBIFIRWOF_CRC_ERROR = 6618;
static const uint64_t IDX_CEN_MBIFIRWOF_FRAME_NOACK = 6619;
static const uint64_t IDX_CEN_MBIFIRWOF_SEQID_OUT_OF_ORDER = 6620;
static const uint64_t IDX_CEN_MBIFIRWOF_REPLAY_BUFFER_ECC_CE = 6621;
static const uint64_t IDX_CEN_MBIFIRWOF_REPLAY_BUFFER_ECC_UE = 6622;
static const uint64_t IDX_CEN_MBIFIRWOF_MBI_STATE_MACHINE_TIMEOUT = 6623;
static const uint64_t IDX_CEN_MBIFIRWOF_MBI_INTERNAL_CONTROL_PARITY_ERROR = 6624;
static const uint64_t IDX_CEN_MBIFIRWOF_MBI_DATA_FLOW_PARITY_ERROR = 6625;
static const uint64_t IDX_CEN_MBIFIRWOF_CRC_PERFORMANCE_DEGRADATION = 6626;
static const uint64_t IDX_CEN_MBIFIRWOF_HOST_MC_GLOBAL_CHECKSTOP = 6627;
static const uint64_t IDX_CEN_MBIFIRWOF_HOST_MC_TRACESTOP = 6628;
static const uint64_t IDX_CEN_MBIFIRWOF_CHANNEL_INTERLOCK_FAIL = 6629;
static const uint64_t IDX_CEN_MBIFIRWOF_HOST_MC_LOCAL_CHECKSTOP = 6630;
static const uint64_t IDX_CEN_MBIFIRWOF_FRTL_CONTER_OVERFLOW = 6631;
static const uint64_t IDX_CEN_MBIFIRWOF_SCOM_REGISTER_PARITY_ERROR = 6632;
static const uint64_t IDX_CEN_MBIFIRWOF_IO_FAULT = 6633;
static const uint64_t IDX_CEN_MBIFIRWOF_MULTIPLE_REPLAY = 6634;
static const uint64_t IDX_CEN_MBIFIRWOF_MBICFG_PARITY_SCOM_ERROR = 6635;
static const uint64_t IDX_CEN_MBIFIRWOF_BUFFER_OVERRUN_ERROR = 6636;
static const uint64_t IDX_CEN_MBIFIRWOF_RESERVED_21_24 = 6637;
static const uint64_t IDX_CEN_MBIFIRWOF_RESERVED_21_24_LEN = 6638;
static const uint64_t IDX_CEN_MBIFIRWOF_INTERNAL_SCOM_ERROR_CLONE = 6639;
static const uint64_t IDX_CEN_MBIFIRWOF_INTERNAL_SCOM_ERROR_CLONE_COPY = 6640;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA0_DATA = 6641;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA0_DATA_LEN = 6642;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA1_DATA = 6643;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA1_DATA_LEN = 6644;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA2_DATA = 6645;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA2_DATA_LEN = 6646;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA3_DATA = 6647;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA3_DATA_LEN = 6648;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA4_DATA = 6649;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA4_DATA_LEN = 6650;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA5_DATA = 6651;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA5_DATA_LEN = 6652;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA6_DATA = 6653;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA6_DATA_LEN = 6654;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA7_DATA = 6655;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA7_DATA_LEN = 6656;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC0_SPARE = 6657;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC0_ECC = 6658;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC0_ECC_LEN = 6659;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC1_SPARE = 6660;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC1_ECC = 6661;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC1_ECC_LEN = 6662;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC2_SPARE = 6663;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC2_ECC = 6664;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC2_ECC_LEN = 6665;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC3_SPARE = 6666;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC3_ECC = 6667;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC3_ECC_LEN = 6668;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC4_SPARE = 6669;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC4_ECC = 6670;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC4_ECC_LEN = 6671;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC5_SPARE = 6672;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC5_ECC = 6673;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC5_ECC_LEN = 6674;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC6_SPARE = 6675;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC6_ECC = 6676;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC6_ECC_LEN = 6677;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC7_SPARE = 6678;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC7_ECC = 6679;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF0_DATA_ECC7_ECC_LEN = 6680;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA0_DATA = 6681;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA0_DATA_LEN = 6682;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA1_DATA = 6683;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA1_DATA_LEN = 6684;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA2_DATA = 6685;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA2_DATA_LEN = 6686;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA3_DATA = 6687;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA3_DATA_LEN = 6688;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA4_DATA = 6689;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA4_DATA_LEN = 6690;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA5_DATA = 6691;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA5_DATA_LEN = 6692;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA6_DATA = 6693;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA6_DATA_LEN = 6694;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA7_DATA = 6695;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA7_DATA_LEN = 6696;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC0_SPARE = 6697;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC0_ECC = 6698;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC0_ECC_LEN = 6699;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC1_SPARE = 6700;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC1_ECC = 6701;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC1_ECC_LEN = 6702;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC2_SPARE = 6703;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC2_ECC = 6704;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC2_ECC_LEN = 6705;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC3_SPARE = 6706;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC3_ECC = 6707;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC3_ECC_LEN = 6708;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC4_SPARE = 6709;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC4_ECC = 6710;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC4_ECC_LEN = 6711;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC5_SPARE = 6712;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC5_ECC = 6713;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC5_ECC_LEN = 6714;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC6_SPARE = 6715;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC6_ECC = 6716;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC6_ECC_LEN = 6717;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC7_SPARE = 6718;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC7_ECC = 6719;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF1_DATA_ECC7_ECC_LEN = 6720;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA0_DATA = 6721;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA0_DATA_LEN = 6722;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA1_DATA = 6723;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA1_DATA_LEN = 6724;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA2_DATA = 6725;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA2_DATA_LEN = 6726;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA3_DATA = 6727;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA3_DATA_LEN = 6728;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA4_DATA = 6729;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA4_DATA_LEN = 6730;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA5_DATA = 6731;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA5_DATA_LEN = 6732;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA6_DATA = 6733;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA6_DATA_LEN = 6734;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA7_DATA = 6735;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA7_DATA_LEN = 6736;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC0_SPARE = 6737;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC0_ECC = 6738;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC0_ECC_LEN = 6739;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC1_SPARE = 6740;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC1_ECC = 6741;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC1_ECC_LEN = 6742;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC2_SPARE = 6743;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC2_ECC = 6744;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC2_ECC_LEN = 6745;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC3_SPARE = 6746;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC3_ECC = 6747;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC3_ECC_LEN = 6748;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC4_SPARE = 6749;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC4_ECC = 6750;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC4_ECC_LEN = 6751;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC5_SPARE = 6752;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC5_ECC = 6753;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC5_ECC_LEN = 6754;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC6_SPARE = 6755;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC6_ECC = 6756;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC6_ECC_LEN = 6757;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC7_SPARE = 6758;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC7_ECC = 6759;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF2_DATA_ECC7_ECC_LEN = 6760;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA0_DATA = 6761;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA0_DATA_LEN = 6762;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA1_DATA = 6763;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA1_DATA_LEN = 6764;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA2_DATA = 6765;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA2_DATA_LEN = 6766;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA3_DATA = 6767;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA3_DATA_LEN = 6768;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA4_DATA = 6769;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA4_DATA_LEN = 6770;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA5_DATA = 6771;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA5_DATA_LEN = 6772;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA6_DATA = 6773;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA6_DATA_LEN = 6774;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA7_DATA = 6775;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA7_DATA_LEN = 6776;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC0_SPARE = 6777;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC0_ECC = 6778;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC0_ECC_LEN = 6779;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC1_SPARE = 6780;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC1_ECC = 6781;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC1_ECC_LEN = 6782;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC2_SPARE = 6783;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC2_ECC = 6784;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC2_ECC_LEN = 6785;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC3_SPARE = 6786;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC3_ECC = 6787;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC3_ECC_LEN = 6788;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC4_SPARE = 6789;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC4_ECC = 6790;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC4_ECC_LEN = 6791;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC5_SPARE = 6792;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC5_ECC = 6793;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC5_ECC_LEN = 6794;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC6_SPARE = 6795;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC6_ECC = 6796;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC6_ECC_LEN = 6797;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC7_SPARE = 6798;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC7_ECC = 6799;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF3_DATA_ECC7_ECC_LEN = 6800;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_CHECKBIT0_1 = 6801;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_TAG0_2 = 6802;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_TAG1_3 = 6803;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_MDI = 6804;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C6_C5_C4 = 6805;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C6_C5_C4_LEN = 6806;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C3_C2_C1_C0 = 6807;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C3_C2_C1_C0_LEN = 6808;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_SPARE_ECC_BITS = 6809;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_SPARE_ECC_BITS_LEN = 6810;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_FABRIC_ECC = 6811;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC0_FABRIC_ECC_LEN = 6812;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_CHECKBIT0_1 = 6813;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_TAG0_2 = 6814;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_TAG1_3 = 6815;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_MDI = 6816;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C6_C5_C4 = 6817;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C6_C5_C4_LEN = 6818;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C3_C2_C1_C0 = 6819;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C3_C2_C1_C0_LEN = 6820;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_SPARE_ECC_BITS = 6821;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_SPARE_ECC_BITS_LEN = 6822;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_FABRIC_ECC = 6823;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC1_FABRIC_ECC_LEN = 6824;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_CHECKBIT0_1 = 6825;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_TAG0_2 = 6826;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_TAG1_3 = 6827;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_MDI = 6828;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C6_C5_C4 = 6829;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C6_C5_C4_LEN = 6830;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C3_C2_C1_C0 = 6831;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C3_C2_C1_C0_LEN = 6832;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_SPARE_ECC_BITS = 6833;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_SPARE_ECC_BITS_LEN = 6834;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_FABRIC_ECC = 6835;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC2_FABRIC_ECC_LEN = 6836;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_CHECKBIT0_1 = 6837;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_TAG0_2 = 6838;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_TAG1_3 = 6839;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_MDI = 6840;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C6_C5_C4 = 6841;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C6_C5_C4_LEN = 6842;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C3_C2_C1_C0 = 6843;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C3_C2_C1_C0_LEN = 6844;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_SPARE_ECC_BITS = 6845;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_SPARE_ECC_BITS_LEN = 6846;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_FABRIC_ECC = 6847;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC3_FABRIC_ECC_LEN = 6848;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_CHECKBIT0_1 = 6849;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_TAG0_2 = 6850;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_TAG1_3 = 6851;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_MDI = 6852;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C6_C5_C4 = 6853;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C6_C5_C4_LEN = 6854;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C3_C2_C1_C0 = 6855;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C3_C2_C1_C0_LEN = 6856;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_SPARE_ECC_BITS = 6857;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_SPARE_ECC_BITS_LEN = 6858;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_FABRIC_ECC = 6859;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC4_FABRIC_ECC_LEN = 6860;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_CHECKBIT0_1 = 6861;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_TAG0_2 = 6862;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_TAG1_3 = 6863;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_MDI = 6864;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C6_C5_C4 = 6865;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C6_C5_C4_LEN = 6866;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C3_C2_C1_C0 = 6867;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C3_C2_C1_C0_LEN = 6868;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_SPARE_ECC_BITS = 6869;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_SPARE_ECC_BITS_LEN = 6870;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_FABRIC_ECC = 6871;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC5_FABRIC_ECC_LEN = 6872;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_CHECKBIT0_1 = 6873;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_TAG0_2 = 6874;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_TAG1_3 = 6875;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_MDI = 6876;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C6_C5_C4 = 6877;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C6_C5_C4_LEN = 6878;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C3_C2_C1_C0 = 6879;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C3_C2_C1_C0_LEN = 6880;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_SPARE_ECC_BITS = 6881;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_SPARE_ECC_BITS_LEN = 6882;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_FABRIC_ECC = 6883;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC6_FABRIC_ECC_LEN = 6884;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_CHECKBIT0_1 = 6885;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_TAG0_2 = 6886;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_TAG1_3 = 6887;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_MDI = 6888;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C6_C5_C4 = 6889;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C6_C5_C4_LEN = 6890;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C3_C2_C1_C0 = 6891;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C3_C2_C1_C0_LEN = 6892;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_SPARE_ECC_BITS = 6893;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_SPARE_ECC_BITS_LEN = 6894;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_FABRIC_ECC = 6895;
static const uint64_t IDX_CEN_MAINT1_MAINT_BUFF_65TH_BYTE_64B_ECC7_FABRIC_ECC_LEN = 6896;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA0_DATA = 6897;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA0_DATA_LEN = 6898;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA1_DATA = 6899;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA1_DATA_LEN = 6900;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA2_DATA = 6901;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA2_DATA_LEN = 6902;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA3_DATA = 6903;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA3_DATA_LEN = 6904;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA4_DATA = 6905;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA4_DATA_LEN = 6906;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA5_DATA = 6907;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA5_DATA_LEN = 6908;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA6_DATA = 6909;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA6_DATA_LEN = 6910;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA7_DATA = 6911;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA7_DATA_LEN = 6912;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC0_SPARE = 6913;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC0_ECC = 6914;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC0_ECC_LEN = 6915;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC1_SPARE = 6916;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC1_ECC = 6917;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC1_ECC_LEN = 6918;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC2_SPARE = 6919;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC2_ECC = 6920;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC2_ECC_LEN = 6921;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC3_SPARE = 6922;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC3_ECC = 6923;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC3_ECC_LEN = 6924;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC4_SPARE = 6925;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC4_ECC = 6926;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC4_ECC_LEN = 6927;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC5_SPARE = 6928;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC5_ECC = 6929;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC5_ECC_LEN = 6930;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC6_SPARE = 6931;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC6_ECC = 6932;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC6_ECC_LEN = 6933;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC7_SPARE = 6934;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC7_ECC = 6935;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF0_DATA_ECC7_ECC_LEN = 6936;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA0_DATA = 6937;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA0_DATA_LEN = 6938;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA1_DATA = 6939;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA1_DATA_LEN = 6940;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA2_DATA = 6941;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA2_DATA_LEN = 6942;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA3_DATA = 6943;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA3_DATA_LEN = 6944;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA4_DATA = 6945;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA4_DATA_LEN = 6946;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA5_DATA = 6947;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA5_DATA_LEN = 6948;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA6_DATA = 6949;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA6_DATA_LEN = 6950;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA7_DATA = 6951;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA7_DATA_LEN = 6952;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC0_SPARE = 6953;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC0_ECC = 6954;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC0_ECC_LEN = 6955;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC1_SPARE = 6956;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC1_ECC = 6957;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC1_ECC_LEN = 6958;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC2_SPARE = 6959;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC2_ECC = 6960;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC2_ECC_LEN = 6961;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC3_SPARE = 6962;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC3_ECC = 6963;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC3_ECC_LEN = 6964;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC4_SPARE = 6965;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC4_ECC = 6966;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC4_ECC_LEN = 6967;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC5_SPARE = 6968;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC5_ECC = 6969;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC5_ECC_LEN = 6970;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC6_SPARE = 6971;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC6_ECC = 6972;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC6_ECC_LEN = 6973;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC7_SPARE = 6974;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC7_ECC = 6975;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF1_DATA_ECC7_ECC_LEN = 6976;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA0_DATA = 6977;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA0_DATA_LEN = 6978;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA1_DATA = 6979;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA1_DATA_LEN = 6980;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA2_DATA = 6981;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA2_DATA_LEN = 6982;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA3_DATA = 6983;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA3_DATA_LEN = 6984;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA4_DATA = 6985;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA4_DATA_LEN = 6986;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA5_DATA = 6987;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA5_DATA_LEN = 6988;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA6_DATA = 6989;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA6_DATA_LEN = 6990;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA7_DATA = 6991;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA7_DATA_LEN = 6992;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC0_SPARE = 6993;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC0_ECC = 6994;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC0_ECC_LEN = 6995;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC1_SPARE = 6996;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC1_ECC = 6997;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC1_ECC_LEN = 6998;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC2_SPARE = 6999;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC2_ECC = 7000;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC2_ECC_LEN = 7001;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC3_SPARE = 7002;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC3_ECC = 7003;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC3_ECC_LEN = 7004;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC4_SPARE = 7005;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC4_ECC = 7006;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC4_ECC_LEN = 7007;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC5_SPARE = 7008;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC5_ECC = 7009;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC5_ECC_LEN = 7010;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC6_SPARE = 7011;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC6_ECC = 7012;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC6_ECC_LEN = 7013;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC7_SPARE = 7014;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC7_ECC = 7015;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF2_DATA_ECC7_ECC_LEN = 7016;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA0_DATA = 7017;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA0_DATA_LEN = 7018;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA1_DATA = 7019;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA1_DATA_LEN = 7020;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA2_DATA = 7021;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA2_DATA_LEN = 7022;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA3_DATA = 7023;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA3_DATA_LEN = 7024;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA4_DATA = 7025;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA4_DATA_LEN = 7026;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA5_DATA = 7027;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA5_DATA_LEN = 7028;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA6_DATA = 7029;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA6_DATA_LEN = 7030;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA7_DATA = 7031;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA7_DATA_LEN = 7032;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC0_SPARE = 7033;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC0_ECC = 7034;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC0_ECC_LEN = 7035;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC1_SPARE = 7036;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC1_ECC = 7037;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC1_ECC_LEN = 7038;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC2_SPARE = 7039;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC2_ECC = 7040;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC2_ECC_LEN = 7041;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC3_SPARE = 7042;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC3_ECC = 7043;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC3_ECC_LEN = 7044;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC4_SPARE = 7045;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC4_ECC = 7046;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC4_ECC_LEN = 7047;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC5_SPARE = 7048;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC5_ECC = 7049;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC5_ECC_LEN = 7050;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC6_SPARE = 7051;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC6_ECC = 7052;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC6_ECC_LEN = 7053;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC7_SPARE = 7054;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC7_ECC = 7055;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF3_DATA_ECC7_ECC_LEN = 7056;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_CHECKBIT0_1 = 7057;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_TAG0_2 = 7058;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_TAG1_3 = 7059;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_MDI = 7060;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C6_C5_C4 = 7061;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C6_C5_C4_LEN = 7062;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C3_C2_C1_C0 = 7063;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_ECC_C3_C2_C1_C0_LEN = 7064;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_SPARE_ECC_BITS = 7065;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_SPARE_ECC_BITS_LEN = 7066;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_FABRIC_ECC = 7067;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC0_FABRIC_ECC_LEN = 7068;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_CHECKBIT0_1 = 7069;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_TAG0_2 = 7070;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_TAG1_3 = 7071;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_MDI = 7072;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C6_C5_C4 = 7073;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C6_C5_C4_LEN = 7074;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C3_C2_C1_C0 = 7075;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_ECC_C3_C2_C1_C0_LEN = 7076;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_SPARE_ECC_BITS = 7077;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_SPARE_ECC_BITS_LEN = 7078;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_FABRIC_ECC = 7079;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC1_FABRIC_ECC_LEN = 7080;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_CHECKBIT0_1 = 7081;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_TAG0_2 = 7082;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_TAG1_3 = 7083;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_MDI = 7084;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C6_C5_C4 = 7085;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C6_C5_C4_LEN = 7086;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C3_C2_C1_C0 = 7087;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_ECC_C3_C2_C1_C0_LEN = 7088;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_SPARE_ECC_BITS = 7089;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_SPARE_ECC_BITS_LEN = 7090;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_FABRIC_ECC = 7091;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC2_FABRIC_ECC_LEN = 7092;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_CHECKBIT0_1 = 7093;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_TAG0_2 = 7094;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_TAG1_3 = 7095;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_MDI = 7096;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C6_C5_C4 = 7097;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C6_C5_C4_LEN = 7098;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C3_C2_C1_C0 = 7099;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_ECC_C3_C2_C1_C0_LEN = 7100;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_SPARE_ECC_BITS = 7101;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_SPARE_ECC_BITS_LEN = 7102;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_FABRIC_ECC = 7103;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC3_FABRIC_ECC_LEN = 7104;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_CHECKBIT0_1 = 7105;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_TAG0_2 = 7106;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_TAG1_3 = 7107;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_MDI = 7108;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C6_C5_C4 = 7109;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C6_C5_C4_LEN = 7110;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C3_C2_C1_C0 = 7111;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_ECC_C3_C2_C1_C0_LEN = 7112;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_SPARE_ECC_BITS = 7113;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_SPARE_ECC_BITS_LEN = 7114;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_FABRIC_ECC = 7115;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC4_FABRIC_ECC_LEN = 7116;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_CHECKBIT0_1 = 7117;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_TAG0_2 = 7118;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_TAG1_3 = 7119;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_MDI = 7120;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C6_C5_C4 = 7121;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C6_C5_C4_LEN = 7122;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C3_C2_C1_C0 = 7123;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_ECC_C3_C2_C1_C0_LEN = 7124;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_SPARE_ECC_BITS = 7125;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_SPARE_ECC_BITS_LEN = 7126;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_FABRIC_ECC = 7127;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC5_FABRIC_ECC_LEN = 7128;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_CHECKBIT0_1 = 7129;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_TAG0_2 = 7130;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_TAG1_3 = 7131;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_MDI = 7132;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C6_C5_C4 = 7133;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C6_C5_C4_LEN = 7134;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C3_C2_C1_C0 = 7135;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_ECC_C3_C2_C1_C0_LEN = 7136;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_SPARE_ECC_BITS = 7137;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_SPARE_ECC_BITS_LEN = 7138;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_FABRIC_ECC = 7139;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC6_FABRIC_ECC_LEN = 7140;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_CHECKBIT0_1 = 7141;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_TAG0_2 = 7142;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_TAG1_3 = 7143;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_MDI = 7144;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C6_C5_C4 = 7145;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C6_C5_C4_LEN = 7146;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C3_C2_C1_C0 = 7147;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_ECC_C3_C2_C1_C0_LEN = 7148;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_SPARE_ECC_BITS = 7149;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_SPARE_ECC_BITS_LEN = 7150;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_FABRIC_ECC = 7151;
static const uint64_t IDX_CEN_MBA_MAINT0_MAINT_BUFF_65TH_BYTE_64B_ECC7_FABRIC_ECC_LEN = 7152;
static const uint64_t IDX_CEN_MBA_MBABS0_WRITE_BIT_STEER_MUX_SELECT_0 = 7153;
static const uint64_t IDX_CEN_MBA_MBABS0_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7154;
static const uint64_t IDX_CEN_MBA_MBABS0_WRITE_BIT_STEER_MUX_SELECT_1 = 7155;
static const uint64_t IDX_CEN_MBA_MBABS0_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7156;
static const uint64_t IDX_CEN_MBA_MBABS0_WRITE_BIT_STEER_MUX_SELECT_2 = 7157;
static const uint64_t IDX_CEN_MBA_MBABS0_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7158;
static const uint64_t IDX_CEN_MBA_MBABS1_WRITE_BIT_STEER_MUX_SELECT_0 = 7159;
static const uint64_t IDX_CEN_MBA_MBABS1_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7160;
static const uint64_t IDX_CEN_MBA_MBABS1_WRITE_BIT_STEER_MUX_SELECT_1 = 7161;
static const uint64_t IDX_CEN_MBA_MBABS1_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7162;
static const uint64_t IDX_CEN_MBA_MBABS1_WRITE_BIT_STEER_MUX_SELECT_2 = 7163;
static const uint64_t IDX_CEN_MBA_MBABS1_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7164;
static const uint64_t IDX_CEN_MBA_MBABS2_WRITE_BIT_STEER_MUX_SELECT_0 = 7165;
static const uint64_t IDX_CEN_MBA_MBABS2_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7166;
static const uint64_t IDX_CEN_MBA_MBABS2_WRITE_BIT_STEER_MUX_SELECT_1 = 7167;
static const uint64_t IDX_CEN_MBA_MBABS2_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7168;
static const uint64_t IDX_CEN_MBA_MBABS2_WRITE_BIT_STEER_MUX_SELECT_2 = 7169;
static const uint64_t IDX_CEN_MBA_MBABS2_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7170;
static const uint64_t IDX_CEN_MBA_MBABS3_WRITE_BIT_STEER_MUX_SELECT_0 = 7171;
static const uint64_t IDX_CEN_MBA_MBABS3_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7172;
static const uint64_t IDX_CEN_MBA_MBABS3_WRITE_BIT_STEER_MUX_SELECT_1 = 7173;
static const uint64_t IDX_CEN_MBA_MBABS3_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7174;
static const uint64_t IDX_CEN_MBA_MBABS3_WRITE_BIT_STEER_MUX_SELECT_2 = 7175;
static const uint64_t IDX_CEN_MBA_MBABS3_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7176;
static const uint64_t IDX_CEN_MBA_MBABS4_WRITE_BIT_STEER_MUX_SELECT_0 = 7177;
static const uint64_t IDX_CEN_MBA_MBABS4_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7178;
static const uint64_t IDX_CEN_MBA_MBABS4_WRITE_BIT_STEER_MUX_SELECT_1 = 7179;
static const uint64_t IDX_CEN_MBA_MBABS4_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7180;
static const uint64_t IDX_CEN_MBA_MBABS4_WRITE_BIT_STEER_MUX_SELECT_2 = 7181;
static const uint64_t IDX_CEN_MBA_MBABS4_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7182;
static const uint64_t IDX_CEN_MBA_MBABS5_WRITE_BIT_STEER_MUX_SELECT_0 = 7183;
static const uint64_t IDX_CEN_MBA_MBABS5_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7184;
static const uint64_t IDX_CEN_MBA_MBABS5_WRITE_BIT_STEER_MUX_SELECT_1 = 7185;
static const uint64_t IDX_CEN_MBA_MBABS5_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7186;
static const uint64_t IDX_CEN_MBA_MBABS5_WRITE_BIT_STEER_MUX_SELECT_2 = 7187;
static const uint64_t IDX_CEN_MBA_MBABS5_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7188;
static const uint64_t IDX_CEN_MBA_MBABS6_WRITE_BIT_STEER_MUX_SELECT_0 = 7189;
static const uint64_t IDX_CEN_MBA_MBABS6_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7190;
static const uint64_t IDX_CEN_MBA_MBABS6_WRITE_BIT_STEER_MUX_SELECT_1 = 7191;
static const uint64_t IDX_CEN_MBA_MBABS6_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7192;
static const uint64_t IDX_CEN_MBA_MBABS6_WRITE_BIT_STEER_MUX_SELECT_2 = 7193;
static const uint64_t IDX_CEN_MBA_MBABS6_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7194;
static const uint64_t IDX_CEN_MBA_MBABS7_WRITE_BIT_STEER_MUX_SELECT_0 = 7195;
static const uint64_t IDX_CEN_MBA_MBABS7_WRITE_BIT_STEER_MUX_SELECT_0_LEN = 7196;
static const uint64_t IDX_CEN_MBA_MBABS7_WRITE_BIT_STEER_MUX_SELECT_1 = 7197;
static const uint64_t IDX_CEN_MBA_MBABS7_WRITE_BIT_STEER_MUX_SELECT_1_LEN = 7198;
static const uint64_t IDX_CEN_MBA_MBABS7_WRITE_BIT_STEER_MUX_SELECT_2 = 7199;
static const uint64_t IDX_CEN_MBA_MBABS7_WRITE_BIT_STEER_MUX_SELECT_2_LEN = 7200;
static const uint64_t IDX_CEN_MBA_MBA_INJQ_INJQ_CFG_RDTAG_ERR_INJ = 7201;
static const uint64_t IDX_CEN_MBA_MBA_INJQ_INJQ_CFG_RRQ_POP_ERR_INJ = 7202;
static const uint64_t IDX_CEN_MBA_MBA_INJQ_INJQ_CFG_WR_ECC_INJ_MODE = 7203;
static const uint64_t IDX_CEN_MBA_MBA_INJQ_INJQ_CFG_WR_ECC_ERR_INJ = 7204;
static const uint64_t IDX_CEN_MBA_MBA_INJQ_INJQ_CFG_WRD_BUFF_INJ_MODE = 7205;
static const uint64_t IDX_CEN_MBA_MBA_INJQ_INJQ_CFG_WRD_BUFFER_CE_INJ = 7206;
static const uint64_t IDX_CEN_MBA_MBA_INJQ_INJQ_CFG_WRD_BUFFER_UE_INJ = 7207;
static const uint64_t IDX_CEN_MBA_MBA_WRD_MODE_WRD_MODE_CFG_ECC_CHK_DISABLE = 7208;
static const uint64_t IDX_CEN_MBA_MBA_WRD_MODE_WRD_MODE_CFG_ECC_COR_DISABLE = 7209;
static const uint64_t IDX_CEN_MBA_MBA_WRD_MODE_WRD_MODE_ECC_METADATA = 7210;
static const uint64_t IDX_CEN_MBA_MBA_WRD_MODE_WRD_MODE_ECC_METADATA_LEN = 7211;
static const uint64_t IDX_CEN_MBA_MBA_WRD_MODE_WRD_MODE_CFG_MAINT_ECC_CHK_DISABLE = 7212;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE = 7213;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ = 7214;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE = 7215;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ = 7216;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CS_CHIP_ID_2N_MODE = 7217;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_DISABLE_2N_MODE = 7218;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_RESERVED_6_14 = 7219;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_RESERVED_6_14_LEN = 7220;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE = 7221;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0 = 7222;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN = 7223;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1 = 7224;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN = 7225;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2 = 7226;
static const uint64_t IDX_CEN_MBA_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN = 7227;
static const uint64_t IDX_CEN_MBA_CCS_CNTLQ_START = 7228;
static const uint64_t IDX_CEN_MBA_CCS_CNTLQ_STOP = 7229;
static const uint64_t IDX_CEN_MBA_CCS_FIXED_DATA0Q_DATA_0_63 = 7230;
static const uint64_t IDX_CEN_MBA_CCS_FIXED_DATA0Q_DATA_0_63_LEN = 7231;
static const uint64_t IDX_CEN_MBA_CCS_FIXED_DATA1Q_DATA_64_79 = 7232;
static const uint64_t IDX_CEN_MBA_CCS_FIXED_DATA1Q_DATA_64_79_LEN = 7233;
static const uint64_t IDX_CEN_MBA_CCS_FIXED_DATA1Q_RESERVED_16_63 = 7234;
static const uint64_t IDX_CEN_MBA_CCS_FIXED_DATA1Q_RESERVED_16_63_LEN = 7235;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_STOP_ON_ERR = 7236;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_UE_DISABLE = 7237;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DATA_SEL = 7238;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DATA_SEL_LEN = 7239;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MCBIST_DDR_DPHY_NCLK = 7240;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MCBIST_DDR_DPHY_NCLK_LEN = 7241;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MCBIST_DDR_DPHY_PCLK = 7242;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MCBIST_DDR_DPHY_PCLK_LEN = 7243;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT = 7244;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN = 7245;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MCBIST_DDR_RESETN = 7246;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MCBIST_DDR_DFI_RESET_RECOVER = 7247;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_COPY_CKE_TO_SPARE = 7248;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK = 7249;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION = 7250;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_ADDR_MUX_SEL = 7251;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT = 7252;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 7253;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_ADDRESS_IDLE_PAT = 7254;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_ADDRESS_IDLE_PAT_LEN = 7255;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_BANK_IDLE_PAT = 7256;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_BANK_IDLE_PAT_LEN = 7257;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_ACTIVATE_IDLE_PAT = 7258;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_RASN_IDLE_PAT = 7259;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_CASN_IDLE_PAT = 7260;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_MA_B_WEN_IDLE_PAT = 7261;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_NTTM_MODE = 7262;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_NTTM_RW_DATA_DLY = 7263;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN = 7264;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DDR_RESETN_ENABLE = 7265;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_DDR_PARITY_ENABLE = 7266;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_GP_BIT_3_ENABLE = 7267;
static const uint64_t IDX_CEN_MBA_CCS_MODEQ_FORCE_MCLK_LOW_N = 7268;
static const uint64_t IDX_CEN_MBA_CCS_STATQ_IP = 7269;
static const uint64_t IDX_CEN_MBA_CCS_STATQ_DONE = 7270;
static const uint64_t IDX_CEN_MBA_CCS_STATQ_FAIL = 7271;
static const uint64_t IDX_CEN_MBA_CCS_STATQ_FAIL_TYPE = 7272;
static const uint64_t IDX_CEN_MBA_CCS_STATQ_FAIL_TYPE_LEN = 7273;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_INVALID_MAINT_CMD = 7274;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_INVALID_MAINT_ADDRESS = 7275;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_MULTI_ADDRESS_MAINT_TIMEOUT = 7276;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_INTERNAL_FSM_ERROR = 7277;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_MCBIST_ERROR = 7278;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_SCOM_CMD_REG_PE = 7279;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_CHANNEL_CHKSTP_ERR = 7280;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_WRD_CAW2_DATA_CE_UE_ERR = 7281;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_MAINT_1HOT_ST_ERROR_DD2 = 7282;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_RESERVED_9_14 = 7283;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_RESERVED_9_14_LEN = 7284;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_INTERNAL_SCOM_ERROR = 7285;
static const uint64_t IDX_CEN_MBA_MBAFIRACT0_INTERNAL_SCOM_ERROR_CLONE = 7286;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_INVALID_MAINT_CMD = 7287;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_INVALID_MAINT_ADDRESS = 7288;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_MULTI_ADDRESS_MAINT_TIMEOUT = 7289;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_INTERNAL_FSM_ERROR = 7290;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_MCBIST_ERROR = 7291;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_SCOM_CMD_REG_PE = 7292;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_CHANNEL_CHKSTP_ERR = 7293;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_WRD_CAW2_DATA_CE_UE_ERR = 7294;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_MAINT_1HOT_ST_ERROR_DD2 = 7295;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_RESERVED_9_14 = 7296;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_RESERVED_9_14_LEN = 7297;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_INTERNAL_SCOM_ERROR = 7298;
static const uint64_t IDX_CEN_MBA_MBAFIRACT1_INTERNAL_SCOM_ERROR_CLONE = 7299;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_INVALID_MAINT_CMD = 7300;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_INVALID_MAINT_ADDRESS = 7301;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_MULTI_ADDRESS_MAINT_TIMEOUT = 7302;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_INTERNAL_FSM_ERROR = 7303;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_MCBIST_ERROR = 7304;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_SCOM_CMD_REG_PE = 7305;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_CHANNEL_CHKSTP_ERR = 7306;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_WRD_CAW2_DATA_CE_UE_ERR = 7307;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_MAINT_1HOT_ST_ERROR_DD2 = 7308;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_RESERVED_9_14 = 7309;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_RESERVED_9_14_LEN = 7310;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_INTERNAL_SCOM_ERROR = 7311;
static const uint64_t IDX_CEN_MBA_MBAFIRMASK_INTERNAL_SCOM_ERROR_CLONE = 7312;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_INVALID_MAINT_CMD = 7313;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_INVALID_MAINT_ADDRESS = 7314;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_MULTI_ADDRESS_MAINT_TIMEOUT = 7315;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_INTERNAL_FSM_ERROR = 7316;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_MCBIST_ERROR = 7317;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_SCOM_CMD_REG_PE = 7318;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_CHANNEL_CHKSTP_ERR = 7319;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_WRD_CAW2_DATA_CE_UE_ERR = 7320;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_MAINT_1HOT_ST_ERROR_DD2 = 7321;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_RESERVED_9_14 = 7322;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_RESERVED_9_14_LEN = 7323;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_INTERNAL_SCOM_ERROR = 7324;
static const uint64_t IDX_CEN_MBA_MBAFIRQ_INTERNAL_SCOM_ERROR_CLONE = 7325;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_INVALID_MAINT_CMD = 7326;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_INVALID_MAINT_ADDRESS = 7327;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_MULTI_ADDRESS_MAINT_TIMEOUT = 7328;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_INTERNAL_FSM_ERROR = 7329;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_MCBIST_ERROR = 7330;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_SCOM_CMD_REG_PE = 7331;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_CHANNEL_CHKSTP_ERR = 7332;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_WRD_CAW2_DATA_CE_UE_ERR = 7333;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_RESERVED_8_14 = 7334;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_RESERVED_8_14_LEN = 7335;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_INTERNAL_SCOM_ERROR = 7336;
static const uint64_t IDX_CEN_MBA_MBAFIRWOF_INTERNAL_SCOM_ERROR_CLONE = 7337;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_ETE_NOW = 7338;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_ETE_RANK_END = 7339;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_NCE_HARD = 7340;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_NCE_INTERMITTENT = 7341;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_NCE_SOFT = 7342;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_SCE = 7343;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_MCE = 7344;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_RETRYCE = 7345;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_MPE = 7346;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_UE = 7347;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_ON_END_ADDRESS = 7348;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_ENABLE_ATT_MAINT_CMD_DONE = 7349;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_STOP_SUE = 7350;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_CMD_TIMEOUT_SEL = 7351;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_CMD_TIMEOUT_SEL_LEN = 7352;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_RESET_KEEPER = 7353;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_MBSPA_BIT_0_MODE = 7354;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_RESERVED_17_63 = 7355;
static const uint64_t IDX_CEN_MBA_MBASCTLQ_RESERVED_17_63_LEN = 7356;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MAINT_START_ADDR_ERR = 7357;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MAINT_END_ADDR_ERR = 7358;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MCB_FIR_CCS_ERR = 7359;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MAINT_1HOT_ST_ERROR = 7360;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MCB_FIR_MCBAGEN_ERR = 7361;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MCB_FIR_MCBFSM_ERR = 7362;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBMCCQ_PE = 7363;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_CCS_CNTLQ_PE = 7364;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MCB_CNTLQ_PE = 7365;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBSPAQ_PE = 7366;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MAINT_CCS_PE = 7367;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MCBAGEN_PE = 7368;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MCBDGEN_PE = 7369;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MCB_CONTROLLER_PE = 7370;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS0_PE = 7371;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS1_PE = 7372;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS2_PE = 7373;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS3_PE = 7374;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS4_PE = 7375;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS5_PE = 7376;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS6_PE = 7377;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBABS7_PE = 7378;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_INJQ_PE = 7379;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_WRD_MODE_PE = 7380;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBMACAQ_PE = 7381;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_MBMCTQ_PE = 7382;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_RESERVED_26_63 = 7383;
static const uint64_t IDX_CEN_MBA_MBA_MCBERRPTQ_MCBERRPTQ_RESERVED_26_63_LEN = 7384;
static const uint64_t IDX_CEN_MBA_MBECTLQ_ATOMIC_ALT_CE_INJ = 7385;
static const uint64_t IDX_CEN_MBA_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ = 7386;
static const uint64_t IDX_CEN_MBA_MBECTLQ_ATOMIC_ALT_SD_UE_INJ = 7387;
static const uint64_t IDX_CEN_MBA_MBECTLQ_ATOMIC_ALT_SUE_INJ = 7388;
static const uint64_t IDX_CEN_MBA_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL = 7389;
static const uint64_t IDX_CEN_MBA_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN = 7390;
static const uint64_t IDX_CEN_MBA_MBECTLQ_ATOMIC_ALT_INJ_DATA_SEL = 7391;
static const uint64_t IDX_CEN_MBA_MBECTLQ_SCOM_CMD_REG_INJ_MODE = 7392;
static const uint64_t IDX_CEN_MBA_MBECTLQ_SCOM_CMD_REG_INJ = 7393;
static const uint64_t IDX_CEN_MBA_MBECTLQ_MAINT_INTERNAL_FSM_INJ_MODE = 7394;
static const uint64_t IDX_CEN_MBA_MBECTLQ_MAINT_INTERNAL_FSM_INJ_REG = 7395;
static const uint64_t IDX_CEN_MBA_MBECTLQ_CCS_INTERNAL_FSM_INJ_MODE = 7396;
static const uint64_t IDX_CEN_MBA_MBECTLQ_CCS_INTERNAL_FSM_INJ_REG = 7397;
static const uint64_t IDX_CEN_MBA_MBECTLQ_WRD_CAW2_UE_CE_DETECT = 7398;
static const uint64_t IDX_CEN_MBA_MBECTLQ_RESERVED_19_31 = 7399;
static const uint64_t IDX_CEN_MBA_MBECTLQ_RESERVED_19_31_LEN = 7400;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_MASTER_RANK0 = 7401;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_DIMM_SELECT = 7402;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_MASTER_RANK1 = 7403;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_MASTER_RANK2 = 7404;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_SLAVE_RANK = 7405;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_SLAVE_RANK_LEN = 7406;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_BANK = 7407;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_BANK_LEN = 7408;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_ROW = 7409;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_ROW_LEN = 7410;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_COL = 7411;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_COL_LEN = 7412;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_ERR_STATUS = 7413;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_ERR_STATUS_LEN = 7414;
static const uint64_t IDX_CEN_MBA_MBMACAQ_MRANK_SCRUBED = 7415;
static const uint64_t IDX_CEN_MBA_MBMACAQ_MRANK_SCRUBED_LEN = 7416;
static const uint64_t IDX_CEN_MBA_MBMACAQ_CMD_ROW17 = 7417;
static const uint64_t IDX_CEN_MBA_MBMCCQ_MAINT_CMD_START = 7418;
static const uint64_t IDX_CEN_MBA_MBMCCQ_MAINT_CMD_STOP = 7419;
static const uint64_t IDX_CEN_MBA_MBMCTQ_MAINT_CMD_TYPE = 7420;
static const uint64_t IDX_CEN_MBA_MBMCTQ_MAINT_CMD_TYPE_LEN = 7421;
static const uint64_t IDX_CEN_MBA_MBMCTQ_SF_INCREMENT_MODE = 7422;
static const uint64_t IDX_CEN_MBA_MBMCTQ_BURST_WINDOW_SEL = 7423;
static const uint64_t IDX_CEN_MBA_MBMCTQ_RESERVED_7_8 = 7424;
static const uint64_t IDX_CEN_MBA_MBMCTQ_RESERVED_7_8_LEN = 7425;
static const uint64_t IDX_CEN_MBA_MBMCTQ_TIMEBASE_SEL = 7426;
static const uint64_t IDX_CEN_MBA_MBMCTQ_TIMEBASE_SEL_LEN = 7427;
static const uint64_t IDX_CEN_MBA_MBMCTQ_TIMEBASE_BURST_SEL = 7428;
static const uint64_t IDX_CEN_MBA_MBMCTQ_TIMEBASE_INTERVAL = 7429;
static const uint64_t IDX_CEN_MBA_MBMCTQ_TIMEBASE_INTERVAL_LEN = 7430;
static const uint64_t IDX_CEN_MBA_MBMCTQ_BURST_WINDOW = 7431;
static const uint64_t IDX_CEN_MBA_MBMCTQ_BURST_WINDOW_LEN = 7432;
static const uint64_t IDX_CEN_MBA_MBMCTQ_BURST_INTERVAL = 7433;
static const uint64_t IDX_CEN_MBA_MBMCTQ_BURST_INTERVAL_LEN = 7434;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_MASTER_RANK0 = 7435;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_DIMM_SELECT = 7436;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_MASTER_RANK1 = 7437;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_MASTER_RANK2 = 7438;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_SLAVE_RANK = 7439;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_SLAVE_RANK_LEN = 7440;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_BANK = 7441;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_BANK_LEN = 7442;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_ROW = 7443;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_ROW_LEN = 7444;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_COL = 7445;
static const uint64_t IDX_CEN_MBA_MBMEAQ_END_COL_LEN = 7446;
static const uint64_t IDX_CEN_MBA_MBMEAQ_CMD_ROW17 = 7447;
static const uint64_t IDX_CEN_MBA_MBMSRQ_MAINT_CMD_IP = 7448;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_COMMAND_COMPLETE_WO_ENA_ERR_ATTN = 7449;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_HARD_CE_ETE_ATTN = 7450;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_SOFT_CE_ETE_ATTN = 7451;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_INTERMITTENT_ETE_ATTN = 7452;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_RCE_ETE_ATTN = 7453;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_EMERGENCY_THROTTLE_ATTN = 7454;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_FIRMWARE_ATTN0 = 7455;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_FIRMWARE_ATTN1 = 7456;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_WAT_DEBUG_ATTN = 7457;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_SPARE_ATTN1 = 7458;
static const uint64_t IDX_CEN_MBA_MBSPAMSKQ_MCBIST_DONE = 7459;
static const uint64_t IDX_CEN_MBA_MBSPAQ_COMMAND_COMPLETE_WO_ENA_ERR_ATTN = 7460;
static const uint64_t IDX_CEN_MBA_MBSPAQ_HARD_CE_ETE_ATTN = 7461;
static const uint64_t IDX_CEN_MBA_MBSPAQ_SOFT_CE_ETE_ATTN = 7462;
static const uint64_t IDX_CEN_MBA_MBSPAQ_INTERMITTENT_ETE_ATTN = 7463;
static const uint64_t IDX_CEN_MBA_MBSPAQ_RCE_ETE_ATTN = 7464;
static const uint64_t IDX_CEN_MBA_MBSPAQ_EMERGENCY_THROTTLE_ATTN = 7465;
static const uint64_t IDX_CEN_MBA_MBSPAQ_FIRMWARE_ATTN0 = 7466;
static const uint64_t IDX_CEN_MBA_MBSPAQ_FIRMWARE_ATTN1 = 7467;
static const uint64_t IDX_CEN_MBA_MBSPAQ_WAT_DEBUG_ATTN = 7468;
static const uint64_t IDX_CEN_MBA_MBSPAQ_SPARE_ATTN1 = 7469;
static const uint64_t IDX_CEN_MBA_MBSPAQ_MCBIST_DONE = 7470;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_FIXED_WIDTH_A0 = 7471;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_FIXED_WIDTH_A0_LEN = 7472;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_FIXED_WIDTH_A1 = 7473;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_FIXED_WIDTH_A1_LEN = 7474;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_PORTA0_RATIO = 7475;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_PORTA0_RATIO_LEN = 7476;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_PORTA1_RATIO = 7477;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_PORTA1_RATIO_LEN = 7478;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_RANDPORT_WGT_A = 7479;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_RANDPORT_WGT_A_LEN = 7480;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_DET_RAND_WGT_A = 7481;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_PORTA_SCKT_PPLTD = 7482;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_CFG_PORTA_SCKT_PPLTD_LEN = 7483;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_RESERVED_26_31 = 7484;
static const uint64_t IDX_CEN_MBA_MCBAGRAQ_RESERVED_26_31_LEN = 7485;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK0 = 7486;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK0_LEN = 7487;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK1 = 7488;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK1_LEN = 7489;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK2 = 7490;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK2_LEN = 7491;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK3 = 7492;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_MRANK3_LEN = 7493;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_SRANK0 = 7494;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_SRANK0_LEN = 7495;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_SRANK1 = 7496;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_SRANK1_LEN = 7497;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_SRANK2 = 7498;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_SRANK2_LEN = 7499;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_BANK3 = 7500;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_BANK3_LEN = 7501;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_BANK2 = 7502;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_BANK2_LEN = 7503;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_BANK1 = 7504;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_CFG_A0MAP_BANK1_LEN = 7505;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_RESERVED_60_63 = 7506;
static const uint64_t IDX_CEN_MBA_MCBAMR0A0Q_RESERVED_60_63_LEN = 7507;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK0 = 7508;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK0_LEN = 7509;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK1 = 7510;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK1_LEN = 7511;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK2 = 7512;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK2_LEN = 7513;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK3 = 7514;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_MRANK3_LEN = 7515;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_SRANK0 = 7516;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_SRANK0_LEN = 7517;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_SRANK1 = 7518;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_SRANK1_LEN = 7519;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_SRANK2 = 7520;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_SRANK2_LEN = 7521;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_BANK3 = 7522;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_BANK3_LEN = 7523;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_BANK2 = 7524;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_BANK2_LEN = 7525;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_BANK1 = 7526;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_CFG_A1MAP_BANK1_LEN = 7527;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_RESERVED_60_63 = 7528;
static const uint64_t IDX_CEN_MBA_MCBAMR0A1Q_RESERVED_60_63_LEN = 7529;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_BANK0 = 7530;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_BANK0_LEN = 7531;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW16 = 7532;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW16_LEN = 7533;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW15 = 7534;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW15_LEN = 7535;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW14 = 7536;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW14_LEN = 7537;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW13 = 7538;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW13_LEN = 7539;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW12 = 7540;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW12_LEN = 7541;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW11 = 7542;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW11_LEN = 7543;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW10 = 7544;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW10_LEN = 7545;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW9 = 7546;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW9_LEN = 7547;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW8 = 7548;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_CFG_A0MAP_ROW8_LEN = 7549;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_RESERVED_60_63 = 7550;
static const uint64_t IDX_CEN_MBA_MCBAMR1A0Q_RESERVED_60_63_LEN = 7551;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_BANK0 = 7552;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_BANK0_LEN = 7553;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW16 = 7554;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW16_LEN = 7555;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW15 = 7556;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW15_LEN = 7557;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW14 = 7558;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW14_LEN = 7559;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW13 = 7560;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW13_LEN = 7561;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW12 = 7562;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW12_LEN = 7563;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW11 = 7564;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW11_LEN = 7565;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW10 = 7566;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW10_LEN = 7567;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW9 = 7568;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW9_LEN = 7569;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW8 = 7570;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_CFG_A1MAP_ROW8_LEN = 7571;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_RESERVED_60_63 = 7572;
static const uint64_t IDX_CEN_MBA_MCBAMR1A1Q_RESERVED_60_63_LEN = 7573;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW7 = 7574;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW7_LEN = 7575;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW6 = 7576;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW6_LEN = 7577;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW5 = 7578;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW5_LEN = 7579;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW4 = 7580;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW4_LEN = 7581;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW3 = 7582;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW3_LEN = 7583;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW2 = 7584;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW2_LEN = 7585;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW1 = 7586;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW1_LEN = 7587;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW0 = 7588;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_ROW0_LEN = 7589;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_COL13 = 7590;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_COL13_LEN = 7591;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_COL11 = 7592;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_CFG_A0MAP_COL11_LEN = 7593;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_RESERVED_60_63 = 7594;
static const uint64_t IDX_CEN_MBA_MCBAMR2A0Q_RESERVED_60_63_LEN = 7595;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW7 = 7596;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW7_LEN = 7597;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW6 = 7598;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW6_LEN = 7599;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW5 = 7600;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW5_LEN = 7601;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW4 = 7602;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW4_LEN = 7603;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW3 = 7604;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW3_LEN = 7605;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW2 = 7606;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW2_LEN = 7607;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW1 = 7608;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW1_LEN = 7609;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW0 = 7610;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_ROW0_LEN = 7611;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_COL13 = 7612;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_COL13_LEN = 7613;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_COL11 = 7614;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_CFG_A1MAP_COL11_LEN = 7615;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_RESERVED_60_63 = 7616;
static const uint64_t IDX_CEN_MBA_MCBAMR2A1Q_RESERVED_60_63_LEN = 7617;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL9 = 7618;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL9_LEN = 7619;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL8 = 7620;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL8_LEN = 7621;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL7 = 7622;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL7_LEN = 7623;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL6 = 7624;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL6_LEN = 7625;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL5 = 7626;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL5_LEN = 7627;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL4 = 7628;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL4_LEN = 7629;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL3 = 7630;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL3_LEN = 7631;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL2 = 7632;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_CFG_A0MAP_COL2_LEN = 7633;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_RESERVED_48_63 = 7634;
static const uint64_t IDX_CEN_MBA_MCBAMR3A0Q_RESERVED_48_63_LEN = 7635;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL9 = 7636;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL9_LEN = 7637;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL8 = 7638;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL8_LEN = 7639;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL7 = 7640;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL7_LEN = 7641;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL6 = 7642;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL6_LEN = 7643;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL5 = 7644;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL5_LEN = 7645;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL4 = 7646;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL4_LEN = 7647;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL3 = 7648;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL3_LEN = 7649;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL2 = 7650;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_CFG_A1MAP_COL2_LEN = 7651;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_RESERVED_48_63 = 7652;
static const uint64_t IDX_CEN_MBA_MCBAMR3A1Q_RESERVED_48_63_LEN = 7653;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_RESERVED_0_37 = 7654;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_RESERVED_0_37_LEN = 7655;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN = 7656;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 7657;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 7658;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_RAND_ADDR_ALL_MODE_EN = 7659;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME = 7660;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN = 7661;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_RESERVED_56_59 = 7662;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_RESERVED_56_59_LEN = 7663;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_MCBIST_CFG_RESET_ERROR_DATA = 7664;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_MCBIST_CFG_BREAK_ON_SUBTEST = 7665;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_MCBIST_CFG_STOP_ON_ERR = 7666;
static const uint64_t IDX_CEN_MBA_MCBCFGQ_RESERVED_63 = 7667;
static const uint64_t IDX_CEN_MBA_MCBDRCRQ_CFG_DATA_ROT = 7668;
static const uint64_t IDX_CEN_MBA_MCBDRCRQ_CFG_DATA_ROT_LEN = 7669;
static const uint64_t IDX_CEN_MBA_MCBDRCRQ_CFG_DATA_ROT_SEED = 7670;
static const uint64_t IDX_CEN_MBA_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN = 7671;
static const uint64_t IDX_CEN_MBA_MCBDRCRQ_CFG_INVERT_DATA = 7672;
static const uint64_t IDX_CEN_MBA_MCBDRCRQ_RESERVED_21_63 = 7673;
static const uint64_t IDX_CEN_MBA_MCBDRCRQ_RESERVED_21_63_LEN = 7674;
static const uint64_t IDX_CEN_MBA_MCBDRSRQ_CFG_DATA_ROT_SEED = 7675;
static const uint64_t IDX_CEN_MBA_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN = 7676;
static const uint64_t IDX_CEN_MBA_MCBFD0Q_CFG_FIXED_SEED = 7677;
static const uint64_t IDX_CEN_MBA_MCBFD0Q_CFG_FIXED_SEED_LEN = 7678;
static const uint64_t IDX_CEN_MBA_MCBFD1Q_CFG_FIXED_SEED = 7679;
static const uint64_t IDX_CEN_MBA_MCBFD1Q_CFG_FIXED_SEED_LEN = 7680;
static const uint64_t IDX_CEN_MBA_MCBFD2Q_CFG_FIXED_SEED = 7681;
static const uint64_t IDX_CEN_MBA_MCBFD2Q_CFG_FIXED_SEED_LEN = 7682;
static const uint64_t IDX_CEN_MBA_MCBFD3Q_CFG_FIXED_SEED = 7683;
static const uint64_t IDX_CEN_MBA_MCBFD3Q_CFG_FIXED_SEED_LEN = 7684;
static const uint64_t IDX_CEN_MBA_MCBFD4Q_CFG_FIXED_SEED = 7685;
static const uint64_t IDX_CEN_MBA_MCBFD4Q_CFG_FIXED_SEED_LEN = 7686;
static const uint64_t IDX_CEN_MBA_MCBFD5Q_CFG_FIXED_SEED = 7687;
static const uint64_t IDX_CEN_MBA_MCBFD5Q_CFG_FIXED_SEED_LEN = 7688;
static const uint64_t IDX_CEN_MBA_MCBFD6Q_CFG_FIXED_SEED = 7689;
static const uint64_t IDX_CEN_MBA_MCBFD6Q_CFG_FIXED_SEED_LEN = 7690;
static const uint64_t IDX_CEN_MBA_MCBFD7Q_CFG_FIXED_SEED = 7691;
static const uint64_t IDX_CEN_MBA_MCBFD7Q_CFG_FIXED_SEED_LEN = 7692;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED1 = 7693;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED1_LEN = 7694;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED2 = 7695;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED2_LEN = 7696;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED3 = 7697;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED3_LEN = 7698;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED4 = 7699;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED4_LEN = 7700;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED5 = 7701;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED5_LEN = 7702;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED6 = 7703;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED6_LEN = 7704;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED7 = 7705;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED7_LEN = 7706;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED8 = 7707;
static const uint64_t IDX_CEN_MBA_MCBFDQ_CFG_FIXED_SEED8_LEN = 7708;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED1 = 7709;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED1_LEN = 7710;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED2 = 7711;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED2_LEN = 7712;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED3 = 7713;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED3_LEN = 7714;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED4 = 7715;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED4_LEN = 7716;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED5 = 7717;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED5_LEN = 7718;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED6 = 7719;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED6_LEN = 7720;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED7 = 7721;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED7_LEN = 7722;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED8 = 7723;
static const uint64_t IDX_CEN_MBA_MCBFDSPQ_CFG_FIXED_SEED8_LEN = 7724;
static const uint64_t IDX_CEN_MBA_MCBLFSRA0Q_CFG_LFSR_MASK_A0 = 7725;
static const uint64_t IDX_CEN_MBA_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN = 7726;
static const uint64_t IDX_CEN_MBA_MCBLFSRA0Q_RESERVED_38_63 = 7727;
static const uint64_t IDX_CEN_MBA_MCBLFSRA0Q_RESERVED_38_63_LEN = 7728;
static const uint64_t IDX_CEN_MBA_MCBLFSRA1Q_CFG_LFSR_MASK_A1 = 7729;
static const uint64_t IDX_CEN_MBA_MCBLFSRA1Q_CFG_LFSR_MASK_A1_LEN = 7730;
static const uint64_t IDX_CEN_MBA_MCBLFSRA1Q_RESERVED_38_63 = 7731;
static const uint64_t IDX_CEN_MBA_MCBLFSRA1Q_RESERVED_38_63_LEN = 7732;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE = 7733;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN = 7734;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 7735;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 7736;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 7737;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_MODE = 7738;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_MODE_LEN = 7739;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE = 7740;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN = 7741;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_DONE = 7742;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_DATA_SEL = 7743;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_DATA_SEL_LEN = 7744;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL = 7745;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 7746;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE = 7747;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN = 7748;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 7749;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 7750;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 7751;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_MODE = 7752;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_MODE_LEN = 7753;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE = 7754;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN = 7755;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_DONE = 7756;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_DATA_SEL = 7757;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_DATA_SEL_LEN = 7758;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL = 7759;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 7760;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE = 7761;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN = 7762;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 7763;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 7764;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 7765;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_MODE = 7766;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_MODE_LEN = 7767;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE = 7768;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN = 7769;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_DONE = 7770;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_DATA_SEL = 7771;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_DATA_SEL_LEN = 7772;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL = 7773;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 7774;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE = 7775;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN = 7776;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 7777;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 7778;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 7779;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_MODE = 7780;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_MODE_LEN = 7781;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE = 7782;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN = 7783;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_DONE = 7784;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_DATA_SEL = 7785;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_DATA_SEL_LEN = 7786;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL = 7787;
static const uint64_t IDX_CEN_MBA_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 7788;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE = 7789;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN = 7790;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 7791;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 7792;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 7793;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_MODE = 7794;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_MODE_LEN = 7795;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE = 7796;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN = 7797;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_DONE = 7798;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_DATA_SEL = 7799;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_DATA_SEL_LEN = 7800;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL = 7801;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 7802;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE = 7803;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN = 7804;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 7805;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 7806;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 7807;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_MODE = 7808;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_MODE_LEN = 7809;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE = 7810;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN = 7811;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_DONE = 7812;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_DATA_SEL = 7813;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_DATA_SEL_LEN = 7814;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL = 7815;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 7816;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE = 7817;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN = 7818;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 7819;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 7820;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 7821;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_MODE = 7822;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_MODE_LEN = 7823;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE = 7824;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN = 7825;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_DONE = 7826;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_DATA_SEL = 7827;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_DATA_SEL_LEN = 7828;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL = 7829;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 7830;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE = 7831;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN = 7832;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 7833;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 7834;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 7835;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_MODE = 7836;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_MODE_LEN = 7837;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE = 7838;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN = 7839;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_DONE = 7840;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_DATA_SEL = 7841;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_DATA_SEL_LEN = 7842;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL = 7843;
static const uint64_t IDX_CEN_MBA_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 7844;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE = 7845;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN = 7846;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 7847;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 7848;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 7849;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_MODE = 7850;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_MODE_LEN = 7851;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE = 7852;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN = 7853;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_DONE = 7854;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_DATA_SEL = 7855;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_DATA_SEL_LEN = 7856;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL = 7857;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 7858;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE = 7859;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN = 7860;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 7861;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 7862;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 7863;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_MODE = 7864;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_MODE_LEN = 7865;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE = 7866;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN = 7867;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_DONE = 7868;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_DATA_SEL = 7869;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_DATA_SEL_LEN = 7870;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL = 7871;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 7872;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE = 7873;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN = 7874;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 7875;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 7876;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 7877;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_MODE = 7878;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_MODE_LEN = 7879;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE = 7880;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN = 7881;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_DONE = 7882;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_DATA_SEL = 7883;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_DATA_SEL_LEN = 7884;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL = 7885;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 7886;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE = 7887;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN = 7888;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 7889;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 7890;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 7891;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_MODE = 7892;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_MODE_LEN = 7893;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE = 7894;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN = 7895;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_DONE = 7896;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_DATA_SEL = 7897;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_DATA_SEL_LEN = 7898;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL = 7899;
static const uint64_t IDX_CEN_MBA_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 7900;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE = 7901;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN = 7902;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 7903;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 7904;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 7905;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_MODE = 7906;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_MODE_LEN = 7907;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE = 7908;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN = 7909;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_DONE = 7910;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_DATA_SEL = 7911;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_DATA_SEL_LEN = 7912;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL = 7913;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 7914;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE = 7915;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN = 7916;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 7917;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 7918;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 7919;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_MODE = 7920;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_MODE_LEN = 7921;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE = 7922;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN = 7923;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_DONE = 7924;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_DATA_SEL = 7925;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_DATA_SEL_LEN = 7926;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL = 7927;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 7928;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE = 7929;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN = 7930;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 7931;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 7932;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 7933;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_MODE = 7934;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_MODE_LEN = 7935;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE = 7936;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN = 7937;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_DONE = 7938;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_DATA_SEL = 7939;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_DATA_SEL_LEN = 7940;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL = 7941;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 7942;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE = 7943;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN = 7944;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 7945;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 7946;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 7947;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_MODE = 7948;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_MODE_LEN = 7949;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE = 7950;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN = 7951;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_DONE = 7952;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_DATA_SEL = 7953;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_DATA_SEL_LEN = 7954;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL = 7955;
static const uint64_t IDX_CEN_MBA_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 7956;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE = 7957;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN = 7958;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 7959;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 7960;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 7961;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_MODE = 7962;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_MODE_LEN = 7963;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE = 7964;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN = 7965;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_DONE = 7966;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_DATA_SEL = 7967;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_DATA_SEL_LEN = 7968;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL = 7969;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 7970;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE = 7971;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN = 7972;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 7973;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 7974;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 7975;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_MODE = 7976;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_MODE_LEN = 7977;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE = 7978;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN = 7979;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_DONE = 7980;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_DATA_SEL = 7981;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_DATA_SEL_LEN = 7982;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL = 7983;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 7984;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE = 7985;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN = 7986;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 7987;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 7988;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 7989;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_MODE = 7990;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_MODE_LEN = 7991;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE = 7992;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN = 7993;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_DONE = 7994;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_DATA_SEL = 7995;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_DATA_SEL_LEN = 7996;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL = 7997;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 7998;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE = 7999;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN = 8000;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 8001;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 8002;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 8003;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_MODE = 8004;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_MODE_LEN = 8005;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE = 8006;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN = 8007;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_DONE = 8008;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_DATA_SEL = 8009;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_DATA_SEL_LEN = 8010;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL = 8011;
static const uint64_t IDX_CEN_MBA_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 8012;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE = 8013;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN = 8014;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 8015;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 8016;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 8017;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_MODE = 8018;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_MODE_LEN = 8019;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE = 8020;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN = 8021;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_DONE = 8022;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_DATA_SEL = 8023;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_DATA_SEL_LEN = 8024;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL = 8025;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 8026;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE = 8027;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN = 8028;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 8029;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 8030;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 8031;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_MODE = 8032;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_MODE_LEN = 8033;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE = 8034;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN = 8035;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_DONE = 8036;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_DATA_SEL = 8037;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_DATA_SEL_LEN = 8038;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL = 8039;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 8040;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE = 8041;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN = 8042;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 8043;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 8044;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 8045;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_MODE = 8046;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_MODE_LEN = 8047;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE = 8048;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN = 8049;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_DONE = 8050;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_DATA_SEL = 8051;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_DATA_SEL_LEN = 8052;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL = 8053;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 8054;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE = 8055;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN = 8056;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 8057;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 8058;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 8059;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_MODE = 8060;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_MODE_LEN = 8061;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE = 8062;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN = 8063;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_DONE = 8064;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_DATA_SEL = 8065;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_DATA_SEL_LEN = 8066;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL = 8067;
static const uint64_t IDX_CEN_MBA_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 8068;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE = 8069;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN = 8070;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 8071;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 8072;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 8073;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_MODE = 8074;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_MODE_LEN = 8075;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE = 8076;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN = 8077;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_DONE = 8078;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_DATA_SEL = 8079;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_DATA_SEL_LEN = 8080;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL = 8081;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 8082;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE = 8083;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN = 8084;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 8085;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 8086;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 8087;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_MODE = 8088;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_MODE_LEN = 8089;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE = 8090;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN = 8091;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_DONE = 8092;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_DATA_SEL = 8093;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_DATA_SEL_LEN = 8094;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL = 8095;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 8096;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE = 8097;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN = 8098;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 8099;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 8100;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 8101;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_MODE = 8102;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_MODE_LEN = 8103;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE = 8104;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN = 8105;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_DONE = 8106;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_DATA_SEL = 8107;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_DATA_SEL_LEN = 8108;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL = 8109;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 8110;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE = 8111;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN = 8112;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 8113;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 8114;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 8115;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_MODE = 8116;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_MODE_LEN = 8117;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE = 8118;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN = 8119;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_DONE = 8120;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_DATA_SEL = 8121;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_DATA_SEL_LEN = 8122;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL = 8123;
static const uint64_t IDX_CEN_MBA_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 8124;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE = 8125;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN = 8126;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 8127;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 8128;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 8129;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_MODE = 8130;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_MODE_LEN = 8131;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE = 8132;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN = 8133;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_DONE = 8134;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_DATA_SEL = 8135;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_DATA_SEL_LEN = 8136;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL = 8137;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 8138;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE = 8139;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN = 8140;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 8141;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 8142;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 8143;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_MODE = 8144;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_MODE_LEN = 8145;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE = 8146;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN = 8147;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_DONE = 8148;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_DATA_SEL = 8149;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_DATA_SEL_LEN = 8150;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL = 8151;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 8152;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE = 8153;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN = 8154;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 8155;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 8156;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 8157;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_MODE = 8158;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_MODE_LEN = 8159;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE = 8160;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN = 8161;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_DONE = 8162;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_DATA_SEL = 8163;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_DATA_SEL_LEN = 8164;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL = 8165;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 8166;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE = 8167;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN = 8168;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 8169;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 8170;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 8171;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_MODE = 8172;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_MODE_LEN = 8173;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE = 8174;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN = 8175;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_DONE = 8176;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_DATA_SEL = 8177;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_DATA_SEL_LEN = 8178;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL = 8179;
static const uint64_t IDX_CEN_MBA_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 8180;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_RESERVED_0_49 = 8181;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_RESERVED_0_49_LEN = 8182;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_RANDCMD_WGT = 8183;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_RANDCMD_WGT_LEN = 8184;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_MIN_CMD_GAP = 8185;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_MIN_CMD_GAP_LEN = 8186;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_EN_RANDCMD_GAP = 8187;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_RANDGAP_WGT = 8188;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_RANDGAP_WGT_LEN = 8189;
static const uint64_t IDX_CEN_MBA_MCBPARMQ_CFG_BC4_EN = 8190;
static const uint64_t IDX_CEN_MBA_MCBRCRQ_RESERVED_0_31 = 8191;
static const uint64_t IDX_CEN_MBA_MCBRCRQ_RESERVED_0_31_LEN = 8192;
static const uint64_t IDX_CEN_MBA_MCBRCRQ_CFG_RUNTIME_MCBALL = 8193;
static const uint64_t IDX_CEN_MBA_MCBRCRQ_CFG_RUNTIME_SUBTEST = 8194;
static const uint64_t IDX_CEN_MBA_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN = 8195;
static const uint64_t IDX_CEN_MBA_MCBRCRQ_CFG_RUNTIME_OVERHEAD = 8196;
static const uint64_t IDX_CEN_MBA_MCBRCRQ_RESERVED_39 = 8197;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED0 = 8198;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED0_LEN = 8199;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED1 = 8200;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED1_LEN = 8201;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED2 = 8202;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED2_LEN = 8203;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED3 = 8204;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED3_LEN = 8205;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED4 = 8206;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED4_LEN = 8207;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED5 = 8208;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED5_LEN = 8209;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED6 = 8210;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED6_LEN = 8211;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED7 = 8212;
static const uint64_t IDX_CEN_MBA_MCBRDS0Q_DGEN_RNDD_SEED7_LEN = 8213;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED0 = 8214;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED0_LEN = 8215;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED1 = 8216;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED1_LEN = 8217;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED2 = 8218;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED2_LEN = 8219;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED3 = 8220;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED3_LEN = 8221;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED4 = 8222;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED4_LEN = 8223;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED5 = 8224;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED5_LEN = 8225;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED6 = 8226;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED6_LEN = 8227;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED7 = 8228;
static const uint64_t IDX_CEN_MBA_MCBRDS1Q_DGEN_RNDD_SEED7_LEN = 8229;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED0 = 8230;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED0_LEN = 8231;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED1 = 8232;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED1_LEN = 8233;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED2 = 8234;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED2_LEN = 8235;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED3 = 8236;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED3_LEN = 8237;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED4 = 8238;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED4_LEN = 8239;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED5 = 8240;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED5_LEN = 8241;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED6 = 8242;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED6_LEN = 8243;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED7 = 8244;
static const uint64_t IDX_CEN_MBA_MCBRDS2Q_DGEN_RNDD_SEED7_LEN = 8245;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED0 = 8246;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED0_LEN = 8247;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED1 = 8248;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED1_LEN = 8249;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED2 = 8250;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED2_LEN = 8251;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED3 = 8252;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED3_LEN = 8253;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED4 = 8254;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED4_LEN = 8255;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED5 = 8256;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED5_LEN = 8257;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED6 = 8258;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED6_LEN = 8259;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED7 = 8260;
static const uint64_t IDX_CEN_MBA_MCBRDS3Q_DGEN_RNDD_SEED7_LEN = 8261;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED0 = 8262;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED0_LEN = 8263;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED1 = 8264;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED1_LEN = 8265;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED2 = 8266;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED2_LEN = 8267;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED3 = 8268;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED3_LEN = 8269;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED4 = 8270;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED4_LEN = 8271;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED5 = 8272;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED5_LEN = 8273;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED6 = 8274;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED6_LEN = 8275;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED7 = 8276;
static const uint64_t IDX_CEN_MBA_MCBRDS4Q_DGEN_RNDD_SEED7_LEN = 8277;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED0 = 8278;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED0_LEN = 8279;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED1 = 8280;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED1_LEN = 8281;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED2 = 8282;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED2_LEN = 8283;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED3 = 8284;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED3_LEN = 8285;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED4 = 8286;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED4_LEN = 8287;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED5 = 8288;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED5_LEN = 8289;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED6 = 8290;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED6_LEN = 8291;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED7 = 8292;
static const uint64_t IDX_CEN_MBA_MCBRDS5Q_DGEN_RNDD_SEED7_LEN = 8293;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED0 = 8294;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED0_LEN = 8295;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED1 = 8296;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED1_LEN = 8297;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED2 = 8298;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED2_LEN = 8299;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED3 = 8300;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED3_LEN = 8301;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED4 = 8302;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED4_LEN = 8303;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED5 = 8304;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED5_LEN = 8305;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED6 = 8306;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED6_LEN = 8307;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED7 = 8308;
static const uint64_t IDX_CEN_MBA_MCBRDS6Q_DGEN_RNDD_SEED7_LEN = 8309;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED0 = 8310;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED0_LEN = 8311;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED1 = 8312;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED1_LEN = 8313;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED2 = 8314;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED2_LEN = 8315;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED3 = 8316;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED3_LEN = 8317;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED4 = 8318;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED4_LEN = 8319;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED5 = 8320;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED5_LEN = 8321;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED6 = 8322;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED6_LEN = 8323;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED7 = 8324;
static const uint64_t IDX_CEN_MBA_MCBRDS7Q_DGEN_RNDD_SEED7_LEN = 8325;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED0 = 8326;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED0_LEN = 8327;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED1 = 8328;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED1_LEN = 8329;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED2 = 8330;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED2_LEN = 8331;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED3 = 8332;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED3_LEN = 8333;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED4 = 8334;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED4_LEN = 8335;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED5 = 8336;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED5_LEN = 8337;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED6 = 8338;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED6_LEN = 8339;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED7 = 8340;
static const uint64_t IDX_CEN_MBA_MCBRDS8Q_DGEN_RNDD_SEED7_LEN = 8341;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED0 = 8342;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED0_LEN = 8343;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED1 = 8344;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED1_LEN = 8345;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED2 = 8346;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED2_LEN = 8347;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED3 = 8348;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED3_LEN = 8349;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED4 = 8350;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED4_LEN = 8351;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED5 = 8352;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED5_LEN = 8353;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED6 = 8354;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED6_LEN = 8355;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED7 = 8356;
static const uint64_t IDX_CEN_MBA_MCBRDSSPQ_DGEN_RNDD_SEED7_LEN = 8357;
static const uint64_t IDX_CEN_MBA_MCBREARA0Q_CFG_RAND_END_ADDR_A0 = 8358;
static const uint64_t IDX_CEN_MBA_MCBREARA0Q_CFG_RAND_END_ADDR_A0_LEN = 8359;
static const uint64_t IDX_CEN_MBA_MCBREARA0Q_RESERVED_38_63 = 8360;
static const uint64_t IDX_CEN_MBA_MCBREARA0Q_RESERVED_38_63_LEN = 8361;
static const uint64_t IDX_CEN_MBA_MCBREARA1Q_CFG_RAND_END_ADDR_A1 = 8362;
static const uint64_t IDX_CEN_MBA_MCBREARA1Q_CFG_RAND_END_ADDR_A1_LEN = 8363;
static const uint64_t IDX_CEN_MBA_MCBREARA1Q_RESERVED_38_63 = 8364;
static const uint64_t IDX_CEN_MBA_MCBREARA1Q_RESERVED_38_63_LEN = 8365;
static const uint64_t IDX_CEN_MBA_MCBRSARA0Q_CFG_RAND_START_ADDR_A0 = 8366;
static const uint64_t IDX_CEN_MBA_MCBRSARA0Q_CFG_RAND_START_ADDR_A0_LEN = 8367;
static const uint64_t IDX_CEN_MBA_MCBRSARA0Q_RESERVED_38_63 = 8368;
static const uint64_t IDX_CEN_MBA_MCBRSARA0Q_RESERVED_38_63_LEN = 8369;
static const uint64_t IDX_CEN_MBA_MCBRSARA1Q_CFG_RAND_START_ADDR_A1 = 8370;
static const uint64_t IDX_CEN_MBA_MCBRSARA1Q_CFG_RAND_START_ADDR_A1_LEN = 8371;
static const uint64_t IDX_CEN_MBA_MCBRSARA1Q_RESERVED_38_63 = 8372;
static const uint64_t IDX_CEN_MBA_MCBRSARA1Q_RESERVED_38_63_LEN = 8373;
static const uint64_t IDX_CEN_MBA_MCBSEARA0Q_CFG_SEQ_END_ADDR_A0 = 8374;
static const uint64_t IDX_CEN_MBA_MCBSEARA0Q_CFG_SEQ_END_ADDR_A0_LEN = 8375;
static const uint64_t IDX_CEN_MBA_MCBSEARA0Q_RESERVED_38_63 = 8376;
static const uint64_t IDX_CEN_MBA_MCBSEARA0Q_RESERVED_38_63_LEN = 8377;
static const uint64_t IDX_CEN_MBA_MCBSEARA1Q_CFG_SEQ_END_ADDR_A1 = 8378;
static const uint64_t IDX_CEN_MBA_MCBSEARA1Q_CFG_SEQ_END_ADDR_A1_LEN = 8379;
static const uint64_t IDX_CEN_MBA_MCBSEARA1Q_RESERVED_38_63 = 8380;
static const uint64_t IDX_CEN_MBA_MCBSEARA1Q_RESERVED_38_63_LEN = 8381;
static const uint64_t IDX_CEN_MBA_MCBSSARA0Q_CFG_SEQ_START_ADDR_A0 = 8382;
static const uint64_t IDX_CEN_MBA_MCBSSARA0Q_CFG_SEQ_START_ADDR_A0_LEN = 8383;
static const uint64_t IDX_CEN_MBA_MCBSSARA0Q_RESERVED_38_63 = 8384;
static const uint64_t IDX_CEN_MBA_MCBSSARA0Q_RESERVED_38_63_LEN = 8385;
static const uint64_t IDX_CEN_MBA_MCBSSARA1Q_CFG_SEQ_START_ADDR_A1 = 8386;
static const uint64_t IDX_CEN_MBA_MCBSSARA1Q_CFG_SEQ_START_ADDR_A1_LEN = 8387;
static const uint64_t IDX_CEN_MBA_MCBSSARA1Q_RESERVED_38_63 = 8388;
static const uint64_t IDX_CEN_MBA_MCBSSARA1Q_RESERVED_38_63_LEN = 8389;
static const uint64_t IDX_CEN_MBA_MCB_CNTLQ_START = 8390;
static const uint64_t IDX_CEN_MBA_MCB_CNTLQ_STOP = 8391;
static const uint64_t IDX_CEN_MBA_MCB_CNTLSTATQ_IP = 8392;
static const uint64_t IDX_CEN_MBA_MCB_CNTLSTATQ_DONE = 8393;
static const uint64_t IDX_CEN_MBA_MCB_CNTLSTATQ_FAIL = 8394;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM = 8395;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN = 8396;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1 = 8397;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN = 8398;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2 = 8399;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN = 8400;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3 = 8401;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN = 8402;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4 = 8403;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN = 8404;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5 = 8405;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN = 8406;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6 = 8407;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN = 8408;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7 = 8409;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN = 8410;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8 = 8411;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN = 8412;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9 = 8413;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN = 8414;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10 = 8415;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN = 8416;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11 = 8417;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN = 8418;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12 = 8419;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN = 8420;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13 = 8421;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN = 8422;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14 = 8423;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN = 8424;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15 = 8425;
static const uint64_t IDX_CEN_MBA_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN = 8426;
static const uint64_t IDX_CEN_MBA_RUNTIMECTRQ_CFG_RUNTIME_CTR = 8427;
static const uint64_t IDX_CEN_MBA_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN = 8428;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_ADDRESS = 8429;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_ADDRESS_LEN = 8430;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_DDR_RESETN = 8431;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_BANK = 8432;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_BANK_LEN = 8433;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_ACTIVATE = 8434;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_RASN = 8435;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_CASN = 8436;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_WEN = 8437;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_CKE = 8438;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_CKE_LEN = 8439;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_CSN = 8440;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_CSN_LEN = 8441;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_ODT = 8442;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_ODT_LEN = 8443;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_DDR_CALIBRATION_TYPE = 8444;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_DDR_CALIBRATION_TYPE_LEN = 8445;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_DDR_PARITY = 8446;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_MA_B_CKE3_7 = 8447;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_LOOP_BREAK_MODE = 8448;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_0_LOOP_BREAK_MODE_LEN = 8449;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_ADDRESS = 8450;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_ADDRESS_LEN = 8451;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_DDR_RESETN = 8452;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_BANK = 8453;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_BANK_LEN = 8454;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_ACTIVATE = 8455;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_RASN = 8456;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_CASN = 8457;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_WEN = 8458;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_CKE = 8459;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_CKE_LEN = 8460;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_CSN = 8461;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_CSN_LEN = 8462;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_ODT = 8463;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_ODT_LEN = 8464;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_DDR_CALIBRATION_TYPE = 8465;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_DDR_CALIBRATION_TYPE_LEN = 8466;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_DDR_PARITY = 8467;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_MA_B_CKE3_7 = 8468;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_LOOP_BREAK_MODE = 8469;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_1_LOOP_BREAK_MODE_LEN = 8470;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_ADDRESS = 8471;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_ADDRESS_LEN = 8472;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_DDR_RESETN = 8473;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_BANK = 8474;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_BANK_LEN = 8475;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_ACTIVATE = 8476;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_RASN = 8477;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_CASN = 8478;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_WEN = 8479;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_CKE = 8480;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_CKE_LEN = 8481;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_CSN = 8482;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_CSN_LEN = 8483;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_ODT = 8484;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_ODT_LEN = 8485;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_DDR_CALIBRATION_TYPE = 8486;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_DDR_CALIBRATION_TYPE_LEN = 8487;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_DDR_PARITY = 8488;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_MA_B_CKE3_7 = 8489;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_LOOP_BREAK_MODE = 8490;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN = 8491;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_ADDRESS = 8492;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_ADDRESS_LEN = 8493;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_DDR_RESETN = 8494;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_BANK = 8495;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_BANK_LEN = 8496;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_ACTIVATE = 8497;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_RASN = 8498;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_CASN = 8499;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_WEN = 8500;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_CKE = 8501;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_CKE_LEN = 8502;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_CSN = 8503;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_CSN_LEN = 8504;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_ODT = 8505;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_ODT_LEN = 8506;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_DDR_CALIBRATION_TYPE = 8507;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_DDR_CALIBRATION_TYPE_LEN = 8508;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_DDR_PARITY = 8509;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_MA_B_CKE3_7 = 8510;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_LOOP_BREAK_MODE = 8511;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN = 8512;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_ADDRESS = 8513;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_ADDRESS_LEN = 8514;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_DDR_RESETN = 8515;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_BANK = 8516;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_BANK_LEN = 8517;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_ACTIVATE = 8518;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_RASN = 8519;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_CASN = 8520;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_WEN = 8521;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_CKE = 8522;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_CKE_LEN = 8523;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_CSN = 8524;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_CSN_LEN = 8525;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_ODT = 8526;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_ODT_LEN = 8527;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_DDR_CALIBRATION_TYPE = 8528;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_DDR_CALIBRATION_TYPE_LEN = 8529;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_DDR_PARITY = 8530;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_MA_B_CKE3_7 = 8531;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_LOOP_BREAK_MODE = 8532;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN = 8533;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_ADDRESS = 8534;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_ADDRESS_LEN = 8535;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_DDR_RESETN = 8536;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_BANK = 8537;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_BANK_LEN = 8538;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_ACTIVATE = 8539;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_RASN = 8540;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_CASN = 8541;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_WEN = 8542;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_CKE = 8543;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_CKE_LEN = 8544;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_CSN = 8545;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_CSN_LEN = 8546;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_ODT = 8547;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_ODT_LEN = 8548;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_DDR_CALIBRATION_TYPE = 8549;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_DDR_CALIBRATION_TYPE_LEN = 8550;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_DDR_PARITY = 8551;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_MA_B_CKE3_7 = 8552;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_LOOP_BREAK_MODE = 8553;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN = 8554;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_ADDRESS = 8555;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_ADDRESS_LEN = 8556;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_DDR_RESETN = 8557;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_BANK = 8558;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_BANK_LEN = 8559;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_ACTIVATE = 8560;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_RASN = 8561;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_CASN = 8562;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_WEN = 8563;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_CKE = 8564;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_CKE_LEN = 8565;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_CSN = 8566;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_CSN_LEN = 8567;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_ODT = 8568;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_ODT_LEN = 8569;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_DDR_CALIBRATION_TYPE = 8570;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_DDR_CALIBRATION_TYPE_LEN = 8571;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_DDR_PARITY = 8572;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_MA_B_CKE3_7 = 8573;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_LOOP_BREAK_MODE = 8574;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN = 8575;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_ADDRESS = 8576;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_ADDRESS_LEN = 8577;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_DDR_RESETN = 8578;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_BANK = 8579;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_BANK_LEN = 8580;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_ACTIVATE = 8581;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_RASN = 8582;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_CASN = 8583;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_WEN = 8584;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_CKE = 8585;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_CKE_LEN = 8586;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_CSN = 8587;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_CSN_LEN = 8588;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_ODT = 8589;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_ODT_LEN = 8590;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_DDR_CALIBRATION_TYPE = 8591;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_DDR_CALIBRATION_TYPE_LEN = 8592;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_DDR_PARITY = 8593;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_MA_B_CKE3_7 = 8594;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_LOOP_BREAK_MODE = 8595;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN = 8596;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_ADDRESS = 8597;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_ADDRESS_LEN = 8598;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_DDR_RESETN = 8599;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_BANK = 8600;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_BANK_LEN = 8601;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_ACTIVATE = 8602;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_RASN = 8603;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_CASN = 8604;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_WEN = 8605;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_CKE = 8606;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_CKE_LEN = 8607;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_CSN = 8608;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_CSN_LEN = 8609;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_ODT = 8610;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_ODT_LEN = 8611;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_DDR_CALIBRATION_TYPE = 8612;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_DDR_CALIBRATION_TYPE_LEN = 8613;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_DDR_PARITY = 8614;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_MA_B_CKE3_7 = 8615;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_LOOP_BREAK_MODE = 8616;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN = 8617;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_ADDRESS = 8618;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_ADDRESS_LEN = 8619;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_DDR_RESETN = 8620;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_BANK = 8621;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_BANK_LEN = 8622;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_ACTIVATE = 8623;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_RASN = 8624;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_CASN = 8625;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_WEN = 8626;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_CKE = 8627;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_CKE_LEN = 8628;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_CSN = 8629;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_CSN_LEN = 8630;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_ODT = 8631;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_ODT_LEN = 8632;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_DDR_CALIBRATION_TYPE = 8633;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_DDR_CALIBRATION_TYPE_LEN = 8634;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_DDR_PARITY = 8635;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_MA_B_CKE3_7 = 8636;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_LOOP_BREAK_MODE = 8637;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN = 8638;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_ADDRESS = 8639;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_ADDRESS_LEN = 8640;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_DDR_RESETN = 8641;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_BANK = 8642;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_BANK_LEN = 8643;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_ACTIVATE = 8644;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_RASN = 8645;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_CASN = 8646;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_WEN = 8647;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_CKE = 8648;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_CKE_LEN = 8649;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_CSN = 8650;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_CSN_LEN = 8651;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_ODT = 8652;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_ODT_LEN = 8653;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_DDR_CALIBRATION_TYPE = 8654;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_DDR_CALIBRATION_TYPE_LEN = 8655;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_DDR_PARITY = 8656;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_MA_B_CKE3_7 = 8657;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_LOOP_BREAK_MODE = 8658;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN = 8659;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_ADDRESS = 8660;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_ADDRESS_LEN = 8661;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_DDR_RESETN = 8662;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_BANK = 8663;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_BANK_LEN = 8664;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_ACTIVATE = 8665;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_RASN = 8666;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_CASN = 8667;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_WEN = 8668;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_CKE = 8669;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_CKE_LEN = 8670;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_CSN = 8671;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_CSN_LEN = 8672;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_ODT = 8673;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_ODT_LEN = 8674;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_DDR_CALIBRATION_TYPE = 8675;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_DDR_CALIBRATION_TYPE_LEN = 8676;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_DDR_PARITY = 8677;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_MA_B_CKE3_7 = 8678;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_LOOP_BREAK_MODE = 8679;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN = 8680;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_ADDRESS = 8681;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_ADDRESS_LEN = 8682;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_DDR_RESETN = 8683;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_BANK = 8684;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_BANK_LEN = 8685;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_ACTIVATE = 8686;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_RASN = 8687;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_CASN = 8688;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_WEN = 8689;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_CKE = 8690;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_CKE_LEN = 8691;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_CSN = 8692;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_CSN_LEN = 8693;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_ODT = 8694;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_ODT_LEN = 8695;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_DDR_CALIBRATION_TYPE = 8696;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_DDR_CALIBRATION_TYPE_LEN = 8697;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_DDR_PARITY = 8698;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_MA_B_CKE3_7 = 8699;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_LOOP_BREAK_MODE = 8700;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_2_LOOP_BREAK_MODE_LEN = 8701;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_ADDRESS = 8702;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_ADDRESS_LEN = 8703;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_DDR_RESETN = 8704;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_BANK = 8705;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_BANK_LEN = 8706;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_ACTIVATE = 8707;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_RASN = 8708;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_CASN = 8709;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_WEN = 8710;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_CKE = 8711;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_CKE_LEN = 8712;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_CSN = 8713;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_CSN_LEN = 8714;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_ODT = 8715;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_ODT_LEN = 8716;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_DDR_CALIBRATION_TYPE = 8717;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_DDR_CALIBRATION_TYPE_LEN = 8718;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_DDR_PARITY = 8719;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_MA_B_CKE3_7 = 8720;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_LOOP_BREAK_MODE = 8721;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN = 8722;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_ADDRESS = 8723;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_ADDRESS_LEN = 8724;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_DDR_RESETN = 8725;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_BANK = 8726;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_BANK_LEN = 8727;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_ACTIVATE = 8728;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_RASN = 8729;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_CASN = 8730;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_WEN = 8731;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_CKE = 8732;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_CKE_LEN = 8733;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_CSN = 8734;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_CSN_LEN = 8735;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_ODT = 8736;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_ODT_LEN = 8737;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_DDR_CALIBRATION_TYPE = 8738;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_DDR_CALIBRATION_TYPE_LEN = 8739;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_DDR_PARITY = 8740;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_MA_B_CKE3_7 = 8741;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_LOOP_BREAK_MODE = 8742;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN = 8743;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_ADDRESS = 8744;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_ADDRESS_LEN = 8745;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_DDR_RESETN = 8746;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_BANK = 8747;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_BANK_LEN = 8748;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_ACTIVATE = 8749;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_RASN = 8750;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_CASN = 8751;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_WEN = 8752;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_CKE = 8753;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_CKE_LEN = 8754;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_CSN = 8755;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_CSN_LEN = 8756;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_ODT = 8757;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_ODT_LEN = 8758;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_DDR_CALIBRATION_TYPE = 8759;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_DDR_CALIBRATION_TYPE_LEN = 8760;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_DDR_PARITY = 8761;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_MA_B_CKE3_7 = 8762;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_LOOP_BREAK_MODE = 8763;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN = 8764;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_ADDRESS = 8765;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_ADDRESS_LEN = 8766;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_DDR_RESETN = 8767;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_BANK = 8768;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_BANK_LEN = 8769;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_ACTIVATE = 8770;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_RASN = 8771;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_CASN = 8772;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_WEN = 8773;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_CKE = 8774;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_CKE_LEN = 8775;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_CSN = 8776;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_CSN_LEN = 8777;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_ODT = 8778;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_ODT_LEN = 8779;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_DDR_CALIBRATION_TYPE = 8780;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_DDR_CALIBRATION_TYPE_LEN = 8781;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_DDR_PARITY = 8782;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_MA_B_CKE3_7 = 8783;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_LOOP_BREAK_MODE = 8784;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN = 8785;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_ADDRESS = 8786;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_ADDRESS_LEN = 8787;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_DDR_RESETN = 8788;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_BANK = 8789;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_BANK_LEN = 8790;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_ACTIVATE = 8791;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_RASN = 8792;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_CASN = 8793;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_WEN = 8794;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_CKE = 8795;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_CKE_LEN = 8796;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_CSN = 8797;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_CSN_LEN = 8798;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_ODT = 8799;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_ODT_LEN = 8800;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_DDR_CALIBRATION_TYPE = 8801;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_DDR_CALIBRATION_TYPE_LEN = 8802;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_DDR_PARITY = 8803;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_MA_B_CKE3_7 = 8804;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_LOOP_BREAK_MODE = 8805;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN = 8806;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_ADDRESS = 8807;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_ADDRESS_LEN = 8808;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_DDR_RESETN = 8809;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_BANK = 8810;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_BANK_LEN = 8811;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_ACTIVATE = 8812;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_RASN = 8813;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_CASN = 8814;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_WEN = 8815;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_CKE = 8816;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_CKE_LEN = 8817;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_CSN = 8818;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_CSN_LEN = 8819;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_ODT = 8820;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_ODT_LEN = 8821;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_DDR_CALIBRATION_TYPE = 8822;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_DDR_CALIBRATION_TYPE_LEN = 8823;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_DDR_PARITY = 8824;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_MA_B_CKE3_7 = 8825;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_LOOP_BREAK_MODE = 8826;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN = 8827;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_ADDRESS = 8828;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_ADDRESS_LEN = 8829;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_DDR_RESETN = 8830;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_BANK = 8831;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_BANK_LEN = 8832;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_ACTIVATE = 8833;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_RASN = 8834;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_CASN = 8835;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_WEN = 8836;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_CKE = 8837;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_CKE_LEN = 8838;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_CSN = 8839;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_CSN_LEN = 8840;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_ODT = 8841;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_ODT_LEN = 8842;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_DDR_CALIBRATION_TYPE = 8843;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_DDR_CALIBRATION_TYPE_LEN = 8844;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_DDR_PARITY = 8845;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_MA_B_CKE3_7 = 8846;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_LOOP_BREAK_MODE = 8847;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN = 8848;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_ADDRESS = 8849;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_ADDRESS_LEN = 8850;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_DDR_RESETN = 8851;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_BANK = 8852;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_BANK_LEN = 8853;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_ACTIVATE = 8854;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_RASN = 8855;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_CASN = 8856;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_WEN = 8857;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_CKE = 8858;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_CKE_LEN = 8859;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_CSN = 8860;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_CSN_LEN = 8861;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_ODT = 8862;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_ODT_LEN = 8863;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_DDR_CALIBRATION_TYPE = 8864;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_DDR_CALIBRATION_TYPE_LEN = 8865;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_DDR_PARITY = 8866;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_MA_B_CKE3_7 = 8867;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_LOOP_BREAK_MODE = 8868;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN = 8869;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_ADDRESS = 8870;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_ADDRESS_LEN = 8871;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_DDR_RESETN = 8872;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_BANK = 8873;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_BANK_LEN = 8874;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_ACTIVATE = 8875;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_RASN = 8876;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_CASN = 8877;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_WEN = 8878;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_CKE = 8879;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_CKE_LEN = 8880;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_CSN = 8881;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_CSN_LEN = 8882;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_ODT = 8883;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_ODT_LEN = 8884;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_DDR_CALIBRATION_TYPE = 8885;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_DDR_CALIBRATION_TYPE_LEN = 8886;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_DDR_PARITY = 8887;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_MA_B_CKE3_7 = 8888;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_LOOP_BREAK_MODE = 8889;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN = 8890;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_ADDRESS = 8891;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_ADDRESS_LEN = 8892;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_DDR_RESETN = 8893;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_BANK = 8894;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_BANK_LEN = 8895;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_ACTIVATE = 8896;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_RASN = 8897;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_CASN = 8898;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_WEN = 8899;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_CKE = 8900;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_CKE_LEN = 8901;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_CSN = 8902;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_CSN_LEN = 8903;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_ODT = 8904;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_ODT_LEN = 8905;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_DDR_CALIBRATION_TYPE = 8906;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_DDR_CALIBRATION_TYPE_LEN = 8907;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_DDR_PARITY = 8908;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_MA_B_CKE3_7 = 8909;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_LOOP_BREAK_MODE = 8910;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN = 8911;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_ADDRESS = 8912;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_ADDRESS_LEN = 8913;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_DDR_RESETN = 8914;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_BANK = 8915;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_BANK_LEN = 8916;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_ACTIVATE = 8917;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_RASN = 8918;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_CASN = 8919;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_WEN = 8920;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_CKE = 8921;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_CKE_LEN = 8922;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_CSN = 8923;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_CSN_LEN = 8924;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_ODT = 8925;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_ODT_LEN = 8926;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_DDR_CALIBRATION_TYPE = 8927;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_DDR_CALIBRATION_TYPE_LEN = 8928;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_DDR_PARITY = 8929;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_MA_B_CKE3_7 = 8930;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_LOOP_BREAK_MODE = 8931;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_3_LOOP_BREAK_MODE_LEN = 8932;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_ADDRESS = 8933;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_ADDRESS_LEN = 8934;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_DDR_RESETN = 8935;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_BANK = 8936;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_BANK_LEN = 8937;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_ACTIVATE = 8938;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_RASN = 8939;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_CASN = 8940;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_WEN = 8941;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_CKE = 8942;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_CKE_LEN = 8943;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_CSN = 8944;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_CSN_LEN = 8945;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_ODT = 8946;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_ODT_LEN = 8947;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_DDR_CALIBRATION_TYPE = 8948;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_DDR_CALIBRATION_TYPE_LEN = 8949;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_DDR_PARITY = 8950;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_MA_B_CKE3_7 = 8951;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_LOOP_BREAK_MODE = 8952;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN = 8953;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_ADDRESS = 8954;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_ADDRESS_LEN = 8955;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_DDR_RESETN = 8956;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_BANK = 8957;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_BANK_LEN = 8958;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_ACTIVATE = 8959;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_RASN = 8960;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_CASN = 8961;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_WEN = 8962;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_CKE = 8963;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_CKE_LEN = 8964;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_CSN = 8965;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_CSN_LEN = 8966;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_ODT = 8967;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_ODT_LEN = 8968;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_DDR_CALIBRATION_TYPE = 8969;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_DDR_CALIBRATION_TYPE_LEN = 8970;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_DDR_PARITY = 8971;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_MA_B_CKE3_7 = 8972;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_LOOP_BREAK_MODE = 8973;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN = 8974;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_ADDRESS = 8975;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_ADDRESS_LEN = 8976;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_DDR_RESETN = 8977;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_BANK = 8978;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_BANK_LEN = 8979;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_ACTIVATE = 8980;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_RASN = 8981;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_CASN = 8982;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_WEN = 8983;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_CKE = 8984;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_CKE_LEN = 8985;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_CSN = 8986;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_CSN_LEN = 8987;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_ODT = 8988;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_ODT_LEN = 8989;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_DDR_CALIBRATION_TYPE = 8990;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_DDR_CALIBRATION_TYPE_LEN = 8991;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_DDR_PARITY = 8992;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_MA_B_CKE3_7 = 8993;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_LOOP_BREAK_MODE = 8994;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_4_LOOP_BREAK_MODE_LEN = 8995;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_ADDRESS = 8996;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_ADDRESS_LEN = 8997;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_DDR_RESETN = 8998;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_BANK = 8999;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_BANK_LEN = 9000;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_ACTIVATE = 9001;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_RASN = 9002;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_CASN = 9003;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_WEN = 9004;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_CKE = 9005;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_CKE_LEN = 9006;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_CSN = 9007;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_CSN_LEN = 9008;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_ODT = 9009;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_ODT_LEN = 9010;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_DDR_CALIBRATION_TYPE = 9011;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_DDR_CALIBRATION_TYPE_LEN = 9012;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_DDR_PARITY = 9013;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_MA_B_CKE3_7 = 9014;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_LOOP_BREAK_MODE = 9015;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_5_LOOP_BREAK_MODE_LEN = 9016;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_ADDRESS = 9017;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_ADDRESS_LEN = 9018;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_DDR_RESETN = 9019;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_BANK = 9020;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_BANK_LEN = 9021;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_ACTIVATE = 9022;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_RASN = 9023;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_CASN = 9024;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_WEN = 9025;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_CKE = 9026;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_CKE_LEN = 9027;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_CSN = 9028;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_CSN_LEN = 9029;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_ODT = 9030;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_ODT_LEN = 9031;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_DDR_CALIBRATION_TYPE = 9032;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_DDR_CALIBRATION_TYPE_LEN = 9033;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_DDR_PARITY = 9034;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_MA_B_CKE3_7 = 9035;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_LOOP_BREAK_MODE = 9036;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_6_LOOP_BREAK_MODE_LEN = 9037;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_ADDRESS = 9038;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_ADDRESS_LEN = 9039;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_DDR_RESETN = 9040;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_BANK = 9041;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_BANK_LEN = 9042;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_ACTIVATE = 9043;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_RASN = 9044;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_CASN = 9045;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_WEN = 9046;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_CKE = 9047;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_CKE_LEN = 9048;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_CSN = 9049;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_CSN_LEN = 9050;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_ODT = 9051;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_ODT_LEN = 9052;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_DDR_CALIBRATION_TYPE = 9053;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_DDR_CALIBRATION_TYPE_LEN = 9054;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_DDR_PARITY = 9055;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_MA_B_CKE3 = 9056;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_LOOP_BREAK_MODE = 9057;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_7_LOOP_BREAK_MODE_LEN = 9058;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_ADDRESS = 9059;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_ADDRESS_LEN = 9060;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_DDR_RESETN = 9061;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_BANK = 9062;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_BANK_LEN = 9063;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_ACTIVATE = 9064;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_RASN = 9065;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_CASN = 9066;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_WEN = 9067;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_CKE = 9068;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_CKE_LEN = 9069;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_CSN = 9070;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_CSN_LEN = 9071;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_ODT = 9072;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_ODT_LEN = 9073;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_DDR_CALIBRATION_TYPE = 9074;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_DDR_CALIBRATION_TYPE_LEN = 9075;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_DDR_PARITY = 9076;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_MA_B_CKE3_7 = 9077;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_LOOP_BREAK_MODE = 9078;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_8_LOOP_BREAK_MODE_LEN = 9079;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_ADDRESS = 9080;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_ADDRESS_LEN = 9081;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_DDR_RESETN = 9082;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_BANK = 9083;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_BANK_LEN = 9084;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_ACTIVATE = 9085;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_RASN = 9086;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_CASN = 9087;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_WEN = 9088;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_CKE = 9089;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_CKE_LEN = 9090;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_CSN = 9091;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_CSN_LEN = 9092;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_ODT = 9093;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_ODT_LEN = 9094;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_DDR_CALIBRATION_TYPE = 9095;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_DDR_CALIBRATION_TYPE_LEN = 9096;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_DDR_PARITY = 9097;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_MA_B_CKE3_7 = 9098;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_LOOP_BREAK_MODE = 9099;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR0_9_LOOP_BREAK_MODE_LEN = 9100;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_IDLES = 9101;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_IDLES_LEN = 9102;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_REPEAT_CMD_CNT = 9103;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_REPEAT_CMD_CNT_LEN = 9104;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_READ_OR_WRITE_DATA = 9105;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_READ_OR_WRITE_DATA_LEN = 9106;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_READ_COMPARE_REQUIRED = 9107;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_DDR_CAL_RANK = 9108;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_DDR_CAL_RANK_LEN = 9109;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_DDR_CALIBRATION_ENABLE = 9110;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_END = 9111;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_GOTO_CMD = 9112;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_0_GOTO_CMD_LEN = 9113;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_IDLES = 9114;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_IDLES_LEN = 9115;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_REPEAT_CMD_CNT = 9116;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_REPEAT_CMD_CNT_LEN = 9117;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_READ_OR_WRITE_DATA = 9118;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_READ_OR_WRITE_DATA_LEN = 9119;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_READ_COMPARE_REQUIRED = 9120;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_DDR_CAL_RANK = 9121;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_DDR_CAL_RANK_LEN = 9122;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_DDR_CALIBRATION_ENABLE = 9123;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_END = 9124;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_GOTO_CMD = 9125;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_1_GOTO_CMD_LEN = 9126;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_IDLES = 9127;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_IDLES_LEN = 9128;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_REPEAT_CMD_CNT = 9129;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN = 9130;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_READ_OR_WRITE_DATA = 9131;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN = 9132;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED = 9133;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_DDR_CAL_RANK = 9134;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_DDR_CAL_RANK_LEN = 9135;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_DDR_CALIBRATION_ENABLE = 9136;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_END = 9137;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_GOTO_CMD = 9138;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_10_GOTO_CMD_LEN = 9139;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_IDLES = 9140;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_IDLES_LEN = 9141;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_REPEAT_CMD_CNT = 9142;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN = 9143;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_READ_OR_WRITE_DATA = 9144;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN = 9145;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED = 9146;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_DDR_CAL_RANK = 9147;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_DDR_CAL_RANK_LEN = 9148;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_DDR_CALIBRATION_ENABLE = 9149;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_END = 9150;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_GOTO_CMD = 9151;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_11_GOTO_CMD_LEN = 9152;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_IDLES = 9153;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_IDLES_LEN = 9154;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_REPEAT_CMD_CNT = 9155;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN = 9156;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_READ_OR_WRITE_DATA = 9157;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN = 9158;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED = 9159;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_DDR_CAL_RANK = 9160;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_DDR_CAL_RANK_LEN = 9161;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_DDR_CALIBRATION_ENABLE = 9162;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_END = 9163;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_GOTO_CMD = 9164;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_12_GOTO_CMD_LEN = 9165;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_IDLES = 9166;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_IDLES_LEN = 9167;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_REPEAT_CMD_CNT = 9168;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN = 9169;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_READ_OR_WRITE_DATA = 9170;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN = 9171;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED = 9172;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_DDR_CAL_RANK = 9173;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_DDR_CAL_RANK_LEN = 9174;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_DDR_CALIBRATION_ENABLE = 9175;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_END = 9176;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_GOTO_CMD = 9177;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_13_GOTO_CMD_LEN = 9178;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_IDLES = 9179;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_IDLES_LEN = 9180;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_REPEAT_CMD_CNT = 9181;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN = 9182;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_READ_OR_WRITE_DATA = 9183;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN = 9184;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED = 9185;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_DDR_CAL_RANK = 9186;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_DDR_CAL_RANK_LEN = 9187;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_DDR_CALIBRATION_ENABLE = 9188;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_END = 9189;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_GOTO_CMD = 9190;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_14_GOTO_CMD_LEN = 9191;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_IDLES = 9192;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_IDLES_LEN = 9193;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_REPEAT_CMD_CNT = 9194;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN = 9195;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_READ_OR_WRITE_DATA = 9196;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN = 9197;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED = 9198;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_DDR_CAL_RANK = 9199;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_DDR_CAL_RANK_LEN = 9200;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_DDR_CALIBRATION_ENABLE = 9201;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_END = 9202;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_GOTO_CMD = 9203;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_15_GOTO_CMD_LEN = 9204;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_IDLES = 9205;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_IDLES_LEN = 9206;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_REPEAT_CMD_CNT = 9207;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN = 9208;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_READ_OR_WRITE_DATA = 9209;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN = 9210;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED = 9211;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_DDR_CAL_RANK = 9212;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_DDR_CAL_RANK_LEN = 9213;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_DDR_CALIBRATION_ENABLE = 9214;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_END = 9215;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_GOTO_CMD = 9216;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_16_GOTO_CMD_LEN = 9217;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_IDLES = 9218;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_IDLES_LEN = 9219;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_REPEAT_CMD_CNT = 9220;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN = 9221;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_READ_OR_WRITE_DATA = 9222;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN = 9223;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED = 9224;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_DDR_CAL_RANK = 9225;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_DDR_CAL_RANK_LEN = 9226;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_DDR_CALIBRATION_ENABLE = 9227;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_END = 9228;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_GOTO_CMD = 9229;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_17_GOTO_CMD_LEN = 9230;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_IDLES = 9231;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_IDLES_LEN = 9232;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_REPEAT_CMD_CNT = 9233;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN = 9234;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_READ_OR_WRITE_DATA = 9235;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN = 9236;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED = 9237;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_DDR_CAL_RANK = 9238;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_DDR_CAL_RANK_LEN = 9239;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_DDR_CALIBRATION_ENABLE = 9240;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_END = 9241;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_GOTO_CMD = 9242;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_18_GOTO_CMD_LEN = 9243;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_IDLES = 9244;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_IDLES_LEN = 9245;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_REPEAT_CMD_CNT = 9246;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN = 9247;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_READ_OR_WRITE_DATA = 9248;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN = 9249;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED = 9250;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_DDR_CAL_RANK = 9251;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_DDR_CAL_RANK_LEN = 9252;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_DDR_CALIBRATION_ENABLE = 9253;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_END = 9254;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_GOTO_CMD = 9255;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_19_GOTO_CMD_LEN = 9256;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_IDLES = 9257;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_IDLES_LEN = 9258;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_REPEAT_CMD_CNT = 9259;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_REPEAT_CMD_CNT_LEN = 9260;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_READ_OR_WRITE_DATA = 9261;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_READ_OR_WRITE_DATA_LEN = 9262;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_READ_COMPARE_REQUIRED = 9263;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_DDR_CAL_RANK = 9264;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_DDR_CAL_RANK_LEN = 9265;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_DDR_CALIBRATION_ENABLE = 9266;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_END = 9267;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_GOTO_CMD = 9268;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_2_GOTO_CMD_LEN = 9269;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_IDLES = 9270;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_IDLES_LEN = 9271;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_REPEAT_CMD_CNT = 9272;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN = 9273;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_READ_OR_WRITE_DATA = 9274;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN = 9275;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED = 9276;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_DDR_CAL_RANK = 9277;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_DDR_CAL_RANK_LEN = 9278;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_DDR_CALIBRATION_ENABLE = 9279;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_END = 9280;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_GOTO_CMD = 9281;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_20_GOTO_CMD_LEN = 9282;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_IDLES = 9283;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_IDLES_LEN = 9284;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_REPEAT_CMD_CNT = 9285;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN = 9286;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_READ_OR_WRITE_DATA = 9287;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN = 9288;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED = 9289;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_DDR_CAL_RANK = 9290;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_DDR_CAL_RANK_LEN = 9291;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_DDR_CALIBRATION_ENABLE = 9292;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_END = 9293;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_GOTO_CMD = 9294;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_21_GOTO_CMD_LEN = 9295;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_IDLES = 9296;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_IDLES_LEN = 9297;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_REPEAT_CMD_CNT = 9298;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN = 9299;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_READ_OR_WRITE_DATA = 9300;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN = 9301;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED = 9302;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_DDR_CAL_RANK = 9303;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_DDR_CAL_RANK_LEN = 9304;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_DDR_CALIBRATION_ENABLE = 9305;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_END = 9306;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_GOTO_CMD = 9307;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_22_GOTO_CMD_LEN = 9308;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_IDLES = 9309;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_IDLES_LEN = 9310;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_REPEAT_CMD_CNT = 9311;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN = 9312;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_READ_OR_WRITE_DATA = 9313;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN = 9314;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED = 9315;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_DDR_CAL_RANK = 9316;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_DDR_CAL_RANK_LEN = 9317;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_DDR_CALIBRATION_ENABLE = 9318;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_END = 9319;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_GOTO_CMD = 9320;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_23_GOTO_CMD_LEN = 9321;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_IDLES = 9322;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_IDLES_LEN = 9323;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_REPEAT_CMD_CNT = 9324;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN = 9325;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_READ_OR_WRITE_DATA = 9326;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN = 9327;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED = 9328;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_DDR_CAL_RANK = 9329;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_DDR_CAL_RANK_LEN = 9330;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_DDR_CALIBRATION_ENABLE = 9331;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_END = 9332;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_GOTO_CMD = 9333;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_24_GOTO_CMD_LEN = 9334;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_IDLES = 9335;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_IDLES_LEN = 9336;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_REPEAT_CMD_CNT = 9337;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN = 9338;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_READ_OR_WRITE_DATA = 9339;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN = 9340;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED = 9341;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_DDR_CAL_RANK = 9342;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_DDR_CAL_RANK_LEN = 9343;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_DDR_CALIBRATION_ENABLE = 9344;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_END = 9345;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_GOTO_CMD = 9346;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_25_GOTO_CMD_LEN = 9347;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_IDLES = 9348;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_IDLES_LEN = 9349;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_REPEAT_CMD_CNT = 9350;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN = 9351;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_READ_OR_WRITE_DATA = 9352;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN = 9353;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED = 9354;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_DDR_CAL_RANK = 9355;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_DDR_CAL_RANK_LEN = 9356;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_DDR_CALIBRATION_ENABLE = 9357;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_END = 9358;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_GOTO_CMD = 9359;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_26_GOTO_CMD_LEN = 9360;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_IDLES = 9361;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_IDLES_LEN = 9362;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_REPEAT_CMD_CNT = 9363;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN = 9364;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_READ_OR_WRITE_DATA = 9365;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN = 9366;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED = 9367;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_DDR_CAL_RANK = 9368;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_DDR_CAL_RANK_LEN = 9369;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_DDR_CALIBRATION_ENABLE = 9370;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_END = 9371;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_GOTO_CMD = 9372;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_27_GOTO_CMD_LEN = 9373;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_IDLES = 9374;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_IDLES_LEN = 9375;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_REPEAT_CMD_CNT = 9376;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN = 9377;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_READ_OR_WRITE_DATA = 9378;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN = 9379;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED = 9380;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_DDR_CAL_RANK = 9381;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_DDR_CAL_RANK_LEN = 9382;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_DDR_CALIBRATION_ENABLE = 9383;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_END = 9384;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_GOTO_CMD = 9385;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_28_GOTO_CMD_LEN = 9386;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_IDLES = 9387;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_IDLES_LEN = 9388;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_REPEAT_CMD_CNT = 9389;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN = 9390;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_READ_OR_WRITE_DATA = 9391;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN = 9392;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED = 9393;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_DDR_CAL_RANK = 9394;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_DDR_CAL_RANK_LEN = 9395;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_DDR_CALIBRATION_ENABLE = 9396;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_END = 9397;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_GOTO_CMD = 9398;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_29_GOTO_CMD_LEN = 9399;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_IDLES = 9400;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_IDLES_LEN = 9401;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_REPEAT_CMD_CNT = 9402;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_REPEAT_CMD_CNT_LEN = 9403;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_READ_OR_WRITE_DATA = 9404;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_READ_OR_WRITE_DATA_LEN = 9405;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_READ_COMPARE_REQUIRED = 9406;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_DDR_CAL_RANK = 9407;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_DDR_CAL_RANK_LEN = 9408;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_DDR_CALIBRATION_ENABLE = 9409;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_END = 9410;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_GOTO_CMD = 9411;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_3_GOTO_CMD_LEN = 9412;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_IDLES = 9413;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_IDLES_LEN = 9414;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_REPEAT_CMD_CNT = 9415;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN = 9416;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_READ_OR_WRITE_DATA = 9417;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN = 9418;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED = 9419;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_DDR_CAL_RANK = 9420;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_DDR_CAL_RANK_LEN = 9421;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_DDR_CALIBRATION_ENABLE = 9422;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_END = 9423;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_GOTO_CMD = 9424;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_30_GOTO_CMD_LEN = 9425;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_IDLES = 9426;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_IDLES_LEN = 9427;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_REPEAT_CMD_CNT = 9428;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN = 9429;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_READ_OR_WRITE_DATA = 9430;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN = 9431;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED = 9432;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_DDR_CAL_RANK = 9433;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_DDR_CAL_RANK_LEN = 9434;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_DDR_CALIBRATION_ENABLE = 9435;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_END = 9436;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_GOTO_CMD = 9437;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_31_GOTO_CMD_LEN = 9438;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_IDLES = 9439;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_IDLES_LEN = 9440;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_REPEAT_CMD_CNT = 9441;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_REPEAT_CMD_CNT_LEN = 9442;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_READ_OR_WRITE_DATA = 9443;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_READ_OR_WRITE_DATA_LEN = 9444;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_READ_COMPARE_REQUIRED = 9445;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_DDR_CAL_RANK = 9446;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_DDR_CAL_RANK_LEN = 9447;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_DDR_CALIBRATION_ENABLE = 9448;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_END = 9449;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_GOTO_CMD = 9450;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_4_GOTO_CMD_LEN = 9451;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_IDLES = 9452;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_IDLES_LEN = 9453;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_REPEAT_CMD_CNT = 9454;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_REPEAT_CMD_CNT_LEN = 9455;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_READ_OR_WRITE_DATA = 9456;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_READ_OR_WRITE_DATA_LEN = 9457;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_READ_COMPARE_REQUIRED = 9458;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_DDR_CAL_RANK = 9459;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_DDR_CAL_RANK_LEN = 9460;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_DDR_CALIBRATION_ENABLE = 9461;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_END = 9462;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_GOTO_CMD = 9463;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_5_GOTO_CMD_LEN = 9464;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_IDLES = 9465;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_IDLES_LEN = 9466;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_REPEAT_CMD_CNT = 9467;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_REPEAT_CMD_CNT_LEN = 9468;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_READ_OR_WRITE_DATA = 9469;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_READ_OR_WRITE_DATA_LEN = 9470;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_READ_COMPARE_REQUIRED = 9471;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_DDR_CAL_RANK = 9472;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_DDR_CAL_RANK_LEN = 9473;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_DDR_CALIBRATION_ENABLE = 9474;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_END = 9475;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_GOTO_CMD = 9476;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_6_GOTO_CMD_LEN = 9477;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_IDLES = 9478;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_IDLES_LEN = 9479;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_REPEAT_CMD_CNT = 9480;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_REPEAT_CMD_CNT_LEN = 9481;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_READ_OR_WRITE_DATA = 9482;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_READ_OR_WRITE_DATA_LEN = 9483;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_READ_COMPARE_REQUIRED = 9484;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_DDR_CAL_RANK = 9485;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_DDR_CAL_RANK_LEN = 9486;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_DDR_CALIBRATION_ENABLE = 9487;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_END = 9488;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_GOTO_CMD = 9489;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_7_GOTO_CMD_LEN = 9490;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_IDLES = 9491;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_IDLES_LEN = 9492;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_REPEAT_CMD_CNT = 9493;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_REPEAT_CMD_CNT_LEN = 9494;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_READ_OR_WRITE_DATA = 9495;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_READ_OR_WRITE_DATA_LEN = 9496;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_READ_COMPARE_REQUIRED = 9497;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_DDR_CAL_RANK = 9498;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_DDR_CAL_RANK_LEN = 9499;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_DDR_CALIBRATION_ENABLE = 9500;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_END = 9501;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_GOTO_CMD = 9502;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_8_GOTO_CMD_LEN = 9503;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_IDLES = 9504;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_IDLES_LEN = 9505;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_REPEAT_CMD_CNT = 9506;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_REPEAT_CMD_CNT_LEN = 9507;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_READ_OR_WRITE_DATA = 9508;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_READ_OR_WRITE_DATA_LEN = 9509;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_READ_COMPARE_REQUIRED = 9510;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_DDR_CAL_RANK = 9511;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_DDR_CAL_RANK_LEN = 9512;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_DDR_CALIBRATION_ENABLE = 9513;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_END = 9514;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_GOTO_CMD = 9515;
static const uint64_t IDX_CEN_MBA_CCS_INST_ARR1_9_GOTO_CMD_LEN = 9516;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_RECOVERABLE_ERROR = 9517;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_NONRECOVERABLE_ERROR = 9518;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_REFRESH_OVERRUN = 9519;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WAT__ERROR = 9520;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_RCD_PARITY_ERROR_0 = 9521;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_DDR0_CAL_TIMEOUT_ERR = 9522;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_DDR1_CAL_TIMEOUT_ERR = 9523;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_RCD_PARITY_ERROR_1 = 9524;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_MBX_TO_PAR_ERROR = 9525;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WRD_UE = 9526;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WRD_CE = 9527;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_MAINT_UE = 9528;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_MAINT_CE = 9529;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_DDR_CAL_RESET_TIMEOUT = 9530;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WRQ_DATA_CE = 9531;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WRQ_DATA_UE = 9532;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WRQ_DATA_SUE = 9533;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WRQ_RRQ_HANG_ERR = 9534;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_SM_1HOT_ERR = 9535;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_WRD_SCOM_ERROR = 9536;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_RHMR_PRIM_REACHED_MAX = 9537;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_RHMR_SEC_REACHED_MAX = 9538;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_RHMR_SEC_ALREADY_FULL = 9539;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_RESERVED_23 = 9540;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_INTERNAL_SCOM_ERROR = 9541;
static const uint64_t IDX_CEN_MBA_MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY = 9542;
static const uint64_t IDX_CEN_MBA_MBACALFIR_ACTION0_FIR = 9543;
static const uint64_t IDX_CEN_MBA_MBACALFIR_ACTION0_FIR_LEN = 9544;
static const uint64_t IDX_CEN_MBA_MBACALFIR_ACTION1_FIR = 9545;
static const uint64_t IDX_CEN_MBA_MBACALFIR_ACTION1_FIR_LEN = 9546;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_RECOVERABLE_ERROR = 9547;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_NONRECOVERABLE_ERROR = 9548;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_REFRESH_OVERRUN = 9549;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WAT__ERROR = 9550;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_RCD_PARITY_ERROR_0 = 9551;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_DDR0_CAL_TIMEOUT_ERR = 9552;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_DDR1_CAL_TIMEOUT_ERR = 9553;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_RCD_PARITY_ERROR_1 = 9554;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_MBX_TO_PAR_ERROR = 9555;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WRD_UE = 9556;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WRD_CE = 9557;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_MAINT_UE = 9558;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_MAINT_CE = 9559;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_DDR_CAL_RESET_TIMEOUT = 9560;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WRQ_DATA_CE = 9561;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WRQ_DATA_UE = 9562;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WRQ_DATA_SUE = 9563;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WRQ_RRQ_HANG_ERR = 9564;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_SM_1HOT_ERR = 9565;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_WRD_SCOM_ERROR = 9566;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_RHMR_PRIM_REACHED_MAX = 9567;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_RHMR_SEC_REACHED_MAX = 9568;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_RHMR_SEC_ALREADY_FULL = 9569;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_RESERVED_23 = 9570;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR = 9571;
static const uint64_t IDX_CEN_MBA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR_COPY = 9572;
static const uint64_t IDX_CEN_MBA_MBASIRACT0_ACTION_0 = 9573;
static const uint64_t IDX_CEN_MBA_MBASIRACT0_ACTION_0_LEN = 9574;
static const uint64_t IDX_CEN_MBA_MBASIRACT1_ACTION_1 = 9575;
static const uint64_t IDX_CEN_MBA_MBASIRACT1_ACTION_1_LEN = 9576;
static const uint64_t IDX_CEN_MBA_MBASIRMASK_SIR_MASK = 9577;
static const uint64_t IDX_CEN_MBA_MBASIRMASK_SIR_MASK_LEN = 9578;
static const uint64_t IDX_CEN_MBA_MBASIRQ_INVALID_CAL0Q_ACCESS = 9579;
static const uint64_t IDX_CEN_MBA_MBASIRQ_INVALID_CAL1Q_ACCESS = 9580;
static const uint64_t IDX_CEN_MBA_MBASIRQ_INVALID_CAL2Q_ACCESS = 9581;
static const uint64_t IDX_CEN_MBA_MBASIRQ_INVALID_CAL3Q_ACCESS = 9582;
static const uint64_t IDX_CEN_MBA_MBASIRQ_INVALID_DDR_CONFIG_REG_ACCESS = 9583;
static const uint64_t IDX_CEN_MBA_MBASIRQ_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS = 9584;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_INTERVAL_TMR0_ENABLE = 9585;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_TIME_BASE_TMR0 = 9586;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_TIME_BASE_TMR0_LEN = 9587;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_INTERVAL_COUNTER_TMR0 = 9588;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_INTERVAL_COUNTER_TMR0_LEN = 9589;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL1_ENABLE = 9590;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE = 9591;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE_LEN = 9592;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL1_DDR_DONE = 9593;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL2_ENABLE = 9594;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE = 9595;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE_LEN = 9596;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL2_DDR_DONE = 9597;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL3_ENABLE = 9598;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE = 9599;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE_LEN = 9600;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_CAL3_DDR_DONE = 9601;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_Z_SYNC = 9602;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_Z_SYNC_LEN = 9603;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR = 9604;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 9605;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 9606;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 9607;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_DDR_RESET_ENABLE = 9608;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_TMR0_SINGLE_RANK = 9609;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_INJECT_CAL0_PAR_ERROR = 9610;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_INJECT_1HOT_SM_ERROR = 9611;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_SINGLE_PORT_MODE = 9612;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_CFG_CAL_SINGLE_PORT_MODE_LEN = 9613;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_RESERVED_56_63 = 9614;
static const uint64_t IDX_CEN_MBA_MBA_CAL0Q_CAL0Q_RESERVED_56_63_LEN = 9615;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE = 9616;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_TIME_BASE_TMR1 = 9617;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_TIME_BASE_TMR1_LEN = 9618;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_INTERVAL_COUNTER_TMR1 = 9619;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_INTERVAL_COUNTER_TMR1_LEN = 9620;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL1_ENABLE = 9621;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE = 9622;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE_LEN = 9623;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL1_DDR_DONE = 9624;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL2_ENABLE = 9625;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE = 9626;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE_LEN = 9627;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL2_DDR_DONE = 9628;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL3_ENABLE = 9629;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE = 9630;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE_LEN = 9631;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_CAL3_DDR_DONE = 9632;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_Z_SYNC = 9633;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_Z_SYNC_LEN = 9634;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_CFG_CAL_TMR1_SINGLE_RANK = 9635;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_RESERVED_40_63 = 9636;
static const uint64_t IDX_CEN_MBA_MBA_CAL1Q_CAL1Q_RESERVED_40_63_LEN = 9637;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_INTERVAL_TMR2_ENABLE = 9638;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_TIME_BASE_TMR2 = 9639;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_TIME_BASE_TMR2_LEN = 9640;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_INTERVAL_COUNTER_TMR2 = 9641;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_INTERVAL_COUNTER_TMR2_LEN = 9642;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL1_ENABLE = 9643;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE = 9644;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE_LEN = 9645;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL1_DDR_DONE = 9646;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL2_ENABLE = 9647;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE = 9648;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE_LEN = 9649;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL2_DDR_DONE = 9650;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL3_ENABLE = 9651;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE = 9652;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE_LEN = 9653;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_CAL3_DDR_DONE = 9654;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_Z_SYNC = 9655;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_Z_SYNC_LEN = 9656;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_SINGLE_RANK = 9657;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 9658;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_RCD_ERROR_START_DLY = 9659;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_RCD_ERROR_START_DLY_LEN = 9660;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_RESERVED_57_63 = 9661;
static const uint64_t IDX_CEN_MBA_MBA_CAL2Q_CAL2Q_RESERVED_57_63_LEN = 9662;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_INTERNAL_ZQ_TB = 9663;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_INTERNAL_ZQ_TB_LEN = 9664;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_INTERNAL_ZQ_LENGTH = 9665;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_INTERNAL_ZQ_LENGTH_LEN = 9666;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_EXTERNAL_ZQ_TB = 9667;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_EXTERNAL_ZQ_TB_LEN = 9668;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH = 9669;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH_LEN = 9670;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_RDCLK_SYSCLK_TB = 9671;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_RDCLK_SYSCLK_TB_LEN = 9672;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH = 9673;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH_LEN = 9674;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_DQS_ALIGNMENT_TB = 9675;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_DQS_ALIGNMENT_TB_LEN = 9676;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH = 9677;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH_LEN = 9678;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_MPR_READEYE_TB = 9679;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_MPR_READEYE_TB_LEN = 9680;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_MPR_READEYE_LENGTH = 9681;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_MPR_READEYE_LENGTH_LEN = 9682;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_ALL_PERIODIC_TB = 9683;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_ALL_PERIODIC_TB_LEN = 9684;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_ALL_PERIODIC_LENGTH = 9685;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN = 9686;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_RESERVED_60_63 = 9687;
static const uint64_t IDX_CEN_MBA_MBA_CAL3Q_CAL3Q_RESERVED_60_63_LEN = 9688;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RODT_START_DLY = 9689;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RODT_START_DLY_LEN = 9690;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RODT_END_DLY = 9691;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RODT_END_DLY_LEN = 9692;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WODT_START_DLY = 9693;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WODT_START_DLY_LEN = 9694;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WODT_END_DLY = 9695;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WODT_END_DLY_LEN = 9696;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WRDONE_DLY = 9697;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WRDONE_DLY_LEN = 9698;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WRDATA_DLY = 9699;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WRDATA_DLY_LEN = 9700;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RDTAG_DLY = 9701;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RDTAG_DLY_LEN = 9702;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RDTAG_MBX_CYCLE = 9703;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RODT_BC4_END_DLY = 9704;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RODT_BC4_END_DLY_LEN = 9705;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WODT_BC4_END_DLY = 9706;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_WODT_BC4_END_DLY_LEN = 9707;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_SYNC_RDTAG_ENABLE = 9708;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_GOLDEN_DELAY_MODE = 9709;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_GOLDEN_DELAY_MODE_LEN = 9710;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_CFG_RESET_MISR_ON_REFR_SYNC_EN = 9711;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_RESERVED_59_63 = 9712;
static const uint64_t IDX_CEN_MBA_MBA_DSM0Q_DSM0Q_RESERVED_59_63_LEN = 9713;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RDCMD_PAR = 9714;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RDCMD_PAR_RC = 9715;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RDCMD_PAR_RD1 = 9716;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RDCMD_PAR_RC_RD1 = 9717;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_WRCMD_PAR = 9718;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_WRCMD_PAR_RC = 9719;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_WRD_IDX_PAR = 9720;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RHMR_PRIM_PE = 9721;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RHMR_SEC_PE = 9722;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RHMR_LRU_ERROR = 9723;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_WRQ_HANG = 9724;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RRQ_HANG = 9725;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_DSM_PE = 9726;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_TMR_PE = 9727;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RRQ_PE = 9728;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_WRQ_PE = 9729;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_FARB_PE = 9730;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_PC_PE = 9731;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL0_PE = 9732;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL1_PE = 9733;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL2_PE = 9734;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL3_PE = 9735;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_DDR_IF_SM_1HOT = 9736;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL_SM_1HOT = 9737;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RANK_SM_1HOT = 9738;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_PC_CAL_REFFSM_1HOT = 9739;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_PC_CAL_PCFSM_1HOT = 9740;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_FARB_CAL_RECVFSM_1HOT = 9741;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RESERVED_CERR_28 = 9742;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RESERVED_CERR_29 = 9743;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RESERVED_CERR_30 = 9744;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RESERVED_CERR_31 = 9745;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RESERVED_CERR_32 = 9746;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_SIR_CERR = 9747;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RDCMD_RDCHECK = 9748;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_WRD_RDCHECK = 9749;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL0_INVALID_ACCESS = 9750;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL1_INVALID_ACCESS = 9751;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL2_INVALID_ACCESS = 9752;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_CAL3_INVALID_ACCESS = 9753;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_DDR_INVALID_ACCESS = 9754;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RESERVED_CERR_41 = 9755;
static const uint64_t IDX_CEN_MBA_MBA_ERR_REPORTQ_ERR_REPORTQ_RESERVED_CERR_42 = 9756;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_MISR_BLOCK = 9757;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_MISR_BLOCK_LEN = 9758;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_MISR_FEEDBACK_ENABLE = 9759;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_RESERVED_17_23 = 9760;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_RESERVED_17_23_LEN = 9761;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_MAX_READS_IN_A_ROW = 9762;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN = 9763;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_MAX_WRITES_IN_A_ROW = 9764;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN = 9765;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_PARITY_AFTER_CMD = 9766;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_INJECT_PARITY_ERR_RAS0 = 9767;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_INJECT_PARITY_ERR_CAS0 = 9768;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_INJECT_PARITY_ERR_RAS1 = 9769;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_INJECT_PARITY_ERR_CAS1 = 9770;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_PARITY_DETECT_TIME = 9771;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_PARITY_DETECT_TIME_LEN = 9772;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_RCD_PROTECTION_TIME = 9773;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN = 9774;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_DISABLE_RCD_RECOVERY = 9775;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_OE_ALWAYS_ON = 9776;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_FLIP_PORT1_ADDR = 9777;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_DISABLE_REFRESH_DURING_NOISE_WDW = 9778;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_RESERVED_58 = 9779;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT = 9780;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_IGNORE_RCD_PARITY_ERR = 9781;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_CFG_ENABLE_RCD_RW_RETRY = 9782;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_RESERVED_62_63 = 9783;
static const uint64_t IDX_CEN_MBA_MBA_FARB0Q_FARB0Q_RESERVED_62_63_LEN = 9784;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S0_CS = 9785;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S0_CS_LEN = 9786;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S1_CS = 9787;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S1_CS_LEN = 9788;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S2_CS = 9789;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S2_CS_LEN = 9790;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S3_CS = 9791;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S3_CS_LEN = 9792;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S4_CS = 9793;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S4_CS_LEN = 9794;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S5_CS = 9795;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S5_CS_LEN = 9796;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S6_CS = 9797;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S6_CS_LEN = 9798;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S7_CS = 9799;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_M0S7_CS_LEN = 9800;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_CS_S0_MASK = 9801;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_CS_S0_MASK_LEN = 9802;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_S0_DIS_SMDR = 9803;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS = 9804;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_S0_RSV0 = 9805;
static const uint64_t IDX_CEN_MBA_MBA_FARB1Q_FARB1Q_CFG_S0_RSV0_LEN = 9806;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S0_CS = 9807;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S0_CS_LEN = 9808;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S1_CS = 9809;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S1_CS_LEN = 9810;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S2_CS = 9811;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S2_CS_LEN = 9812;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S3_CS = 9813;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S3_CS_LEN = 9814;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S4_CS = 9815;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S4_CS_LEN = 9816;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S5_CS = 9817;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S5_CS_LEN = 9818;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S6_CS = 9819;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S6_CS_LEN = 9820;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S7_CS = 9821;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_M1S7_CS_LEN = 9822;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_S0_RSV1 = 9823;
static const uint64_t IDX_CEN_MBA_MBA_FARB2Q_FARB2Q_CFG_S0_RSV1_LEN = 9824;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_N_PER = 9825;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_N_PER_LEN = 9826;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_N_PER_CHIP = 9827;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_N_PER_CHIP_LEN = 9828;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_M = 9829;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_M_LEN = 9830;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_RAS_WEIGHT = 9831;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_RAS_WEIGHT_LEN = 9832;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_CAS_WEIGHT = 9833;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_CAS_WEIGHT_LEN = 9834;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_PER_SLOT_ENABLED = 9835;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_COUNT_OTHER_DIS = 9836;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC = 9837;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_RESERVED_54_63 = 9838;
static const uint64_t IDX_CEN_MBA_MBA_FARB3Q_FARB3Q_RESERVED_54_63_LEN = 9839;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_EN = 9840;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_EN_LEN = 9841;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_SECONDARY_EN = 9842;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_HASH_SWIZZLE_EN = 9843;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_RESERVED_4_9 = 9844;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_RESERVED_4_9_LEN = 9845;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_DECREMENT_WEIGHT = 9846;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_DECREMENT_WEIGHT_LEN = 9847;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_PRIMARY_DECR_INTV = 9848;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_PRIMARY_DECR_INTV_LEN = 9849;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_SECONDARY_DECR_INTV = 9850;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_SECONDARY_DECR_INTV_LEN = 9851;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_CFG_RHMR_SIM_EN = 9852;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_EMERGENCY_N = 9853;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_EMERGENCY_N_LEN = 9854;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_EMERGENCY_M = 9855;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_EMERGENCY_M_LEN = 9856;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_RESERVED_56_63 = 9857;
static const uint64_t IDX_CEN_MBA_MBA_FARB4Q_FARB4Q_RESERVED_56_63_LEN = 9858;
static const uint64_t IDX_CEN_MBA_MBA_PMU0Q_PMU0Q_READ_COUNT = 9859;
static const uint64_t IDX_CEN_MBA_MBA_PMU0Q_PMU0Q_READ_COUNT_LEN = 9860;
static const uint64_t IDX_CEN_MBA_MBA_PMU0Q_PMU0Q_WRITE_COUNT = 9861;
static const uint64_t IDX_CEN_MBA_MBA_PMU0Q_PMU0Q_WRITE_COUNT_LEN = 9862;
static const uint64_t IDX_CEN_MBA_MBA_PMU1Q_PMU1Q_ACTIVATE_COUNT = 9863;
static const uint64_t IDX_CEN_MBA_MBA_PMU1Q_PMU1Q_ACTIVATE_COUNT_LEN = 9864;
static const uint64_t IDX_CEN_MBA_MBA_PMU1Q_PMU1Q_PU_COUNTS = 9865;
static const uint64_t IDX_CEN_MBA_MBA_PMU1Q_PMU1Q_PU_COUNTS_LEN = 9866;
static const uint64_t IDX_CEN_MBA_MBA_PMU2Q_PMU2Q_FRAME_COUNT = 9867;
static const uint64_t IDX_CEN_MBA_MBA_PMU2Q_PMU2Q_FRAME_COUNT_LEN = 9868;
static const uint64_t IDX_CEN_MBA_MBA_PMU3Q_PMU3Q_LOW_IDLE_THRESHOLD = 9869;
static const uint64_t IDX_CEN_MBA_MBA_PMU3Q_PMU3Q_LOW_IDLE_THRESHOLD_LEN = 9870;
static const uint64_t IDX_CEN_MBA_MBA_PMU3Q_PMU3Q_MED_IDLE_THRESHOLD = 9871;
static const uint64_t IDX_CEN_MBA_MBA_PMU3Q_PMU3Q_MED_IDLE_THRESHOLD_LEN = 9872;
static const uint64_t IDX_CEN_MBA_MBA_PMU3Q_PMU3Q_HIGH_IDLE_THRESHOLD = 9873;
static const uint64_t IDX_CEN_MBA_MBA_PMU3Q_PMU3Q_HIGH_IDLE_THRESHOLD_LEN = 9874;
static const uint64_t IDX_CEN_MBA_MBA_PMU4Q_PMU4Q_BASE_IDLE_COUNT = 9875;
static const uint64_t IDX_CEN_MBA_MBA_PMU4Q_PMU4Q_BASE_IDLE_COUNT_LEN = 9876;
static const uint64_t IDX_CEN_MBA_MBA_PMU4Q_PMU4Q_LOW_IDLE_COUNT = 9877;
static const uint64_t IDX_CEN_MBA_MBA_PMU4Q_PMU4Q_LOW_IDLE_COUNT_LEN = 9878;
static const uint64_t IDX_CEN_MBA_MBA_PMU5Q_PMU5Q_MED_IDLE_COUNT = 9879;
static const uint64_t IDX_CEN_MBA_MBA_PMU5Q_PMU5Q_MED_IDLE_COUNT_LEN = 9880;
static const uint64_t IDX_CEN_MBA_MBA_PMU5Q_PMU5Q_HIGH_IDLE_COUNT = 9881;
static const uint64_t IDX_CEN_MBA_MBA_PMU5Q_PMU5Q_HIGH_IDLE_COUNT_LEN = 9882;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_TOTAL_GAP_COUNTS = 9883;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_TOTAL_GAP_COUNTS_LEN = 9884;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_SPECIFIC_GAP_COUNT = 9885;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_SPECIFIC_GAP_COUNT_LEN = 9886;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_GAP_LENGTH_ADDER = 9887;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_GAP_LENGTH_ADDER_LEN = 9888;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_SPECIFIC_GAP_CONDITION = 9889;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_SPECIFIC_GAP_CONDITION_LEN = 9890;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_CMD_TO_COUNT = 9891;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_CMD_TO_COUNT_LEN = 9892;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_COMMAND_PATTERN_TO_COUNT = 9893;
static const uint64_t IDX_CEN_MBA_MBA_PMU6Q_PMU6Q_COMMAND_PATTERN_TO_COUNT_LEN = 9894;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RRQ_SKIP_LIMIT = 9895;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN = 9896;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RRQ_REORDER_DEPTH = 9897;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RRQ_REORDER_DEPTH_LEN = 9898;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_DISABLE_RD_PG_MODE = 9899;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_DISABLE_FAST_PATH = 9900;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR0 = 9901;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR0_LEN = 9902;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR1 = 9903;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR1_LEN = 9904;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR2 = 9905;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR2_LEN = 9906;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR3 = 9907;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RD_IDLE_ALLOW_WR3_LEN = 9908;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_CFG_RRQ_OPP_PAGE_MODE_EN = 9909;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_RESERVED_58_63 = 9910;
static const uint64_t IDX_CEN_MBA_MBA_RRQ0Q_RRQ0Q_RESERVED_58_63_LEN = 9911;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RRSMSR_DLY = 9912;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RRSMSR_DLY_LEN = 9913;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RRSMDR_DLY = 9914;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RRSMDR_DLY_LEN = 9915;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RRDM_DLY = 9916;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RRDM_DLY_LEN = 9917;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RWSMSR_DLY = 9918;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RWSMSR_DLY_LEN = 9919;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RWSMDR_DLY = 9920;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RWSMDR_DLY_LEN = 9921;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RWDM_DLY = 9922;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RWDM_DLY_LEN = 9923;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WRSMSR_DLY = 9924;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WRSMSR_DLY_LEN = 9925;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WRSMDR_DLY = 9926;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WRSMDR_DLY_LEN = 9927;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WRDM_DLY = 9928;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WRDM_DLY_LEN = 9929;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWSMSR_DLY = 9930;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWSMSR_DLY_LEN = 9931;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWSMDR_DLY = 9932;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWSMDR_DLY_LEN = 9933;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWDM_DLY = 9934;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWDM_DLY_LEN = 9935;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RROP_DLY = 9936;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_RROP_DLY_LEN = 9937;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWOP_DLY = 9938;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_WWOP_DLY_LEN = 9939;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_TRRD = 9940;
static const uint64_t IDX_CEN_MBA_MBA_TMR0Q_TMR0Q_TRRD_LEN = 9941;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_TRAP = 9942;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_TRAP_LEN = 9943;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_TWAP = 9944;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_TWAP_LEN = 9945;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_TFAW = 9946;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_TFAW_LEN = 9947;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RRSBG_DLY = 9948;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RRSBG_DLY_LEN = 9949;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_WRSBG_DLY = 9950;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_WRSBG_DLY_LEN = 9951;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_DDR4_CL_INTL_DIS = 9952;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_ACTREF = 9953;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_CFG_ACTREF_LEN = 9954;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RESERVED_35_47 = 9955;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RESERVED_35_47_LEN = 9956;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RWSMSR_MSB = 9957;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RWSMDR_MSB = 9958;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RWDM_MSB = 9959;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RESERVED_51_63 = 9960;
static const uint64_t IDX_CEN_MBA_MBA_TMR1Q_TMR1Q_RESERVED_51_63_LEN = 9961;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRITE_HW_MARK = 9962;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRITE_HW_MARK_LEN = 9963;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_FIFO_MODE = 9964;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_DISABLE_WR_PG_MODE = 9965;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY = 9966;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN = 9967;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK = 9968;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR = 9969;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 9970;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 9971;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_RRQ_IDLE_LOW_WATERMARK = 9972;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_RRQ_IDLE_LOW_WATERMARK_LEN = 9973;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_SKIP_LIMIT = 9974;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN = 9975;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_CLN_HP_ENABLE = 9976;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_HANG_THRESHOLD = 9977;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_WRQ_HANG_THRESHOLD_LEN = 9978;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_RRQ_HANG_THRESHOLD = 9979;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_CFG_RRQ_HANG_THRESHOLD_LEN = 9980;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_RESERVED_61_63 = 9981;
static const uint64_t IDX_CEN_MBA_MBA_WRQ0Q_WRQ0Q_RESERVED_61_63_LEN = 9982;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_ENABLE = 9983;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 9984;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 9985;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_RESERVED_3 = 9986;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD = 9987;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 9988;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_INTERVAL = 9989;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN = 9990;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL = 9991;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN = 9992;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_TRFC = 9993;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_TRFC_LEN = 9994;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFR_TSV_STACK = 9995;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFR_TSV_STACK_LEN = 9996;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL = 9997;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN = 9998;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF = 9999;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_RESERVED_62_63 = 10000;
static const uint64_t IDX_CEN_MBA_MBAREF0Q_RESERVED_62_63_LEN = 10001;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK0_PRIM_CKE = 10002;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK0_PRIM_CKE_LEN = 10003;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK1_PRIM_CKE = 10004;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK1_PRIM_CKE_LEN = 10005;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK2_PRIM_CKE = 10006;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK2_PRIM_CKE_LEN = 10007;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK3_PRIM_CKE = 10008;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK3_PRIM_CKE_LEN = 10009;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK4_PRIM_CKE = 10010;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK4_PRIM_CKE_LEN = 10011;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK5_PRIM_CKE = 10012;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK5_PRIM_CKE_LEN = 10013;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK6_PRIM_CKE = 10014;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK6_PRIM_CKE_LEN = 10015;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK7_PRIM_CKE = 10016;
static const uint64_t IDX_CEN_MBA_MBAREF1Q_CFG_MRNK7_PRIM_CKE_LEN = 10017;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_LP_DYN_WAIT_ENABLE = 10018;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_HP_RANK_BIAS_ENABLE = 10019;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 10020;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_RESERVED_3 = 10021;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_PUP_THRESHOLD = 10022;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_PUP_THRESHOLD_LEN = 10023;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ1_COEF = 10024;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ1_COEF_LEN = 10025;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ2_COEF = 10026;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ2_COEF_LEN = 10027;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ3_COEF = 10028;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ3_COEF_LEN = 10029;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ4_COEF = 10030;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ4_COEF_LEN = 10031;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ5_COEF = 10032;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ5_COEF_LEN = 10033;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ6_COEF = 10034;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REFRESH_BLQ_EQ6_COEF_LEN = 10035;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_RRQ_REF_HINT_DLY = 10036;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_RRQ_REF_HINT_DLY_LEN = 10037;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_ASSERT_REFRESH_BLOCK_DLY = 10038;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_ASSERT_REFRESH_BLOCK_DLY_LEN = 10039;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_FORCE_HP_REF_REQ_DLY = 10040;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_FORCE_HP_REF_REQ_DLY_LEN = 10041;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY = 10042;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN = 10043;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_MODE_HP_SUB_CNT = 10044;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_MODE_HP_SUB_CNT_LEN = 10045;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_MODE_LP_SUB_CNT = 10046;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_MODE_LP_SUB_CNT_LEN = 10047;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_RESERVED_54_63 = 10048;
static const uint64_t IDX_CEN_MBA_MBAREFAQ_RESERVED_54_63_LEN = 10049;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_LP2_ENTRY_REQ = 10050;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_LP2_STATE = 10051;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE = 10052;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_MIN_MAX_DOMAINS = 10053;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN = 10054;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PUP_AVAIL = 10055;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PUP_AVAIL_LEN = 10056;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PDN_PUP = 10057;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PDN_PUP_LEN = 10058;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PUP_PDN = 10059;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PUP_PDN_LEN = 10060;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_RESERVED_21 = 10061;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 10062;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME = 10063;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 10064;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 10065;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 10066;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 10067;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_CFG_FORCE_SPARE_PUP = 10068;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_MODE_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 10069;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_MODE_EMER_MIN_MAX_DOMAIN = 10070;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_MODE_EMER_MIN_MAX_DOMAIN_LEN = 10071;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_RESERVED_47_63 = 10072;
static const uint64_t IDX_CEN_MBA_MBARPC0Q_RESERVED_47_63_LEN = 10073;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK0_RD_CKE = 10074;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK0_RD_CKE_LEN = 10075;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK1_RD_CKE = 10076;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK1_RD_CKE_LEN = 10077;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK2_RD_CKE = 10078;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK2_RD_CKE_LEN = 10079;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK3_RD_CKE = 10080;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK3_RD_CKE_LEN = 10081;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK4_RD_CKE = 10082;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK4_RD_CKE_LEN = 10083;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK5_RD_CKE = 10084;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK5_RD_CKE_LEN = 10085;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK6_RD_CKE = 10086;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK6_RD_CKE_LEN = 10087;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK7_RD_CKE = 10088;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK7_RD_CKE_LEN = 10089;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK0_WR_CKE = 10090;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK0_WR_CKE_LEN = 10091;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK1_WR_CKE = 10092;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK1_WR_CKE_LEN = 10093;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK2_WR_CKE = 10094;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK2_WR_CKE_LEN = 10095;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK3_WR_CKE = 10096;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK3_WR_CKE_LEN = 10097;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK4_WR_CKE = 10098;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK4_WR_CKE_LEN = 10099;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK5_WR_CKE = 10100;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK5_WR_CKE_LEN = 10101;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK6_WR_CKE = 10102;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK6_WR_CKE_LEN = 10103;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK7_WR_CKE = 10104;
static const uint64_t IDX_CEN_MBA_MBARPC1Q_CFG_MRNK7_WR_CKE_LEN = 10105;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_ISLE_XSTOP_MASK_B = 10106;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_PCB_XSTOP_MASK_B = 10107;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_CLKSTP_EN = 10108;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_EDRAM_XSTOP_MASK_B = 10109;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_PLL_XSTOP_MASK_B = 10110;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_LOCAL_XSTOP_MASK_B = 10111;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_DISABLE_PCB_ITR = 10112;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_USE_FOR_SCAN = 10113;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_KEEP_EDRAM_ON_XSTOP = 10114;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_TRIGGER_OPCG_ON_XSTOP = 10115;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_SEL_EXT_OPCG_TRIGGER = 10116;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_LISTEN_TO_PULSE = 10117;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_CLK_START_ENABLE = 10118;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_CLK_STOP_ENABLE = 10119;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_CHIP_PROTECTION_ENABLE = 10120;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_SPARE15 = 10121;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_SPARE16 = 10122;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_SPARE17 = 10123;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_SPARE18 = 10124;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_SPARE19 = 10125;
static const uint64_t IDX_CEN_TCN_SYNC_CONFIG_SPARE20 = 10126;
static const uint64_t IDX_CEN_TCN_PHASE_SHADOW_COUNT_Q = 10127;
static const uint64_t IDX_CEN_TCN_PHASE_SHADOW_COUNT_Q_LEN = 10128;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_RUNN_MODE = 10129;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_GO = 10130;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_RUN_SCAN0 = 10131;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_SCAN0_MODE = 10132;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_SCAN_RATIO = 10133;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_SCAN_RATIO_LEN = 10134;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_INOP_FORCE_SG = 10135;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_INOP_ALIGN = 10136;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_INOP_ALIGN_LEN = 10137;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_INOP_WAIT = 10138;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_INOP_WAIT_LEN = 10139;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_SNOP_ALIGN = 10140;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_SNOP_ALIGN_LEN = 10141;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_SNOP_WAIT = 10142;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_SNOP_WAIT_LEN = 10143;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_ENOP_ALIGN = 10144;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_ENOP_ALIGN_LEN = 10145;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_ENOP_WAIT = 10146;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_ENOP_WAIT_LEN = 10147;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_ENOP_FORCE_SG = 10148;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_LOOP_COUNT = 10149;
static const uint64_t IDX_CEN_TCN_OPCG_REG0_LOOP_COUNT_LEN = 10150;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_COUNT = 10151;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_COUNT_LEN = 10152;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ01_01F = 10153;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ01_01F_LEN = 10154;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ02_02F = 10155;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ02_02F_LEN = 10156;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ03_03F = 10157;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ03_03F_LEN = 10158;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ04_04F = 10159;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ04_04F_LEN = 10160;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ05_05F = 10161;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ05_05F_LEN = 10162;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ06_06F = 10163;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ06_06F_LEN = 10164;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ07_07F = 10165;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ07_07F_LEN = 10166;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ08_08F = 10167;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ08_08F_LEN = 10168;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ09_01FBY2 = 10169;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ09_01FBY2_LEN = 10170;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ10_02FBY2 = 10171;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ10_02FBY2_LEN = 10172;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ11_03FBY2 = 10173;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ11_03FBY2_LEN = 10174;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ12_04FBY2 = 10175;
static const uint64_t IDX_CEN_TCN_OPCG_REG1_FUNC_CAPT_SEQ12_04FBY2_LEN = 10176;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_SCAN_COUNT = 10177;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_SCAN_COUNT_LEN = 10178;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_MISR_A_VAL = 10179;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_MISR_A_VAL_LEN = 10180;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_MISR_B_VAL = 10181;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_MISR_B_VAL_LEN = 10182;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_MISR_INIT_WAIT = 10183;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_MISR_INIT_WAIT_LEN = 10184;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_SUPPRESS_EVEN_CLK = 10185;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_PAD_VALUE = 10186;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_PAD_VALUE_LEN = 10187;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_USE_F_AND_FDIV2 = 10188;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_USE_ARY_CLK_DURING_FILL = 10189;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_SG_HIGH_DURING_FILL = 10190;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_RTIM_THOLD_FORCE = 10191;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_LBIST_SKITTER_CTL = 10192;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_MISR_MODE = 10193;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_INFINITE_MODE = 10194;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_NSL_FILL_COUNT = 10195;
static const uint64_t IDX_CEN_TCN_OPCG_REG2_NSL_FILL_COUNT_LEN = 10196;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_GO2 = 10197;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_RUN_ON_UPDATE_DR = 10198;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_RUN_ON_CAPTURE_DR = 10199;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_ALIGN_SOURCE_SELECT = 10200;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_ALIGN_SOURCE_SELECT_LEN = 10201;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_WEIGHTING = 10202;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_WEIGHTING_LEN = 10203;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_VALUE = 10204;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_VALUE_LEN = 10205;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_EXTEND_INOPW_ENOPW = 10206;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_EXTEND_SNOPW = 10207;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_FORCE_SG_HIGH_DURING_SNOP = 10208;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_CHKSW = 10209;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_CHKSW_LEN = 10210;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_A_VAL = 10211;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_A_VAL_LEN = 10212;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_B_VAL = 10213;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_B_VAL_LEN = 10214;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_PRPG_MODE = 10215;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_SCAN_CLK_USE_EVEN = 10216;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_SPARE3 = 10217;
static const uint64_t IDX_CEN_TCN_OPCG_REG3_SPARE3_LEN = 10218;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_CMD = 10219;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_CMD_LEN = 10220;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_PERV = 10221;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_FASTUNIT0 = 10222;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_FASTUNIT1 = 10223;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_UNIT2 = 10224;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_UNIT3 = 10225;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_UNIT4 = 10226;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_UNIT5 = 10227;
static const uint64_t IDX_CEN_TCN_CLK_REGION_CLOCK_PLL = 10228;
static const uint64_t IDX_CEN_TCN_CLK_REGION_SEL_THOLD_SL = 10229;
static const uint64_t IDX_CEN_TCN_CLK_REGION_SEL_THOLD_NSL = 10230;
static const uint64_t IDX_CEN_TCN_CLK_REGION_SEL_THOLD_ARY = 10231;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_VITL = 10232;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_PERV = 10233;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_FASTUNIT0 = 10234;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_FASTUNIT1 = 10235;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_UNIT2 = 10236;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_UNIT3 = 10237;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_UNIT4 = 10238;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_UNIT5 = 10239;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CLK_PLL = 10240;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_FUNC = 10241;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CFG = 10242;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CCFG_GPTR = 10243;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_REGF = 10244;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_LBIST = 10245;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_ABIST = 10246;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_REPR = 10247;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_TIME = 10248;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_BNDY_FARY = 10249;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_FARR = 10250;
static const uint64_t IDX_CEN_TCN_SCANSELQ_SCANSEL_CMSK = 10251;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_PERV_FUNC_SL = 10252;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_PERV_FUNC_NSL = 10253;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_PERV_ARY_NSL = 10254;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT0_ODD_FUNC_SL = 10255;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT0_EVEN_FUNC_SL = 10256;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT0_ODD_FUNC_NSL = 10257;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT0_EVEN_FUNC_NSL = 10258;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT0_ODD_ARY_NSL = 10259;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT0_EVEN_ARY_NSL = 10260;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT1_ODD_FUNC_SL = 10261;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT1_EVEN_FUNC_SL = 10262;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT1_ODD_FUNC_NSL = 10263;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT1_EVEN_FUNC_NSL = 10264;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT1_ODD_ARY_NSL = 10265;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_FASTUNIT1_EVEN_ARY_NSL = 10266;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT2_FUNC_SL = 10267;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT2_FUNC_NSL = 10268;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT2_ARY_NSL = 10269;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT3_FUNC_SL = 10270;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT3_FUNC_NSL = 10271;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT3_ARY_NSL = 10272;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT4_FUNC_SL = 10273;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT4_FUNC_NSL = 10274;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT4_ARY_NSL = 10275;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT5_FUNC_SL = 10276;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT5_FUNC_NSL = 10277;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_UNIT5_ARY_NSL = 10278;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_PLL_FUNC_SL = 10279;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_PLL_FUNC_NSL = 10280;
static const uint64_t IDX_CEN_TCN_CLOCK_STAT_STATUS_PLL_ARY_NSL = 10281;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED = 10282;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_READ_NOT_ALLOWED = 10283;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_PARITY_ERR_ON_CMD = 10284;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_ADDRESS_NOT_VALID = 10285;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_PARITY_ADDR_ERR = 10286;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_PARITY_DATA_ERR = 10287;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID = 10288;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_PARITY_SPCIF_ERR = 10289;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PCB_WRITE_AND_OPCG = 10290;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_CLOCK_CMD_CONFLICT = 10291;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_SCAN_COLLISION = 10292;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_OPCG_TRIGGER = 10293;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_OPCG_PARITY = 10294;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_PHASE_CNT_CORRUPTED = 10295;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_CC_PAR_ERR = 10296;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_CC_PAR_ERR_LEN = 10297;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_GPIO_PAR_ERR = 10298;
static const uint64_t IDX_CEN_TCN_ERROR_STATUS_SECURITY_VIOLATION = 10299;
static const uint64_t IDX_CEN_TCN_CC_PROTECT_MODE_REG_READ_ENABLE = 10300;
static const uint64_t IDX_CEN_TCN_CC_PROTECT_MODE_REG_WRITE_ENABLE = 10301;
static const uint64_t IDX_CEN_TCN_CC_ATOMIC_LOCK_REG_ENABLE = 10302;
static const uint64_t IDX_CEN_TCN_CC_ATOMIC_LOCK_REG_ID = 10303;
static const uint64_t IDX_CEN_TCN_CC_ATOMIC_LOCK_REG_ID_LEN = 10304;
static const uint64_t IDX_CEN_TCN_GP0_TC_UNIT_ABSTCLK_MUXSEL_DC = 10305;
static const uint64_t IDX_CEN_TCN_GP0_TC_UNIT_SYNCCLK_MUXSEL_DC = 10306;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_FLUSHMODE_INH_DC_OUT = 10307;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_FORCEALIGN = 10308;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_AVP_MODE_DC_OUT = 10309;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED9 = 10310;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_CC_SCAN_DIS_DC_B_OUT = 10311;
static const uint64_t IDX_CEN_TCN_GP0_TC_SKIT_MODE_BIST_DC = 10312;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_LBIST_EN_DC_OUT = 10313;
static const uint64_t IDX_CEN_TCN_GP0_TC_UNIT_LBIST_AC_MODE_DC = 10314;
static const uint64_t IDX_CEN_TCN_GP0_TC_UNIT_LBIST_ARY_WRT_THRU_DC = 10315;
static const uint64_t IDX_CEN_TCN_GP0_TC_ABIST_MODE_DC = 10316;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_ABIST_START_TEST_DC_OUT = 10317;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED0 = 10318;
static const uint64_t IDX_CEN_TCN_GP0_TC_UNIT_ATPG_EN_DC = 10319;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_SCAN_PROTECT_DC_OUT = 10320;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED1 = 10321;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED2 = 10322;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED3 = 10323;
static const uint64_t IDX_CEN_TCN_GP0_TC_FENCE_EDRAM = 10324;
static const uint64_t IDX_CEN_TCN_GP0_TP_GPIO_TRACE_START = 10325;
static const uint64_t IDX_CEN_TCN_GP0_TP_GPIO_TRACE_STOP = 10326;
static const uint64_t IDX_CEN_TCN_GP0_TP_GPIO_TRACE_RESET = 10327;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED5 = 10328;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_CLKDIV_SEL_DC = 10329;
static const uint64_t IDX_CEN_TCN_GP0_TC_GPIO_CLKDIV_SEL_DC_LEN = 10330;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED6 = 10331;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED7 = 10332;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED8 = 10333;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED8_LEN = 10334;
static const uint64_t IDX_CEN_TCN_GP0_TC_PSRO_SEL_DC = 10335;
static const uint64_t IDX_CEN_TCN_GP0_TC_PSRO_SEL_DC_LEN = 10336;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED10 = 10337;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED10_LEN = 10338;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED11 = 10339;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED11_LEN = 10340;
static const uint64_t IDX_CEN_TCN_GP0_TC_PLLNSTIO_PADTEST_T_K = 10341;
static const uint64_t IDX_CEN_TCN_GP0_TC_PLLNSTIO_PADTEST_C_K = 10342;
static const uint64_t IDX_CEN_TCN_GP0_TC_UNIT_FENCE_RAM_DOUT_DC = 10343;
static const uint64_t IDX_CEN_TCN_GP0_TC_SENS0_TUNEBITS_DC = 10344;
static const uint64_t IDX_CEN_TCN_GP0_TC_SENS0_TUNEBITS_DC_LEN = 10345;
static const uint64_t IDX_CEN_TCN_GP0_TC_SENS1_TUNEBITS_DC = 10346;
static const uint64_t IDX_CEN_TCN_GP0_TC_SENS1_TUNEBITS_DC_LEN = 10347;
static const uint64_t IDX_CEN_TCN_GP0_TC_MBI_FENCE_EN_DC = 10348;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED22 = 10349;
static const uint64_t IDX_CEN_TCN_GP0_NOT_USED21 = 10350;
static const uint64_t IDX_CEN_TCN_GP0_TC_MASK_CC_PCB_ERR_DC = 10351;
static const uint64_t IDX_CEN_TCN_GP0_TC_MASK_CC_SCAN_OPCG_ERR_DC = 10352;
static const uint64_t IDX_CEN_TCN_GP0_TC_CC_LCC_EDGE_DELAYED_DC = 10353;
static const uint64_t IDX_CEN_TCN_GP0_TC_FENCE_PERV_DC = 10354;
static const uint64_t IDX_CEN_TCN_GP1_REFR_ABIST_DONE = 10355;
static const uint64_t IDX_CEN_TCN_GP1_MBS_ABIST_DONE = 10356;
static const uint64_t IDX_CEN_TCN_GP1_MBI_ABIST_DONE = 10357;
static const uint64_t IDX_CEN_TCN_GP1_TRA_ABIST_DONE = 10358;
static const uint64_t IDX_CEN_TCN_GP1_REFR_ABIST_DIAG = 10359;
static const uint64_t IDX_CEN_TCN_GP1_MBS_ABIST_DIAG = 10360;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED27 = 10361;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED28 = 10362;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED29 = 10363;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED30 = 10364;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED31 = 10365;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED32 = 10366;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED33 = 10367;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED34 = 10368;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED35 = 10369;
static const uint64_t IDX_CEN_TCN_GP1_TC_OPCG_DONE_DC = 10370;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED36 = 10371;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED37 = 10372;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED38 = 10373;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED39 = 10374;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED40 = 10375;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED41 = 10376;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED42 = 10377;
static const uint64_t IDX_CEN_TCN_GP1_NOT_USED43 = 10378;
static const uint64_t IDX_CEN_TCN_GP2_GPIN_MASKING = 10379;
static const uint64_t IDX_CEN_TCN_GP2_GPIN_MASKING_LEN = 10380;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE0_SEL_DC = 10381;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE0_SEL_DC_LEN = 10382;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED44 = 10383;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED44_LEN = 10384;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE1_SEL_DC = 10385;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE1_SEL_DC_LEN = 10386;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED45 = 10387;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED45_LEN = 10388;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE2_SEL_DC = 10389;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE2_SEL_DC_LEN = 10390;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED46 = 10391;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED46_LEN = 10392;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE3_SEL_DC = 10393;
static const uint64_t IDX_CEN_TCN_GP4_TC_PROBE3_SEL_DC_LEN = 10394;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED47 = 10395;
static const uint64_t IDX_CEN_TCN_GP4_TC_OFLOW_FEH_SEL_DC = 10396;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED48 = 10397;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED49 = 10398;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED50 = 10399;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED51 = 10400;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED52 = 10401;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED53 = 10402;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED54 = 10403;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED55 = 10404;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED56 = 10405;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED57 = 10406;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED58 = 10407;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED59 = 10408;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED60 = 10409;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED61 = 10410;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED62 = 10411;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED63 = 10412;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED64 = 10413;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED65 = 10414;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED66 = 10415;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED67 = 10416;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED68 = 10417;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED69 = 10418;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED70 = 10419;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED71 = 10420;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED72 = 10421;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED73 = 10422;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED74 = 10423;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED75 = 10424;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED76 = 10425;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED77 = 10426;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED78 = 10427;
static const uint64_t IDX_CEN_TCN_GP4_NOT_USED79 = 10428;
static const uint64_t IDX_CEN_TCN_GPIO_PROTECT_MODE_REG_READ_ENABLE = 10429;
static const uint64_t IDX_CEN_TCN_GPIO_PROTECT_MODE_REG_WRITE_ENABLE = 10430;
static const uint64_t IDX_CEN_TCN_GPIO_ATOMIC_LOCK_REG_ENABLE = 10431;
static const uint64_t IDX_CEN_TCN_GPIO_ATOMIC_LOCK_REG_ID = 10432;
static const uint64_t IDX_CEN_TCN_GPIO_ATOMIC_LOCK_REG_ID_LEN = 10433;
static const uint64_t IDX_CEN_TCN_XFIR_IN0 = 10434;
static const uint64_t IDX_CEN_TCN_XFIR_IN1 = 10435;
static const uint64_t IDX_CEN_TCN_XFIR_IN2 = 10436;
static const uint64_t IDX_CEN_TCN_XFIR_IN3 = 10437;
static const uint64_t IDX_CEN_TCN_XFIR_IN4 = 10438;
static const uint64_t IDX_CEN_TCN_XFIR_IN5 = 10439;
static const uint64_t IDX_CEN_TCN_XFIR_IN6 = 10440;
static const uint64_t IDX_CEN_TCN_XFIR_IN7 = 10441;
static const uint64_t IDX_CEN_TCN_XFIR_IN8 = 10442;
static const uint64_t IDX_CEN_TCN_XFIR_IN9 = 10443;
static const uint64_t IDX_CEN_TCN_XFIR_IN10 = 10444;
static const uint64_t IDX_CEN_TCN_XFIR_IN11 = 10445;
static const uint64_t IDX_CEN_TCN_XFIR_IN12 = 10446;
static const uint64_t IDX_CEN_TCN_XFIR_IN13 = 10447;
static const uint64_t IDX_CEN_TCN_XFIR_IN14 = 10448;
static const uint64_t IDX_CEN_TCN_XFIR_IN15 = 10449;
static const uint64_t IDX_CEN_TCN_XFIR_IN15_LEN = 10450;
static const uint64_t IDX_CEN_TCN_XFIR_IN26 = 10451;
static const uint64_t IDX_CEN_TCN_RFIR_IN0 = 10452;
static const uint64_t IDX_CEN_TCN_RFIR_LFIR_RECOV_ERR = 10453;
static const uint64_t IDX_CEN_TCN_RFIR_IN = 10454;
static const uint64_t IDX_CEN_TCN_RFIR_IN_LEN = 10455;
static const uint64_t IDX_CEN_TCN_FIR_MASK_IN0 = 10456;
static const uint64_t IDX_CEN_TCN_FIR_MASK_IN1 = 10457;
static const uint64_t IDX_CEN_TCN_FIR_MASK_IN2 = 10458;
static const uint64_t IDX_CEN_TCN_FIR_MASK_IN3 = 10459;
static const uint64_t IDX_CEN_TCN_FIR_MASK_IN4 = 10460;
static const uint64_t IDX_CEN_TCN_FIR_MASK_IN4_LEN = 10461;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN0 = 10462;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN1 = 10463;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN2 = 10464;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN3 = 10465;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN4 = 10466;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN5 = 10467;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN6 = 10468;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN7 = 10469;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN8 = 10470;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN9 = 10471;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN10 = 10472;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN11 = 10473;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN12 = 10474;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN13 = 10475;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN13_LEN = 10476;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_IN40 = 10477;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 10478;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 10479;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR = 10480;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 10481;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_WATCHDOG_ENABLE = 10482;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 10483;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 10484;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_FORCE_ALL_RINGS = 10485;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 10486;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_RESERVED_LT = 10487;
static const uint64_t IDX_CEN_TCN_PSCOM_MODE_REG_RESERVED_LT_LEN = 10488;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 10489;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 10490;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 10491;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 10492;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 10493;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 10494;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 10495;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 10496;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 10497;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 10498;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10499;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 10500;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 10501;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 10502;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 10503;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 10504;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 10505;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 10506;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 10507;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 10508;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 10509;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 10510;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 10511;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 10512;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 10513;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 10514;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 10515;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 10516;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10517;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 10518;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 10519;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 10520;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 10521;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 10522;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 10523;
static const uint64_t IDX_CEN_TCN_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 10524;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 10525;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 10526;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 10527;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_DL_RETURN_P0 = 10528;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 10529;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_UL_P0 = 10530;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 10531;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 10532;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 10533;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 10534;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10535;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_MASK_PARALLEL_WRITE_NVLD = 10536;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_MASK_PARALLEL_READ_NVLD = 10537;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_MASK_PARALLEL_ADDR_INVALID = 10538;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 10539;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 10540;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 10541;
static const uint64_t IDX_CEN_TCN_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 10542;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 10543;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 10544;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 10545;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_RESERVED_LAST_LT = 10546;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 10547;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 10548;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 10549;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 10550;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 10551;
static const uint64_t IDX_CEN_TCN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 10552;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN = 10553;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_TRACE_STATE_LAT = 10554;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN = 10555;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_TRACE_FREEZE = 10556;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_COND3_STATE_LT = 10557;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_COND3_STATE_LT_LEN = 10558;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_COND5_STATE_LT = 10559;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_COND5_STATE_LT_LEN = 10560;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT = 10561;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT = 10562;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT = 10563;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT = 10564;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT = 10565;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT = 10566;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_RESERVED_TCDBG_LT = 10567;
static const uint64_t IDX_CEN_TCN_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN = 10568;
static const uint64_t IDX_CEN_TCN_PSCOM_WRITE_PROTECT_REG_ENABLE_SERIAL_RING = 10569;
static const uint64_t IDX_CEN_TCN_PSCOM_WRITE_PROTECT_REG_RESERVED = 10570;
static const uint64_t IDX_CEN_TCN_ATOMIC_LOCK_REG_ENABLE = 10571;
static const uint64_t IDX_CEN_TCN_ATOMIC_LOCK_REG_ID = 10572;
static const uint64_t IDX_CEN_TCN_ATOMIC_LOCK_REG_ID_LEN = 10573;
static const uint64_t IDX_CEN_TCN_SPATTN_IN0 = 10574;
static const uint64_t IDX_CEN_TCN_SPATTN_IN1 = 10575;
static const uint64_t IDX_CEN_TCN_SPATTN_IN2 = 10576;
static const uint64_t IDX_CEN_TCN_SPATTN_IN2_LEN = 10577;
static const uint64_t IDX_CEN_TCN_SPA_MASK_IN = 10578;
static const uint64_t IDX_CEN_TCN_SPA_MASK_IN_LEN = 10579;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN0 = 10580;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN1 = 10581;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN2 = 10582;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN3 = 10583;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN4 = 10584;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN5 = 10585;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN6 = 10586;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN7 = 10587;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN8 = 10588;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN9 = 10589;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN10 = 10590;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN11 = 10591;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN = 10592;
static const uint64_t IDX_CEN_TCN_MODE_REG_IN_LEN = 10593;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_ACTION0_IN = 10594;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_ACTION0_IN_LEN = 10595;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_ACTION1_IN = 10596;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_ACTION1_IN_LEN = 10597;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_MASK_LFIR_IN = 10598;
static const uint64_t IDX_CEN_TCN_LOCAL_FIR_MASK_LFIR_IN_LEN = 10599;
static const uint64_t IDX_CEN_TCN_DTS_RESULT0_0_RESULT = 10600;
static const uint64_t IDX_CEN_TCN_DTS_RESULT0_0_RESULT_LEN = 10601;
static const uint64_t IDX_CEN_TCN_DTS_RESULT0_1_RESULT = 10602;
static const uint64_t IDX_CEN_TCN_DTS_RESULT0_1_RESULT_LEN = 10603;
static const uint64_t IDX_CEN_TCN_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 10604;
static const uint64_t IDX_CEN_TCN_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 10605;
static const uint64_t IDX_CEN_TCN_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 10606;
static const uint64_t IDX_CEN_TCN_DTS_TRC_RESULT_0_RESULT = 10607;
static const uint64_t IDX_CEN_TCN_DTS_TRC_RESULT_0_RESULT_LEN = 10608;
static const uint64_t IDX_CEN_TCN_ENC_CPM_RESULT0_DTS_0_RESULT = 10609;
static const uint64_t IDX_CEN_TCN_ENC_CPM_RESULT0_DTS_0_RESULT_LEN = 10610;
static const uint64_t IDX_CEN_TCN_ENC_CPM_RESULT0_DTS_1_RESULT = 10611;
static const uint64_t IDX_CEN_TCN_ENC_CPM_RESULT0_DTS_1_RESULT_LEN = 10612;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 10613;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_FORCE_THRES_ACT = 10614;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_THRES_TRIP_ENA = 10615;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 10616;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DTS_SAMPLE_ENA = 10617;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_SAMPLE_PULSE_CNT = 10618;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 10619;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_THRES_ENA = 10620;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_THRES_ENA_LEN = 10621;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DTS_TRIGGER = 10622;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DTS_TRIGGER_SEL = 10623;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_UNUSED = 10624;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_UNUSED_LEN = 10625;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DTS_READ_SEL = 10626;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DTS_READ_SEL_LEN = 10627;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DTS_ENABLE = 10628;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_DTS_ENABLE_LEN = 10629;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_CPM_ENABLE = 10630;
static const uint64_t IDX_CEN_TCN_THERM_MODE_REG_CPM_ENABLE_LEN = 10631;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_HOLD_SAMPLE = 10632;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_DISABLE_STICKINESS = 10633;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_UNUSED1 = 10634;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_UNUSED1_LEN = 10635;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 10636;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 10637;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_RESET_TRIG_SEL = 10638;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 10639;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_SAMPLE_GUTS = 10640;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 10641;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 10642;
static const uint64_t IDX_CEN_TCN_SKITTER_MODE_REG_DATA_V_LT = 10643;
static const uint64_t IDX_CEN_TCN_SKITTER_CLKSRC_REG_SKITTER0 = 10644;
static const uint64_t IDX_CEN_TCN_SKITTER_CLKSRC_REG_SKITTER0_LEN = 10645;
static const uint64_t IDX_CEN_TCN_INJECT_REG_THERM_TRIP = 10646;
static const uint64_t IDX_CEN_TCN_INJECT_REG_THERM_TRIP_LEN = 10647;
static const uint64_t IDX_CEN_TCN_INJECT_REG_THERM_MODE = 10648;
static const uint64_t IDX_CEN_TCN_INJECT_REG_THERM_MODE_LEN = 10649;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 10650;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 10651;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 10652;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 10653;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_MASK = 10654;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 10655;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_COUNT_STATE_MASK = 10656;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_RUN_STATE_MASK = 10657;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_THRES_STATE_MASK = 10658;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_OVERFLOW_MASK = 10659;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 10660;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_SHIFTER_VALID_MASK = 10661;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_TIMEOUT_MASK = 10662;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_F_SKITTER_READ_MASK = 10663;
static const uint64_t IDX_CEN_TCN_ERR_STATUS_REG_PCB_MASK = 10664;
static const uint64_t IDX_CEN_TCN_SKITTER_FORCE_REG_F_READ = 10665;
static const uint64_t IDX_CEN_TCN_VOLT_MODE_REG_MEASURE_ENA = 10666;
static const uint64_t IDX_CEN_TCN_VOLT_MODE_REG_TRIP_ENA = 10667;
static const uint64_t IDX_CEN_TCN_VOLT_MODE_REG_ENABLE = 10668;
static const uint64_t IDX_CEN_TCN_VOLT_MODE_REG_ENABLE_LEN = 10669;
static const uint64_t IDX_CEN_TCN_TIMESTAMP_COUNTER_READ_VALUE = 10670;
static const uint64_t IDX_CEN_TCN_TIMESTAMP_COUNTER_READ_VALUE_LEN = 10671;
static const uint64_t IDX_CEN_TCN_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 10672;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_GLB_BRCST = 10673;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_GLB_BRCST_LEN = 10674;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_TRACE_SEL = 10675;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_TRACE_SEL_LEN = 10676;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_TRIG_SEL = 10677;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_TRIG_SEL_LEN = 10678;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 10679;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 10680;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10681;
static const uint64_t IDX_CEN_TCN_DBG_MODE_REG_FREEZE_SEL = 10682;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND1_SEL_A = 10683;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 10684;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND1_SEL_B = 10685;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 10686;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND2_SEL_A = 10687;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 10688;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND2_SEL_B = 10689;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 10690;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 10691;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 10692;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 10693;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 10694;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 = 10695;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN = 10696;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 10697;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 10698;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 10699;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 10700;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 = 10701;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN = 10702;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 10703;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 10704;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 10705;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 10706;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 10707;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 10708;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_C1_COUNT_LT = 10709;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 10710;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_C2_COUNT_LT = 10711;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 10712;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 10713;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 10714;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_1_A = 10715;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_1_A_LEN = 10716;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 10717;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 10718;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_A = 10719;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_A_LEN = 10720;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_B = 10721;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_B_LEN = 10722;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_SP_COUNT_LT = 10723;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN = 10724;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE = 10725;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN = 10726;
static const uint64_t IDX_CEN_TCN_DBG_INST1_COND_REG_2_FORCE_TEST_MODE = 10727;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND1_SEL_A = 10728;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 10729;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND1_SEL_B = 10730;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 10731;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND2_SEL_A = 10732;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 10733;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND2_SEL_B = 10734;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 10735;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 10736;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 10737;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 10738;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 10739;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 = 10740;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN = 10741;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 10742;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 10743;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 10744;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 10745;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 = 10746;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN = 10747;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 10748;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 10749;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 10750;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 10751;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 10752;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 10753;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_C1_COUNT_LT = 10754;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 10755;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_C2_COUNT_LT = 10756;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 10757;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 10758;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 10759;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_1_A = 10760;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_1_A_LEN = 10761;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 10762;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 10763;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_A = 10764;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_A_LEN = 10765;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_B = 10766;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_B_LEN = 10767;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_SP_COUNT_LT = 10768;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN = 10769;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE = 10770;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN = 10771;
static const uint64_t IDX_CEN_TCN_DBG_INST2_COND_REG_2_FORCE_TEST_MODE = 10772;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 10773;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 10774;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 10775;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 10776;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 10777;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 10778;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 10779;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 10780;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 10781;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 10782;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10783;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 10784;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 10785;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 10786;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 10787;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 10788;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 10789;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 10790;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 10791;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 10792;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 10793;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 10794;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 10795;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 10796;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 10797;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 10798;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 10799;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 10800;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_ARM_SEL = 10801;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_ARM_SEL_LEN = 10802;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 10803;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 10804;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 10805;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 10806;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 10807;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 10808;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 10809;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 10810;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 10811;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 10812;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 10813;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 10814;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 10815;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 10816;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10817;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 10818;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 10819;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 10820;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 10821;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 10822;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 10823;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 10824;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 10825;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 10826;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 10827;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 10828;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 10829;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 10830;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 10831;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 10832;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 10833;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 10834;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 10835;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 10836;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 10837;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 10838;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 10839;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 10840;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 10841;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_FORCE_TEST = 10842;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 10843;
static const uint64_t IDX_CEN_TCN_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON = 10844;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 10845;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 10846;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE = 10847;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN = 10848;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_BANK_MODE = 10849;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_ENH_MODE = 10850;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL = 10851;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN = 10852;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 10853;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 10854;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 10855;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 10856;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_2_PATTERNA = 10857;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 10858;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_2_PATTERNB = 10859;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 10860;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_3_PATTERNC = 10861;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 10862;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_3_PATTERND = 10863;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 10864;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_4_MASKA = 10865;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 10866;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_4_MASKB = 10867;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 10868;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_5_MASKC = 10869;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 10870;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_5_MASKD = 10871;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 10872;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 10873;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 10874;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 10875;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 10876;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 10877;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 10878;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 10879;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 10880;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 10881;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 10882;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10883;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 10884;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 10885;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 10886;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 10887;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 10888;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 10889;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 10890;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 10891;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 10892;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 10893;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 10894;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_HI_DATA_REG_DATA = 10895;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_HI_DATA_REG_DATA_LEN = 10896;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_DATA = 10897;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_DATA_LEN = 10898;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_ADDRESS = 10899;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_ADDRESS_LEN = 10900;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_LAST_BANK = 10901;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_LAST_BANK_LEN = 10902;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_LAST_BANK_VALID = 10903;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_WRITE_ON_RUN = 10904;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_RUNNING = 10905;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_HOLD_ADDRESS = 10906;
static const uint64_t IDX_CEN_TCN_TRA_MBS2TRA_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10907;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 10908;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 10909;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE = 10910;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN = 10911;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_BANK_MODE = 10912;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_ENH_MODE = 10913;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL = 10914;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN = 10915;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 10916;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 10917;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 10918;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 10919;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_2_PATTERNA = 10920;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 10921;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_2_PATTERNB = 10922;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 10923;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_3_PATTERNC = 10924;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 10925;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_3_PATTERND = 10926;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 10927;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_4_MASKA = 10928;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 10929;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_4_MASKB = 10930;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 10931;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_5_MASKC = 10932;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 10933;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_5_MASKD = 10934;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 10935;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 10936;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 10937;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 10938;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 10939;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 10940;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 10941;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 10942;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 10943;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 10944;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 10945;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10946;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 10947;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 10948;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 10949;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 10950;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 10951;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 10952;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 10953;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 10954;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 10955;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 10956;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 10957;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_HI_DATA_REG_DATA = 10958;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_HI_DATA_REG_DATA_LEN = 10959;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_DATA = 10960;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_DATA_LEN = 10961;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_ADDRESS = 10962;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_ADDRESS_LEN = 10963;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_LAST_BANK = 10964;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_LAST_BANK_LEN = 10965;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_LAST_BANK_VALID = 10966;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_WRITE_ON_RUN = 10967;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_RUNNING = 10968;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_HOLD_ADDRESS = 10969;
static const uint64_t IDX_CEN_TCN_TRA_MBS1TRA_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10970;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 10971;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 10972;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE = 10973;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN = 10974;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_BANK_MODE = 10975;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_ENH_MODE = 10976;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL = 10977;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN = 10978;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 10979;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 10980;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 10981;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 10982;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_2_PATTERNA = 10983;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 10984;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_2_PATTERNB = 10985;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 10986;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_3_PATTERNC = 10987;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 10988;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_3_PATTERND = 10989;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 10990;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_4_MASKA = 10991;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 10992;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_4_MASKB = 10993;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 10994;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_5_MASKC = 10995;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 10996;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_5_MASKD = 10997;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 10998;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 10999;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 11000;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 11001;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 11002;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 11003;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 11004;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 11005;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 11006;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 11007;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 11008;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 11009;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 11010;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 11011;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 11012;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 11013;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 11014;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 11015;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 11016;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 11017;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 11018;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 11019;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 11020;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_HI_DATA_REG_DATA = 11021;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_HI_DATA_REG_DATA_LEN = 11022;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_DATA = 11023;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_DATA_LEN = 11024;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_ADDRESS = 11025;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_ADDRESS_LEN = 11026;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_LAST_BANK = 11027;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_LAST_BANK_LEN = 11028;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_LAST_BANK_VALID = 11029;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_WRITE_ON_RUN = 11030;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_RUNNING = 11031;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_HOLD_ADDRESS = 11032;
static const uint64_t IDX_CEN_TCN_TRA_MBITRA_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 11033;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL = 11034;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL_LEN = 11035;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR0 = 11036;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR1 = 11037;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR2 = 11038;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR3 = 11039;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR4 = 11040;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL = 11041;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL_LEN = 11042;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_CNTL = 11043;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_CNTL_LEN = 11044;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_INJECT_FIR_ERR0 = 11045;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_INJECT_FIR_ERR1 = 11046;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_INJECT_FIR_ERR2 = 11047;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_INJECT_FIR_ERR3 = 11048;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_INJECT_FIR_ERR4 = 11049;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_VPROTH_CTL = 11050;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ATEST_MUX_SEL_P1_VPROTH_CTL_LEN = 11051;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P0_DISABLE_PARITY_CHECKER = 11052;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P0_RESET_ERR_RPT = 11053;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P0_FORCE_ON_CLK_GATE = 11054;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL_LO = 11055;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P0_DEBUG__BUS_SEL_HI = 11056;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P0_DEBUG__BUS_SEL_HI_LEN = 11057;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P1_DISABLE_PARITY_CHECKER = 11058;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P1_RESET_ERR_RPT = 11059;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P1_FORCE_ON_CLK_GATE = 11060;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P1_DEBUG_BUS_SEL_LO = 11061;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P1_DEBUG__BUS_SEL_HI = 11062;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_CONFIG0_P1_DEBUG__BUS_SEL_HI_LEN = 11063;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_MASK0_P0_INVALID_ADDRESS_MASK = 11064;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_MASK0_P0_WR_PAR_ERR_MASK = 11065;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_MASK0_P1_INVALID_ADDRESS_MASK = 11066;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_MASK0_P1_WR_PAR_ERR_MASK = 11067;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_STATUS0_P0_INVALID_ADDRESS = 11068;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_STATUS0_P0_WR_PAR_ERR = 11069;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_STATUS0_P1_INVALID_ADDRESS = 11070;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_ERROR_STATUS0_P1_WR_PAR_ERR = 11071;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET0 = 11072;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET1 = 11073;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET2 = 11074;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET3 = 11075;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET4 = 11076;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET5 = 11077;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP18 = 11078;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP18_LEN = 11079;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP18 = 11080;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP18_LEN = 11081;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_SET0 = 11082;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_SET1 = 11083;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_SET2 = 11084;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_SET3 = 11085;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_SET4 = 11086;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_SET5 = 11087;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_FSM_DP18 = 11088;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_FSM_DP18_LEN = 11089;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_REG_DP18 = 11090;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR0_P1_ERR_REG_DP18_LEN = 11091;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P0_PC_ERR_STATUS0 = 11092;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P0_PC_ERR_STATUS0_LEN = 11093;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR = 11094;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN = 11095;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P1_PC_ERR_STATUS0 = 11096;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P1_PC_ERR_STATUS0_LEN = 11097;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P1_PC_INIT_CAL_ERR = 11098;
static const uint64_t IDX_CEN_MBA_DDRPHY_APB_FIR_ERR1_P1_PC_INIT_CAL_ERR_LEN = 11099;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_LOCK = 11100;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_LOCK_LEN = 11101;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_LOCK = 11102;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_LOCK_LEN = 11103;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC = 11104;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC_LEN = 11105;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR0_P1_PERIODIC = 11106;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR0_P1_PERIODIC_LEN = 11107;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC = 11108;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC_LEN = 11109;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR1_P1_PERIODIC = 11110;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_BASE_CNTR1_P1_PERIODIC_LEN = 11111;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC = 11112;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN = 11113;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P1_PERIODIC = 11114;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P1_PERIODIC_LEN = 11115;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC = 11116;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC_LEN = 11117;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_P1_PERIODIC = 11118;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CAL_TIMER_P1_PERIODIC_LEN = 11119;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_PROTOCOL = 11120;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_PROTOCOL_LEN = 11121;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_DATA_MUX4_1MODE = 11122;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_SPAM_EN = 11123;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION = 11124;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_SYSCLK_2X_MEMINTCLKO = 11125;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE = 11126;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE = 11127;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE_LEN = 11128;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_LOW_LATENCY = 11129;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS = 11130;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP = 11131;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P0_ZCAL_NOT_CONT = 11132;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_PROTOCOL = 11133;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_PROTOCOL_LEN = 11134;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_DATA_MUX4_1MODE = 11135;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_SPAM_EN = 11136;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_DDR4_CMD_SIG_REDUCTION = 11137;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_SYSCLK_2X_MEMINTCLKO = 11138;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_RANK_OVERRIDE = 11139;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_RANK_OVERRIDE_VALUE = 11140;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_RANK_OVERRIDE_VALUE_LEN = 11141;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_LOW_LATENCY = 11142;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_DDR4_IPW_LOOP_DIS = 11143;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_DDR4_VLEVEL_BANK_GROUP = 11144;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG0_P1_ZCAL_NOT_CONT = 11145;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET = 11146;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN = 11147;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET = 11148;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET_LEN = 11149;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CIC_FAST = 11150;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CTRN_IGNORE = 11151;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_DISABLE_MEMCTL_CAL = 11152;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE = 11153;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN = 11154;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW = 11155;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P0_RETRAIN_PERCAL_SW = 11156;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_WRITE_LATENCY_OFFSET = 11157;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_WRITE_LATENCY_OFFSET_LEN = 11158;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_READ_LATENCY_OFFSET = 11159;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_READ_LATENCY_OFFSET_LEN = 11160;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_MEMCTL_CIC_FAST = 11161;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_MEMCTL_CTRN_IGNORE = 11162;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_DISABLE_MEMCTL_CAL = 11163;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_MEMORY_TYPE = 11164;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_MEMORY_TYPE_LEN = 11165;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_DDR4_LATENCY_SW = 11166;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CONFIG1_P1_RETRAIN_PERCAL_SW = 11167;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS0_INIT_CAL_VALUE = 11168;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS1_INIT_CAL_VALUE = 11169;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS2_INIT_CAL_VALUE = 11170;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS3_INIT_CAL_VALUE = 11171;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS4_INIT_CAL_VALUE = 11172;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS5_INIT_CAL_VALUE = 11173;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS6_INIT_CAL_VALUE = 11174;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P0_CS7_INIT_CAL_VALUE = 11175;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS0_INIT_CAL_VALUE = 11176;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS1_INIT_CAL_VALUE = 11177;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS2_INIT_CAL_VALUE = 11178;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS3_INIT_CAL_VALUE = 11179;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS4_INIT_CAL_VALUE = 11180;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS5_INIT_CAL_VALUE = 11181;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS6_INIT_CAL_VALUE = 11182;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_CSID_CFG_P1_CS7_INIT_CAL_VALUE = 11183;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_LOCK = 11184;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_LOCK_LEN = 11185;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_LOCK = 11186;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_LOCK_LEN = 11187;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P0_RC_ERROR_MASK = 11188;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P0_WC_ERROR_MASK = 11189;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P0_SEQ_ERROR_MASK = 11190;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P0_CC_ERROR_MASK = 11191;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P0_APB_ERROR_MASK = 11192;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P0_ERROR_MASK = 11193;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P1_RC_ERROR_MASK = 11194;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P1_WC_ERROR_MASK = 11195;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P1_SEQ_ERROR_MASK = 11196;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P1_CC_ERROR_MASK = 11197;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P1_APB_ERROR_MASK = 11198;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_MASK0_P1_ERROR_MASK = 11199;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P0_RC_ERROR = 11200;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P0_WC_ERROR = 11201;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P0_SEQ_ERROR = 11202;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P0_CC_ERROR = 11203;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P0_APB_ERROR = 11204;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P0_ERROR = 11205;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P1_RC_ERROR = 11206;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P1_WC_ERROR = 11207;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P1_SEQ_ERROR = 11208;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P1_CC_ERROR = 11209;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P1_APB_ERROR = 11210;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ERROR_STATUS0_P1_ERROR = 11211;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WR_LEVEL = 11212;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_PAT_WR = 11213;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DQS_ALIGN = 11214;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RDCLK_ALIGN = 11215;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_READ_CTR = 11216;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WRITE_CTR = 11217;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_COARSE_WR = 11218;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_COARSE_RD = 11219;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_RD = 11220;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_WR = 11221;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR = 11222;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DIGITAL_EYE = 11223;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR = 11224;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR_LEN = 11225;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_WR_LEVEL = 11226;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_INITIAL_PAT_WR = 11227;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_DQS_ALIGN = 11228;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_RDCLK_ALIGN = 11229;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_READ_CTR = 11230;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_WRITE_CTR = 11231;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_INITIAL_COARSE_WR = 11232;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_COARSE_RD = 11233;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_CUSTOM_RD = 11234;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_CUSTOM_WR = 11235;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ABORT_ON_ERROR = 11236;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_DIGITAL_EYE = 11237;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_RANK_PAIR = 11238;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG0_P1_ENA_RANK_PAIR_LEN = 11239;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT = 11240;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT_LEN = 11241;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL = 11242;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL_LEN = 11243;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_ALL_RANKS = 11244;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_SNOOP_DIS = 11245;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL = 11246;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL_LEN = 11247;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_REFRESH_COUNT = 11248;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_REFRESH_COUNT_LEN = 11249;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_REFRESH_CONTROL = 11250;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_REFRESH_CONTROL_LEN = 11251;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_REFRESH_ALL_RANKS = 11252;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_SNOOP_DIS = 11253;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_REFRESH_INTERVAL = 11254;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_CONFIG1_P1_REFRESH_INTERVAL_LEN = 11255;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_WR_LEVEL = 11256;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_INITIAL_PAT_WRITE = 11257;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_DQS_ALIGN = 11258;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_RDCLK_ALIGN = 11259;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_READ_CTR = 11260;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_WRITE_CTR = 11261;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_INITIAL_COARSE_WR = 11262;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_COARSE_RD = 11263;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_CUSTOM_RD = 11264;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_CUSTOM_WR = 11265;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_DIGITAL_EYE = 11266;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_RANK_PAIR = 11267;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P0_ERROR_RANK_PAIR_LEN = 11268;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_WR_LEVEL = 11269;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_INITIAL_PAT_WRITE = 11270;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_DQS_ALIGN = 11271;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_RDCLK_ALIGN = 11272;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_READ_CTR = 11273;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_WRITE_CTR = 11274;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_INITIAL_COARSE_WR = 11275;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_COARSE_RD = 11276;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_CUSTOM_RD = 11277;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_CUSTOM_WR = 11278;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_DIGITAL_EYE = 11279;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_RANK_PAIR = 11280;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_ERROR_P1_ERROR_RANK_PAIR_LEN = 11281;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WR_LEVEL = 11282;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_PAT_WRITE = 11283;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DQS_ALIGN = 11284;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_RDCLK_ALIGN = 11285;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_READ_CTR = 11286;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WRITE_CTR = 11287;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_COARSE_WR = 11288;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_COARSE_RD = 11289;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_RD = 11290;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_WR = 11291;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DIGITAL_EYE = 11292;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_WR_LEVEL = 11293;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_INITIAL_PAT_WRITE = 11294;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_DQS_ALIGN = 11295;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_RDCLK_ALIGN = 11296;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_READ_CTR = 11297;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_WRITE_CTR = 11298;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_INITIAL_COARSE_WR = 11299;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_COARSE_RD = 11300;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_CUSTOM_RD = 11301;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_CUSTOM_WR = 11302;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_MASK_P1_ERROR_DIGITAL_EYE = 11303;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE = 11304;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE_LEN = 11305;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_STATUS_P0_PER_ABORT = 11306;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_STATUS_P1_COMPLETE = 11307;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_STATUS_P1_COMPLETE_LEN = 11308;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_INIT_CAL_STATUS_P1_PER_ABORT = 11309;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTP = 11310;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTP_LEN = 11311;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTN = 11312;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTN_LEN = 11313;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_OVERRIDE = 11314;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_ENABLE_ZCAL = 11315;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_RESET_ZCAL = 11316;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_PVTP = 11317;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_PVTP_LEN = 11318;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_PVTN = 11319;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_PVTN_LEN = 11320;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_OVERRIDE = 11321;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_ENABLE_ZCAL = 11322;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_RESET_ZCAL = 11323;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTP = 11324;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTP_LEN = 11325;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTN = 11326;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTN_LEN = 11327;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P1_PVTP = 11328;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P1_PVTP_LEN = 11329;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P1_PVTN = 11330;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_IO_PVT_FET_STATUS_P1_PVTN_LEN = 11331;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP0_P0_MODE_REGISTER_0_VALUE = 11332;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP0_P0_MODE_REGISTER_0_VALUE_LEN = 11333;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP0_P1_MODE_REGISTER_0_VALUE = 11334;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP0_P1_MODE_REGISTER_0_VALUE_LEN = 11335;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP1_P0_MODE_REGISTER_0_VALUE = 11336;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP1_P0_MODE_REGISTER_0_VALUE_LEN = 11337;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP1_P1_MODE_REGISTER_0_VALUE = 11338;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP1_P1_MODE_REGISTER_0_VALUE_LEN = 11339;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP2_P0_MODE_REGISTER_0_VALUE = 11340;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP2_P0_MODE_REGISTER_0_VALUE_LEN = 11341;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP2_P1_MODE_REGISTER_0_VALUE = 11342;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP2_P1_MODE_REGISTER_0_VALUE_LEN = 11343;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP3_P0_MODE_REGISTER_0_VALUE = 11344;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP3_P0_MODE_REGISTER_0_VALUE_LEN = 11345;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP3_P1_MODE_REGISTER_0_VALUE = 11346;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_PRI_RP3_P1_MODE_REGISTER_0_VALUE_LEN = 11347;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP0_P0_MODE_REGISTER_0_VALUE = 11348;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP0_P0_MODE_REGISTER_0_VALUE_LEN = 11349;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP0_P1_MODE_REGISTER_0_VALUE = 11350;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP0_P1_MODE_REGISTER_0_VALUE_LEN = 11351;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP1_P0_MODE_REGISTER_0_VALUE = 11352;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP1_P0_MODE_REGISTER_0_VALUE_LEN = 11353;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP1_P1_MODE_REGISTER_0_VALUE = 11354;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP1_P1_MODE_REGISTER_0_VALUE_LEN = 11355;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP2_P0_MODE_REGISTER_0_VALUE = 11356;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP2_P0_MODE_REGISTER_0_VALUE_LEN = 11357;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP2_P1_MODE_REGISTER_0_VALUE = 11358;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP2_P1_MODE_REGISTER_0_VALUE_LEN = 11359;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP3_P0_MODE_REGISTER_0_VALUE = 11360;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP3_P0_MODE_REGISTER_0_VALUE_LEN = 11361;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP3_P1_MODE_REGISTER_0_VALUE = 11362;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR0_SEC_RP3_P1_MODE_REGISTER_0_VALUE_LEN = 11363;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP0_P0_MODE_REGISTER_1_VALUE = 11364;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP0_P0_MODE_REGISTER_1_VALUE_LEN = 11365;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP0_P1_MODE_REGISTER_1_VALUE = 11366;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP0_P1_MODE_REGISTER_1_VALUE_LEN = 11367;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP1_P0_MODE_REGISTER_1_VALUE = 11368;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP1_P0_MODE_REGISTER_1_VALUE_LEN = 11369;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP1_P1_MODE_REGISTER_1_VALUE = 11370;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP1_P1_MODE_REGISTER_1_VALUE_LEN = 11371;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP2_P0_MODE_REGISTER_1_VALUE = 11372;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP2_P0_MODE_REGISTER_1_VALUE_LEN = 11373;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP2_P1_MODE_REGISTER_1_VALUE = 11374;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP2_P1_MODE_REGISTER_1_VALUE_LEN = 11375;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP3_P0_MODE_REGISTER_1_VALUE = 11376;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP3_P0_MODE_REGISTER_1_VALUE_LEN = 11377;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP3_P1_MODE_REGISTER_1_VALUE = 11378;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_PRI_RP3_P1_MODE_REGISTER_1_VALUE_LEN = 11379;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP0_P0_MODE_REGISTER_1_VALUE = 11380;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP0_P0_MODE_REGISTER_1_VALUE_LEN = 11381;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP0_P1_MODE_REGISTER_1_VALUE = 11382;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP0_P1_MODE_REGISTER_1_VALUE_LEN = 11383;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP1_P0_MODE_REGISTER_1_VALUE = 11384;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP1_P0_MODE_REGISTER_1_VALUE_LEN = 11385;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP1_P1_MODE_REGISTER_1_VALUE = 11386;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP1_P1_MODE_REGISTER_1_VALUE_LEN = 11387;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP2_P0_MODE_REGISTER_1_VALUE = 11388;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP2_P0_MODE_REGISTER_1_VALUE_LEN = 11389;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP2_P1_MODE_REGISTER_1_VALUE = 11390;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP2_P1_MODE_REGISTER_1_VALUE_LEN = 11391;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP3_P0_MODE_REGISTER_1_VALUE = 11392;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP3_P0_MODE_REGISTER_1_VALUE_LEN = 11393;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP3_P1_MODE_REGISTER_1_VALUE = 11394;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR1_SEC_RP3_P1_MODE_REGISTER_1_VALUE_LEN = 11395;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP0_P0_MODE_REGISTER_2_VALUE = 11396;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP0_P0_MODE_REGISTER_2_VALUE_LEN = 11397;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP0_P1_MODE_REGISTER_2_VALUE = 11398;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP0_P1_MODE_REGISTER_2_VALUE_LEN = 11399;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP1_P0_MODE_REGISTER_2_VALUE = 11400;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP1_P0_MODE_REGISTER_2_VALUE_LEN = 11401;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP1_P1_MODE_REGISTER_2_VALUE = 11402;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP1_P1_MODE_REGISTER_2_VALUE_LEN = 11403;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP2_P0_MODE_REGISTER_2_VALUE = 11404;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP2_P0_MODE_REGISTER_2_VALUE_LEN = 11405;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP2_P1_MODE_REGISTER_2_VALUE = 11406;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP2_P1_MODE_REGISTER_2_VALUE_LEN = 11407;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP3_P0_MODE_REGISTER_2_VALUE = 11408;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP3_P0_MODE_REGISTER_2_VALUE_LEN = 11409;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP3_P1_MODE_REGISTER_2_VALUE = 11410;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_PRI_RP3_P1_MODE_REGISTER_2_VALUE_LEN = 11411;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP0_P0_MODE_REGISTER_2_VALUE = 11412;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP0_P0_MODE_REGISTER_2_VALUE_LEN = 11413;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP0_P1_MODE_REGISTER_2_VALUE = 11414;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP0_P1_MODE_REGISTER_2_VALUE_LEN = 11415;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP1_P0_MODE_REGISTER_2_VALUE = 11416;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP1_P0_MODE_REGISTER_2_VALUE_LEN = 11417;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP1_P1_MODE_REGISTER_2_VALUE = 11418;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP1_P1_MODE_REGISTER_2_VALUE_LEN = 11419;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP2_P0_MODE_REGISTER_2_VALUE = 11420;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP2_P0_MODE_REGISTER_2_VALUE_LEN = 11421;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP2_P1_MODE_REGISTER_2_VALUE = 11422;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP2_P1_MODE_REGISTER_2_VALUE_LEN = 11423;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP3_P0_MODE_REGISTER_2_VALUE = 11424;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP3_P0_MODE_REGISTER_2_VALUE_LEN = 11425;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP3_P1_MODE_REGISTER_2_VALUE = 11426;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR2_SEC_RP3_P1_MODE_REGISTER_2_VALUE_LEN = 11427;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP0_P0_MODE_REGISTER_3_VALUE = 11428;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP0_P0_MODE_REGISTER_3_VALUE_LEN = 11429;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP0_P1_MODE_REGISTER_3_VALUE = 11430;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP0_P1_MODE_REGISTER_3_VALUE_LEN = 11431;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP1_P0_MODE_REGISTER_3_VALUE = 11432;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP1_P0_MODE_REGISTER_3_VALUE_LEN = 11433;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP1_P1_MODE_REGISTER_3_VALUE = 11434;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP1_P1_MODE_REGISTER_3_VALUE_LEN = 11435;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP2_P0_MODE_REGISTER_3_VALUE = 11436;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP2_P0_MODE_REGISTER_3_VALUE_LEN = 11437;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP2_P1_MODE_REGISTER_3_VALUE = 11438;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP2_P1_MODE_REGISTER_3_VALUE_LEN = 11439;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP3_P0_MODE_REGISTER_3_VALUE = 11440;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP3_P0_MODE_REGISTER_3_VALUE_LEN = 11441;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP3_P1_MODE_REGISTER_3_VALUE = 11442;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_PRI_RP3_P1_MODE_REGISTER_3_VALUE_LEN = 11443;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP0_P0_MODE_REGISTER_3_VALUE = 11444;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP0_P0_MODE_REGISTER_3_VALUE_LEN = 11445;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP0_P1_MODE_REGISTER_3_VALUE = 11446;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP0_P1_MODE_REGISTER_3_VALUE_LEN = 11447;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP1_P0_MODE_REGISTER_3_VALUE = 11448;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP1_P0_MODE_REGISTER_3_VALUE_LEN = 11449;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP1_P1_MODE_REGISTER_3_VALUE = 11450;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP1_P1_MODE_REGISTER_3_VALUE_LEN = 11451;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP2_P0_MODE_REGISTER_3_VALUE = 11452;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP2_P0_MODE_REGISTER_3_VALUE_LEN = 11453;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP2_P1_MODE_REGISTER_3_VALUE = 11454;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP2_P1_MODE_REGISTER_3_VALUE_LEN = 11455;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP3_P0_MODE_REGISTER_3_VALUE = 11456;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP3_P0_MODE_REGISTER_3_VALUE_LEN = 11457;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP3_P1_MODE_REGISTER_3_VALUE = 11458;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_MR3_SEC_RP3_P1_MODE_REGISTER_3_VALUE_LEN = 11459;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR = 11460;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR_LEN = 11461;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_ZCAL = 11462;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_SYSCLK_ALIGN = 11463;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_READ_CTR = 11464;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RDCLK_ALIGN = 11465;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_DQS_ALIGN = 11466;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR = 11467;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR_LEN = 11468;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_FAST_SIM_CNTR = 11469;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_START_INIT = 11470;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_START = 11471;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_ABORT_ON_ERR_EN = 11472;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P0_DD2_FIX_DIS = 11473;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ENA_RANK_PAIR = 11474;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ENA_RANK_PAIR_LEN = 11475;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ENA_ZCAL = 11476;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ENA_SYSCLK_ALIGN = 11477;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ENA_READ_CTR = 11478;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ENA_RDCLK_ALIGN = 11479;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ENA_DQS_ALIGN = 11480;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_NEXT_RANK_PAIR = 11481;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_NEXT_RANK_PAIR_LEN = 11482;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_FAST_SIM_CNTR = 11483;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_START_INIT = 11484;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_START = 11485;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_ABORT_ON_ERR_EN = 11486;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_CAL_CONFIG_P1_DD2_FIX_DIS = 11487;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK = 11488;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK_LEN = 11489;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK = 11490;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK_LEN = 11491;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_START = 11492;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P1_ENA_RANK = 11493;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P1_ENA_RANK_LEN = 11494;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P1_NEXT_RANK = 11495;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P1_NEXT_RANK_LEN = 11496;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_PER_ZCAL_CONFIG_P1_START = 11497;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_MASTER_PD_CNTL = 11498;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB2 = 11499;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_EYEDAC_PD = 11500;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_PHYTOP_CLK_GATE = 11501;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_EXT_VREF_PD = 11502;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_RESET_STAB = 11503;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_OUTPUT_STAB = 11504;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB1 = 11505;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_SYSCLK_CLK_GATE = 11506;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_DELAY_LINE_CTL_OVERRIDE = 11507;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_WR_FIFO_STAB = 11508;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_ADR_RX_PD = 11509;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_DP18_RX_PD = 11510;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_DP18_RX_PD_LEN = 11511;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_TX_TRISTATE_CNTL = 11512;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P0_VCC_REG_PD = 11513;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_MASTER_PD_CNTL = 11514;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_ANALOG_INPUT_STAB2 = 11515;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_EYEDAC_PD = 11516;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_PHYTOP_CLK_GATE = 11517;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_EXT_VREF_PD = 11518;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_RESET_STAB = 11519;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_ANALOG_OUTPUT_STAB = 11520;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_ANALOG_INPUT_STAB1 = 11521;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_SYSCLK_CLK_GATE = 11522;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_DELAY_LINE_CTL_OVERRIDE = 11523;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_WR_FIFO_STAB = 11524;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_ADR_RX_PD = 11525;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_DP18_RX_PD = 11526;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_DP18_RX_PD_LEN = 11527;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_TX_TRISTATE_CNTL = 11528;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_POWERDOWN_1_P1_VCC_REG_PD = 11529;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_TER = 11530;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_QUA = 11531;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_TER = 11532;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_QUA = 11533;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_TER = 11534;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_QUA = 11535;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_TER = 11536;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_QUA = 11537;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP0_TER = 11538;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP0_QUA = 11539;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP1_TER = 11540;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP1_QUA = 11541;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP2_TER = 11542;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP2_QUA = 11543;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP3_TER = 11544;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_EXT_P1_ADDR_MIRROR_RP3_QUA = 11545;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP0_PRI = 11546;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP0_SEC = 11547;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP1_PRI = 11548;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP1_SEC = 11549;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP2_PRI = 11550;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP2_SEC = 11551;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP3_PRI = 11552;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP3_SEC = 11553;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_GROUPING = 11554;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_GROUPING_LEN = 11555;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A3_A4 = 11556;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A5_A6 = 11557;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A7_A8 = 11558;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A11_A13 = 11559;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_BA0_BA1 = 11560;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_BG0_BG1 = 11561;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP0_PRI = 11562;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP0_SEC = 11563;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP1_PRI = 11564;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP1_SEC = 11565;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP2_PRI = 11566;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP2_SEC = 11567;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP3_PRI = 11568;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_RP3_SEC = 11569;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_GROUPING = 11570;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_GROUPING_LEN = 11571;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_A3_A4 = 11572;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_A5_A6 = 11573;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_A7_A8 = 11574;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_A11_A13 = 11575;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_BA0_BA1 = 11576;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_GROUP_P1_ADDR_MIRROR_BG0_BG1 = 11577;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PRI = 11578;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PRI_LEN = 11579;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PRI_V = 11580;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_SEC = 11581;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_SEC_LEN = 11582;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_SEC_V = 11583;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI = 11584;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_LEN = 11585;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_V = 11586;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC = 11587;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_LEN = 11588;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_V = 11589;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PRI = 11590;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PRI_LEN = 11591;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PRI_V = 11592;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_SEC = 11593;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_SEC_LEN = 11594;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_SEC_V = 11595;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PAIR1_PRI = 11596;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PAIR1_PRI_LEN = 11597;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PAIR1_PRI_V = 11598;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PAIR1_SEC = 11599;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PAIR1_SEC_LEN = 11600;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR0_P1_PAIR1_SEC_V = 11601;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI = 11602;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_LEN = 11603;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_V = 11604;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC = 11605;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_LEN = 11606;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_V = 11607;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI = 11608;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_LEN = 11609;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_V = 11610;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC = 11611;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_LEN = 11612;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_V = 11613;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR2_PRI = 11614;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR2_PRI_LEN = 11615;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR2_PRI_V = 11616;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR2_SEC = 11617;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR2_SEC_LEN = 11618;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR2_SEC_V = 11619;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR3_PRI = 11620;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR3_PRI_LEN = 11621;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR3_PRI_V = 11622;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR3_SEC = 11623;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR3_SEC_LEN = 11624;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR1_P1_PAIR3_SEC_V = 11625;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER = 11626;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_LEN = 11627;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_V = 11628;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA = 11629;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_LEN = 11630;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_V = 11631;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER = 11632;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_LEN = 11633;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_V = 11634;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA = 11635;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_LEN = 11636;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_V = 11637;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR0_TER = 11638;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR0_TER_LEN = 11639;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR0_TER_V = 11640;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR0_QUA = 11641;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR0_QUA_LEN = 11642;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR0_QUA_V = 11643;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR1_TER = 11644;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR1_TER_LEN = 11645;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR1_TER_V = 11646;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR1_QUA = 11647;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR1_QUA_LEN = 11648;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR2_P1_PAIR1_QUA_V = 11649;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER = 11650;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_LEN = 11651;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_V = 11652;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA = 11653;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_LEN = 11654;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_V = 11655;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_TER = 11656;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_TER_LEN = 11657;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_TER_V = 11658;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_QUA = 11659;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_QUA_LEN = 11660;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P0_QUA_V = 11661;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_PAIR2_TER = 11662;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_PAIR2_TER_LEN = 11663;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_PAIR2_TER_V = 11664;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_PAIR2_QUA = 11665;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_PAIR2_QUA_LEN = 11666;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_PAIR2_QUA_V = 11667;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_TER = 11668;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_TER_LEN = 11669;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_TER_V = 11670;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_QUA = 11671;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_QUA_LEN = 11672;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RANK_PAIR3_P1_QUA_V = 11673;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_CAL_REQ_EN = 11674;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC = 11675;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_LEN = 11676;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RELOAD_VALUE0_P1_PERIODIC_CAL_REQ_EN = 11677;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RELOAD_VALUE0_P1_PERIODIC = 11678;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RELOAD_VALUE0_P1_PERIODIC_LEN = 11679;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RESETS_P0_PLL_RESET = 11680;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET = 11681;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RESETS_P1_PLL_RESET = 11682;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_RESETS_P1_SYSCLK_RESET = 11683;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0DSGN = 11684;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0D = 11685;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0D_LEN = 11686;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1DSGN = 11687;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1D = 11688;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1D_LEN = 11689;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P1_VREFDQ0DSGN = 11690;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P1_VREFDQ0D = 11691;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P1_VREFDQ0D_LEN = 11692;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P1_VREFDQ1DSGN = 11693;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P1_VREFDQ1D = 11694;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_VREF_DRV_CONTROL_P1_VREFDQ1D_LEN = 11695;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC = 11696;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN = 11697;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P1_PERIODIC = 11698;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P1_PERIODIC_LEN = 11699;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC = 11700;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC_LEN = 11701;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_P1_PERIODIC = 11702;
static const uint64_t IDX_CEN_MBA_DDRPHY_PC_ZCAL_TIMER_P1_PERIODIC_LEN = 11703;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET = 11704;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET_LEN = 11705;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_ADVANCE_RD_VALID = 11706;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_PER_DUTY_CYCLE_SW = 11707;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT = 11708;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT_LEN = 11709;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP0 = 11710;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP1 = 11711;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP2 = 11712;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP3 = 11713;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_ALIGN_ON_EVEN_CYCLES = 11714;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_PERFORM_RDCLK_ALIGN = 11715;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P0_STAGGERED_PATTERN = 11716;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_GLOBAL_PHY_OFFSET = 11717;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_GLOBAL_PHY_OFFSET_LEN = 11718;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_ADVANCE_RD_VALID = 11719;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_PER_DUTY_CYCLE_SW = 11720;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_PER_REPEAT_COUNT = 11721;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_PER_REPEAT_COUNT_LEN = 11722;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_SINGLE_BIT_MPR_RP0 = 11723;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_SINGLE_BIT_MPR_RP1 = 11724;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_SINGLE_BIT_MPR_RP2 = 11725;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_SINGLE_BIT_MPR_RP3 = 11726;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_ALIGN_ON_EVEN_CYCLES = 11727;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_PERFORM_RDCLK_ALIGN = 11728;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG0_P1_STAGGERED_PATTERN = 11729;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT = 11730;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT_LEN = 11731;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG1_P1_OUTER_LOOP_CNT = 11732;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG1_P1_OUTER_LOOP_CNT_LEN = 11733;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P0_CONSEQ_PASS = 11734;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P0_CONSEQ_PASS_LEN = 11735;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P0_BURST_WINDOW = 11736;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P0_BURST_WINDOW_LEN = 11737;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P0_ALLOW_RD_FIFO_AUTO_RESET = 11738;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P1_CONSEQ_PASS = 11739;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P1_CONSEQ_PASS_LEN = 11740;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P1_BURST_WINDOW = 11741;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P1_BURST_WINDOW_LEN = 11742;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG2_P1_ALLOW_RD_FIFO_AUTO_RESET = 11743;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE = 11744;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE_LEN = 11745;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE = 11746;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE_LEN = 11747;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD = 11748;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD_LEN = 11749;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE = 11750;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE_LEN = 11751;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_FINE_CAL_STEP_SIZE = 11752;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_FINE_CAL_STEP_SIZE_LEN = 11753;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_COARSE_CAL_STEP_SIZE = 11754;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_COARSE_CAL_STEP_SIZE_LEN = 11755;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_DQ_SEL_QUAD = 11756;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_DQ_SEL_QUAD_LEN = 11757;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_DQ_SEL_LANE = 11758;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_CONFIG3_P1_DQ_SEL_LANE_LEN = 11759;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_ERROR_MASK0_P0_RD_CNTL_ERROR_MASK = 11760;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_ERROR_MASK0_P1_RD_CNTL_ERROR_MASK = 11761;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_ERROR_STATUS0_P0_RD_CNTL_ERROR = 11762;
static const uint64_t IDX_CEN_MBA_DDRPHY_RC_ERROR_STATUS0_P1_RD_CNTL_ERROR = 11763;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_MPR_PATTERN_BIT = 11764;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_TWO_CYCLE_ADDR_EN = 11765;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN = 11766;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN_LEN = 11767;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_DELAYED_PAR = 11768;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_LRDIMM_CONTEXT = 11769;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_FORCE_RESERVED = 11770;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_HALT_ROTATION = 11771;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_FORCE_MPR = 11772;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_CLONE_CS_MODE = 11773;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_PAR_INVERT = 11774;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_IPW_SIDEAB_SEL = 11775;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_PAR_A17_MASK = 11776;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P0_CW_MIRROR = 11777;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_MPR_PATTERN_BIT = 11778;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_TWO_CYCLE_ADDR_EN = 11779;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_MR_MASK_EN = 11780;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_MR_MASK_EN_LEN = 11781;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_DELAYED_PAR = 11782;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_LRDIMM_CONTEXT = 11783;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_FORCE_RESERVED = 11784;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_HALT_ROTATION = 11785;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_FORCE_MPR = 11786;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_CLONE_CS_MODE = 11787;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_PAR_INVERT = 11788;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_IPW_SIDEAB_SEL = 11789;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_PAR_A17_MASK = 11790;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_CONFIG0_P1_CW_MIRROR = 11791;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_MASK0_P0_MULT_REQ_ERR_MASK = 11792;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_MASK0_P0_INVALID_REQTYPE_ERR_MASK = 11793;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_MASK0_P0_EARLY_REQ_ERR_MASK = 11794;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_MASK0_P1_MULT_REQ_ERR_MASK = 11795;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_MASK0_P1_INVALID_REQTYPE_ERR_MASK = 11796;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_MASK0_P1_EARLY_REQ_ERR_MASK = 11797;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_ERROR = 11798;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE_ERROR = 11799;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_ERROR = 11800;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE = 11801;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE_LEN = 11802;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE = 11803;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE_LEN = 11804;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE = 11805;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE_LEN = 11806;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE = 11807;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE_LEN = 11808;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_MULTIPLE_REQ_ERROR = 11809;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_INVALID_REQTYPE_ERROR = 11810;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_EARLY_REQ_ERROR = 11811;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_MULTIPLE_REQ_SOURCE = 11812;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_MULTIPLE_REQ_SOURCE_LEN = 11813;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_INVALID_REQTYPE = 11814;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_INVALID_REQTYPE_LEN = 11815;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_INVALID_REQ_SOURCE = 11816;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_INVALID_REQ_SOURCE_LEN = 11817;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_EARLY_REQ_SOURCE = 11818;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ERROR_STATUS0_P1_EARLY_REQ_SOURCE_LEN = 11819;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2 = 11820;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2_LEN = 11821;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR2_P1_ADDR2 = 11822;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR2_P1_ADDR2_LEN = 11823;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3 = 11824;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3_LEN = 11825;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR3_P1_ADDR3 = 11826;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR3_P1_ADDR3_LEN = 11827;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4 = 11828;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4_LEN = 11829;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR4_P1_ADDR4 = 11830;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_LPT_ADDR4_P1_ADDR4_LEN = 11831;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES = 11832;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES_LEN = 11833;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES = 11834;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES_LEN = 11835;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES = 11836;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES_LEN = 11837;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES = 11838;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES_LEN = 11839;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TMOD_CYCLES = 11840;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TMOD_CYCLES_LEN = 11841;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TRCD_CYCLES = 11842;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TRCD_CYCLES_LEN = 11843;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TRP_CYCLES = 11844;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TRP_CYCLES_LEN = 11845;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TRFC_CYCLES = 11846;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1_TRFC_CYCLES_LEN = 11847;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES = 11848;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES_LEN = 11849;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES = 11850;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES_LEN = 11851;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES = 11852;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES_LEN = 11853;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES = 11854;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES_LEN = 11855;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TZQINIT_CYCLES = 11856;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TZQINIT_CYCLES_LEN = 11857;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TZQCS_CYCLES = 11858;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TZQCS_CYCLES_LEN = 11859;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TWLDQSEN_CYCLES = 11860;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TWLDQSEN_CYCLES_LEN = 11861;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TWRMRD_CYCLES = 11862;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1_TWRMRD_CYCLES_LEN = 11863;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES = 11864;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES_LEN = 11865;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES = 11866;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES_LEN = 11867;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES = 11868;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES_LEN = 11869;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1_TODTLON_OFF_CYCLES = 11870;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1_TODTLON_OFF_CYCLES_LEN = 11871;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1_TRC_CYCLES = 11872;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1_TRC_CYCLES_LEN = 11873;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1_TMRSC_CYCLES = 11874;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1_TMRSC_CYCLES_LEN = 11875;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P0_DEF_VALUES = 11876;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P0_DEF_VALUES_LEN = 11877;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P1_DEF_VALUES = 11878;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P1_DEF_VALUES_LEN = 11879;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0 = 11880;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0_LEN = 11881;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1 = 11882;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1_LEN = 11883;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P1_VALUES0 = 11884;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P1_VALUES0_LEN = 11885;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P1_VALUES1 = 11886;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG0_P1_VALUES1_LEN = 11887;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2 = 11888;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2_LEN = 11889;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3 = 11890;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3_LEN = 11891;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P1_VALUES2 = 11892;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P1_VALUES2_LEN = 11893;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P1_VALUES3 = 11894;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG1_P1_VALUES3_LEN = 11895;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES4 = 11896;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES4_LEN = 11897;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5 = 11898;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5_LEN = 11899;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P1_VALUES4 = 11900;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P1_VALUES4_LEN = 11901;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P1_VALUES5 = 11902;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG2_P1_VALUES5_LEN = 11903;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES6 = 11904;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES6_LEN = 11905;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7 = 11906;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7_LEN = 11907;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P1_VALUES6 = 11908;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P1_VALUES6_LEN = 11909;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P1_VALUES7 = 11910;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_RD_CONFIG3_P1_VALUES7_LEN = 11911;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0 = 11912;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0_LEN = 11913;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1 = 11914;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1_LEN = 11915;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P1_VALUES0 = 11916;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P1_VALUES0_LEN = 11917;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P1_VALUES1 = 11918;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG0_P1_VALUES1_LEN = 11919;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2 = 11920;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2_LEN = 11921;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3 = 11922;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3_LEN = 11923;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P1_VALUES2 = 11924;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P1_VALUES2_LEN = 11925;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P1_VALUES3 = 11926;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG1_P1_VALUES3_LEN = 11927;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES4 = 11928;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES4_LEN = 11929;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5 = 11930;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5_LEN = 11931;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P1_VALUES4 = 11932;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P1_VALUES4_LEN = 11933;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P1_VALUES5 = 11934;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG2_P1_VALUES5_LEN = 11935;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES6 = 11936;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES6_LEN = 11937;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7 = 11938;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7_LEN = 11939;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P1_VALUES6 = 11940;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P1_VALUES6_LEN = 11941;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P1_VALUES7 = 11942;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ODT_WR_CONFIG3_P1_VALUES7_LEN = 11943;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0 = 11944;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN = 11945;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA0_P1_DATA_REG0 = 11946;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA0_P1_DATA_REG0_LEN = 11947;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1 = 11948;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1_LEN = 11949;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA1_P1_DATA_REG1 = 11950;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RD_WR_DATA1_P1_DATA_REG1_LEN = 11951;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0 = 11952;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0_LEN = 11953;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR0_P1_ADDR0 = 11954;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR0_P1_ADDR0_LEN = 11955;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1 = 11956;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1_LEN = 11957;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR1_P1_ADDR1 = 11958;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR1_P1_ADDR1_LEN = 11959;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2 = 11960;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2_LEN = 11961;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR2_P1_ADDR2 = 11962;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR2_P1_ADDR2_LEN = 11963;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3 = 11964;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3_LEN = 11965;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR3_P1_ADDR3 = 11966;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR3_P1_ADDR3_LEN = 11967;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4 = 11968;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4_LEN = 11969;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR4_P1_ADDR4 = 11970;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_RESERVED_ADDR4_P1_ADDR4_LEN = 11971;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_0_2 = 11972;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_0_2 = 11973;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2 = 11974;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2_LEN = 11975;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_1_3 = 11976;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_1_3 = 11977;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3 = 11978;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3_LEN = 11979;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_0_2 = 11980;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_SEL_TYPE_0_2 = 11981;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_SEL_0_2 = 11982;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_SEL_0_2_LEN = 11983;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_1_3 = 11984;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_SEL_TYPE_1_3 = 11985;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_SEL_1_3 = 11986;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1_SEL_1_3_LEN = 11987;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_0_2 = 11988;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_0_2 = 11989;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2 = 11990;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2_LEN = 11991;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_1_3 = 11992;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_1_3 = 11993;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3 = 11994;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3_LEN = 11995;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_0_2 = 11996;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_SEL_TYPE_0_2 = 11997;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_SEL_0_2 = 11998;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_SEL_0_2_LEN = 11999;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_1_3 = 12000;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_SEL_TYPE_1_3 = 12001;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_SEL_1_3 = 12002;
static const uint64_t IDX_CEN_MBA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1_SEL_1_3_LEN = 12003;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE = 12004;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE_LEN = 12005;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P0_WL_ONE_DQS_PULSE = 12006;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD = 12007;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD_LEN = 12008;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P0_CUSTOM_INIT_WRITE = 12009;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P1_TWLO_TWLOE = 12010;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P1_TWLO_TWLOE_LEN = 12011;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P1_WL_ONE_DQS_PULSE = 12012;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P1_FW_WR_RD = 12013;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P1_FW_WR_RD_LEN = 12014;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG0_P1_CUSTOM_INIT_WRITE = 12015;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P0_BIG_STEP = 12016;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P0_BIG_STEP_LEN = 12017;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP = 12018;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP_LEN = 12019;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY = 12020;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY_LEN = 12021;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P1_BIG_STEP = 12022;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P1_BIG_STEP_LEN = 12023;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P1_SMALL_STEP = 12024;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P1_SMALL_STEP_LEN = 12025;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P1_WR_PRE_DLY = 12026;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG1_P1_WR_PRE_DLY_LEN = 12027;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES = 12028;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES_LEN = 12029;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR = 12030;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR_LEN = 12031;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_IPW_WR = 12032;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_IPW_WR_LEN = 12033;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_EN_RESET_DD2_FIX_DIS = 12034;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL = 12035;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_NUM_VALID_SAMPLES = 12036;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_NUM_VALID_SAMPLES_LEN = 12037;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_FW_RD_WR = 12038;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_FW_RD_WR_LEN = 12039;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_IPW_WR = 12040;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_IPW_WR_LEN = 12041;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_EN_RESET_DD2_FIX_DIS = 12042;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG2_P1_EN_RESET_WR_DELAY_WL = 12043;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P0_DDR4_MRS_CMD_DQ_EN = 12044;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON = 12045;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON_LEN = 12046;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF = 12047;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF_LEN = 12048;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P1_DDR4_MRS_CMD_DQ_EN = 12049;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P1_MRS_CMD_DQ_ON = 12050;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P1_MRS_CMD_DQ_ON_LEN = 12051;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P1_MRS_CMD_DQ_OFF = 12052;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_CONFIG3_P1_MRS_CMD_DQ_OFF_LEN = 12053;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_ERROR_MASK0_P0_WR_CNTL_ERROR_MASK = 12054;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_ERROR_MASK0_P1_WR_CNTL_ERROR_MASK = 12055;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_ERROR_STATUS0_P0_WR_CNTL_ERROR = 12056;
static const uint64_t IDX_CEN_MBA_DDRPHY_WC_ERROR_STATUS0_P1_WR_CNTL_ERROR = 12057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_0_01_DIR_15 = 12058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_0_01_DIR_15_LEN = 12059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_1_01_DIR_0_15 = 12060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_1_01_DIR_0_15_LEN = 12061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_0_01_DIR_15 = 12062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_0_01_DIR_15_LEN = 12063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_1_01_DIR_0_15 = 12064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_1_01_DIR_0_15_LEN = 12065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_2_23_DIR_0_15 = 12066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_2_23_DIR_0_15_LEN = 12067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_3_23_DIR_0_15 = 12068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_3_23_DIR_0_15_LEN = 12069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_2_23_DIR_0_15 = 12070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_2_23_DIR_0_15_LEN = 12071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_3_23_DIR_0_15 = 12072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_3_23_DIR_0_15_LEN = 12073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_4_DIR_0_15 = 12074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P0_4_DIR_0_15_LEN = 12075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_4_DIR_0_15 = 12076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR0_P1_4_DIR_0_15_LEN = 12077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_DD2_FIX_DIS = 12078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_TOXDRV_HIBERNATE = 12079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_ATEST_MUX_CTL_EN = 12080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_WL_ADVANCE_DISABLE = 12081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_DISABLE_PING_PONG = 12082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_DELAY_PING_PONG_HALF = 12083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_ADVANCE_PING_PONG = 12084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_ATEST_MUX_CTL0 = 12085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_ATEST_MUX_CTL1 = 12086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_ATEST_MUX_CTL2 = 12087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_0_01_ATEST_MUX_CTL3 = 12088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_DD2_FIX_DIS = 12089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_TOXDRV_HIBERNATE = 12090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_ATEST_MUX_CTL_EN = 12091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_WL_ADVANCE_DISABLE = 12092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_DISABLE_PING_PONG = 12093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_DELAY_PING_PONG_HALF = 12094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_ADVANCE_PING_PONG = 12095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_ATEST_MUX_CTL0 = 12096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_ATEST_MUX_CTL1 = 12097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_ATEST_MUX_CTL2 = 12098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_1_01_ATEST_MUX_CTL3 = 12099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_DD2_FIX_DIS = 12100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_TOXDRV_HIBERNATE = 12101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_ATEST_MUX_CTL_EN = 12102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_WL_ADVANCE_DISABLE = 12103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_DISABLE_PING_PONG = 12104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_DELAY_PING_PONG_HALF = 12105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_ADVANCE_PING_PONG = 12106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_ATEST_MUX_CTL0 = 12107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_ATEST_MUX_CTL1 = 12108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_ATEST_MUX_CTL2 = 12109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_0_01_ATEST_MUX_CTL3 = 12110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_DD2_FIX_DIS = 12111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_TOXDRV_HIBERNATE = 12112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_ATEST_MUX_CTL_EN = 12113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_WL_ADVANCE_DISABLE = 12114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_DISABLE_PING_PONG = 12115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_DELAY_PING_PONG_HALF = 12116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_ADVANCE_PING_PONG = 12117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_ATEST_MUX_CTL0 = 12118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_ATEST_MUX_CTL1 = 12119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_ATEST_MUX_CTL2 = 12120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_1_01_ATEST_MUX_CTL3 = 12121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_DD2_FIX_DIS = 12122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_TOXDRV_HIBERNATE = 12123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_ATEST_MUX_CTL_EN = 12124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_WL_ADVANCE_DISABLE = 12125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_DISABLE_PING_PONG = 12126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_DELAY_PING_PONG_HALF = 12127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_ADVANCE_PING_PONG = 12128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_ATEST_MUX_CTL0 = 12129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_ATEST_MUX_CTL1 = 12130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_ATEST_MUX_CTL2 = 12131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_2_23_ATEST_MUX_CTL3 = 12132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_DD2_FIX_DIS = 12133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_TOXDRV_HIBERNATE = 12134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_ATEST_MUX_CTL_EN = 12135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_WL_ADVANCE_DISABLE = 12136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_DISABLE_PING_PONG = 12137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_DELAY_PING_PONG_HALF = 12138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_ADVANCE_PING_PONG = 12139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_ATEST_MUX_CTL0 = 12140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_ATEST_MUX_CTL1 = 12141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_ATEST_MUX_CTL2 = 12142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_3_23_ATEST_MUX_CTL3 = 12143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_DD2_FIX_DIS = 12144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_TOXDRV_HIBERNATE = 12145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_ATEST_MUX_CTL_EN = 12146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_WL_ADVANCE_DISABLE = 12147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_DISABLE_PING_PONG = 12148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_DELAY_PING_PONG_HALF = 12149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_ADVANCE_PING_PONG = 12150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_ATEST_MUX_CTL0 = 12151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_ATEST_MUX_CTL1 = 12152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_ATEST_MUX_CTL2 = 12153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_2_23_ATEST_MUX_CTL3 = 12154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_DD2_FIX_DIS = 12155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_TOXDRV_HIBERNATE = 12156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_ATEST_MUX_CTL_EN = 12157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_WL_ADVANCE_DISABLE = 12158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_DISABLE_PING_PONG = 12159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_DELAY_PING_PONG_HALF = 12160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_ADVANCE_PING_PONG = 12161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_ATEST_MUX_CTL0 = 12162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_ATEST_MUX_CTL1 = 12163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_ATEST_MUX_CTL2 = 12164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_3_23_ATEST_MUX_CTL3 = 12165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_DD2_FIX_DIS = 12166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_TOXDRV_HIBERNATE = 12167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_ATEST_MUX_CTL_EN = 12168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_WL_ADVANCE_DISABLE = 12169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_DISABLE_PING_PONG = 12170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_DELAY_PING_PONG_HALF = 12171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_ADVANCE_PING_PONG = 12172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_ATEST_MUX_CTL0 = 12173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_ATEST_MUX_CTL1 = 12174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_ATEST_MUX_CTL2 = 12175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P0_4_ATEST_MUX_CTL3 = 12176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_DD2_FIX_DIS = 12177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_TOXDRV_HIBERNATE = 12178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_ATEST_MUX_CTL_EN = 12179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_WL_ADVANCE_DISABLE = 12180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_DISABLE_PING_PONG = 12181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_DELAY_PING_PONG_HALF = 12182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_ADVANCE_PING_PONG = 12183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_ATEST_MUX_CTL0 = 12184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_ATEST_MUX_CTL1 = 12185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_ATEST_MUX_CTL2 = 12186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DIR1_P1_4_ATEST_MUX_CTL3 = 12187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_01_DISABLE_15 = 12188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_01_DISABLE_15_LEN = 12189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_01_DISABLE_0_15 = 12190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_01_DISABLE_0_15_LEN = 12191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_01_DISABLE_15 = 12192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_01_DISABLE_15_LEN = 12193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_01_DISABLE_0_15 = 12194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_01_DISABLE_0_15_LEN = 12195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_23_DISABLE_0_15 = 12196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_23_DISABLE_0_15_LEN = 12197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_23_DISABLE_0_15 = 12198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_23_DISABLE_0_15_LEN = 12199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_23_DISABLE_0_15 = 12200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_23_DISABLE_0_15_LEN = 12201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_23_DISABLE_0_15 = 12202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_23_DISABLE_0_15_LEN = 12203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_DISABLE_0_15 = 12204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_DISABLE_0_15_LEN = 12205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_DISABLE_0_15 = 12206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_DISABLE_0_15_LEN = 12207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_01_DISABLE_15 = 12208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_01_DISABLE_15_LEN = 12209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_01_DISABLE_0_15 = 12210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_01_DISABLE_0_15_LEN = 12211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_01_DISABLE_15 = 12212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_01_DISABLE_15_LEN = 12213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_01_DISABLE_0_15 = 12214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_01_DISABLE_0_15_LEN = 12215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_23_DISABLE_0_15 = 12216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_23_DISABLE_0_15_LEN = 12217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_23_DISABLE_0_15 = 12218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_23_DISABLE_0_15_LEN = 12219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_23_DISABLE_0_15 = 12220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_23_DISABLE_0_15_LEN = 12221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_23_DISABLE_0_15 = 12222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_23_DISABLE_0_15_LEN = 12223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_DISABLE_0_15 = 12224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_DISABLE_0_15_LEN = 12225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_DISABLE_0_15 = 12226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_DISABLE_0_15_LEN = 12227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_01_DISABLE_15 = 12228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_01_DISABLE_15_LEN = 12229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_01_DISABLE_0_15 = 12230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_01_DISABLE_0_15_LEN = 12231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_01_DISABLE_15 = 12232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_01_DISABLE_15_LEN = 12233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_01_DISABLE_0_15 = 12234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_01_DISABLE_0_15_LEN = 12235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_23_DISABLE_0_15 = 12236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_23_DISABLE_0_15_LEN = 12237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_23_DISABLE_0_15 = 12238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_23_DISABLE_0_15_LEN = 12239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_23_DISABLE_0_15 = 12240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_23_DISABLE_0_15_LEN = 12241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_23_DISABLE_0_15 = 12242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_23_DISABLE_0_15_LEN = 12243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_DISABLE_0_15 = 12244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_DISABLE_0_15_LEN = 12245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_DISABLE_0_15 = 12246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_DISABLE_0_15_LEN = 12247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_01_DISABLE_15 = 12248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_01_DISABLE_15_LEN = 12249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_01_DISABLE_0_15 = 12250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_01_DISABLE_0_15_LEN = 12251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_01_DISABLE_15 = 12252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_01_DISABLE_15_LEN = 12253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_01_DISABLE_0_15 = 12254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_01_DISABLE_0_15_LEN = 12255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_23_DISABLE_0_15 = 12256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_23_DISABLE_0_15_LEN = 12257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_23_DISABLE_0_15 = 12258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_23_DISABLE_0_15_LEN = 12259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_23_DISABLE_0_15 = 12260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_23_DISABLE_0_15_LEN = 12261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_23_DISABLE_0_15 = 12262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_23_DISABLE_0_15_LEN = 12263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_DISABLE_0_15 = 12264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_DISABLE_0_15_LEN = 12265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_DISABLE_0_15 = 12266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_DISABLE_0_15_LEN = 12267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_0_01_DISABLE_16_23 = 12268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_0_01_DISABLE_16_23_LEN = 12269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_1_01_DISABLE_16_23 = 12270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_1_01_DISABLE_16_23_LEN = 12271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_0_01_DISABLE_16_23 = 12272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_0_01_DISABLE_16_23_LEN = 12273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_1_01_DISABLE_16_23 = 12274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_1_01_DISABLE_16_23_LEN = 12275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_2_23_DISABLE_16 = 12276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_2_23_DISABLE_16_LEN = 12277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_3_23_DISABLE_16 = 12278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_3_23_DISABLE_16_LEN = 12279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_2_23_DISABLE_16 = 12280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_2_23_DISABLE_16_LEN = 12281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_3_23_DISABLE_16 = 12282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_3_23_DISABLE_16_LEN = 12283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_4_DISABLE_16_23 = 12284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_4_DISABLE_16_23_LEN = 12285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_4_DISABLE_16_23 = 12286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P1_4_DISABLE_16_23_LEN = 12287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_0_01_DISABLE_16_23 = 12288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_0_01_DISABLE_16_23_LEN = 12289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_1_01_DISABLE_16_23 = 12290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_1_01_DISABLE_16_23_LEN = 12291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_0_01_DISABLE_16_23 = 12292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_0_01_DISABLE_16_23_LEN = 12293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_1_01_DISABLE_16_23 = 12294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_1_01_DISABLE_16_23_LEN = 12295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_2_23_DISABLE_16 = 12296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_2_23_DISABLE_16_LEN = 12297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_3_23_DISABLE_16 = 12298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_3_23_DISABLE_16_LEN = 12299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_2_23_DISABLE_16 = 12300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_2_23_DISABLE_16_LEN = 12301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_3_23_DISABLE_16 = 12302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_3_23_DISABLE_16_LEN = 12303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_4_DISABLE_16_23 = 12304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P0_4_DISABLE_16_23_LEN = 12305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_4_DISABLE_16_23 = 12306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP1_P1_4_DISABLE_16_23_LEN = 12307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_0_01_DISABLE_16_23 = 12308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_0_01_DISABLE_16_23_LEN = 12309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_1_01_DISABLE_16_23 = 12310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_1_01_DISABLE_16_23_LEN = 12311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_0_01_DISABLE_16_23 = 12312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_0_01_DISABLE_16_23_LEN = 12313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_1_01_DISABLE_16_23 = 12314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_1_01_DISABLE_16_23_LEN = 12315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_2_23_DISABLE_16 = 12316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_2_23_DISABLE_16_LEN = 12317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_3_23_DISABLE_16 = 12318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_3_23_DISABLE_16_LEN = 12319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_2_23_DISABLE_16 = 12320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_2_23_DISABLE_16_LEN = 12321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_3_23_DISABLE_16 = 12322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_3_23_DISABLE_16_LEN = 12323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_4_DISABLE_16_23 = 12324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P0_4_DISABLE_16_23_LEN = 12325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_4_DISABLE_16_23 = 12326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP2_P1_4_DISABLE_16_23_LEN = 12327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_0_01_DISABLE_16_23 = 12328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_0_01_DISABLE_16_23_LEN = 12329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_1_01_DISABLE_16_23 = 12330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_1_01_DISABLE_16_23_LEN = 12331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_0_01_DISABLE_16_23 = 12332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_0_01_DISABLE_16_23_LEN = 12333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_1_01_DISABLE_16_23 = 12334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_1_01_DISABLE_16_23_LEN = 12335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_2_23_DISABLE_16 = 12336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_2_23_DISABLE_16_LEN = 12337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_3_23_DISABLE_16 = 12338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_3_23_DISABLE_16_LEN = 12339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_2_23_DISABLE_16 = 12340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_2_23_DISABLE_16_LEN = 12341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_3_23_DISABLE_16 = 12342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_3_23_DISABLE_16_LEN = 12343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_4_DISABLE_16_23 = 12344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P0_4_DISABLE_16_23_LEN = 12345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_4_DISABLE_16_23 = 12346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE1_RP3_P1_4_DISABLE_16_23_LEN = 12347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0_01_ENABLE_15 = 12348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0_01_ENABLE_15_LEN = 12349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1_01_ENABLE_0_15 = 12350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1_01_ENABLE_0_15_LEN = 12351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0_01_ENABLE_15 = 12352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0_01_ENABLE_15_LEN = 12353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1_01_ENABLE_0_15 = 12354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1_01_ENABLE_0_15_LEN = 12355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2_23_ENABLE_0_15 = 12356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2_23_ENABLE_0_15_LEN = 12357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3_23_ENABLE_0_15 = 12358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3_23_ENABLE_0_15_LEN = 12359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2_23_ENABLE_0_15 = 12360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2_23_ENABLE_0_15_LEN = 12361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3_23_ENABLE_0_15 = 12362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3_23_ENABLE_0_15_LEN = 12363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4_ENABLE_0_15 = 12364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4_ENABLE_0_15_LEN = 12365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4_ENABLE_0_15 = 12366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4_ENABLE_0_15_LEN = 12367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_ENABLE_16_23 = 12368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_ENABLE_16_23_LEN = 12369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_DFT_FORCE_OUTPUTS = 12370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_DFT_PRBS7_GEN_EN = 12371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_WRAPSEL = 12372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_HW_VALUE = 12373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0 = 12374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1 = 12375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2 = 12376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N3 = 12377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_ENABLE_16_23 = 12378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_ENABLE_16_23_LEN = 12379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_DFT_FORCE_OUTPUTS = 12380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_DFT_PRBS7_GEN_EN = 12381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_WRAPSEL = 12382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_HW_VALUE = 12383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N0 = 12384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N1 = 12385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N2 = 12386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N3 = 12387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_ENABLE_16_23 = 12388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_ENABLE_16_23_LEN = 12389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_DFT_FORCE_OUTPUTS = 12390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_DFT_PRBS7_GEN_EN = 12391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_WRAPSEL = 12392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_HW_VALUE = 12393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_MRS_CMD_N0 = 12394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_MRS_CMD_N1 = 12395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_MRS_CMD_N2 = 12396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_01_MRS_CMD_N3 = 12397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_ENABLE_16_23 = 12398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_ENABLE_16_23_LEN = 12399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_DFT_FORCE_OUTPUTS = 12400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_DFT_PRBS7_GEN_EN = 12401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_WRAPSEL = 12402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_HW_VALUE = 12403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_MRS_CMD_N0 = 12404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_MRS_CMD_N1 = 12405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_MRS_CMD_N2 = 12406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_01_MRS_CMD_N3 = 12407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_ENABLE_16 = 12408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_ENABLE_16_LEN = 12409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_DFT_FORCE_OUTPUTS = 12410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_DFT_PRBS7_GEN_EN = 12411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_WRAPSEL = 12412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_HW_VALUE = 12413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N0 = 12414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N1 = 12415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N2 = 12416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N3 = 12417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_ENABLE_16 = 12418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_ENABLE_16_LEN = 12419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_DFT_FORCE_OUTPUTS = 12420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_DFT_PRBS7_GEN_EN = 12421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_WRAPSEL = 12422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_HW_VALUE = 12423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N0 = 12424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N1 = 12425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N2 = 12426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N3 = 12427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_ENABLE_16 = 12428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_ENABLE_16_LEN = 12429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_DFT_FORCE_OUTPUTS = 12430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_DFT_PRBS7_GEN_EN = 12431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_WRAPSEL = 12432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_HW_VALUE = 12433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_MRS_CMD_N0 = 12434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_MRS_CMD_N1 = 12435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_MRS_CMD_N2 = 12436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_23_MRS_CMD_N3 = 12437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_ENABLE_16 = 12438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_ENABLE_16_LEN = 12439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_DFT_FORCE_OUTPUTS = 12440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_DFT_PRBS7_GEN_EN = 12441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_WRAPSEL = 12442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_HW_VALUE = 12443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_MRS_CMD_N0 = 12444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_MRS_CMD_N1 = 12445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_MRS_CMD_N2 = 12446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_23_MRS_CMD_N3 = 12447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_ENABLE_16_23 = 12448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_ENABLE_16_23_LEN = 12449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_DFT_FORCE_OUTPUTS = 12450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_DFT_PRBS7_GEN_EN = 12451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_WRAPSEL = 12452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_HW_VALUE = 12453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_MRS_CMD_N0 = 12454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_MRS_CMD_N1 = 12455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_MRS_CMD_N2 = 12456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_MRS_CMD_N3 = 12457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_ENABLE_16_23 = 12458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_ENABLE_16_23_LEN = 12459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_DFT_FORCE_OUTPUTS = 12460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_DFT_PRBS7_GEN_EN = 12461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_WRAPSEL = 12462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_HW_VALUE = 12463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_MRS_CMD_N0 = 12464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_MRS_CMD_N1 = 12465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_MRS_CMD_N2 = 12466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_MRS_CMD_N3 = 12467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_HS_PROBE_A = 12468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_HS_PROBE_A_LEN = 12469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_HS_PROBE_B = 12470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_HS_PROBE_B_LEN = 12471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_RD = 12472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_RD_LEN = 12473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_WR = 12474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_0_01_WR_LEN = 12475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_HS_PROBE_A = 12476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_HS_PROBE_A_LEN = 12477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_HS_PROBE_B = 12478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_HS_PROBE_B_LEN = 12479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_RD = 12480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_RD_LEN = 12481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_WR = 12482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_1_01_WR_LEN = 12483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_HS_PROBE_A = 12484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_HS_PROBE_A_LEN = 12485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_HS_PROBE_B = 12486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_HS_PROBE_B_LEN = 12487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_RD = 12488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_RD_LEN = 12489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_WR = 12490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_0_01_WR_LEN = 12491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_HS_PROBE_A = 12492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_HS_PROBE_A_LEN = 12493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_HS_PROBE_B = 12494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_HS_PROBE_B_LEN = 12495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_RD = 12496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_RD_LEN = 12497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_WR = 12498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_1_01_WR_LEN = 12499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_HS_PROBE_A = 12500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_HS_PROBE_A_LEN = 12501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_HS_PROBE_B = 12502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_HS_PROBE_B_LEN = 12503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_RD = 12504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_RD_LEN = 12505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_WR = 12506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_2_23_WR_LEN = 12507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_HS_PROBE_A = 12508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_HS_PROBE_A_LEN = 12509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_HS_PROBE_B = 12510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_HS_PROBE_B_LEN = 12511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_RD = 12512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_RD_LEN = 12513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_WR = 12514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_3_23_WR_LEN = 12515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_HS_PROBE_A = 12516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_HS_PROBE_A_LEN = 12517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_HS_PROBE_B = 12518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_HS_PROBE_B_LEN = 12519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_RD = 12520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_RD_LEN = 12521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_WR = 12522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_2_23_WR_LEN = 12523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_HS_PROBE_A = 12524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_HS_PROBE_A_LEN = 12525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_HS_PROBE_B = 12526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_HS_PROBE_B_LEN = 12527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_RD = 12528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_RD_LEN = 12529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_WR = 12530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_3_23_WR_LEN = 12531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_HS_PROBE_A = 12532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_HS_PROBE_A_LEN = 12533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_HS_PROBE_B = 12534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_HS_PROBE_B_LEN = 12535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_RD = 12536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_RD_LEN = 12537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_WR = 12538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P0_4_WR_LEN = 12539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_HS_PROBE_A = 12540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_HS_PROBE_A_LEN = 12541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_HS_PROBE_B = 12542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_HS_PROBE_B_LEN = 12543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_RD = 12544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_RD_LEN = 12545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_WR = 12546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DEBUG_SEL_P1_4_WR_LEN = 12547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_0_01_DIGITAL_EN = 12548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_0_01_BUMP = 12549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_0_01_TRIG_PERIOD = 12550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_0_01_CNTL_POL = 12551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_0_01_CNTL_SRC = 12552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_1_01_DIGITAL_EN = 12553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_1_01_BUMP = 12554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_1_01_TRIG_PERIOD = 12555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_1_01_CNTL_POL = 12556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_1_01_CNTL_SRC = 12557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_0_01_DIGITAL_EN = 12558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_0_01_BUMP = 12559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_0_01_TRIG_PERIOD = 12560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_0_01_CNTL_POL = 12561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_0_01_CNTL_SRC = 12562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_1_01_DIGITAL_EN = 12563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_1_01_BUMP = 12564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_1_01_TRIG_PERIOD = 12565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_1_01_CNTL_POL = 12566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_1_01_CNTL_SRC = 12567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_2_23_DIGITAL_EN = 12568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_2_23_BUMP = 12569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_2_23_TRIG_PERIOD = 12570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_2_23_CNTL_POL = 12571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_2_23_CNTL_SRC = 12572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_3_23_DIGITAL_EN = 12573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_3_23_BUMP = 12574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_3_23_TRIG_PERIOD = 12575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_3_23_CNTL_POL = 12576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_3_23_CNTL_SRC = 12577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_2_23_DIGITAL_EN = 12578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_2_23_BUMP = 12579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_2_23_TRIG_PERIOD = 12580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_2_23_CNTL_POL = 12581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_2_23_CNTL_SRC = 12582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_3_23_DIGITAL_EN = 12583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_3_23_BUMP = 12584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_3_23_TRIG_PERIOD = 12585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_3_23_CNTL_POL = 12586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_3_23_CNTL_SRC = 12587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_4_DIGITAL_EN = 12588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_4_BUMP = 12589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_4_TRIG_PERIOD = 12590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_4_CNTL_POL = 12591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P0_4_CNTL_SRC = 12592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_4_DIGITAL_EN = 12593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_4_BUMP = 12594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_4_TRIG_PERIOD = 12595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_4_CNTL_POL = 12596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_DIG_EYE_P1_4_CNTL_SRC = 12597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_01_CHECKER_ENABLE = 12598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_01_CHECKER_RESET = 12599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_01_SYNC = 12600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_01_SYNC_LEN = 12601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_01_ERROR = 12602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_01_ERROR_LEN = 12603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_1_01_CHECKER_ENABLE = 12604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_1_01_CHECKER_RESET = 12605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_1_01_SYNC = 12606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_1_01_SYNC_LEN = 12607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_1_01_ERROR = 12608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_1_01_ERROR_LEN = 12609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_0_01_CHECKER_ENABLE = 12610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_0_01_CHECKER_RESET = 12611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_0_01_SYNC = 12612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_0_01_SYNC_LEN = 12613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_0_01_ERROR = 12614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_0_01_ERROR_LEN = 12615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_1_01_CHECKER_ENABLE = 12616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_1_01_CHECKER_RESET = 12617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_1_01_SYNC = 12618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_1_01_SYNC_LEN = 12619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_1_01_ERROR = 12620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_1_01_ERROR_LEN = 12621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_2_23_CHECKER_ENABLE = 12622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_2_23_CHECKER_RESET = 12623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_2_23_SYNC = 12624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_2_23_SYNC_LEN = 12625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_2_23_ERROR = 12626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_2_23_ERROR_LEN = 12627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_3_23_CHECKER_ENABLE = 12628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_3_23_CHECKER_RESET = 12629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_3_23_SYNC = 12630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_3_23_SYNC_LEN = 12631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_3_23_ERROR = 12632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_3_23_ERROR_LEN = 12633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_2_23_CHECKER_ENABLE = 12634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_2_23_CHECKER_RESET = 12635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_2_23_SYNC = 12636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_2_23_SYNC_LEN = 12637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_2_23_ERROR = 12638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_2_23_ERROR_LEN = 12639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_23_CHECKER_ENABLE = 12640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_23_CHECKER_RESET = 12641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_23_SYNC = 12642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_23_SYNC_LEN = 12643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_23_ERROR = 12644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_23_ERROR_LEN = 12645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_4_CHECKER_ENABLE = 12646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_4_CHECKER_RESET = 12647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_4_SYNC = 12648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_4_SYNC_LEN = 12649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_4_ERROR = 12650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P0_4_ERROR_LEN = 12651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_CHECKER_ENABLE = 12652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_CHECKER_RESET = 12653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_SYNC = 12654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_SYNC_LEN = 12655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_ERROR = 12656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_ERROR_LEN = 12657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_01_DQS = 12658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_01_DQS_LEN = 12659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_01_DQS = 12660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_01_DQS_LEN = 12661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_01_DQS = 12662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_01_DQS_LEN = 12663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_01_DQS = 12664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_01_DQS_LEN = 12665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_23_DQS = 12666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_23_DQS_LEN = 12667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_23_DQS = 12668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_23_DQS_LEN = 12669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_23_DQS = 12670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_23_DQS_LEN = 12671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_23_DQS = 12672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_23_DQS_LEN = 12673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_DQS = 12674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_DQS_LEN = 12675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_4_DQS = 12676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_OFFSET_P1_4_DQS_LEN = 12677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0 = 12678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN = 12679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1 = 12680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN = 12681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0 = 12682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN = 12683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1 = 12684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN = 12685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_0_01_ROT_CLK_N0 = 12686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_0_01_ROT_CLK_N0_LEN = 12687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_0_01_ROT_CLK_N1 = 12688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_0_01_ROT_CLK_N1_LEN = 12689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_1_01_ROT_CLK_N0 = 12690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_1_01_ROT_CLK_N0_LEN = 12691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_1_01_ROT_CLK_N1 = 12692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_1_01_ROT_CLK_N1_LEN = 12693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0 = 12694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN = 12695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1 = 12696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN = 12697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0 = 12698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN = 12699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1 = 12700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN = 12701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_2_23_ROT_CLK_N0 = 12702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_2_23_ROT_CLK_N0_LEN = 12703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_2_23_ROT_CLK_N1 = 12704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_2_23_ROT_CLK_N1_LEN = 12705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_3_23_ROT_CLK_N0 = 12706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_3_23_ROT_CLK_N0_LEN = 12707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_3_23_ROT_CLK_N1 = 12708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_3_23_ROT_CLK_N1_LEN = 12709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_4_ROT_CLK_N0 = 12710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_4_ROT_CLK_N0_LEN = 12711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_4_ROT_CLK_N1 = 12712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_4_ROT_CLK_N1_LEN = 12713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_4_ROT_CLK_N0 = 12714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_4_ROT_CLK_N0_LEN = 12715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_4_ROT_CLK_N1 = 12716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_4_ROT_CLK_N1_LEN = 12717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0 = 12718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN = 12719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1 = 12720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN = 12721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0 = 12722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN = 12723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1 = 12724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN = 12725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_0_01_ROT_CLK_N0 = 12726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_0_01_ROT_CLK_N0_LEN = 12727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_0_01_ROT_CLK_N1 = 12728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_0_01_ROT_CLK_N1_LEN = 12729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_1_01_ROT_CLK_N0 = 12730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_1_01_ROT_CLK_N0_LEN = 12731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_1_01_ROT_CLK_N1 = 12732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_1_01_ROT_CLK_N1_LEN = 12733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0 = 12734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN = 12735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1 = 12736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN = 12737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0 = 12738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN = 12739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1 = 12740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN = 12741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_2_23_ROT_CLK_N0 = 12742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_2_23_ROT_CLK_N0_LEN = 12743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_2_23_ROT_CLK_N1 = 12744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_2_23_ROT_CLK_N1_LEN = 12745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_3_23_ROT_CLK_N0 = 12746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_3_23_ROT_CLK_N0_LEN = 12747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_3_23_ROT_CLK_N1 = 12748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_3_23_ROT_CLK_N1_LEN = 12749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_4_ROT_CLK_N0 = 12750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_4_ROT_CLK_N0_LEN = 12751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_4_ROT_CLK_N1 = 12752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P0_4_ROT_CLK_N1_LEN = 12753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_4_ROT_CLK_N0 = 12754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_4_ROT_CLK_N0_LEN = 12755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_4_ROT_CLK_N1 = 12756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR1_P1_4_ROT_CLK_N1_LEN = 12757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0 = 12758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN = 12759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1 = 12760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN = 12761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0 = 12762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN = 12763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1 = 12764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN = 12765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_0_01_ROT_CLK_N0 = 12766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_0_01_ROT_CLK_N0_LEN = 12767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_0_01_ROT_CLK_N1 = 12768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_0_01_ROT_CLK_N1_LEN = 12769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_1_01_ROT_CLK_N0 = 12770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_1_01_ROT_CLK_N0_LEN = 12771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_1_01_ROT_CLK_N1 = 12772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_1_01_ROT_CLK_N1_LEN = 12773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0 = 12774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN = 12775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1 = 12776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN = 12777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0 = 12778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN = 12779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1 = 12780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN = 12781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_2_23_ROT_CLK_N0 = 12782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_2_23_ROT_CLK_N0_LEN = 12783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_2_23_ROT_CLK_N1 = 12784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_2_23_ROT_CLK_N1_LEN = 12785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_3_23_ROT_CLK_N0 = 12786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_3_23_ROT_CLK_N0_LEN = 12787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_3_23_ROT_CLK_N1 = 12788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_3_23_ROT_CLK_N1_LEN = 12789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_4_ROT_CLK_N0 = 12790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_4_ROT_CLK_N0_LEN = 12791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_4_ROT_CLK_N1 = 12792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P0_4_ROT_CLK_N1_LEN = 12793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_4_ROT_CLK_N0 = 12794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_4_ROT_CLK_N0_LEN = 12795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_4_ROT_CLK_N1 = 12796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR2_P1_4_ROT_CLK_N1_LEN = 12797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0 = 12798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN = 12799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1 = 12800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN = 12801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0 = 12802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN = 12803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1 = 12804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN = 12805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_0_01_ROT_CLK_N0 = 12806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_0_01_ROT_CLK_N0_LEN = 12807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_0_01_ROT_CLK_N1 = 12808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_0_01_ROT_CLK_N1_LEN = 12809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_1_01_ROT_CLK_N0 = 12810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_1_01_ROT_CLK_N0_LEN = 12811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_1_01_ROT_CLK_N1 = 12812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_1_01_ROT_CLK_N1_LEN = 12813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0 = 12814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN = 12815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1 = 12816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN = 12817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0 = 12818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN = 12819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1 = 12820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN = 12821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_2_23_ROT_CLK_N0 = 12822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_2_23_ROT_CLK_N0_LEN = 12823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_2_23_ROT_CLK_N1 = 12824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_2_23_ROT_CLK_N1_LEN = 12825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_3_23_ROT_CLK_N0 = 12826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_3_23_ROT_CLK_N0_LEN = 12827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_3_23_ROT_CLK_N1 = 12828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_3_23_ROT_CLK_N1_LEN = 12829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_4_ROT_CLK_N0 = 12830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_4_ROT_CLK_N0_LEN = 12831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_4_ROT_CLK_N1 = 12832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P0_4_ROT_CLK_N1_LEN = 12833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_4_ROT_CLK_N0 = 12834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_4_ROT_CLK_N0_LEN = 12835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_4_ROT_CLK_N1 = 12836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR3_P1_4_ROT_CLK_N1_LEN = 12837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0 = 12838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN = 12839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1 = 12840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN = 12841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0 = 12842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN = 12843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1 = 12844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN = 12845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_0_01_ROT_CLK_N0 = 12846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_0_01_ROT_CLK_N0_LEN = 12847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_0_01_ROT_CLK_N1 = 12848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_0_01_ROT_CLK_N1_LEN = 12849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_1_01_ROT_CLK_N0 = 12850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_1_01_ROT_CLK_N0_LEN = 12851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_1_01_ROT_CLK_N1 = 12852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_1_01_ROT_CLK_N1_LEN = 12853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0 = 12854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN = 12855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1 = 12856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN = 12857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0 = 12858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN = 12859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1 = 12860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN = 12861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_2_23_ROT_CLK_N0 = 12862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_2_23_ROT_CLK_N0_LEN = 12863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_2_23_ROT_CLK_N1 = 12864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_2_23_ROT_CLK_N1_LEN = 12865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_3_23_ROT_CLK_N0 = 12866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_3_23_ROT_CLK_N0_LEN = 12867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_3_23_ROT_CLK_N1 = 12868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_3_23_ROT_CLK_N1_LEN = 12869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_4_ROT_CLK_N0 = 12870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_4_ROT_CLK_N0_LEN = 12871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_4_ROT_CLK_N1 = 12872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_4_ROT_CLK_N1_LEN = 12873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_4_ROT_CLK_N0 = 12874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_4_ROT_CLK_N0_LEN = 12875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_4_ROT_CLK_N1 = 12876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_4_ROT_CLK_N1_LEN = 12877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0 = 12878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN = 12879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1 = 12880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN = 12881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0 = 12882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN = 12883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1 = 12884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN = 12885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_0_01_ROT_CLK_N0 = 12886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_0_01_ROT_CLK_N0_LEN = 12887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_0_01_ROT_CLK_N1 = 12888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_0_01_ROT_CLK_N1_LEN = 12889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_1_01_ROT_CLK_N0 = 12890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_1_01_ROT_CLK_N0_LEN = 12891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_1_01_ROT_CLK_N1 = 12892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_1_01_ROT_CLK_N1_LEN = 12893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0 = 12894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN = 12895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1 = 12896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN = 12897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0 = 12898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN = 12899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1 = 12900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN = 12901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_2_23_ROT_CLK_N0 = 12902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_2_23_ROT_CLK_N0_LEN = 12903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_2_23_ROT_CLK_N1 = 12904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_2_23_ROT_CLK_N1_LEN = 12905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_3_23_ROT_CLK_N0 = 12906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_3_23_ROT_CLK_N0_LEN = 12907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_3_23_ROT_CLK_N1 = 12908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_3_23_ROT_CLK_N1_LEN = 12909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_4_ROT_CLK_N0 = 12910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_4_ROT_CLK_N0_LEN = 12911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_4_ROT_CLK_N1 = 12912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P0_4_ROT_CLK_N1_LEN = 12913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_4_ROT_CLK_N0 = 12914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_4_ROT_CLK_N0_LEN = 12915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_4_ROT_CLK_N1 = 12916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR1_P1_4_ROT_CLK_N1_LEN = 12917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0 = 12918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN = 12919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1 = 12920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN = 12921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0 = 12922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN = 12923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1 = 12924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN = 12925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_0_01_ROT_CLK_N0 = 12926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_0_01_ROT_CLK_N0_LEN = 12927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_0_01_ROT_CLK_N1 = 12928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_0_01_ROT_CLK_N1_LEN = 12929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_1_01_ROT_CLK_N0 = 12930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_1_01_ROT_CLK_N0_LEN = 12931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_1_01_ROT_CLK_N1 = 12932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_1_01_ROT_CLK_N1_LEN = 12933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0 = 12934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN = 12935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1 = 12936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN = 12937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0 = 12938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN = 12939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1 = 12940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN = 12941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_2_23_ROT_CLK_N0 = 12942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_2_23_ROT_CLK_N0_LEN = 12943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_2_23_ROT_CLK_N1 = 12944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_2_23_ROT_CLK_N1_LEN = 12945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_3_23_ROT_CLK_N0 = 12946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_3_23_ROT_CLK_N0_LEN = 12947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_3_23_ROT_CLK_N1 = 12948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_3_23_ROT_CLK_N1_LEN = 12949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_4_ROT_CLK_N0 = 12950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_4_ROT_CLK_N0_LEN = 12951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_4_ROT_CLK_N1 = 12952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P0_4_ROT_CLK_N1_LEN = 12953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_4_ROT_CLK_N0 = 12954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_4_ROT_CLK_N0_LEN = 12955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_4_ROT_CLK_N1 = 12956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR2_P1_4_ROT_CLK_N1_LEN = 12957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0 = 12958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN = 12959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1 = 12960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN = 12961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0 = 12962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN = 12963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1 = 12964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN = 12965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_0_01_ROT_CLK_N0 = 12966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_0_01_ROT_CLK_N0_LEN = 12967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_0_01_ROT_CLK_N1 = 12968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_0_01_ROT_CLK_N1_LEN = 12969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_1_01_ROT_CLK_N0 = 12970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_1_01_ROT_CLK_N0_LEN = 12971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_1_01_ROT_CLK_N1 = 12972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_1_01_ROT_CLK_N1_LEN = 12973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0 = 12974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN = 12975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1 = 12976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN = 12977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0 = 12978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN = 12979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1 = 12980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN = 12981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_2_23_ROT_CLK_N0 = 12982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_2_23_ROT_CLK_N0_LEN = 12983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_2_23_ROT_CLK_N1 = 12984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_2_23_ROT_CLK_N1_LEN = 12985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_3_23_ROT_CLK_N0 = 12986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_3_23_ROT_CLK_N0_LEN = 12987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_3_23_ROT_CLK_N1 = 12988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_3_23_ROT_CLK_N1_LEN = 12989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_4_ROT_CLK_N0 = 12990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_4_ROT_CLK_N0_LEN = 12991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_4_ROT_CLK_N1 = 12992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P0_4_ROT_CLK_N1_LEN = 12993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_4_ROT_CLK_N0 = 12994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_4_ROT_CLK_N0_LEN = 12995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_4_ROT_CLK_N1 = 12996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR3_P1_4_ROT_CLK_N1_LEN = 12997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N0 = 12998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N0_LEN = 12999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N1 = 13000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N1_LEN = 13001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N2 = 13002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N2_LEN = 13003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N3 = 13004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0_01_N3_LEN = 13005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N0 = 13006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N0_LEN = 13007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N1 = 13008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N1_LEN = 13009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N2 = 13010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N2_LEN = 13011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N3 = 13012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_1_01_N3_LEN = 13013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N0 = 13014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N0_LEN = 13015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N1 = 13016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N1_LEN = 13017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N2 = 13018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N2_LEN = 13019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N3 = 13020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_0_01_N3_LEN = 13021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N0 = 13022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N0_LEN = 13023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N1 = 13024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N1_LEN = 13025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N2 = 13026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N2_LEN = 13027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N3 = 13028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_1_01_N3_LEN = 13029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N0 = 13030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N0_LEN = 13031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N1 = 13032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N1_LEN = 13033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N2 = 13034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N2_LEN = 13035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N3 = 13036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_2_23_N3_LEN = 13037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N0 = 13038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N0_LEN = 13039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N1 = 13040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N1_LEN = 13041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N2 = 13042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N2_LEN = 13043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N3 = 13044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_3_23_N3_LEN = 13045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N0 = 13046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N0_LEN = 13047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N1 = 13048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N1_LEN = 13049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N2 = 13050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N2_LEN = 13051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N3 = 13052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_2_23_N3_LEN = 13053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N0 = 13054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N0_LEN = 13055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N1 = 13056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N1_LEN = 13057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N2 = 13058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N2_LEN = 13059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N3 = 13060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_3_23_N3_LEN = 13061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N0 = 13062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N0_LEN = 13063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N1 = 13064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N1_LEN = 13065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N2 = 13066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N2_LEN = 13067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N3 = 13068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_4_N3_LEN = 13069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N0 = 13070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N0_LEN = 13071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N1 = 13072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N1_LEN = 13073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N2 = 13074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N2_LEN = 13075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N3 = 13076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P1_4_N3_LEN = 13077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N0 = 13078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N0_LEN = 13079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N1 = 13080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N1_LEN = 13081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N2 = 13082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N2_LEN = 13083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N3 = 13084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_0_01_N3_LEN = 13085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N0 = 13086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N0_LEN = 13087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N1 = 13088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N1_LEN = 13089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N2 = 13090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N2_LEN = 13091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N3 = 13092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_1_01_N3_LEN = 13093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N0 = 13094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N0_LEN = 13095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N1 = 13096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N1_LEN = 13097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N2 = 13098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N2_LEN = 13099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N3 = 13100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_0_01_N3_LEN = 13101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N0 = 13102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N0_LEN = 13103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N1 = 13104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N1_LEN = 13105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N2 = 13106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N2_LEN = 13107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N3 = 13108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_1_01_N3_LEN = 13109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N0 = 13110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N0_LEN = 13111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N1 = 13112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N1_LEN = 13113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N2 = 13114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N2_LEN = 13115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N3 = 13116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_2_23_N3_LEN = 13117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N0 = 13118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N0_LEN = 13119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N1 = 13120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N1_LEN = 13121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N2 = 13122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N2_LEN = 13123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N3 = 13124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_3_23_N3_LEN = 13125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N0 = 13126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N0_LEN = 13127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N1 = 13128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N1_LEN = 13129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N2 = 13130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N2_LEN = 13131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N3 = 13132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_2_23_N3_LEN = 13133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N0 = 13134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N0_LEN = 13135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N1 = 13136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N1_LEN = 13137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N2 = 13138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N2_LEN = 13139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N3 = 13140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_3_23_N3_LEN = 13141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N0 = 13142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N0_LEN = 13143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N1 = 13144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N1_LEN = 13145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N2 = 13146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N2_LEN = 13147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N3 = 13148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P0_4_N3_LEN = 13149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N0 = 13150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N0_LEN = 13151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N1 = 13152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N1_LEN = 13153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N2 = 13154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N2_LEN = 13155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N3 = 13156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP1_P1_4_N3_LEN = 13157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N0 = 13158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N0_LEN = 13159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N1 = 13160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N1_LEN = 13161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N2 = 13162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N2_LEN = 13163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N3 = 13164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_0_01_N3_LEN = 13165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N0 = 13166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N0_LEN = 13167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N1 = 13168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N1_LEN = 13169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N2 = 13170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N2_LEN = 13171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N3 = 13172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_1_01_N3_LEN = 13173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N0 = 13174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N0_LEN = 13175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N1 = 13176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N1_LEN = 13177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N2 = 13178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N2_LEN = 13179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N3 = 13180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_0_01_N3_LEN = 13181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N0 = 13182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N0_LEN = 13183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N1 = 13184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N1_LEN = 13185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N2 = 13186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N2_LEN = 13187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N3 = 13188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_1_01_N3_LEN = 13189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N0 = 13190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N0_LEN = 13191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N1 = 13192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N1_LEN = 13193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N2 = 13194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N2_LEN = 13195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N3 = 13196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_2_23_N3_LEN = 13197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N0 = 13198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N0_LEN = 13199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N1 = 13200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N1_LEN = 13201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N2 = 13202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N2_LEN = 13203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N3 = 13204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_3_23_N3_LEN = 13205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N0 = 13206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N0_LEN = 13207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N1 = 13208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N1_LEN = 13209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N2 = 13210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N2_LEN = 13211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N3 = 13212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_2_23_N3_LEN = 13213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N0 = 13214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N0_LEN = 13215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N1 = 13216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N1_LEN = 13217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N2 = 13218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N2_LEN = 13219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N3 = 13220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_3_23_N3_LEN = 13221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N0 = 13222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N0_LEN = 13223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N1 = 13224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N1_LEN = 13225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N2 = 13226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N2_LEN = 13227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N3 = 13228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P0_4_N3_LEN = 13229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N0 = 13230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N0_LEN = 13231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N1 = 13232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N1_LEN = 13233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N2 = 13234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N2_LEN = 13235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N3 = 13236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP2_P1_4_N3_LEN = 13237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N0 = 13238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N0_LEN = 13239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N1 = 13240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N1_LEN = 13241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N2 = 13242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N2_LEN = 13243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N3 = 13244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_0_01_N3_LEN = 13245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N0 = 13246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N0_LEN = 13247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N1 = 13248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N1_LEN = 13249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N2 = 13250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N2_LEN = 13251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N3 = 13252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_1_01_N3_LEN = 13253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N0 = 13254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N0_LEN = 13255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N1 = 13256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N1_LEN = 13257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N2 = 13258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N2_LEN = 13259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N3 = 13260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_0_01_N3_LEN = 13261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N0 = 13262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N0_LEN = 13263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N1 = 13264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N1_LEN = 13265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N2 = 13266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N2_LEN = 13267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N3 = 13268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_1_01_N3_LEN = 13269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N0 = 13270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N0_LEN = 13271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N1 = 13272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N1_LEN = 13273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N2 = 13274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N2_LEN = 13275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N3 = 13276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_2_23_N3_LEN = 13277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N0 = 13278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N0_LEN = 13279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N1 = 13280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N1_LEN = 13281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N2 = 13282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N2_LEN = 13283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N3 = 13284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_3_23_N3_LEN = 13285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N0 = 13286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N0_LEN = 13287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N1 = 13288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N1_LEN = 13289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N2 = 13290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N2_LEN = 13291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N3 = 13292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_2_23_N3_LEN = 13293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N0 = 13294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N0_LEN = 13295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N1 = 13296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N1_LEN = 13297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N2 = 13298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N2_LEN = 13299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N3 = 13300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_3_23_N3_LEN = 13301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N0 = 13302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N0_LEN = 13303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N1 = 13304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N1_LEN = 13305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N2 = 13306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N2_LEN = 13307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N3 = 13308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P0_4_N3_LEN = 13309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N0 = 13310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N0_LEN = 13311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N1 = 13312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N1_LEN = 13313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N2 = 13314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N2_LEN = 13315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N3 = 13316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_GATE_DELAY_RP3_P1_4_N3_LEN = 13317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0 = 13318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0_LEN = 13319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0 = 13320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0_LEN = 13321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1 = 13322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1_LEN = 13323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1 = 13324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1_LEN = 13325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2 = 13326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2_LEN = 13327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2 = 13328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2_LEN = 13329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3 = 13330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3_LEN = 13331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3 = 13332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3_LEN = 13333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0 = 13334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0_LEN = 13335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0 = 13336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0_LEN = 13337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1 = 13338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1_LEN = 13339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1 = 13340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1_LEN = 13341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2 = 13342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2_LEN = 13343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2 = 13344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2_LEN = 13345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3 = 13346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3_LEN = 13347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3 = 13348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3_LEN = 13349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT0 = 13350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT0_LEN = 13351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT0 = 13352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT0_LEN = 13353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT1 = 13354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT1_LEN = 13355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT1 = 13356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT1_LEN = 13357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT2 = 13358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT2_LEN = 13359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT2 = 13360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT2_LEN = 13361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT3 = 13362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_DQSCLK_SELECT3_LEN = 13363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT3 = 13364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_01_RDCLK_SELECT3_LEN = 13365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT0 = 13366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT0_LEN = 13367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT0 = 13368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT0_LEN = 13369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT1 = 13370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT1_LEN = 13371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT1 = 13372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT1_LEN = 13373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT2 = 13374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT2_LEN = 13375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT2 = 13376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT2_LEN = 13377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT3 = 13378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_DQSCLK_SELECT3_LEN = 13379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT3 = 13380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_01_RDCLK_SELECT3_LEN = 13381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0 = 13382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0_LEN = 13383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0 = 13384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0_LEN = 13385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1 = 13386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1_LEN = 13387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1 = 13388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1_LEN = 13389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2 = 13390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2_LEN = 13391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2 = 13392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2_LEN = 13393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3 = 13394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3_LEN = 13395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3 = 13396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3_LEN = 13397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0 = 13398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0_LEN = 13399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0 = 13400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0_LEN = 13401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1 = 13402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1_LEN = 13403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1 = 13404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1_LEN = 13405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2 = 13406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2_LEN = 13407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2 = 13408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2_LEN = 13409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3 = 13410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3_LEN = 13411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3 = 13412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3_LEN = 13413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT0 = 13414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT0_LEN = 13415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT0 = 13416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT0_LEN = 13417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT1 = 13418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT1_LEN = 13419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT1 = 13420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT1_LEN = 13421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT2 = 13422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT2_LEN = 13423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT2 = 13424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT2_LEN = 13425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT3 = 13426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_DQSCLK_SELECT3_LEN = 13427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT3 = 13428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_23_RDCLK_SELECT3_LEN = 13429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT0 = 13430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT0_LEN = 13431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT0 = 13432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT0_LEN = 13433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT1 = 13434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT1_LEN = 13435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT1 = 13436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT1_LEN = 13437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT2 = 13438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT2_LEN = 13439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT2 = 13440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT2_LEN = 13441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT3 = 13442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_DQSCLK_SELECT3_LEN = 13443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT3 = 13444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_23_RDCLK_SELECT3_LEN = 13445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT0 = 13446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT0_LEN = 13447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT0 = 13448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT0_LEN = 13449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT1 = 13450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT1_LEN = 13451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT1 = 13452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT1_LEN = 13453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT2 = 13454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT2_LEN = 13455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT2 = 13456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT2_LEN = 13457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT3 = 13458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_DQSCLK_SELECT3_LEN = 13459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT3 = 13460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_RDCLK_SELECT3_LEN = 13461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT0 = 13462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT0_LEN = 13463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT0 = 13464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT0_LEN = 13465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT1 = 13466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT1_LEN = 13467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT1 = 13468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT1_LEN = 13469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT2 = 13470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT2_LEN = 13471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT2 = 13472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT2_LEN = 13473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT3 = 13474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_DQSCLK_SELECT3_LEN = 13475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT3 = 13476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_RDCLK_SELECT3_LEN = 13477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0 = 13478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0_LEN = 13479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0 = 13480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0_LEN = 13481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1 = 13482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1_LEN = 13483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1 = 13484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1_LEN = 13485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2 = 13486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2_LEN = 13487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2 = 13488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2_LEN = 13489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3 = 13490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3_LEN = 13491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3 = 13492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3_LEN = 13493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0 = 13494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0_LEN = 13495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0 = 13496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0_LEN = 13497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1 = 13498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1_LEN = 13499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1 = 13500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1_LEN = 13501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2 = 13502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2_LEN = 13503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2 = 13504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2_LEN = 13505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3 = 13506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3_LEN = 13507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3 = 13508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3_LEN = 13509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT0 = 13510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT0_LEN = 13511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT0 = 13512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT0_LEN = 13513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT1 = 13514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT1_LEN = 13515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT1 = 13516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT1_LEN = 13517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT2 = 13518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT2_LEN = 13519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT2 = 13520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT2_LEN = 13521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT3 = 13522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_DQSCLK_SELECT3_LEN = 13523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT3 = 13524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_01_RDCLK_SELECT3_LEN = 13525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT0 = 13526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT0_LEN = 13527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT0 = 13528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT0_LEN = 13529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT1 = 13530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT1_LEN = 13531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT1 = 13532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT1_LEN = 13533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT2 = 13534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT2_LEN = 13535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT2 = 13536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT2_LEN = 13537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT3 = 13538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_DQSCLK_SELECT3_LEN = 13539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT3 = 13540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_01_RDCLK_SELECT3_LEN = 13541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0 = 13542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0_LEN = 13543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0 = 13544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0_LEN = 13545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1 = 13546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1_LEN = 13547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1 = 13548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1_LEN = 13549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2 = 13550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2_LEN = 13551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2 = 13552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2_LEN = 13553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3 = 13554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3_LEN = 13555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3 = 13556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3_LEN = 13557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0 = 13558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0_LEN = 13559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0 = 13560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0_LEN = 13561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1 = 13562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1_LEN = 13563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1 = 13564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1_LEN = 13565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2 = 13566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2_LEN = 13567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2 = 13568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2_LEN = 13569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3 = 13570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3_LEN = 13571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3 = 13572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3_LEN = 13573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT0 = 13574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT0_LEN = 13575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT0 = 13576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT0_LEN = 13577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT1 = 13578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT1_LEN = 13579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT1 = 13580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT1_LEN = 13581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT2 = 13582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT2_LEN = 13583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT2 = 13584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT2_LEN = 13585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT3 = 13586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_DQSCLK_SELECT3_LEN = 13587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT3 = 13588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_23_RDCLK_SELECT3_LEN = 13589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT0 = 13590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT0_LEN = 13591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT0 = 13592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT0_LEN = 13593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT1 = 13594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT1_LEN = 13595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT1 = 13596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT1_LEN = 13597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT2 = 13598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT2_LEN = 13599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT2 = 13600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT2_LEN = 13601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT3 = 13602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_DQSCLK_SELECT3_LEN = 13603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT3 = 13604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_23_RDCLK_SELECT3_LEN = 13605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT0 = 13606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT0_LEN = 13607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT0 = 13608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT0_LEN = 13609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT1 = 13610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT1_LEN = 13611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT1 = 13612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT1_LEN = 13613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT2 = 13614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT2_LEN = 13615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT2 = 13616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT2_LEN = 13617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT3 = 13618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_DQSCLK_SELECT3_LEN = 13619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT3 = 13620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_RDCLK_SELECT3_LEN = 13621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT0 = 13622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT0_LEN = 13623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT0 = 13624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT0_LEN = 13625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT1 = 13626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT1_LEN = 13627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT1 = 13628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT1_LEN = 13629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT2 = 13630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT2_LEN = 13631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT2 = 13632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT2_LEN = 13633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT3 = 13634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_DQSCLK_SELECT3_LEN = 13635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT3 = 13636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_RDCLK_SELECT3_LEN = 13637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0 = 13638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0_LEN = 13639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0 = 13640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0_LEN = 13641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1 = 13642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1_LEN = 13643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1 = 13644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1_LEN = 13645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2 = 13646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2_LEN = 13647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2 = 13648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2_LEN = 13649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3 = 13650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3_LEN = 13651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3 = 13652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3_LEN = 13653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0 = 13654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0_LEN = 13655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0 = 13656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0_LEN = 13657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1 = 13658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1_LEN = 13659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1 = 13660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1_LEN = 13661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2 = 13662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2_LEN = 13663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2 = 13664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2_LEN = 13665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3 = 13666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3_LEN = 13667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3 = 13668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3_LEN = 13669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT0 = 13670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT0_LEN = 13671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT0 = 13672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT0_LEN = 13673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT1 = 13674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT1_LEN = 13675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT1 = 13676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT1_LEN = 13677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT2 = 13678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT2_LEN = 13679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT2 = 13680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT2_LEN = 13681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT3 = 13682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_DQSCLK_SELECT3_LEN = 13683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT3 = 13684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_01_RDCLK_SELECT3_LEN = 13685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT0 = 13686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT0_LEN = 13687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT0 = 13688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT0_LEN = 13689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT1 = 13690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT1_LEN = 13691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT1 = 13692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT1_LEN = 13693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT2 = 13694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT2_LEN = 13695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT2 = 13696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT2_LEN = 13697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT3 = 13698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_DQSCLK_SELECT3_LEN = 13699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT3 = 13700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_01_RDCLK_SELECT3_LEN = 13701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0 = 13702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0_LEN = 13703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0 = 13704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0_LEN = 13705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1 = 13706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1_LEN = 13707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1 = 13708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1_LEN = 13709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2 = 13710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2_LEN = 13711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2 = 13712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2_LEN = 13713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3 = 13714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3_LEN = 13715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3 = 13716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3_LEN = 13717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0 = 13718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0_LEN = 13719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0 = 13720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0_LEN = 13721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1 = 13722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1_LEN = 13723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1 = 13724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1_LEN = 13725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2 = 13726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2_LEN = 13727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2 = 13728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2_LEN = 13729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3 = 13730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3_LEN = 13731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3 = 13732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3_LEN = 13733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT0 = 13734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT0_LEN = 13735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT0 = 13736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT0_LEN = 13737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT1 = 13738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT1_LEN = 13739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT1 = 13740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT1_LEN = 13741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT2 = 13742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT2_LEN = 13743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT2 = 13744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT2_LEN = 13745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT3 = 13746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_DQSCLK_SELECT3_LEN = 13747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT3 = 13748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_23_RDCLK_SELECT3_LEN = 13749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT0 = 13750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT0_LEN = 13751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT0 = 13752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT0_LEN = 13753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT1 = 13754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT1_LEN = 13755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT1 = 13756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT1_LEN = 13757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT2 = 13758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT2_LEN = 13759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT2 = 13760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT2_LEN = 13761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT3 = 13762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_DQSCLK_SELECT3_LEN = 13763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT3 = 13764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_23_RDCLK_SELECT3_LEN = 13765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT0 = 13766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT0_LEN = 13767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT0 = 13768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT0_LEN = 13769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT1 = 13770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT1_LEN = 13771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT1 = 13772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT1_LEN = 13773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT2 = 13774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT2_LEN = 13775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT2 = 13776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT2_LEN = 13777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT3 = 13778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_DQSCLK_SELECT3_LEN = 13779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT3 = 13780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_RDCLK_SELECT3_LEN = 13781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT0 = 13782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT0_LEN = 13783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT0 = 13784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT0_LEN = 13785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT1 = 13786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT1_LEN = 13787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT1 = 13788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT1_LEN = 13789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT2 = 13790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT2_LEN = 13791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT2 = 13792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT2_LEN = 13793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT3 = 13794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_DQSCLK_SELECT3_LEN = 13795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT3 = 13796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_RDCLK_SELECT3_LEN = 13797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0 = 13798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0_LEN = 13799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0 = 13800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0_LEN = 13801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1 = 13802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1_LEN = 13803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1 = 13804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1_LEN = 13805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2 = 13806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2_LEN = 13807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2 = 13808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2_LEN = 13809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3 = 13810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3_LEN = 13811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3 = 13812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3_LEN = 13813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0 = 13814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0_LEN = 13815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0 = 13816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0_LEN = 13817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1 = 13818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1_LEN = 13819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1 = 13820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1_LEN = 13821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2 = 13822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2_LEN = 13823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2 = 13824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2_LEN = 13825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3 = 13826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3_LEN = 13827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3 = 13828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3_LEN = 13829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT0 = 13830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT0_LEN = 13831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT0 = 13832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT0_LEN = 13833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT1 = 13834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT1_LEN = 13835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT1 = 13836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT1_LEN = 13837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT2 = 13838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT2_LEN = 13839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT2 = 13840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT2_LEN = 13841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT3 = 13842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_DQSCLK_SELECT3_LEN = 13843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT3 = 13844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_01_RDCLK_SELECT3_LEN = 13845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT0 = 13846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT0_LEN = 13847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT0 = 13848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT0_LEN = 13849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT1 = 13850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT1_LEN = 13851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT1 = 13852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT1_LEN = 13853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT2 = 13854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT2_LEN = 13855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT2 = 13856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT2_LEN = 13857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT3 = 13858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_DQSCLK_SELECT3_LEN = 13859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT3 = 13860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_01_RDCLK_SELECT3_LEN = 13861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0 = 13862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0_LEN = 13863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0 = 13864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0_LEN = 13865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1 = 13866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1_LEN = 13867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1 = 13868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1_LEN = 13869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2 = 13870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2_LEN = 13871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2 = 13872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2_LEN = 13873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3 = 13874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3_LEN = 13875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3 = 13876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3_LEN = 13877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0 = 13878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0_LEN = 13879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0 = 13880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0_LEN = 13881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1 = 13882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1_LEN = 13883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1 = 13884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1_LEN = 13885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2 = 13886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2_LEN = 13887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2 = 13888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2_LEN = 13889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3 = 13890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3_LEN = 13891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3 = 13892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3_LEN = 13893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT0 = 13894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT0_LEN = 13895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT0 = 13896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT0_LEN = 13897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT1 = 13898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT1_LEN = 13899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT1 = 13900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT1_LEN = 13901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT2 = 13902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT2_LEN = 13903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT2 = 13904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT2_LEN = 13905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT3 = 13906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_DQSCLK_SELECT3_LEN = 13907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT3 = 13908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_23_RDCLK_SELECT3_LEN = 13909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT0 = 13910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT0_LEN = 13911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT0 = 13912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT0_LEN = 13913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT1 = 13914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT1_LEN = 13915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT1 = 13916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT1_LEN = 13917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT2 = 13918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT2_LEN = 13919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT2 = 13920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT2_LEN = 13921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT3 = 13922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_DQSCLK_SELECT3_LEN = 13923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT3 = 13924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_23_RDCLK_SELECT3_LEN = 13925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT0 = 13926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT0_LEN = 13927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT0 = 13928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT0_LEN = 13929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT1 = 13930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT1_LEN = 13931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT1 = 13932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT1_LEN = 13933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT2 = 13934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT2_LEN = 13935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT2 = 13936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT2_LEN = 13937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT3 = 13938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_DQSCLK_SELECT3_LEN = 13939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT3 = 13940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_RDCLK_SELECT3_LEN = 13941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT0 = 13942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT0_LEN = 13943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT0 = 13944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT0_LEN = 13945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT1 = 13946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT1_LEN = 13947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT1 = 13948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT1_LEN = 13949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT2 = 13950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT2_LEN = 13951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT2 = 13952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT2_LEN = 13953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT3 = 13954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_DQSCLK_SELECT3_LEN = 13955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT3 = 13956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_RDCLK_SELECT3_LEN = 13957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N0 = 13958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N0_LEN = 13959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N1 = 13960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N1_LEN = 13961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N2 = 13962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N2_LEN = 13963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N3 = 13964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0_01_N3_LEN = 13965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N0 = 13966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N0_LEN = 13967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N1 = 13968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N1_LEN = 13969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N2 = 13970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N2_LEN = 13971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N3 = 13972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_1_01_N3_LEN = 13973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N0 = 13974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N0_LEN = 13975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N1 = 13976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N1_LEN = 13977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N2 = 13978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N2_LEN = 13979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N3 = 13980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_0_01_N3_LEN = 13981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N0 = 13982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N0_LEN = 13983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N1 = 13984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N1_LEN = 13985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N2 = 13986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N2_LEN = 13987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N3 = 13988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_1_01_N3_LEN = 13989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N0 = 13990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N0_LEN = 13991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N1 = 13992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N1_LEN = 13993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N2 = 13994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N2_LEN = 13995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N3 = 13996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_2_23_N3_LEN = 13997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N0 = 13998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N0_LEN = 13999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N1 = 14000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N1_LEN = 14001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N2 = 14002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N2_LEN = 14003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N3 = 14004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_3_23_N3_LEN = 14005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N0 = 14006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N0_LEN = 14007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N1 = 14008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N1_LEN = 14009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N2 = 14010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N2_LEN = 14011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N3 = 14012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_2_23_N3_LEN = 14013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N0 = 14014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N0_LEN = 14015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N1 = 14016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N1_LEN = 14017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N2 = 14018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N2_LEN = 14019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N3 = 14020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_3_23_N3_LEN = 14021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N0 = 14022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N0_LEN = 14023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N1 = 14024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N1_LEN = 14025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N2 = 14026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N2_LEN = 14027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N3 = 14028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_4_N3_LEN = 14029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N0 = 14030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N0_LEN = 14031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N1 = 14032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N1_LEN = 14033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N2 = 14034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N2_LEN = 14035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N3 = 14036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P1_4_N3_LEN = 14037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N0 = 14038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N0_LEN = 14039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N1 = 14040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N1_LEN = 14041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N2 = 14042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N2_LEN = 14043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N3 = 14044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_0_01_N3_LEN = 14045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N0 = 14046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N0_LEN = 14047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N1 = 14048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N1_LEN = 14049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N2 = 14050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N2_LEN = 14051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N3 = 14052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_1_01_N3_LEN = 14053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N0 = 14054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N0_LEN = 14055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N1 = 14056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N1_LEN = 14057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N2 = 14058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N2_LEN = 14059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N3 = 14060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_0_01_N3_LEN = 14061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N0 = 14062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N0_LEN = 14063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N1 = 14064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N1_LEN = 14065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N2 = 14066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N2_LEN = 14067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N3 = 14068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_1_01_N3_LEN = 14069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N0 = 14070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N0_LEN = 14071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N1 = 14072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N1_LEN = 14073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N2 = 14074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N2_LEN = 14075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N3 = 14076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_2_23_N3_LEN = 14077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N0 = 14078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N0_LEN = 14079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N1 = 14080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N1_LEN = 14081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N2 = 14082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N2_LEN = 14083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N3 = 14084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_3_23_N3_LEN = 14085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N0 = 14086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N0_LEN = 14087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N1 = 14088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N1_LEN = 14089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N2 = 14090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N2_LEN = 14091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N3 = 14092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_2_23_N3_LEN = 14093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N0 = 14094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N0_LEN = 14095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N1 = 14096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N1_LEN = 14097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N2 = 14098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N2_LEN = 14099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N3 = 14100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_3_23_N3_LEN = 14101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N0 = 14102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N0_LEN = 14103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N1 = 14104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N1_LEN = 14105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N2 = 14106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N2_LEN = 14107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N3 = 14108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P0_4_N3_LEN = 14109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N0 = 14110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N0_LEN = 14111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N1 = 14112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N1_LEN = 14113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N2 = 14114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N2_LEN = 14115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N3 = 14116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP1_P1_4_N3_LEN = 14117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N0 = 14118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N0_LEN = 14119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N1 = 14120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N1_LEN = 14121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N2 = 14122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N2_LEN = 14123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N3 = 14124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_0_01_N3_LEN = 14125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N0 = 14126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N0_LEN = 14127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N1 = 14128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N1_LEN = 14129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N2 = 14130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N2_LEN = 14131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N3 = 14132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_1_01_N3_LEN = 14133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N0 = 14134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N0_LEN = 14135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N1 = 14136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N1_LEN = 14137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N2 = 14138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N2_LEN = 14139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N3 = 14140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_0_01_N3_LEN = 14141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N0 = 14142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N0_LEN = 14143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N1 = 14144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N1_LEN = 14145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N2 = 14146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N2_LEN = 14147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N3 = 14148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_1_01_N3_LEN = 14149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N0 = 14150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N0_LEN = 14151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N1 = 14152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N1_LEN = 14153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N2 = 14154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N2_LEN = 14155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N3 = 14156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_2_23_N3_LEN = 14157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N0 = 14158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N0_LEN = 14159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N1 = 14160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N1_LEN = 14161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N2 = 14162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N2_LEN = 14163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N3 = 14164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_3_23_N3_LEN = 14165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N0 = 14166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N0_LEN = 14167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N1 = 14168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N1_LEN = 14169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N2 = 14170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N2_LEN = 14171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N3 = 14172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_2_23_N3_LEN = 14173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N0 = 14174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N0_LEN = 14175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N1 = 14176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N1_LEN = 14177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N2 = 14178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N2_LEN = 14179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N3 = 14180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_3_23_N3_LEN = 14181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N0 = 14182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N0_LEN = 14183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N1 = 14184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N1_LEN = 14185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N2 = 14186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N2_LEN = 14187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N3 = 14188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P0_4_N3_LEN = 14189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N0 = 14190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N0_LEN = 14191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N1 = 14192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N1_LEN = 14193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N2 = 14194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N2_LEN = 14195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N3 = 14196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP2_P1_4_N3_LEN = 14197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N0 = 14198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N0_LEN = 14199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N1 = 14200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N1_LEN = 14201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N2 = 14202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N2_LEN = 14203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N3 = 14204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_0_01_N3_LEN = 14205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N0 = 14206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N0_LEN = 14207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N1 = 14208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N1_LEN = 14209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N2 = 14210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N2_LEN = 14211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N3 = 14212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_1_01_N3_LEN = 14213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N0 = 14214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N0_LEN = 14215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N1 = 14216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N1_LEN = 14217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N2 = 14218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N2_LEN = 14219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N3 = 14220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_0_01_N3_LEN = 14221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N0 = 14222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N0_LEN = 14223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N1 = 14224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N1_LEN = 14225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N2 = 14226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N2_LEN = 14227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N3 = 14228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_1_01_N3_LEN = 14229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N0 = 14230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N0_LEN = 14231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N1 = 14232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N1_LEN = 14233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N2 = 14234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N2_LEN = 14235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N3 = 14236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_2_23_N3_LEN = 14237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N0 = 14238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N0_LEN = 14239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N1 = 14240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N1_LEN = 14241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N2 = 14242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N2_LEN = 14243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N3 = 14244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_3_23_N3_LEN = 14245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N0 = 14246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N0_LEN = 14247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N1 = 14248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N1_LEN = 14249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N2 = 14250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N2_LEN = 14251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N3 = 14252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_2_23_N3_LEN = 14253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N0 = 14254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N0_LEN = 14255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N1 = 14256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N1_LEN = 14257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N2 = 14258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N2_LEN = 14259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N3 = 14260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_3_23_N3_LEN = 14261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N0 = 14262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N0_LEN = 14263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N1 = 14264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N1_LEN = 14265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N2 = 14266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N2_LEN = 14267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N3 = 14268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P0_4_N3_LEN = 14269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N0 = 14270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N0_LEN = 14271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N1 = 14272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N1_LEN = 14273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N2 = 14274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N2_LEN = 14275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N3 = 14276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DQ_WR_OFFSET_RP3_P1_4_N3_LEN = 14277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE = 14278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE_LEN = 14279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_0_01_MAX_DQS = 14280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_0_01_MAX_DQS_LEN = 14281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE = 14282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE_LEN = 14283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_1_01_MAX_DQS = 14284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_1_01_MAX_DQS_LEN = 14285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_0_01_MIN_RD_EYE_SIZE = 14286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_0_01_MIN_RD_EYE_SIZE_LEN = 14287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_0_01_MAX_DQS = 14288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_0_01_MAX_DQS_LEN = 14289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_1_01_MIN_RD_EYE_SIZE = 14290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_1_01_MIN_RD_EYE_SIZE_LEN = 14291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_1_01_MAX_DQS = 14292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_1_01_MAX_DQS_LEN = 14293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE = 14294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE_LEN = 14295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_2_23_MAX_DQS = 14296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_2_23_MAX_DQS_LEN = 14297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE = 14298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE_LEN = 14299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_3_23_MAX_DQS = 14300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_3_23_MAX_DQS_LEN = 14301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_2_23_MIN_RD_EYE_SIZE = 14302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_2_23_MIN_RD_EYE_SIZE_LEN = 14303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_2_23_MAX_DQS = 14304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_2_23_MAX_DQS_LEN = 14305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_3_23_MIN_RD_EYE_SIZE = 14306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_3_23_MIN_RD_EYE_SIZE_LEN = 14307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_3_23_MAX_DQS = 14308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_3_23_MAX_DQS_LEN = 14309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_4_MIN_RD_EYE_SIZE = 14310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_4_MIN_RD_EYE_SIZE_LEN = 14311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_4_MAX_DQS = 14312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P0_4_MAX_DQS_LEN = 14313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_4_MIN_RD_EYE_SIZE = 14314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_4_MIN_RD_EYE_SIZE_LEN = 14315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_4_MAX_DQS = 14316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DRIFT_LIMITS_P1_4_MAX_DQS_LEN = 14317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0 = 14318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0_LEN = 14319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1 = 14320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1_LEN = 14321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0 = 14322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0_LEN = 14323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1 = 14324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1_LEN = 14325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0_01_ROT_N0 = 14326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0_01_ROT_N0_LEN = 14327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0_01_ROT_N1 = 14328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0_01_ROT_N1_LEN = 14329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1_01_ROT_N0 = 14330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1_01_ROT_N0_LEN = 14331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1_01_ROT_N1 = 14332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1_01_ROT_N1_LEN = 14333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0 = 14334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0_LEN = 14335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1 = 14336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1_LEN = 14337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0 = 14338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0_LEN = 14339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1 = 14340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1_LEN = 14341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2_23_ROT_N0 = 14342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2_23_ROT_N0_LEN = 14343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2_23_ROT_N1 = 14344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2_23_ROT_N1_LEN = 14345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3_23_ROT_N0 = 14346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3_23_ROT_N0_LEN = 14347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3_23_ROT_N1 = 14348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3_23_ROT_N1_LEN = 14349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_ROT_N0 = 14350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_ROT_N0_LEN = 14351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_ROT_N1 = 14352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_ROT_N1_LEN = 14353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4_ROT_N0 = 14354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4_ROT_N0_LEN = 14355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4_ROT_N1 = 14356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4_ROT_N1_LEN = 14357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0 = 14358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0_LEN = 14359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1 = 14360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1_LEN = 14361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0 = 14362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0_LEN = 14363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1 = 14364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1_LEN = 14365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0_01_ROT_N0 = 14366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0_01_ROT_N0_LEN = 14367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0_01_ROT_N1 = 14368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0_01_ROT_N1_LEN = 14369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1_01_ROT_N0 = 14370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1_01_ROT_N0_LEN = 14371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1_01_ROT_N1 = 14372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1_01_ROT_N1_LEN = 14373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0 = 14374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0_LEN = 14375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1 = 14376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1_LEN = 14377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0 = 14378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0_LEN = 14379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1 = 14380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1_LEN = 14381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2_23_ROT_N0 = 14382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2_23_ROT_N0_LEN = 14383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2_23_ROT_N1 = 14384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2_23_ROT_N1_LEN = 14385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3_23_ROT_N0 = 14386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3_23_ROT_N0_LEN = 14387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3_23_ROT_N1 = 14388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3_23_ROT_N1_LEN = 14389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_ROT_N0 = 14390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_ROT_N0_LEN = 14391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_ROT_N1 = 14392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_ROT_N1_LEN = 14393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4_ROT_N0 = 14394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4_ROT_N0_LEN = 14395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4_ROT_N1 = 14396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4_ROT_N1_LEN = 14397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0 = 14398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0_LEN = 14399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1 = 14400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1_LEN = 14401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0 = 14402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0_LEN = 14403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1 = 14404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1_LEN = 14405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0_01_ROT_N0 = 14406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0_01_ROT_N0_LEN = 14407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0_01_ROT_N1 = 14408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0_01_ROT_N1_LEN = 14409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1_01_ROT_N0 = 14410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1_01_ROT_N0_LEN = 14411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1_01_ROT_N1 = 14412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1_01_ROT_N1_LEN = 14413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0 = 14414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0_LEN = 14415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1 = 14416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1_LEN = 14417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0 = 14418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0_LEN = 14419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1 = 14420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1_LEN = 14421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2_23_ROT_N0 = 14422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2_23_ROT_N0_LEN = 14423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2_23_ROT_N1 = 14424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2_23_ROT_N1_LEN = 14425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3_23_ROT_N0 = 14426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3_23_ROT_N0_LEN = 14427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3_23_ROT_N1 = 14428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3_23_ROT_N1_LEN = 14429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_ROT_N0 = 14430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_ROT_N0_LEN = 14431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_ROT_N1 = 14432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_ROT_N1_LEN = 14433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4_ROT_N0 = 14434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4_ROT_N0_LEN = 14435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4_ROT_N1 = 14436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4_ROT_N1_LEN = 14437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0 = 14438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0_LEN = 14439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1 = 14440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1_LEN = 14441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0 = 14442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0_LEN = 14443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1 = 14444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1_LEN = 14445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0_01_ROT_N0 = 14446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0_01_ROT_N0_LEN = 14447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0_01_ROT_N1 = 14448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0_01_ROT_N1_LEN = 14449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1_01_ROT_N0 = 14450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1_01_ROT_N0_LEN = 14451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1_01_ROT_N1 = 14452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1_01_ROT_N1_LEN = 14453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0 = 14454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0_LEN = 14455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1 = 14456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1_LEN = 14457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0 = 14458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0_LEN = 14459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1 = 14460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1_LEN = 14461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2_23_ROT_N0 = 14462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2_23_ROT_N0_LEN = 14463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2_23_ROT_N1 = 14464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2_23_ROT_N1_LEN = 14465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3_23_ROT_N0 = 14466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3_23_ROT_N0_LEN = 14467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3_23_ROT_N1 = 14468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3_23_ROT_N1_LEN = 14469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_ROT_N0 = 14470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_ROT_N0_LEN = 14471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_ROT_N1 = 14472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_ROT_N1_LEN = 14473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4_ROT_N0 = 14474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4_ROT_N0_LEN = 14475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4_ROT_N1 = 14476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4_ROT_N1_LEN = 14477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0 = 14478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0_LEN = 14479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1 = 14480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1_LEN = 14481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0 = 14482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0_LEN = 14483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1 = 14484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1_LEN = 14485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0_01_ROT_N0 = 14486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0_01_ROT_N0_LEN = 14487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0_01_ROT_N1 = 14488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0_01_ROT_N1_LEN = 14489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1_01_ROT_N0 = 14490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1_01_ROT_N0_LEN = 14491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1_01_ROT_N1 = 14492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1_01_ROT_N1_LEN = 14493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0 = 14494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0_LEN = 14495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1 = 14496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1_LEN = 14497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0 = 14498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0_LEN = 14499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1 = 14500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1_LEN = 14501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2_23_ROT_N0 = 14502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2_23_ROT_N0_LEN = 14503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2_23_ROT_N1 = 14504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2_23_ROT_N1_LEN = 14505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3_23_ROT_N0 = 14506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3_23_ROT_N0_LEN = 14507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3_23_ROT_N1 = 14508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3_23_ROT_N1_LEN = 14509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_ROT_N0 = 14510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_ROT_N0_LEN = 14511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_ROT_N1 = 14512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_ROT_N1_LEN = 14513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4_ROT_N0 = 14514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4_ROT_N0_LEN = 14515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4_ROT_N1 = 14516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4_ROT_N1_LEN = 14517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0 = 14518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0_LEN = 14519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1 = 14520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1_LEN = 14521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0 = 14522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0_LEN = 14523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1 = 14524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1_LEN = 14525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0_01_ROT_N0 = 14526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0_01_ROT_N0_LEN = 14527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0_01_ROT_N1 = 14528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0_01_ROT_N1_LEN = 14529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1_01_ROT_N0 = 14530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1_01_ROT_N0_LEN = 14531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1_01_ROT_N1 = 14532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1_01_ROT_N1_LEN = 14533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0 = 14534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0_LEN = 14535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1 = 14536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1_LEN = 14537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0 = 14538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0_LEN = 14539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1 = 14540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1_LEN = 14541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2_23_ROT_N0 = 14542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2_23_ROT_N0_LEN = 14543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2_23_ROT_N1 = 14544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2_23_ROT_N1_LEN = 14545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3_23_ROT_N0 = 14546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3_23_ROT_N0_LEN = 14547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3_23_ROT_N1 = 14548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3_23_ROT_N1_LEN = 14549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_ROT_N0 = 14550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_ROT_N0_LEN = 14551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_ROT_N1 = 14552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_ROT_N1_LEN = 14553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4_ROT_N0 = 14554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4_ROT_N0_LEN = 14555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4_ROT_N1 = 14556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4_ROT_N1_LEN = 14557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0 = 14558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0_LEN = 14559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1 = 14560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1_LEN = 14561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0 = 14562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0_LEN = 14563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1 = 14564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1_LEN = 14565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0_01_ROT_N0 = 14566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0_01_ROT_N0_LEN = 14567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0_01_ROT_N1 = 14568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0_01_ROT_N1_LEN = 14569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1_01_ROT_N0 = 14570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1_01_ROT_N0_LEN = 14571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1_01_ROT_N1 = 14572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1_01_ROT_N1_LEN = 14573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0 = 14574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0_LEN = 14575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1 = 14576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1_LEN = 14577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0 = 14578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0_LEN = 14579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1 = 14580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1_LEN = 14581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2_23_ROT_N0 = 14582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2_23_ROT_N0_LEN = 14583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2_23_ROT_N1 = 14584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2_23_ROT_N1_LEN = 14585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3_23_ROT_N0 = 14586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3_23_ROT_N0_LEN = 14587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3_23_ROT_N1 = 14588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3_23_ROT_N1_LEN = 14589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_ROT_N0 = 14590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_ROT_N0_LEN = 14591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_ROT_N1 = 14592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_ROT_N1_LEN = 14593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4_ROT_N0 = 14594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4_ROT_N0_LEN = 14595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4_ROT_N1 = 14596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4_ROT_N1_LEN = 14597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0 = 14598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0_LEN = 14599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1 = 14600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1_LEN = 14601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0 = 14602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0_LEN = 14603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1 = 14604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1_LEN = 14605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0_01_ROT_N0 = 14606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0_01_ROT_N0_LEN = 14607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0_01_ROT_N1 = 14608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0_01_ROT_N1_LEN = 14609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1_01_ROT_N0 = 14610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1_01_ROT_N0_LEN = 14611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1_01_ROT_N1 = 14612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1_01_ROT_N1_LEN = 14613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0 = 14614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0_LEN = 14615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1 = 14616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1_LEN = 14617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0 = 14618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0_LEN = 14619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1 = 14620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1_LEN = 14621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2_23_ROT_N0 = 14622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2_23_ROT_N0_LEN = 14623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2_23_ROT_N1 = 14624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2_23_ROT_N1_LEN = 14625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3_23_ROT_N0 = 14626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3_23_ROT_N0_LEN = 14627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3_23_ROT_N1 = 14628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3_23_ROT_N1_LEN = 14629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_ROT_N0 = 14630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_ROT_N0_LEN = 14631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_ROT_N1 = 14632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_ROT_N1_LEN = 14633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4_ROT_N0 = 14634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4_ROT_N0_LEN = 14635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4_ROT_N1 = 14636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4_ROT_N1_LEN = 14637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW = 14638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW_LEN = 14639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_01_POST_CURSOR = 14640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_01_POST_CURSOR_LEN = 14641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_01_SLEW_CTL = 14642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_01_SLEW_CTL_LEN = 14643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_01_INTERP_SIG_SLEW = 14644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_01_INTERP_SIG_SLEW_LEN = 14645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_01_POST_CURSOR = 14646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_01_POST_CURSOR_LEN = 14647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_01_SLEW_CTL = 14648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_01_SLEW_CTL_LEN = 14649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_01_INTERP_SIG_SLEW = 14650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_01_INTERP_SIG_SLEW_LEN = 14651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_01_POST_CURSOR = 14652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_01_POST_CURSOR_LEN = 14653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_01_SLEW_CTL = 14654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_01_SLEW_CTL_LEN = 14655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_01_INTERP_SIG_SLEW = 14656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_01_INTERP_SIG_SLEW_LEN = 14657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_01_POST_CURSOR = 14658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_01_POST_CURSOR_LEN = 14659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_01_SLEW_CTL = 14660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_01_SLEW_CTL_LEN = 14661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_23_INTERP_SIG_SLEW = 14662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_23_INTERP_SIG_SLEW_LEN = 14663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_23_POST_CURSOR = 14664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_23_POST_CURSOR_LEN = 14665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_23_SLEW_CTL = 14666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_23_SLEW_CTL_LEN = 14667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_23_INTERP_SIG_SLEW = 14668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_23_INTERP_SIG_SLEW_LEN = 14669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_23_POST_CURSOR = 14670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_23_POST_CURSOR_LEN = 14671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_23_SLEW_CTL = 14672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_23_SLEW_CTL_LEN = 14673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_23_INTERP_SIG_SLEW = 14674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_23_INTERP_SIG_SLEW_LEN = 14675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_23_POST_CURSOR = 14676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_23_POST_CURSOR_LEN = 14677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_23_SLEW_CTL = 14678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_23_SLEW_CTL_LEN = 14679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_23_INTERP_SIG_SLEW = 14680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_23_INTERP_SIG_SLEW_LEN = 14681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_23_POST_CURSOR = 14682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_23_POST_CURSOR_LEN = 14683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_23_SLEW_CTL = 14684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_23_SLEW_CTL_LEN = 14685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_INTERP_SIG_SLEW = 14686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_INTERP_SIG_SLEW_LEN = 14687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_POST_CURSOR = 14688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_POST_CURSOR_LEN = 14689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_SLEW_CTL = 14690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_SLEW_CTL_LEN = 14691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_INTERP_SIG_SLEW = 14692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_INTERP_SIG_SLEW_LEN = 14693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_POST_CURSOR = 14694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_POST_CURSOR_LEN = 14695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_SLEW_CTL = 14696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_SLEW_CTL_LEN = 14697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR = 14698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR_LEN = 14699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR_FFE = 14700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR_FFE_LEN = 14701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR = 14702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR_LEN = 14703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR_FFE = 14704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR_FFE_LEN = 14705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_01_EN_N_WR = 14706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_01_EN_N_WR_LEN = 14707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_01_EN_N_WR_FFE = 14708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_01_EN_N_WR_FFE_LEN = 14709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_01_EN_N_WR = 14710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_01_EN_N_WR_LEN = 14711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_01_EN_N_WR_FFE = 14712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_01_EN_N_WR_FFE_LEN = 14713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR = 14714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR_LEN = 14715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR_FFE = 14716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR_FFE_LEN = 14717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR = 14718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR_LEN = 14719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR_FFE = 14720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR_FFE_LEN = 14721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_23_EN_N_WR = 14722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_23_EN_N_WR_LEN = 14723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_23_EN_N_WR_FFE = 14724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_23_EN_N_WR_FFE_LEN = 14725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_23_EN_N_WR = 14726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_23_EN_N_WR_LEN = 14727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_23_EN_N_WR_FFE = 14728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_23_EN_N_WR_FFE_LEN = 14729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_EN_N_WR = 14730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_EN_N_WR_LEN = 14731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_EN_N_WR_FFE = 14732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_EN_N_WR_FFE_LEN = 14733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_EN_N_WR = 14734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_EN_N_WR_LEN = 14735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_EN_N_WR_FFE = 14736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_EN_N_WR_FFE_LEN = 14737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_01_EN_N_WR = 14738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_01_EN_N_WR_LEN = 14739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_01_EN_N_WR_FFE = 14740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_01_EN_N_WR_FFE_LEN = 14741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_01_EN_N_WR = 14742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_01_EN_N_WR_LEN = 14743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_01_EN_N_WR_FFE = 14744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_01_EN_N_WR_FFE_LEN = 14745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_01_EN_N_WR = 14746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_01_EN_N_WR_LEN = 14747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_01_EN_N_WR_FFE = 14748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_01_EN_N_WR_FFE_LEN = 14749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_01_EN_N_WR = 14750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_01_EN_N_WR_LEN = 14751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_01_EN_N_WR_FFE = 14752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_01_EN_N_WR_FFE_LEN = 14753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_23_EN_N_WR = 14754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_23_EN_N_WR_LEN = 14755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_23_EN_N_WR_FFE = 14756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_23_EN_N_WR_FFE_LEN = 14757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_23_EN_N_WR = 14758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_23_EN_N_WR_LEN = 14759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_23_EN_N_WR_FFE = 14760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_23_EN_N_WR_FFE_LEN = 14761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_23_EN_N_WR = 14762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_23_EN_N_WR_LEN = 14763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_23_EN_N_WR_FFE = 14764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_23_EN_N_WR_FFE_LEN = 14765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_23_EN_N_WR = 14766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_23_EN_N_WR_LEN = 14767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_23_EN_N_WR_FFE = 14768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_23_EN_N_WR_FFE_LEN = 14769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_EN_N_WR = 14770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_EN_N_WR_LEN = 14771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_EN_N_WR_FFE = 14772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_EN_N_WR_FFE_LEN = 14773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_EN_N_WR = 14774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_EN_N_WR_LEN = 14775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_EN_N_WR_FFE = 14776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_EN_N_WR_FFE_LEN = 14777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR = 14778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR_LEN = 14779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR_FFE = 14780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR_FFE_LEN = 14781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR = 14782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR_LEN = 14783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR_FFE = 14784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR_FFE_LEN = 14785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_01_EN_P_WR = 14786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_01_EN_P_WR_LEN = 14787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_01_EN_P_WR_FFE = 14788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_01_EN_P_WR_FFE_LEN = 14789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_01_EN_P_WR = 14790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_01_EN_P_WR_LEN = 14791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_01_EN_P_WR_FFE = 14792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_01_EN_P_WR_FFE_LEN = 14793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR = 14794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR_LEN = 14795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR_FFE = 14796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR_FFE_LEN = 14797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR = 14798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR_LEN = 14799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR_FFE = 14800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR_FFE_LEN = 14801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_23_EN_P_WR = 14802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_23_EN_P_WR_LEN = 14803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_23_EN_P_WR_FFE = 14804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_23_EN_P_WR_FFE_LEN = 14805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_23_EN_P_WR = 14806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_23_EN_P_WR_LEN = 14807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_23_EN_P_WR_FFE = 14808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_23_EN_P_WR_FFE_LEN = 14809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_EN_P_WR = 14810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_EN_P_WR_LEN = 14811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_EN_P_WR_FFE = 14812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_EN_P_WR_FFE_LEN = 14813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_EN_P_WR = 14814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_EN_P_WR_LEN = 14815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_EN_P_WR_FFE = 14816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_EN_P_WR_FFE_LEN = 14817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_01_EN_P_WR = 14818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_LEN = 14819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_FFE = 14820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_FFE_LEN = 14821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_01_EN_P_WR = 14822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_01_EN_P_WR_LEN = 14823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_01_EN_P_WR_FFE = 14824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_01_EN_P_WR_FFE_LEN = 14825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_01_EN_P_WR = 14826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_01_EN_P_WR_LEN = 14827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_01_EN_P_WR_FFE = 14828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_01_EN_P_WR_FFE_LEN = 14829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_01_EN_P_WR = 14830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_01_EN_P_WR_LEN = 14831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_01_EN_P_WR_FFE = 14832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_01_EN_P_WR_FFE_LEN = 14833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_23_EN_P_WR = 14834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_23_EN_P_WR_LEN = 14835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_23_EN_P_WR_FFE = 14836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_23_EN_P_WR_FFE_LEN = 14837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_23_EN_P_WR = 14838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_23_EN_P_WR_LEN = 14839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_23_EN_P_WR_FFE = 14840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_23_EN_P_WR_FFE_LEN = 14841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_23_EN_P_WR = 14842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_23_EN_P_WR_LEN = 14843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_23_EN_P_WR_FFE = 14844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_23_EN_P_WR_FFE_LEN = 14845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_23_EN_P_WR = 14846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_23_EN_P_WR_LEN = 14847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_23_EN_P_WR_FFE = 14848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_23_EN_P_WR_FFE_LEN = 14849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_EN_P_WR = 14850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_EN_P_WR_LEN = 14851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_EN_P_WR_FFE = 14852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_EN_P_WR_FFE_LEN = 14853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_EN_P_WR = 14854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_EN_P_WR_LEN = 14855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_EN_P_WR_FFE = 14856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_EN_P_WR_FFE_LEN = 14857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD00 = 14858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD00_LEN = 14859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD01 = 14860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD01_LEN = 14861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD02 = 14862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD02_LEN = 14863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD03 = 14864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD03_LEN = 14865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD04 = 14866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD04_LEN = 14867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD05 = 14868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD05_LEN = 14869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD06 = 14870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD06_LEN = 14871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD07 = 14872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_0_01_MEMINTD07_LEN = 14873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD00 = 14874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD00_LEN = 14875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD01 = 14876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD01_LEN = 14877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD02 = 14878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD02_LEN = 14879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD03 = 14880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD03_LEN = 14881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD04 = 14882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD04_LEN = 14883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD05 = 14884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD05_LEN = 14885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD06 = 14886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD06_LEN = 14887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD07 = 14888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_1_01_MEMINTD07_LEN = 14889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD00 = 14890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD00_LEN = 14891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD01 = 14892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD01_LEN = 14893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD02 = 14894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD02_LEN = 14895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD03 = 14896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD03_LEN = 14897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD04 = 14898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD04_LEN = 14899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD05 = 14900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD05_LEN = 14901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD06 = 14902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD06_LEN = 14903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD07 = 14904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_0_01_MEMINTD07_LEN = 14905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD00 = 14906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD00_LEN = 14907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD01 = 14908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD01_LEN = 14909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD02 = 14910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD02_LEN = 14911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD03 = 14912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD03_LEN = 14913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD04 = 14914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD04_LEN = 14915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD05 = 14916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD05_LEN = 14917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD06 = 14918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD06_LEN = 14919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD07 = 14920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_1_01_MEMINTD07_LEN = 14921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD00 = 14922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD00_LEN = 14923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD01 = 14924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD01_LEN = 14925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD02 = 14926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD02_LEN = 14927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD03 = 14928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD03_LEN = 14929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD04 = 14930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD04_LEN = 14931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD05 = 14932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD05_LEN = 14933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD06 = 14934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD06_LEN = 14935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD07 = 14936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_2_23_MEMINTD07_LEN = 14937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD00 = 14938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD00_LEN = 14939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD01 = 14940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD01_LEN = 14941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD02 = 14942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD02_LEN = 14943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD03 = 14944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD03_LEN = 14945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD04 = 14946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD04_LEN = 14947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD05 = 14948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD05_LEN = 14949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD06 = 14950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD06_LEN = 14951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD07 = 14952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_3_23_MEMINTD07_LEN = 14953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD00 = 14954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD00_LEN = 14955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD01 = 14956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD01_LEN = 14957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD02 = 14958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD02_LEN = 14959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD03 = 14960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD03_LEN = 14961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD04 = 14962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD04_LEN = 14963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD05 = 14964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD05_LEN = 14965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD06 = 14966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD06_LEN = 14967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD07 = 14968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_2_23_MEMINTD07_LEN = 14969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD00 = 14970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD00_LEN = 14971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD01 = 14972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD01_LEN = 14973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD02 = 14974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD02_LEN = 14975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD03 = 14976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD03_LEN = 14977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD04 = 14978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD04_LEN = 14979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD05 = 14980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD05_LEN = 14981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD06 = 14982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD06_LEN = 14983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD07 = 14984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_3_23_MEMINTD07_LEN = 14985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD00 = 14986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD00_LEN = 14987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD01 = 14988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD01_LEN = 14989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD02 = 14990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD02_LEN = 14991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD03 = 14992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD03_LEN = 14993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD04 = 14994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD04_LEN = 14995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD05 = 14996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD05_LEN = 14997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD06 = 14998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD06_LEN = 14999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD07 = 15000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P0_4_MEMINTD07_LEN = 15001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD00 = 15002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD00_LEN = 15003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD01 = 15004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD01_LEN = 15005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD02 = 15006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD02_LEN = 15007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD03 = 15008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD03_LEN = 15009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD04 = 15010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD04_LEN = 15011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD05 = 15012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD05_LEN = 15013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD06 = 15014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD06_LEN = 15015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD07 = 15016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_0_P1_4_MEMINTD07_LEN = 15017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD08 = 15018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD08_LEN = 15019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD09 = 15020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD09_LEN = 15021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD10 = 15022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD10_LEN = 15023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD11 = 15024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD11_LEN = 15025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD12 = 15026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD12_LEN = 15027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD13 = 15028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD13_LEN = 15029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD14 = 15030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD14_LEN = 15031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD15 = 15032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_0_01_MEMINTD15_LEN = 15033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD08 = 15034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD08_LEN = 15035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD09 = 15036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD09_LEN = 15037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD10 = 15038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD10_LEN = 15039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD11 = 15040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD11_LEN = 15041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD12 = 15042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD12_LEN = 15043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD13 = 15044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD13_LEN = 15045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD14 = 15046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD14_LEN = 15047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD15 = 15048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_1_01_MEMINTD15_LEN = 15049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD08 = 15050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD08_LEN = 15051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD09 = 15052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD09_LEN = 15053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD10 = 15054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD10_LEN = 15055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD11 = 15056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD11_LEN = 15057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD12 = 15058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD12_LEN = 15059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD13 = 15060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD13_LEN = 15061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD14 = 15062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD14_LEN = 15063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD15 = 15064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_0_01_MEMINTD15_LEN = 15065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD08 = 15066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD08_LEN = 15067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD09 = 15068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD09_LEN = 15069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD10 = 15070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD10_LEN = 15071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD11 = 15072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD11_LEN = 15073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD12 = 15074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD12_LEN = 15075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD13 = 15076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD13_LEN = 15077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD14 = 15078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD14_LEN = 15079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD15 = 15080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_1_01_MEMINTD15_LEN = 15081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD08 = 15082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD08_LEN = 15083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD09 = 15084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD09_LEN = 15085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD10 = 15086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD10_LEN = 15087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD11 = 15088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD11_LEN = 15089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD12 = 15090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD12_LEN = 15091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD13 = 15092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD13_LEN = 15093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD14 = 15094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD14_LEN = 15095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD15 = 15096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_2_23_MEMINTD15_LEN = 15097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD08 = 15098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD08_LEN = 15099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD09 = 15100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD09_LEN = 15101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD10 = 15102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD10_LEN = 15103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD11 = 15104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD11_LEN = 15105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD12 = 15106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD12_LEN = 15107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD13 = 15108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD13_LEN = 15109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD14 = 15110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD14_LEN = 15111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD15 = 15112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_3_23_MEMINTD15_LEN = 15113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD08 = 15114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD08_LEN = 15115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD09 = 15116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD09_LEN = 15117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD10 = 15118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD10_LEN = 15119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD11 = 15120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD11_LEN = 15121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD12 = 15122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD12_LEN = 15123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD13 = 15124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD13_LEN = 15125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD14 = 15126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD14_LEN = 15127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD15 = 15128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_2_23_MEMINTD15_LEN = 15129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD08 = 15130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD08_LEN = 15131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD09 = 15132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD09_LEN = 15133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD10 = 15134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD10_LEN = 15135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD11 = 15136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD11_LEN = 15137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD12 = 15138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD12_LEN = 15139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD13 = 15140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD13_LEN = 15141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD14 = 15142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD14_LEN = 15143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD15 = 15144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_3_23_MEMINTD15_LEN = 15145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD08 = 15146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD08_LEN = 15147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD09 = 15148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD09_LEN = 15149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD10 = 15150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD10_LEN = 15151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD11 = 15152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD11_LEN = 15153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD12 = 15154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD12_LEN = 15155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD13 = 15156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD13_LEN = 15157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD14 = 15158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD14_LEN = 15159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD15 = 15160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P0_4_MEMINTD15_LEN = 15161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD08 = 15162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD08_LEN = 15163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD09 = 15164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD09_LEN = 15165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD10 = 15166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD10_LEN = 15167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD11 = 15168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD11_LEN = 15169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD12 = 15170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD12_LEN = 15171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD13 = 15172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD13_LEN = 15173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD14 = 15174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD14_LEN = 15175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD15 = 15176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_1_P1_4_MEMINTD15_LEN = 15177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD16 = 15178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD16_LEN = 15179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD17 = 15180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD17_LEN = 15181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD18 = 15182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD18_LEN = 15183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD19 = 15184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD19_LEN = 15185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD20 = 15186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD20_LEN = 15187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD21 = 15188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD21_LEN = 15189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD22 = 15190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD22_LEN = 15191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD23 = 15192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_0_01_MEMINTD23_LEN = 15193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD16 = 15194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD16_LEN = 15195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD17 = 15196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD17_LEN = 15197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD18 = 15198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD18_LEN = 15199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD19 = 15200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD19_LEN = 15201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD20 = 15202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD20_LEN = 15203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD21 = 15204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD21_LEN = 15205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD22 = 15206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD22_LEN = 15207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD23 = 15208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_1_01_MEMINTD23_LEN = 15209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD16 = 15210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD16_LEN = 15211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD17 = 15212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD17_LEN = 15213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD18 = 15214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD18_LEN = 15215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD19 = 15216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD19_LEN = 15217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD20 = 15218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD20_LEN = 15219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD21 = 15220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD21_LEN = 15221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD22 = 15222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD22_LEN = 15223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD23 = 15224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_0_01_MEMINTD23_LEN = 15225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD16 = 15226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD16_LEN = 15227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD17 = 15228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD17_LEN = 15229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD18 = 15230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD18_LEN = 15231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD19 = 15232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD19_LEN = 15233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD20 = 15234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD20_LEN = 15235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD21 = 15236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD21_LEN = 15237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD22 = 15238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD22_LEN = 15239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD23 = 15240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_1_01_MEMINTD23_LEN = 15241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD16 = 15242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD16_LEN = 15243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD17 = 15244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD17_LEN = 15245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD18 = 15246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD18_LEN = 15247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD19 = 15248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD19_LEN = 15249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD20 = 15250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD20_LEN = 15251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD21 = 15252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD21_LEN = 15253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD22 = 15254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD22_LEN = 15255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD23 = 15256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_2_23_MEMINTD23_LEN = 15257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD16 = 15258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD16_LEN = 15259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD17 = 15260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD17_LEN = 15261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD18 = 15262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD18_LEN = 15263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD19 = 15264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD19_LEN = 15265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD20 = 15266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD20_LEN = 15267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD21 = 15268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD21_LEN = 15269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD22 = 15270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD22_LEN = 15271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD23 = 15272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_3_23_MEMINTD23_LEN = 15273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD16 = 15274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD16_LEN = 15275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD17 = 15276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD17_LEN = 15277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD18 = 15278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD18_LEN = 15279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD19 = 15280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD19_LEN = 15281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD20 = 15282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD20_LEN = 15283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD21 = 15284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD21_LEN = 15285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD22 = 15286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD22_LEN = 15287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD23 = 15288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_2_23_MEMINTD23_LEN = 15289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD16 = 15290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD16_LEN = 15291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD17 = 15292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD17_LEN = 15293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD18 = 15294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD18_LEN = 15295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD19 = 15296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD19_LEN = 15297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD20 = 15298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD20_LEN = 15299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD21 = 15300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD21_LEN = 15301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD22 = 15302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD22_LEN = 15303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD23 = 15304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_3_23_MEMINTD23_LEN = 15305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD16 = 15306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD16_LEN = 15307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD17 = 15308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD17_LEN = 15309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD18 = 15310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD18_LEN = 15311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD19 = 15312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD19_LEN = 15313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD20 = 15314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD20_LEN = 15315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD21 = 15316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD21_LEN = 15317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD22 = 15318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD22_LEN = 15319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD23 = 15320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P0_4_MEMINTD23_LEN = 15321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD16 = 15322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD16_LEN = 15323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD17 = 15324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD17_LEN = 15325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD18 = 15326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD18_LEN = 15327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD19 = 15328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD19_LEN = 15329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD20 = 15330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD20_LEN = 15331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD21 = 15332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD21_LEN = 15333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD22 = 15334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD22_LEN = 15335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD23 = 15336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PATTERN_POS_2_P1_4_MEMINTD23_LEN = 15337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNE_2 = 15338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNE_2_LEN = 15339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNECP_2 = 15340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNECP_2_LEN = 15341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNEF_5 = 15342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNEF_5_LEN = 15343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNEVCO_1 = 15344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_TUNEVCO_1_LEN = 15345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_PLLXTR_1 = 15346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_0_01_PLLXTR_1_LEN = 15347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNE_0_2 = 15348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNE_0_2_LEN = 15349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNECP_0_2 = 15350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNECP_0_2_LEN = 15351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNEF_0_5 = 15352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNEF_0_5_LEN = 15353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNEVCO_0 = 15354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_TUNEVCO_0_LEN = 15355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_PLLXTR_0 = 15356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_1_01_PLLXTR_0_LEN = 15357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNE_2 = 15358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNE_2_LEN = 15359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNECP_2 = 15360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNECP_2_LEN = 15361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNEF_5 = 15362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNEF_5_LEN = 15363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNEVCO_1 = 15364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_TUNEVCO_1_LEN = 15365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_PLLXTR_1 = 15366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_0_01_PLLXTR_1_LEN = 15367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNE_0_2 = 15368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNE_0_2_LEN = 15369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNECP_0_2 = 15370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNECP_0_2_LEN = 15371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNEF_0_5 = 15372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNEF_0_5_LEN = 15373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNEVCO_0 = 15374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_TUNEVCO_0_LEN = 15375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_PLLXTR_0 = 15376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_1_01_PLLXTR_0_LEN = 15377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNE_0 = 15378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNE_0_LEN = 15379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNECP_0 = 15380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNECP_0_LEN = 15381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNEF_0_5 = 15382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNEF_0_5_LEN = 15383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNEVCO_0_1 = 15384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_TUNEVCO_0_1_LEN = 15385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_PLLXTR_0_1 = 15386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_2_23_PLLXTR_0_1_LEN = 15387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNE_0_2 = 15388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNE_0_2_LEN = 15389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNECP_0_2 = 15390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNECP_0_2_LEN = 15391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNEF_0_5 = 15392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNEF_0_5_LEN = 15393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNEVCO_0_1 = 15394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_TUNEVCO_0_1_LEN = 15395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_PLLXTR_0_1 = 15396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_3_23_PLLXTR_0_1_LEN = 15397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNE_0 = 15398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNE_0_LEN = 15399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNECP_0 = 15400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNECP_0_LEN = 15401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNEF_0_5 = 15402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNEF_0_5_LEN = 15403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNEVCO_0_1 = 15404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_TUNEVCO_0_1_LEN = 15405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_PLLXTR_0_1 = 15406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_2_23_PLLXTR_0_1_LEN = 15407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNE_0_2 = 15408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNE_0_2_LEN = 15409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNECP_0_2 = 15410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNECP_0_2_LEN = 15411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNEF_0_5 = 15412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNEF_0_5_LEN = 15413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNEVCO_0_1 = 15414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_TUNEVCO_0_1_LEN = 15415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_PLLXTR_0_1 = 15416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_3_23_PLLXTR_0_1_LEN = 15417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNE_0_2 = 15418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNE_0_2_LEN = 15419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNECP_0_2 = 15420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNECP_0_2_LEN = 15421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNEF_0_5 = 15422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNEF_0_5_LEN = 15423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNEVCO_0_1 = 15424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_TUNEVCO_0_1_LEN = 15425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_PLLXTR_0_1 = 15426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P0_4_PLLXTR_0_1_LEN = 15427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNE_0_2 = 15428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNE_0_2_LEN = 15429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNECP_0_2 = 15430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNECP_0_2_LEN = 15431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNEF_0_5 = 15432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNEF_0_5_LEN = 15433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNEVCO_0_1 = 15434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_TUNEVCO_0_1_LEN = 15435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_PLLXTR_0_1 = 15436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG0_P1_4_PLLXTR_0_1_LEN = 15437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_TUNETDIV_2 = 15438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_TUNETDIV_2_LEN = 15439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_TUNEMDIV_1 = 15440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_TUNEMDIV_1_LEN = 15441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_TUNEATST = 15442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_VREG_RANGE_1 = 15443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_VREG_RANGE_1_LEN = 15444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_CE0DLTVCCA = 15445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_VREG_VCCTUNE_1 = 15446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_VREG_VCCTUNE_1_LEN = 15447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_CE0DLTVCC1 = 15448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_CE0DLTVCC2 = 15449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_S0INSDLYTAP = 15450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_0_01_S1INSDLYTAP = 15451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_TUNETDIV_0_2 = 15452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_TUNETDIV_0_2_LEN = 15453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_TUNEMDIV_0 = 15454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_TUNEMDIV_0_LEN = 15455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_TUNEATST = 15456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_VREG_RANGE_0 = 15457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_VREG_RANGE_0_LEN = 15458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_CE0DLTVCCA = 15459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_VREG_VCCTUNE_0 = 15460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_VREG_VCCTUNE_0_LEN = 15461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_CE0DLTVCC1 = 15462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_CE0DLTVCC2 = 15463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_S0INSDLYTAP = 15464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_1_01_S1INSDLYTAP = 15465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_TUNETDIV_2 = 15466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_TUNETDIV_2_LEN = 15467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_TUNEMDIV_1 = 15468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_TUNEMDIV_1_LEN = 15469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_TUNEATST = 15470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_VREG_RANGE_1 = 15471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_VREG_RANGE_1_LEN = 15472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_CE0DLTVCCA = 15473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_VREG_VCCTUNE_1 = 15474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_VREG_VCCTUNE_1_LEN = 15475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_CE0DLTVCC1 = 15476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_CE0DLTVCC2 = 15477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_S0INSDLYTAP = 15478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_0_01_S1INSDLYTAP = 15479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_TUNETDIV_0_2 = 15480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_TUNETDIV_0_2_LEN = 15481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_TUNEMDIV_0 = 15482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_TUNEMDIV_0_LEN = 15483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_TUNEATST = 15484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_VREG_RANGE_0 = 15485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_VREG_RANGE_0_LEN = 15486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_CE0DLTVCCA = 15487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_VREG_VCCTUNE_0 = 15488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_VREG_VCCTUNE_0_LEN = 15489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_CE0DLTVCC1 = 15490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_CE0DLTVCC2 = 15491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_S0INSDLYTAP = 15492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_1_01_S1INSDLYTAP = 15493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_TUNETDIV_0 = 15494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_TUNETDIV_0_LEN = 15495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_TUNEMDIV_0_1 = 15496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_TUNEMDIV_0_1_LEN = 15497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_TUNEATST = 15498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_VREG_RANGE_0_1 = 15499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_VREG_RANGE_0_1_LEN = 15500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_CE0DLTVCCA = 15501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_VREG_VCCTUNE_0_1 = 15502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_VREG_VCCTUNE_0_1_LEN = 15503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_CE0DLTVCC1 = 15504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_CE0DLTVCC2 = 15505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_S0INSDLYTAP = 15506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_2_23_S1INSDLYTAP = 15507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_TUNETDIV_0_2 = 15508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_TUNETDIV_0_2_LEN = 15509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_TUNEMDIV_0_1 = 15510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_TUNEMDIV_0_1_LEN = 15511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_TUNEATST = 15512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_VREG_RANGE_0_1 = 15513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_VREG_RANGE_0_1_LEN = 15514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_CE0DLTVCCA = 15515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_VREG_VCCTUNE_0_1 = 15516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_VREG_VCCTUNE_0_1_LEN = 15517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_CE0DLTVCC1 = 15518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_CE0DLTVCC2 = 15519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_S0INSDLYTAP = 15520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_3_23_S1INSDLYTAP = 15521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_TUNETDIV_0 = 15522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_TUNETDIV_0_LEN = 15523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_TUNEMDIV_0_1 = 15524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_TUNEMDIV_0_1_LEN = 15525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_TUNEATST = 15526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_VREG_RANGE_0_1 = 15527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_VREG_RANGE_0_1_LEN = 15528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_CE0DLTVCCA = 15529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_VREG_VCCTUNE_0_1 = 15530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_VREG_VCCTUNE_0_1_LEN = 15531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_CE0DLTVCC1 = 15532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_CE0DLTVCC2 = 15533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_S0INSDLYTAP = 15534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_2_23_S1INSDLYTAP = 15535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_TUNETDIV_0_2 = 15536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_TUNETDIV_0_2_LEN = 15537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_TUNEMDIV_0_1 = 15538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_TUNEMDIV_0_1_LEN = 15539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_TUNEATST = 15540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_VREG_RANGE_0_1 = 15541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_VREG_RANGE_0_1_LEN = 15542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_CE0DLTVCCA = 15543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_VREG_VCCTUNE_0_1 = 15544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_VREG_VCCTUNE_0_1_LEN = 15545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_CE0DLTVCC1 = 15546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_CE0DLTVCC2 = 15547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_S0INSDLYTAP = 15548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_3_23_S1INSDLYTAP = 15549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_TUNETDIV_0_2 = 15550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_TUNETDIV_0_2_LEN = 15551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_TUNEMDIV_0_1 = 15552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_TUNEMDIV_0_1_LEN = 15553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_TUNEATST = 15554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_VREG_RANGE_0_1 = 15555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_VREG_RANGE_0_1_LEN = 15556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_CE0DLTVCCA = 15557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_VREG_VCCTUNE_0_1 = 15558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_VREG_VCCTUNE_0_1_LEN = 15559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_CE0DLTVCC1 = 15560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_CE0DLTVCC2 = 15561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_S0INSDLYTAP = 15562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P0_4_S1INSDLYTAP = 15563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_TUNETDIV_0_2 = 15564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_TUNETDIV_0_2_LEN = 15565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_TUNEMDIV_0_1 = 15566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_TUNEMDIV_0_1_LEN = 15567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_TUNEATST = 15568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_VREG_RANGE_0_1 = 15569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_VREG_RANGE_0_1_LEN = 15570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_CE0DLTVCCA = 15571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_VREG_VCCTUNE_0_1 = 15572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_VREG_VCCTUNE_0_1_LEN = 15573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_CE0DLTVCC1 = 15574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_CE0DLTVCC2 = 15575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_S0INSDLYTAP = 15576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_PLL_CONFIG1_P1_4_S1INSDLYTAP = 15577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_NO_EYE_DETECTED_MASK = 15578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_LEADING_EDGE_FOUND_MASK = 15579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_TRAILING_EDGE_FOUND_MASK = 15580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N0_MASK = 15581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N1_MASK = 15582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N2_MASK = 15583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N3_MASK = 15584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N0_MASK = 15585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N1_MASK = 15586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N2_MASK = 15587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N3_MASK = 15588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_EYE_CLIPPING_MASK = 15589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_NO_DQS_MASK = 15590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_NO_LOCK_MASK = 15591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_DRIFT_ERROR_MASK = 15592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_0_01_MIN_EYE_MASK = 15593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_NO_EYE_DETECTED_MASK = 15594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_LEADING_EDGE_FOUND_MASK = 15595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_TRAILING_EDGE_FOUND_MASK = 15596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N0_MASK = 15597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N1_MASK = 15598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N2_MASK = 15599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N3_MASK = 15600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N0_MASK = 15601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N1_MASK = 15602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N2_MASK = 15603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N3_MASK = 15604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_EYE_CLIPPING_MASK = 15605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_NO_DQS_MASK = 15606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_NO_LOCK_MASK = 15607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_DRIFT_ERROR_MASK = 15608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_1_01_MIN_EYE_MASK = 15609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_NO_EYE_DETECTED_MASK = 15610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_LEADING_EDGE_FOUND_MASK = 15611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_TRAILING_EDGE_FOUND_MASK = 15612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_INCOMPLETE_CAL_N0_MASK = 15613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_INCOMPLETE_CAL_N1_MASK = 15614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_INCOMPLETE_CAL_N2_MASK = 15615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_INCOMPLETE_CAL_N3_MASK = 15616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_COARSE_PATTERN_ERR_N0_MASK = 15617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_COARSE_PATTERN_ERR_N1_MASK = 15618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_COARSE_PATTERN_ERR_N2_MASK = 15619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_COARSE_PATTERN_ERR_N3_MASK = 15620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_EYE_CLIPPING_MASK = 15621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_NO_DQS_MASK = 15622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_NO_LOCK_MASK = 15623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_DRIFT_ERROR_MASK = 15624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_0_01_MIN_EYE_MASK = 15625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_NO_EYE_DETECTED_MASK = 15626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_LEADING_EDGE_FOUND_MASK = 15627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_TRAILING_EDGE_FOUND_MASK = 15628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_INCOMPLETE_CAL_N0_MASK = 15629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_INCOMPLETE_CAL_N1_MASK = 15630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_INCOMPLETE_CAL_N2_MASK = 15631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_INCOMPLETE_CAL_N3_MASK = 15632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_COARSE_PATTERN_ERR_N0_MASK = 15633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_COARSE_PATTERN_ERR_N1_MASK = 15634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_COARSE_PATTERN_ERR_N2_MASK = 15635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_COARSE_PATTERN_ERR_N3_MASK = 15636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_EYE_CLIPPING_MASK = 15637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_NO_DQS_MASK = 15638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_NO_LOCK_MASK = 15639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_DRIFT_ERROR_MASK = 15640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_1_01_MIN_EYE_MASK = 15641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_NO_EYE_DETECTED_MASK = 15642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_LEADING_EDGE_FOUND_MASK = 15643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_TRAILING_EDGE_FOUND_MASK = 15644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N0_MASK = 15645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N1_MASK = 15646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N2_MASK = 15647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N3_MASK = 15648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N0_MASK = 15649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N1_MASK = 15650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N2_MASK = 15651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N3_MASK = 15652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_EYE_CLIPPING_MASK = 15653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_NO_DQS_MASK = 15654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_NO_LOCK_MASK = 15655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_DRIFT_ERROR_MASK = 15656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_2_23_MIN_EYE_MASK = 15657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_NO_EYE_DETECTED_MASK = 15658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_LEADING_EDGE_FOUND_MASK = 15659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_TRAILING_EDGE_FOUND_MASK = 15660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N0_MASK = 15661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N1_MASK = 15662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N2_MASK = 15663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N3_MASK = 15664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N0_MASK = 15665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N1_MASK = 15666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N2_MASK = 15667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N3_MASK = 15668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_EYE_CLIPPING_MASK = 15669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_NO_DQS_MASK = 15670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_NO_LOCK_MASK = 15671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_DRIFT_ERROR_MASK = 15672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_3_23_MIN_EYE_MASK = 15673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_NO_EYE_DETECTED_MASK = 15674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_LEADING_EDGE_FOUND_MASK = 15675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_TRAILING_EDGE_FOUND_MASK = 15676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_INCOMPLETE_CAL_N0_MASK = 15677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_INCOMPLETE_CAL_N1_MASK = 15678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_INCOMPLETE_CAL_N2_MASK = 15679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_INCOMPLETE_CAL_N3_MASK = 15680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_COARSE_PATTERN_ERR_N0_MASK = 15681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_COARSE_PATTERN_ERR_N1_MASK = 15682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_COARSE_PATTERN_ERR_N2_MASK = 15683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_COARSE_PATTERN_ERR_N3_MASK = 15684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_EYE_CLIPPING_MASK = 15685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_NO_DQS_MASK = 15686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_NO_LOCK_MASK = 15687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_DRIFT_ERROR_MASK = 15688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_2_23_MIN_EYE_MASK = 15689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_NO_EYE_DETECTED_MASK = 15690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_LEADING_EDGE_FOUND_MASK = 15691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_TRAILING_EDGE_FOUND_MASK = 15692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_INCOMPLETE_CAL_N0_MASK = 15693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_INCOMPLETE_CAL_N1_MASK = 15694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_INCOMPLETE_CAL_N2_MASK = 15695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_INCOMPLETE_CAL_N3_MASK = 15696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_COARSE_PATTERN_ERR_N0_MASK = 15697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_COARSE_PATTERN_ERR_N1_MASK = 15698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_COARSE_PATTERN_ERR_N2_MASK = 15699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_COARSE_PATTERN_ERR_N3_MASK = 15700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_EYE_CLIPPING_MASK = 15701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_NO_DQS_MASK = 15702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_NO_LOCK_MASK = 15703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_DRIFT_ERROR_MASK = 15704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_3_23_MIN_EYE_MASK = 15705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_NO_EYE_DETECTED_MASK = 15706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_LEADING_EDGE_FOUND_MASK = 15707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_TRAILING_EDGE_FOUND_MASK = 15708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_INCOMPLETE_CAL_N0_MASK = 15709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_INCOMPLETE_CAL_N1_MASK = 15710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_INCOMPLETE_CAL_N2_MASK = 15711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_INCOMPLETE_CAL_N3_MASK = 15712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_COARSE_PATTERN_ERR_N0_MASK = 15713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_COARSE_PATTERN_ERR_N1_MASK = 15714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_COARSE_PATTERN_ERR_N2_MASK = 15715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_COARSE_PATTERN_ERR_N3_MASK = 15716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_EYE_CLIPPING_MASK = 15717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_NO_DQS_MASK = 15718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_NO_LOCK_MASK = 15719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_DRIFT_ERROR_MASK = 15720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P0_4_MIN_EYE_MASK = 15721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_NO_EYE_DETECTED_MASK = 15722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_LEADING_EDGE_FOUND_MASK = 15723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_TRAILING_EDGE_FOUND_MASK = 15724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_INCOMPLETE_CAL_N0_MASK = 15725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_INCOMPLETE_CAL_N1_MASK = 15726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_INCOMPLETE_CAL_N2_MASK = 15727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_INCOMPLETE_CAL_N3_MASK = 15728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_COARSE_PATTERN_ERR_N0_MASK = 15729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_COARSE_PATTERN_ERR_N1_MASK = 15730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_COARSE_PATTERN_ERR_N2_MASK = 15731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_COARSE_PATTERN_ERR_N3_MASK = 15732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_EYE_CLIPPING_MASK = 15733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_NO_DQS_MASK = 15734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_NO_LOCK_MASK = 15735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_DRIFT_ERROR_MASK = 15736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_ERROR_MASK0_P1_4_MIN_EYE_MASK = 15737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15 = 15738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15_LEN = 15739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15 = 15740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_0_01_LEADING_EDGE_NOT_FOUND_15 = 15742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_0_01_LEADING_EDGE_NOT_FOUND_15_LEN = 15743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_1_01_LEADING_EDGE_NOT_FOUND_0_15 = 15744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_1_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15 = 15746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15 = 15748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_2_23_LEADING_EDGE_NOT_FOUND_0_15 = 15750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_2_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_3_23_LEADING_EDGE_NOT_FOUND_0_15 = 15752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_3_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_4_LEADING_EDGE_NOT_FOUND_0_15 = 15754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P0_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_4_LEADING_EDGE_NOT_FOUND_0_15 = 15756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS0_P1_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 15757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_0_01_LEADING_EDGE_NOT_FOUND_16_23 = 15758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_0_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 15759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_1_01_LEADING_EDGE_NOT_FOUND_16_23 = 15760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_1_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 15761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_0_01_LEADING_EDGE_NOT_FOUND_16_23 = 15762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_0_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 15763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_1_01_LEADING_EDGE_NOT_FOUND_16_23 = 15764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_1_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 15765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_2_23_LEADING_EDGE_NOT_FOUND_16 = 15766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_2_23_LEADING_EDGE_NOT_FOUND_16_LEN = 15767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_3_23_LEADING_EDGE_NOT_FOUND_16 = 15768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_3_23_LEADING_EDGE_NOT_FOUND_16_LEN = 15769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_2_23_LEADING_EDGE_NOT_FOUND_16 = 15770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_2_23_LEADING_EDGE_NOT_FOUND_16_LEN = 15771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_3_23_LEADING_EDGE_NOT_FOUND_16 = 15772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_3_23_LEADING_EDGE_NOT_FOUND_16_LEN = 15773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_4_LEADING_EDGE_NOT_FOUND_16_23 = 15774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P0_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 15775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_4_LEADING_EDGE_NOT_FOUND_16_23 = 15776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS1_P1_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 15777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15 = 15778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 15779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15 = 15780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_0_01_TRAILING_EDGE_NOT_FOUND_15 = 15782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_0_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 15783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_1_01_TRAILING_EDGE_NOT_FOUND_0_15 = 15784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_1_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15 = 15786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15 = 15788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_2_23_TRAILING_EDGE_NOT_FOUND_0_15 = 15790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_2_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_3_23_TRAILING_EDGE_NOT_FOUND_0_15 = 15792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_3_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_4_TRAILING_EDGE_NOT_FOUND_0_15 = 15794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P0_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_4_TRAILING_EDGE_NOT_FOUND_0_15 = 15796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS2_P1_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 15797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_0_01_TRAILING_EDGE_NOT_FOUND_16_23 = 15798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_0_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 15799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_1_01_TRAILING_EDGE_NOT_FOUND_16_23 = 15800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_1_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 15801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_0_01_TRAILING_EDGE_NOT_FOUND_16_23 = 15802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_0_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 15803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_1_01_TRAILING_EDGE_NOT_FOUND_16_23 = 15804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_1_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 15805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_2_23_TRAILING_EDGE_NOT_FOUND_16 = 15806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_2_23_TRAILING_EDGE_NOT_FOUND_16_LEN = 15807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_3_23_TRAILING_EDGE_NOT_FOUND_16 = 15808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_3_23_TRAILING_EDGE_NOT_FOUND_16_LEN = 15809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_2_23_TRAILING_EDGE_NOT_FOUND_16 = 15810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_2_23_TRAILING_EDGE_NOT_FOUND_16_LEN = 15811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_3_23_TRAILING_EDGE_NOT_FOUND_16 = 15812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_3_23_TRAILING_EDGE_NOT_FOUND_16_LEN = 15813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_4_TRAILING_EDGE_NOT_FOUND_16_23 = 15814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P0_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 15815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_4_TRAILING_EDGE_NOT_FOUND_16_23 = 15816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_LVL_STATUS3_P1_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 15817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_NO_EYE_DETECTED = 15818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND = 15819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_TRAILING_EDGE_NOT_FOUND = 15820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N0 = 15821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N1 = 15822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N2 = 15823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N3 = 15824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N0 = 15825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N1 = 15826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N2 = 15827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N3 = 15828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_EYE_CLIPPING = 15829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_NO_DQS = 15830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_NO_LOCK = 15831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_DRIFT_ERROR = 15832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_0_01_MIN_EYE = 15833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_NO_EYE_DETECTED = 15834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND = 15835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_TRAILING_EDGE_NOT_FOUND = 15836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N0 = 15837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N1 = 15838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N2 = 15839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N3 = 15840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N0 = 15841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N1 = 15842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N2 = 15843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N3 = 15844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_EYE_CLIPPING = 15845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_NO_DQS = 15846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_NO_LOCK = 15847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_DRIFT_ERROR = 15848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_1_01_MIN_EYE = 15849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_NO_EYE_DETECTED = 15850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_LEADING_EDGE_NOT_FOUND = 15851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_TRAILING_EDGE_NOT_FOUND = 15852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_INCOMPLETE_CAL_N0 = 15853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_INCOMPLETE_CAL_N1 = 15854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_INCOMPLETE_CAL_N2 = 15855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_INCOMPLETE_CAL_N3 = 15856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_COARSE_PATTERN_ERR_N0 = 15857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_COARSE_PATTERN_ERR_N1 = 15858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_COARSE_PATTERN_ERR_N2 = 15859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_COARSE_PATTERN_ERR_N3 = 15860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_EYE_CLIPPING = 15861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_NO_DQS = 15862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_NO_LOCK = 15863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_DRIFT_ERROR = 15864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_0_01_MIN_EYE = 15865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_NO_EYE_DETECTED = 15866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_LEADING_EDGE_NOT_FOUND = 15867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_TRAILING_EDGE_NOT_FOUND = 15868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_INCOMPLETE_CAL_N0 = 15869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_INCOMPLETE_CAL_N1 = 15870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_INCOMPLETE_CAL_N2 = 15871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_INCOMPLETE_CAL_N3 = 15872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_COARSE_PATTERN_ERR_N0 = 15873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_COARSE_PATTERN_ERR_N1 = 15874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_COARSE_PATTERN_ERR_N2 = 15875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_COARSE_PATTERN_ERR_N3 = 15876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_EYE_CLIPPING = 15877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_NO_DQS = 15878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_NO_LOCK = 15879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_DRIFT_ERROR = 15880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_1_01_MIN_EYE = 15881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_NO_EYE_DETECTED = 15882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND = 15883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_TRAILING_EDGE_NOT_FOUND = 15884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N0 = 15885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N1 = 15886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N2 = 15887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N3 = 15888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N0 = 15889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N1 = 15890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N2 = 15891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N3 = 15892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_EYE_CLIPPING = 15893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_NO_DQS = 15894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_NO_LOCK = 15895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_DRIFT_ERROR = 15896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_2_23_MIN_EYE = 15897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_NO_EYE_DETECTED = 15898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND = 15899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_TRAILING_EDGE_NOT_FOUND = 15900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N0 = 15901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N1 = 15902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N2 = 15903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N3 = 15904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N0 = 15905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N1 = 15906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N2 = 15907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N3 = 15908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_EYE_CLIPPING = 15909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_NO_DQS = 15910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_NO_LOCK = 15911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_DRIFT_ERROR = 15912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_3_23_MIN_EYE = 15913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_NO_EYE_DETECTED = 15914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_LEADING_EDGE_NOT_FOUND = 15915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_TRAILING_EDGE_NOT_FOUND = 15916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_INCOMPLETE_CAL_N0 = 15917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_INCOMPLETE_CAL_N1 = 15918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_INCOMPLETE_CAL_N2 = 15919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_INCOMPLETE_CAL_N3 = 15920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_COARSE_PATTERN_ERR_N0 = 15921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_COARSE_PATTERN_ERR_N1 = 15922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_COARSE_PATTERN_ERR_N2 = 15923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_COARSE_PATTERN_ERR_N3 = 15924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_EYE_CLIPPING = 15925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_NO_DQS = 15926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_NO_LOCK = 15927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_DRIFT_ERROR = 15928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_2_23_MIN_EYE = 15929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_NO_EYE_DETECTED = 15930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_LEADING_EDGE_NOT_FOUND = 15931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_TRAILING_EDGE_NOT_FOUND = 15932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_INCOMPLETE_CAL_N0 = 15933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_INCOMPLETE_CAL_N1 = 15934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_INCOMPLETE_CAL_N2 = 15935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_INCOMPLETE_CAL_N3 = 15936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_COARSE_PATTERN_ERR_N0 = 15937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_COARSE_PATTERN_ERR_N1 = 15938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_COARSE_PATTERN_ERR_N2 = 15939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_COARSE_PATTERN_ERR_N3 = 15940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_EYE_CLIPPING = 15941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_NO_DQS = 15942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_NO_LOCK = 15943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_DRIFT_ERROR = 15944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_3_23_MIN_EYE = 15945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_NO_EYE_DETECTED = 15946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_LEADING_EDGE_NOT_FOUND = 15947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_TRAILING_EDGE_NOT_FOUND = 15948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_INCOMPLETE_CAL_N0 = 15949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_INCOMPLETE_CAL_N1 = 15950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_INCOMPLETE_CAL_N2 = 15951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_INCOMPLETE_CAL_N3 = 15952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_COARSE_PATTERN_ERR_N0 = 15953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_COARSE_PATTERN_ERR_N1 = 15954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_COARSE_PATTERN_ERR_N2 = 15955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_COARSE_PATTERN_ERR_N3 = 15956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_EYE_CLIPPING = 15957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_NO_DQS = 15958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_NO_LOCK = 15959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_DRIFT_ERROR = 15960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P0_4_MIN_EYE = 15961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_NO_EYE_DETECTED = 15962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_LEADING_EDGE_NOT_FOUND = 15963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_TRAILING_EDGE_NOT_FOUND = 15964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_INCOMPLETE_CAL_N0 = 15965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_INCOMPLETE_CAL_N1 = 15966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_INCOMPLETE_CAL_N2 = 15967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_INCOMPLETE_CAL_N3 = 15968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_COARSE_PATTERN_ERR_N0 = 15969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_COARSE_PATTERN_ERR_N1 = 15970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_COARSE_PATTERN_ERR_N2 = 15971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_COARSE_PATTERN_ERR_N3 = 15972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_EYE_CLIPPING = 15973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_NO_DQS = 15974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_NO_LOCK = 15975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_DRIFT_ERROR = 15976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_STATUS0_P1_4_MIN_EYE = 15977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16 = 15978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK16 = 15979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK16 = 15980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK16 = 15981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK18 = 15982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK18 = 15983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK20 = 15984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK20 = 15985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK22 = 15986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK22 = 15987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK16_SINGLE_ENDED = 15988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK18_SINGLE_ENDED = 15989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK20_SINGLE_ENDED = 15990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK22_SINGLE_ENDED = 15991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK16 = 15992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK16 = 15993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK16 = 15994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK16 = 15995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK18 = 15996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK18 = 15997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK20 = 15998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK20 = 15999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK22 = 16000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK22 = 16001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK16_SINGLE_ENDED = 16002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK18_SINGLE_ENDED = 16003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK20_SINGLE_ENDED = 16004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK22_SINGLE_ENDED = 16005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD0_CLK16 = 16006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD1_CLK16 = 16007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD2_CLK16 = 16008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD3_CLK16 = 16009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD0_CLK18 = 16010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD1_CLK18 = 16011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD2_CLK20 = 16012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD3_CLK20 = 16013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD2_CLK22 = 16014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_QUAD3_CLK22 = 16015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_CLK16_SINGLE_ENDED = 16016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_CLK18_SINGLE_ENDED = 16017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_CLK20_SINGLE_ENDED = 16018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_01_CLK22_SINGLE_ENDED = 16019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD0_CLK16 = 16020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD1_CLK16 = 16021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD2_CLK16 = 16022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD3_CLK16 = 16023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD0_CLK18 = 16024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD1_CLK18 = 16025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD2_CLK20 = 16026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD3_CLK20 = 16027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD2_CLK22 = 16028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_QUAD3_CLK22 = 16029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_CLK16_SINGLE_ENDED = 16030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_CLK18_SINGLE_ENDED = 16031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_CLK20_SINGLE_ENDED = 16032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_01_CLK22_SINGLE_ENDED = 16033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK16 = 16034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK16 = 16035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK16 = 16036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK16 = 16037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK18 = 16038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK18 = 16039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK20 = 16040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK20 = 16041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK22 = 16042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK22 = 16043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK16_SINGLE_ENDED = 16044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK18_SINGLE_ENDED = 16045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK20_SINGLE_ENDED = 16046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK22_SINGLE_ENDED = 16047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK16 = 16048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK16 = 16049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK16 = 16050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK16 = 16051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK18 = 16052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK18 = 16053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK20 = 16054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK20 = 16055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK22 = 16056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK22 = 16057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK16_SINGLE_ENDED = 16058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK18_SINGLE_ENDED = 16059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK20_SINGLE_ENDED = 16060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK22_SINGLE_ENDED = 16061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD0_CLK16 = 16062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD1_CLK16 = 16063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD2_CLK16 = 16064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD3_CLK16 = 16065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD0_CLK18 = 16066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD1_CLK18 = 16067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD2_CLK20 = 16068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD3_CLK20 = 16069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD2_CLK22 = 16070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_QUAD3_CLK22 = 16071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_CLK16_SINGLE_ENDED = 16072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_CLK18_SINGLE_ENDED = 16073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_CLK20_SINGLE_ENDED = 16074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_23_CLK22_SINGLE_ENDED = 16075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD0_CLK16 = 16076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD1_CLK16 = 16077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD2_CLK16 = 16078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD3_CLK16 = 16079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD0_CLK18 = 16080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD1_CLK18 = 16081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD2_CLK20 = 16082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD3_CLK20 = 16083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD2_CLK22 = 16084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_QUAD3_CLK22 = 16085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_CLK16_SINGLE_ENDED = 16086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_CLK18_SINGLE_ENDED = 16087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_CLK20_SINGLE_ENDED = 16088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_23_CLK22_SINGLE_ENDED = 16089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD0_CLK16 = 16090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD1_CLK16 = 16091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD2_CLK16 = 16092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD3_CLK16 = 16093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD0_CLK18 = 16094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD1_CLK18 = 16095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD2_CLK20 = 16096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD3_CLK20 = 16097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD2_CLK22 = 16098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_QUAD3_CLK22 = 16099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_CLK16_SINGLE_ENDED = 16100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_CLK18_SINGLE_ENDED = 16101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_CLK20_SINGLE_ENDED = 16102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_CLK22_SINGLE_ENDED = 16103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD0_CLK16 = 16104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD1_CLK16 = 16105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD2_CLK16 = 16106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD3_CLK16 = 16107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD0_CLK18 = 16108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD1_CLK18 = 16109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD2_CLK20 = 16110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD3_CLK20 = 16111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD2_CLK22 = 16112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_QUAD3_CLK22 = 16113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_CLK16_SINGLE_ENDED = 16114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_CLK18_SINGLE_ENDED = 16115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_CLK20_SINGLE_ENDED = 16116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_CLK22_SINGLE_ENDED = 16117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK16 = 16118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK16 = 16119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK16 = 16120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK16 = 16121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK18 = 16122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK18 = 16123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK20 = 16124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK20 = 16125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK22 = 16126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK22 = 16127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK16_SINGLE_ENDED = 16128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK18_SINGLE_ENDED = 16129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK20_SINGLE_ENDED = 16130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK22_SINGLE_ENDED = 16131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK16 = 16132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK16 = 16133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK16 = 16134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK16 = 16135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK18 = 16136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK18 = 16137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK20 = 16138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK20 = 16139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK22 = 16140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK22 = 16141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK16_SINGLE_ENDED = 16142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK18_SINGLE_ENDED = 16143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK20_SINGLE_ENDED = 16144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK22_SINGLE_ENDED = 16145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD0_CLK16 = 16146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD1_CLK16 = 16147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD2_CLK16 = 16148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD3_CLK16 = 16149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD0_CLK18 = 16150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD1_CLK18 = 16151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD2_CLK20 = 16152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD3_CLK20 = 16153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD2_CLK22 = 16154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_QUAD3_CLK22 = 16155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_CLK16_SINGLE_ENDED = 16156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_CLK18_SINGLE_ENDED = 16157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_CLK20_SINGLE_ENDED = 16158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_01_CLK22_SINGLE_ENDED = 16159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD0_CLK16 = 16160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD1_CLK16 = 16161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD2_CLK16 = 16162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD3_CLK16 = 16163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD0_CLK18 = 16164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD1_CLK18 = 16165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD2_CLK20 = 16166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD3_CLK20 = 16167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD2_CLK22 = 16168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_QUAD3_CLK22 = 16169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_CLK16_SINGLE_ENDED = 16170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_CLK18_SINGLE_ENDED = 16171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_CLK20_SINGLE_ENDED = 16172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_01_CLK22_SINGLE_ENDED = 16173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK16 = 16174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK16 = 16175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK16 = 16176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK16 = 16177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK18 = 16178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK18 = 16179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK20 = 16180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK20 = 16181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK22 = 16182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK22 = 16183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK16_SINGLE_ENDED = 16184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK18_SINGLE_ENDED = 16185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK20_SINGLE_ENDED = 16186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK22_SINGLE_ENDED = 16187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK16 = 16188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK16 = 16189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK16 = 16190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK16 = 16191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK18 = 16192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK18 = 16193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK20 = 16194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK20 = 16195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK22 = 16196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK22 = 16197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK16_SINGLE_ENDED = 16198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK18_SINGLE_ENDED = 16199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK20_SINGLE_ENDED = 16200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK22_SINGLE_ENDED = 16201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD0_CLK16 = 16202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD1_CLK16 = 16203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD2_CLK16 = 16204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD3_CLK16 = 16205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD0_CLK18 = 16206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD1_CLK18 = 16207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD2_CLK20 = 16208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD3_CLK20 = 16209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD2_CLK22 = 16210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_QUAD3_CLK22 = 16211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_CLK16_SINGLE_ENDED = 16212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_CLK18_SINGLE_ENDED = 16213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_CLK20_SINGLE_ENDED = 16214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_23_CLK22_SINGLE_ENDED = 16215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD0_CLK16 = 16216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD1_CLK16 = 16217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD2_CLK16 = 16218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD3_CLK16 = 16219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD0_CLK18 = 16220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD1_CLK18 = 16221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD2_CLK20 = 16222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD3_CLK20 = 16223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD2_CLK22 = 16224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_QUAD3_CLK22 = 16225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_CLK16_SINGLE_ENDED = 16226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_CLK18_SINGLE_ENDED = 16227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_CLK20_SINGLE_ENDED = 16228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_23_CLK22_SINGLE_ENDED = 16229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD0_CLK16 = 16230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD1_CLK16 = 16231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD2_CLK16 = 16232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD3_CLK16 = 16233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD0_CLK18 = 16234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD1_CLK18 = 16235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD2_CLK20 = 16236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD3_CLK20 = 16237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD2_CLK22 = 16238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_QUAD3_CLK22 = 16239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_CLK16_SINGLE_ENDED = 16240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_CLK18_SINGLE_ENDED = 16241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_CLK20_SINGLE_ENDED = 16242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_CLK22_SINGLE_ENDED = 16243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD0_CLK16 = 16244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD1_CLK16 = 16245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD2_CLK16 = 16246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD3_CLK16 = 16247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD0_CLK18 = 16248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD1_CLK18 = 16249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD2_CLK20 = 16250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD3_CLK20 = 16251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD2_CLK22 = 16252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_QUAD3_CLK22 = 16253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_CLK16_SINGLE_ENDED = 16254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_CLK18_SINGLE_ENDED = 16255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_CLK20_SINGLE_ENDED = 16256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_CLK22_SINGLE_ENDED = 16257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK16 = 16258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK16 = 16259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK16 = 16260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK16 = 16261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK18 = 16262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK18 = 16263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK20 = 16264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK20 = 16265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK22 = 16266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK22 = 16267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK16_SINGLE_ENDED = 16268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK18_SINGLE_ENDED = 16269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK20_SINGLE_ENDED = 16270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK22_SINGLE_ENDED = 16271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK16 = 16272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK16 = 16273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK16 = 16274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK16 = 16275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK18 = 16276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK18 = 16277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK20 = 16278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK20 = 16279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK22 = 16280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK22 = 16281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK16_SINGLE_ENDED = 16282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK18_SINGLE_ENDED = 16283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK20_SINGLE_ENDED = 16284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK22_SINGLE_ENDED = 16285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD0_CLK16 = 16286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD1_CLK16 = 16287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD2_CLK16 = 16288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD3_CLK16 = 16289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD0_CLK18 = 16290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD1_CLK18 = 16291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD2_CLK20 = 16292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD3_CLK20 = 16293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD2_CLK22 = 16294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_QUAD3_CLK22 = 16295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_CLK16_SINGLE_ENDED = 16296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_CLK18_SINGLE_ENDED = 16297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_CLK20_SINGLE_ENDED = 16298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_01_CLK22_SINGLE_ENDED = 16299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD0_CLK16 = 16300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD1_CLK16 = 16301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD2_CLK16 = 16302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD3_CLK16 = 16303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD0_CLK18 = 16304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD1_CLK18 = 16305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD2_CLK20 = 16306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD3_CLK20 = 16307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD2_CLK22 = 16308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_QUAD3_CLK22 = 16309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_CLK16_SINGLE_ENDED = 16310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_CLK18_SINGLE_ENDED = 16311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_CLK20_SINGLE_ENDED = 16312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_01_CLK22_SINGLE_ENDED = 16313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK16 = 16314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK16 = 16315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK16 = 16316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK16 = 16317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK18 = 16318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK18 = 16319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK20 = 16320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK20 = 16321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK22 = 16322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK22 = 16323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK16_SINGLE_ENDED = 16324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK18_SINGLE_ENDED = 16325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK20_SINGLE_ENDED = 16326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK22_SINGLE_ENDED = 16327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK16 = 16328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK16 = 16329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK16 = 16330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK16 = 16331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK18 = 16332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK18 = 16333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK20 = 16334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK20 = 16335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK22 = 16336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK22 = 16337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK16_SINGLE_ENDED = 16338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK18_SINGLE_ENDED = 16339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK20_SINGLE_ENDED = 16340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK22_SINGLE_ENDED = 16341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD0_CLK16 = 16342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD1_CLK16 = 16343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD2_CLK16 = 16344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD3_CLK16 = 16345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD0_CLK18 = 16346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD1_CLK18 = 16347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD2_CLK20 = 16348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD3_CLK20 = 16349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD2_CLK22 = 16350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_QUAD3_CLK22 = 16351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_CLK16_SINGLE_ENDED = 16352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_CLK18_SINGLE_ENDED = 16353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_CLK20_SINGLE_ENDED = 16354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_23_CLK22_SINGLE_ENDED = 16355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD0_CLK16 = 16356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD1_CLK16 = 16357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD2_CLK16 = 16358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD3_CLK16 = 16359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD0_CLK18 = 16360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD1_CLK18 = 16361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD2_CLK20 = 16362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD3_CLK20 = 16363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD2_CLK22 = 16364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_QUAD3_CLK22 = 16365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_CLK16_SINGLE_ENDED = 16366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_CLK18_SINGLE_ENDED = 16367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_CLK20_SINGLE_ENDED = 16368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_23_CLK22_SINGLE_ENDED = 16369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD0_CLK16 = 16370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD1_CLK16 = 16371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD2_CLK16 = 16372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD3_CLK16 = 16373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD0_CLK18 = 16374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD1_CLK18 = 16375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD2_CLK20 = 16376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD3_CLK20 = 16377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD2_CLK22 = 16378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_QUAD3_CLK22 = 16379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_CLK16_SINGLE_ENDED = 16380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_CLK18_SINGLE_ENDED = 16381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_CLK20_SINGLE_ENDED = 16382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_CLK22_SINGLE_ENDED = 16383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD0_CLK16 = 16384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD1_CLK16 = 16385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD2_CLK16 = 16386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD3_CLK16 = 16387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD0_CLK18 = 16388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD1_CLK18 = 16389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD2_CLK20 = 16390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD3_CLK20 = 16391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD2_CLK22 = 16392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_QUAD3_CLK22 = 16393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_CLK16_SINGLE_ENDED = 16394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_CLK18_SINGLE_ENDED = 16395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_CLK20_SINGLE_ENDED = 16396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_CLK22_SINGLE_ENDED = 16397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK16 = 16398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK16 = 16399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK16 = 16400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK16 = 16401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK18 = 16402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK18 = 16403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK20 = 16404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK20 = 16405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK22 = 16406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK22 = 16407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK16_SINGLE_ENDED = 16408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK18_SINGLE_ENDED = 16409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK20_SINGLE_ENDED = 16410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK22_SINGLE_ENDED = 16411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK16 = 16412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK16 = 16413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK16 = 16414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK16 = 16415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK18 = 16416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK18 = 16417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK20 = 16418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK20 = 16419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK22 = 16420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK22 = 16421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK16_SINGLE_ENDED = 16422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK18_SINGLE_ENDED = 16423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK20_SINGLE_ENDED = 16424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK22_SINGLE_ENDED = 16425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD0_CLK16 = 16426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD1_CLK16 = 16427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD2_CLK16 = 16428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD3_CLK16 = 16429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD0_CLK18 = 16430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD1_CLK18 = 16431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD2_CLK20 = 16432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD3_CLK20 = 16433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD2_CLK22 = 16434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_QUAD3_CLK22 = 16435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_CLK16_SINGLE_ENDED = 16436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_CLK18_SINGLE_ENDED = 16437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_CLK20_SINGLE_ENDED = 16438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_01_CLK22_SINGLE_ENDED = 16439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD0_CLK16 = 16440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD1_CLK16 = 16441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD2_CLK16 = 16442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD3_CLK16 = 16443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD0_CLK18 = 16444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD1_CLK18 = 16445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD2_CLK20 = 16446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD3_CLK20 = 16447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD2_CLK22 = 16448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_QUAD3_CLK22 = 16449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_CLK16_SINGLE_ENDED = 16450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_CLK18_SINGLE_ENDED = 16451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_CLK20_SINGLE_ENDED = 16452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_01_CLK22_SINGLE_ENDED = 16453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK16 = 16454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK16 = 16455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK16 = 16456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK16 = 16457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK18 = 16458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK18 = 16459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK20 = 16460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK20 = 16461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK22 = 16462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK22 = 16463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK16_SINGLE_ENDED = 16464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK18_SINGLE_ENDED = 16465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK20_SINGLE_ENDED = 16466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK22_SINGLE_ENDED = 16467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK16 = 16468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK16 = 16469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK16 = 16470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK16 = 16471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK18 = 16472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK18 = 16473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK20 = 16474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK20 = 16475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK22 = 16476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK22 = 16477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK16_SINGLE_ENDED = 16478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK18_SINGLE_ENDED = 16479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK20_SINGLE_ENDED = 16480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK22_SINGLE_ENDED = 16481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD0_CLK16 = 16482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD1_CLK16 = 16483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD2_CLK16 = 16484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD3_CLK16 = 16485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD0_CLK18 = 16486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD1_CLK18 = 16487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD2_CLK20 = 16488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD3_CLK20 = 16489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD2_CLK22 = 16490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_QUAD3_CLK22 = 16491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_CLK16_SINGLE_ENDED = 16492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_CLK18_SINGLE_ENDED = 16493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_CLK20_SINGLE_ENDED = 16494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_23_CLK22_SINGLE_ENDED = 16495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD0_CLK16 = 16496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD1_CLK16 = 16497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD2_CLK16 = 16498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD3_CLK16 = 16499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD0_CLK18 = 16500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD1_CLK18 = 16501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD2_CLK20 = 16502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD3_CLK20 = 16503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD2_CLK22 = 16504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_QUAD3_CLK22 = 16505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_CLK16_SINGLE_ENDED = 16506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_CLK18_SINGLE_ENDED = 16507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_CLK20_SINGLE_ENDED = 16508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_23_CLK22_SINGLE_ENDED = 16509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD0_CLK16 = 16510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD1_CLK16 = 16511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD2_CLK16 = 16512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD3_CLK16 = 16513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD0_CLK18 = 16514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD1_CLK18 = 16515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD2_CLK20 = 16516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD3_CLK20 = 16517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD2_CLK22 = 16518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_QUAD3_CLK22 = 16519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_CLK16_SINGLE_ENDED = 16520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_CLK18_SINGLE_ENDED = 16521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_CLK20_SINGLE_ENDED = 16522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_CLK22_SINGLE_ENDED = 16523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD0_CLK16 = 16524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD1_CLK16 = 16525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD2_CLK16 = 16526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD3_CLK16 = 16527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD0_CLK18 = 16528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD1_CLK18 = 16529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD2_CLK20 = 16530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD3_CLK20 = 16531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD2_CLK22 = 16532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_QUAD3_CLK22 = 16533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_CLK16_SINGLE_ENDED = 16534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_CLK18_SINGLE_ENDED = 16535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_CLK20_SINGLE_ENDED = 16536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_CLK22_SINGLE_ENDED = 16537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_0_01_RD = 16538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_LEN = 16539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1 = 16540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 16541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_1_01_RD = 16542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_LEN = 16543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1 = 16544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 16545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_0_01_RD = 16546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_0_01_RD_LEN = 16547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_0_01_RD_DELAY1 = 16548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_0_01_RD_DELAY1_LEN = 16549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_1_01_RD = 16550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_1_01_RD_LEN = 16551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_1_01_RD_DELAY1 = 16552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_1_01_RD_DELAY1_LEN = 16553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_2_23_RD = 16554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_LEN = 16555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1 = 16556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 16557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_3_23_RD = 16558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_LEN = 16559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1 = 16560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 16561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_2_23_RD = 16562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_2_23_RD_LEN = 16563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_2_23_RD_DELAY1 = 16564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_2_23_RD_DELAY1_LEN = 16565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_3_23_RD = 16566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_3_23_RD_LEN = 16567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_3_23_RD_DELAY1 = 16568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_3_23_RD_DELAY1_LEN = 16569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_4_RD = 16570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_4_RD_LEN = 16571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_4_RD_DELAY1 = 16572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_4_RD_DELAY1_LEN = 16573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_4_RD = 16574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_4_RD_LEN = 16575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_4_RD_DELAY1 = 16576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P1_4_RD_DELAY1_LEN = 16577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2 = 16578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 16579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3 = 16580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 16581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2 = 16582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 16583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3 = 16584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 16585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_0_01_RD_DELAY2 = 16586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_0_01_RD_DELAY2_LEN = 16587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_0_01_RD_DELAY3 = 16588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_0_01_RD_DELAY3_LEN = 16589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_1_01_RD_DELAY2 = 16590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_1_01_RD_DELAY2_LEN = 16591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_1_01_RD_DELAY3 = 16592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_1_01_RD_DELAY3_LEN = 16593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2 = 16594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 16595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3 = 16596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 16597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2 = 16598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 16599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3 = 16600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 16601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_2_23_RD_DELAY2 = 16602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_2_23_RD_DELAY2_LEN = 16603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_2_23_RD_DELAY3 = 16604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_2_23_RD_DELAY3_LEN = 16605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_3_23_RD_DELAY2 = 16606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_3_23_RD_DELAY2_LEN = 16607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_3_23_RD_DELAY3 = 16608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_3_23_RD_DELAY3_LEN = 16609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_4_RD_DELAY2 = 16610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_4_RD_DELAY2_LEN = 16611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_4_RD_DELAY3 = 16612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P0_4_RD_DELAY3_LEN = 16613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_4_RD_DELAY2 = 16614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_4_RD_DELAY2_LEN = 16615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_4_RD_DELAY3 = 16616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR1_P1_4_RD_DELAY3_LEN = 16617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4 = 16618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 16619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5 = 16620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 16621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4 = 16622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 16623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5 = 16624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 16625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_0_01_RD_DELAY4 = 16626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_0_01_RD_DELAY4_LEN = 16627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_0_01_RD_DELAY5 = 16628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_0_01_RD_DELAY5_LEN = 16629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_1_01_RD_DELAY4 = 16630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_1_01_RD_DELAY4_LEN = 16631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_1_01_RD_DELAY5 = 16632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_1_01_RD_DELAY5_LEN = 16633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4 = 16634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 16635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5 = 16636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 16637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4 = 16638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 16639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5 = 16640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 16641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_2_23_RD_DELAY4 = 16642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_2_23_RD_DELAY4_LEN = 16643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_2_23_RD_DELAY5 = 16644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_2_23_RD_DELAY5_LEN = 16645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_3_23_RD_DELAY4 = 16646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_3_23_RD_DELAY4_LEN = 16647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_3_23_RD_DELAY5 = 16648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_3_23_RD_DELAY5_LEN = 16649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_4_RD_DELAY4 = 16650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_4_RD_DELAY4_LEN = 16651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_4_RD_DELAY5 = 16652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P0_4_RD_DELAY5_LEN = 16653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_4_RD_DELAY4 = 16654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_4_RD_DELAY4_LEN = 16655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_4_RD_DELAY5 = 16656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR2_P1_4_RD_DELAY5_LEN = 16657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6 = 16658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 16659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7 = 16660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 16661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6 = 16662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 16663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7 = 16664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 16665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_0_01_RD_DELAY6 = 16666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_0_01_RD_DELAY6_LEN = 16667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_0_01_RD_DELAY7 = 16668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_0_01_RD_DELAY7_LEN = 16669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_1_01_RD_DELAY6 = 16670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_1_01_RD_DELAY6_LEN = 16671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_1_01_RD_DELAY7 = 16672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_1_01_RD_DELAY7_LEN = 16673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6 = 16674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 16675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7 = 16676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 16677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6 = 16678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 16679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7 = 16680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 16681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_2_23_RD_DELAY6 = 16682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_2_23_RD_DELAY6_LEN = 16683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_2_23_RD_DELAY7 = 16684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_2_23_RD_DELAY7_LEN = 16685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_3_23_RD_DELAY6 = 16686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_3_23_RD_DELAY6_LEN = 16687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_3_23_RD_DELAY7 = 16688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_3_23_RD_DELAY7_LEN = 16689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_4_RD_DELAY6 = 16690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_4_RD_DELAY6_LEN = 16691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_4_RD_DELAY7 = 16692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P0_4_RD_DELAY7_LEN = 16693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_4_RD_DELAY6 = 16694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_4_RD_DELAY6_LEN = 16695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_4_RD_DELAY7 = 16696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY0_RANK_PAIR3_P1_4_RD_DELAY7_LEN = 16697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0 = 16698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 16699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_0_01_RD = 16700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_LEN = 16701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0 = 16702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 16703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_1_01_RD = 16704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_LEN = 16705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_0_01_RD_DELAY0 = 16706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_0_01_RD_DELAY0_LEN = 16707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_0_01_RD = 16708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_0_01_RD_LEN = 16709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_1_01_RD_DELAY0 = 16710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_1_01_RD_DELAY0_LEN = 16711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_1_01_RD = 16712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_1_01_RD_LEN = 16713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0 = 16714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 16715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_2_23_RD = 16716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_LEN = 16717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0 = 16718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 16719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_3_23_RD = 16720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_LEN = 16721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_2_23_RD_DELAY0 = 16722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_2_23_RD_DELAY0_LEN = 16723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_2_23_RD = 16724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_2_23_RD_LEN = 16725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_3_23_RD_DELAY0 = 16726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_3_23_RD_DELAY0_LEN = 16727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_3_23_RD = 16728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_3_23_RD_LEN = 16729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_4_RD_DELAY0 = 16730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_4_RD_DELAY0_LEN = 16731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_4_RD = 16732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P0_4_RD_LEN = 16733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_4_RD_DELAY0 = 16734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_4_RD_DELAY0_LEN = 16735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_4_RD = 16736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR0_P1_4_RD_LEN = 16737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2 = 16738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 16739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3 = 16740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 16741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2 = 16742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 16743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3 = 16744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 16745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_0_01_RD_DELAY2 = 16746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_0_01_RD_DELAY2_LEN = 16747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_0_01_RD_DELAY3 = 16748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_0_01_RD_DELAY3_LEN = 16749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_1_01_RD_DELAY2 = 16750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_1_01_RD_DELAY2_LEN = 16751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_1_01_RD_DELAY3 = 16752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_1_01_RD_DELAY3_LEN = 16753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2 = 16754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 16755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3 = 16756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 16757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2 = 16758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 16759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3 = 16760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 16761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_2_23_RD_DELAY2 = 16762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_2_23_RD_DELAY2_LEN = 16763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_2_23_RD_DELAY3 = 16764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_2_23_RD_DELAY3_LEN = 16765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_3_23_RD_DELAY2 = 16766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_3_23_RD_DELAY2_LEN = 16767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_3_23_RD_DELAY3 = 16768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_3_23_RD_DELAY3_LEN = 16769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_4_RD_DELAY2 = 16770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_4_RD_DELAY2_LEN = 16771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_4_RD_DELAY3 = 16772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P0_4_RD_DELAY3_LEN = 16773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_4_RD_DELAY2 = 16774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_4_RD_DELAY2_LEN = 16775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_4_RD_DELAY3 = 16776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR1_P1_4_RD_DELAY3_LEN = 16777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4 = 16778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 16779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5 = 16780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 16781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4 = 16782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 16783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5 = 16784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 16785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_0_01_RD_DELAY4 = 16786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_0_01_RD_DELAY4_LEN = 16787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_0_01_RD_DELAY5 = 16788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_0_01_RD_DELAY5_LEN = 16789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_1_01_RD_DELAY4 = 16790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_1_01_RD_DELAY4_LEN = 16791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_1_01_RD_DELAY5 = 16792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_1_01_RD_DELAY5_LEN = 16793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4 = 16794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 16795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5 = 16796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 16797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4 = 16798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 16799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5 = 16800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 16801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_2_23_RD_DELAY4 = 16802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_2_23_RD_DELAY4_LEN = 16803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_2_23_RD_DELAY5 = 16804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_2_23_RD_DELAY5_LEN = 16805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_3_23_RD_DELAY4 = 16806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_3_23_RD_DELAY4_LEN = 16807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_3_23_RD_DELAY5 = 16808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_3_23_RD_DELAY5_LEN = 16809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_4_RD_DELAY4 = 16810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_4_RD_DELAY4_LEN = 16811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_4_RD_DELAY5 = 16812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P0_4_RD_DELAY5_LEN = 16813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_4_RD_DELAY4 = 16814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_4_RD_DELAY4_LEN = 16815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_4_RD_DELAY5 = 16816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR2_P1_4_RD_DELAY5_LEN = 16817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6 = 16818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 16819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7 = 16820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 16821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6 = 16822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 16823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7 = 16824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 16825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_0_01_RD_DELAY6 = 16826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_0_01_RD_DELAY6_LEN = 16827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_0_01_RD_DELAY7 = 16828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_0_01_RD_DELAY7_LEN = 16829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_1_01_RD_DELAY6 = 16830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_1_01_RD_DELAY6_LEN = 16831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_1_01_RD_DELAY7 = 16832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_1_01_RD_DELAY7_LEN = 16833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6 = 16834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 16835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7 = 16836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 16837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6 = 16838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 16839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7 = 16840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 16841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_2_23_RD_DELAY6 = 16842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_2_23_RD_DELAY6_LEN = 16843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_2_23_RD_DELAY7 = 16844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_2_23_RD_DELAY7_LEN = 16845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_3_23_RD_DELAY6 = 16846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_3_23_RD_DELAY6_LEN = 16847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_3_23_RD_DELAY7 = 16848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_3_23_RD_DELAY7_LEN = 16849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_4_RD_DELAY6 = 16850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_4_RD_DELAY6_LEN = 16851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_4_RD_DELAY7 = 16852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P0_4_RD_DELAY7_LEN = 16853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_4_RD_DELAY6 = 16854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_4_RD_DELAY6_LEN = 16855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_4_RD_DELAY7 = 16856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY1_RANK_PAIR3_P1_4_RD_DELAY7_LEN = 16857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0 = 16858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 16859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1 = 16860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 16861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0 = 16862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 16863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1 = 16864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 16865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_0_01_RD_DELAY0 = 16866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_0_01_RD_DELAY0_LEN = 16867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_0_01_RD_DELAY1 = 16868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_0_01_RD_DELAY1_LEN = 16869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_1_01_RD_DELAY0 = 16870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_1_01_RD_DELAY0_LEN = 16871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_1_01_RD_DELAY1 = 16872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_1_01_RD_DELAY1_LEN = 16873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0 = 16874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 16875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1 = 16876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 16877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0 = 16878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 16879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1 = 16880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 16881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_2_23_RD_DELAY0 = 16882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_2_23_RD_DELAY0_LEN = 16883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_2_23_RD_DELAY1 = 16884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_2_23_RD_DELAY1_LEN = 16885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_3_23_RD_DELAY0 = 16886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_3_23_RD_DELAY0_LEN = 16887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_3_23_RD_DELAY1 = 16888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_3_23_RD_DELAY1_LEN = 16889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_4_RD_DELAY0 = 16890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_4_RD_DELAY0_LEN = 16891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_4_RD_DELAY1 = 16892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P0_4_RD_DELAY1_LEN = 16893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_4_RD_DELAY0 = 16894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_4_RD_DELAY0_LEN = 16895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_4_RD_DELAY1 = 16896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR0_P1_4_RD_DELAY1_LEN = 16897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_0_01_RD = 16898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_LEN = 16899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3 = 16900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 16901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_1_01_RD = 16902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_LEN = 16903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3 = 16904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 16905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_0_01_RD = 16906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_0_01_RD_LEN = 16907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_0_01_RD_DELAY3 = 16908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_0_01_RD_DELAY3_LEN = 16909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_1_01_RD = 16910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_1_01_RD_LEN = 16911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_1_01_RD_DELAY3 = 16912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_1_01_RD_DELAY3_LEN = 16913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_2_23_RD = 16914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_LEN = 16915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3 = 16916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 16917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_3_23_RD = 16918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_LEN = 16919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3 = 16920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 16921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_2_23_RD = 16922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_2_23_RD_LEN = 16923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_2_23_RD_DELAY3 = 16924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_2_23_RD_DELAY3_LEN = 16925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_3_23_RD = 16926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_3_23_RD_LEN = 16927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_3_23_RD_DELAY3 = 16928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_3_23_RD_DELAY3_LEN = 16929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_4_RD = 16930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_4_RD_LEN = 16931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_4_RD_DELAY3 = 16932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P0_4_RD_DELAY3_LEN = 16933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_4_RD = 16934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_4_RD_LEN = 16935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_4_RD_DELAY3 = 16936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR1_P1_4_RD_DELAY3_LEN = 16937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4 = 16938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 16939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5 = 16940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 16941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4 = 16942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 16943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5 = 16944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 16945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_0_01_RD_DELAY4 = 16946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_0_01_RD_DELAY4_LEN = 16947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_0_01_RD_DELAY5 = 16948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_0_01_RD_DELAY5_LEN = 16949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_1_01_RD_DELAY4 = 16950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_1_01_RD_DELAY4_LEN = 16951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_1_01_RD_DELAY5 = 16952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_1_01_RD_DELAY5_LEN = 16953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4 = 16954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 16955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5 = 16956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 16957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4 = 16958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 16959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5 = 16960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 16961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_2_23_RD_DELAY4 = 16962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_2_23_RD_DELAY4_LEN = 16963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_2_23_RD_DELAY5 = 16964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_2_23_RD_DELAY5_LEN = 16965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_3_23_RD_DELAY4 = 16966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_3_23_RD_DELAY4_LEN = 16967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_3_23_RD_DELAY5 = 16968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_3_23_RD_DELAY5_LEN = 16969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_4_RD_DELAY4 = 16970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_4_RD_DELAY4_LEN = 16971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_4_RD_DELAY5 = 16972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P0_4_RD_DELAY5_LEN = 16973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_4_RD_DELAY4 = 16974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_4_RD_DELAY4_LEN = 16975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_4_RD_DELAY5 = 16976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR2_P1_4_RD_DELAY5_LEN = 16977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6 = 16978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 16979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7 = 16980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 16981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6 = 16982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 16983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7 = 16984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 16985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_0_01_RD_DELAY6 = 16986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_0_01_RD_DELAY6_LEN = 16987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_0_01_RD_DELAY7 = 16988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_0_01_RD_DELAY7_LEN = 16989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_1_01_RD_DELAY6 = 16990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_1_01_RD_DELAY6_LEN = 16991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_1_01_RD_DELAY7 = 16992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_1_01_RD_DELAY7_LEN = 16993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6 = 16994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 16995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7 = 16996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 16997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6 = 16998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 16999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7 = 17000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 17001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_2_23_RD_DELAY6 = 17002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_2_23_RD_DELAY6_LEN = 17003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_2_23_RD_DELAY7 = 17004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_2_23_RD_DELAY7_LEN = 17005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_3_23_RD_DELAY6 = 17006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_3_23_RD_DELAY6_LEN = 17007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_3_23_RD_DELAY7 = 17008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_3_23_RD_DELAY7_LEN = 17009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_4_RD_DELAY6 = 17010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_4_RD_DELAY6_LEN = 17011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_4_RD_DELAY7 = 17012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P0_4_RD_DELAY7_LEN = 17013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_4_RD_DELAY6 = 17014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_4_RD_DELAY6_LEN = 17015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_4_RD_DELAY7 = 17016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY2_RANK_PAIR3_P1_4_RD_DELAY7_LEN = 17017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0 = 17018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 17019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1 = 17020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 17021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0 = 17022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 17023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1 = 17024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 17025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_0_01_RD_DELAY0 = 17026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_0_01_RD_DELAY0_LEN = 17027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_0_01_RD_DELAY1 = 17028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_0_01_RD_DELAY1_LEN = 17029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_1_01_RD_DELAY0 = 17030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_1_01_RD_DELAY0_LEN = 17031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_1_01_RD_DELAY1 = 17032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_1_01_RD_DELAY1_LEN = 17033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0 = 17034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 17035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1 = 17036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 17037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0 = 17038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 17039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1 = 17040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 17041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_2_23_RD_DELAY0 = 17042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_2_23_RD_DELAY0_LEN = 17043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_2_23_RD_DELAY1 = 17044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_2_23_RD_DELAY1_LEN = 17045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_3_23_RD_DELAY0 = 17046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_3_23_RD_DELAY0_LEN = 17047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_3_23_RD_DELAY1 = 17048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_3_23_RD_DELAY1_LEN = 17049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_4_RD_DELAY0 = 17050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_4_RD_DELAY0_LEN = 17051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_4_RD_DELAY1 = 17052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P0_4_RD_DELAY1_LEN = 17053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_4_RD_DELAY0 = 17054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_4_RD_DELAY0_LEN = 17055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_4_RD_DELAY1 = 17056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR0_P1_4_RD_DELAY1_LEN = 17057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2 = 17058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 17059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_0_01_RD = 17060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_LEN = 17061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2 = 17062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 17063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_1_01_RD = 17064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_LEN = 17065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_0_01_RD_DELAY2 = 17066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_0_01_RD_DELAY2_LEN = 17067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_0_01_RD = 17068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_0_01_RD_LEN = 17069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_1_01_RD_DELAY2 = 17070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_1_01_RD_DELAY2_LEN = 17071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_1_01_RD = 17072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_1_01_RD_LEN = 17073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2 = 17074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 17075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_2_23_RD = 17076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_LEN = 17077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2 = 17078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 17079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_3_23_RD = 17080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_LEN = 17081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_2_23_RD_DELAY2 = 17082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_2_23_RD_DELAY2_LEN = 17083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_2_23_RD = 17084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_2_23_RD_LEN = 17085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_3_23_RD_DELAY2 = 17086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_3_23_RD_DELAY2_LEN = 17087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_3_23_RD = 17088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_3_23_RD_LEN = 17089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_4_RD_DELAY2 = 17090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_4_RD_DELAY2_LEN = 17091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_4_RD = 17092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P0_4_RD_LEN = 17093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_4_RD_DELAY2 = 17094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_4_RD_DELAY2_LEN = 17095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_4_RD = 17096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR1_P1_4_RD_LEN = 17097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4 = 17098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 17099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5 = 17100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 17101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4 = 17102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 17103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5 = 17104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 17105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_0_01_RD_DELAY4 = 17106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_0_01_RD_DELAY4_LEN = 17107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_0_01_RD_DELAY5 = 17108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_0_01_RD_DELAY5_LEN = 17109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_1_01_RD_DELAY4 = 17110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_1_01_RD_DELAY4_LEN = 17111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_1_01_RD_DELAY5 = 17112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_1_01_RD_DELAY5_LEN = 17113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4 = 17114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 17115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5 = 17116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 17117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4 = 17118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 17119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5 = 17120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 17121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_2_23_RD_DELAY4 = 17122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_2_23_RD_DELAY4_LEN = 17123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_2_23_RD_DELAY5 = 17124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_2_23_RD_DELAY5_LEN = 17125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_3_23_RD_DELAY4 = 17126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_3_23_RD_DELAY4_LEN = 17127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_3_23_RD_DELAY5 = 17128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_3_23_RD_DELAY5_LEN = 17129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_4_RD_DELAY4 = 17130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_4_RD_DELAY4_LEN = 17131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_4_RD_DELAY5 = 17132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P0_4_RD_DELAY5_LEN = 17133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_4_RD_DELAY4 = 17134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_4_RD_DELAY4_LEN = 17135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_4_RD_DELAY5 = 17136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR2_P1_4_RD_DELAY5_LEN = 17137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6 = 17138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 17139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7 = 17140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 17141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6 = 17142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 17143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7 = 17144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 17145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_0_01_RD_DELAY6 = 17146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_0_01_RD_DELAY6_LEN = 17147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_0_01_RD_DELAY7 = 17148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_0_01_RD_DELAY7_LEN = 17149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_1_01_RD_DELAY6 = 17150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_1_01_RD_DELAY6_LEN = 17151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_1_01_RD_DELAY7 = 17152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_1_01_RD_DELAY7_LEN = 17153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6 = 17154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 17155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7 = 17156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 17157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6 = 17158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 17159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7 = 17160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 17161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_2_23_RD_DELAY6 = 17162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_2_23_RD_DELAY6_LEN = 17163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_2_23_RD_DELAY7 = 17164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_2_23_RD_DELAY7_LEN = 17165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_3_23_RD_DELAY6 = 17166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_3_23_RD_DELAY6_LEN = 17167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_3_23_RD_DELAY7 = 17168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_3_23_RD_DELAY7_LEN = 17169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_4_RD_DELAY6 = 17170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_4_RD_DELAY6_LEN = 17171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_4_RD_DELAY7 = 17172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P0_4_RD_DELAY7_LEN = 17173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_4_RD_DELAY6 = 17174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_4_RD_DELAY6_LEN = 17175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_4_RD_DELAY7 = 17176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY3_RANK_PAIR3_P1_4_RD_DELAY7_LEN = 17177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0 = 17178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 17179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1 = 17180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 17181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0 = 17182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 17183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1 = 17184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 17185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_0_01_RD_DELAY0 = 17186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_0_01_RD_DELAY0_LEN = 17187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_0_01_RD_DELAY1 = 17188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_0_01_RD_DELAY1_LEN = 17189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_1_01_RD_DELAY0 = 17190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_1_01_RD_DELAY0_LEN = 17191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_1_01_RD_DELAY1 = 17192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_1_01_RD_DELAY1_LEN = 17193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0 = 17194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 17195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1 = 17196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 17197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0 = 17198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 17199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1 = 17200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 17201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_2_23_RD_DELAY0 = 17202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_2_23_RD_DELAY0_LEN = 17203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_2_23_RD_DELAY1 = 17204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_2_23_RD_DELAY1_LEN = 17205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_3_23_RD_DELAY0 = 17206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_3_23_RD_DELAY0_LEN = 17207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_3_23_RD_DELAY1 = 17208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_3_23_RD_DELAY1_LEN = 17209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_4_RD_DELAY0 = 17210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_4_RD_DELAY0_LEN = 17211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_4_RD_DELAY1 = 17212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P0_4_RD_DELAY1_LEN = 17213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_4_RD_DELAY0 = 17214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_4_RD_DELAY0_LEN = 17215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_4_RD_DELAY1 = 17216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR0_P1_4_RD_DELAY1_LEN = 17217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2 = 17218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 17219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3 = 17220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 17221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2 = 17222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 17223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3 = 17224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 17225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_0_01_RD_DELAY2 = 17226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_0_01_RD_DELAY2_LEN = 17227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_0_01_RD_DELAY3 = 17228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_0_01_RD_DELAY3_LEN = 17229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_1_01_RD_DELAY2 = 17230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_1_01_RD_DELAY2_LEN = 17231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_1_01_RD_DELAY3 = 17232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_1_01_RD_DELAY3_LEN = 17233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2 = 17234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 17235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3 = 17236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 17237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2 = 17238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 17239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3 = 17240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 17241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_2_23_RD_DELAY2 = 17242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_2_23_RD_DELAY2_LEN = 17243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_2_23_RD_DELAY3 = 17244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_2_23_RD_DELAY3_LEN = 17245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_3_23_RD_DELAY2 = 17246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_3_23_RD_DELAY2_LEN = 17247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_3_23_RD_DELAY3 = 17248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_3_23_RD_DELAY3_LEN = 17249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_4_RD_DELAY2 = 17250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_4_RD_DELAY2_LEN = 17251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_4_RD_DELAY3 = 17252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P0_4_RD_DELAY3_LEN = 17253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_4_RD_DELAY2 = 17254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_4_RD_DELAY2_LEN = 17255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_4_RD_DELAY3 = 17256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR1_P1_4_RD_DELAY3_LEN = 17257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_0_01_RD = 17258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_LEN = 17259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5 = 17260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 17261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_1_01_RD = 17262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_LEN = 17263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5 = 17264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 17265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_0_01_RD = 17266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_0_01_RD_LEN = 17267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_0_01_RD_DELAY5 = 17268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_0_01_RD_DELAY5_LEN = 17269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_1_01_RD = 17270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_1_01_RD_LEN = 17271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_1_01_RD_DELAY5 = 17272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_1_01_RD_DELAY5_LEN = 17273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_2_23_RD = 17274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_LEN = 17275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5 = 17276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 17277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_3_23_RD = 17278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_LEN = 17279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5 = 17280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 17281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_2_23_RD = 17282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_2_23_RD_LEN = 17283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_2_23_RD_DELAY5 = 17284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_2_23_RD_DELAY5_LEN = 17285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_3_23_RD = 17286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_3_23_RD_LEN = 17287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_3_23_RD_DELAY5 = 17288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_3_23_RD_DELAY5_LEN = 17289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_4_RD = 17290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_4_RD_LEN = 17291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_4_RD_DELAY5 = 17292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P0_4_RD_DELAY5_LEN = 17293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_4_RD = 17294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_4_RD_LEN = 17295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_4_RD_DELAY5 = 17296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR2_P1_4_RD_DELAY5_LEN = 17297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6 = 17298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 17299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7 = 17300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 17301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6 = 17302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 17303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7 = 17304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 17305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_0_01_RD_DELAY6 = 17306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_0_01_RD_DELAY6_LEN = 17307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_0_01_RD_DELAY7 = 17308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_0_01_RD_DELAY7_LEN = 17309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_1_01_RD_DELAY6 = 17310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_1_01_RD_DELAY6_LEN = 17311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_1_01_RD_DELAY7 = 17312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_1_01_RD_DELAY7_LEN = 17313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6 = 17314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 17315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7 = 17316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 17317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6 = 17318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 17319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7 = 17320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 17321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_2_23_RD_DELAY6 = 17322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_2_23_RD_DELAY6_LEN = 17323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_2_23_RD_DELAY7 = 17324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_2_23_RD_DELAY7_LEN = 17325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_3_23_RD_DELAY6 = 17326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_3_23_RD_DELAY6_LEN = 17327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_3_23_RD_DELAY7 = 17328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_3_23_RD_DELAY7_LEN = 17329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_4_RD_DELAY6 = 17330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_4_RD_DELAY6_LEN = 17331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_4_RD_DELAY7 = 17332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P0_4_RD_DELAY7_LEN = 17333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_4_RD_DELAY6 = 17334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_4_RD_DELAY6_LEN = 17335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_4_RD_DELAY7 = 17336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY4_RANK_PAIR3_P1_4_RD_DELAY7_LEN = 17337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0 = 17338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 17339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1 = 17340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 17341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0 = 17342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 17343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1 = 17344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 17345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_0_01_RD_DELAY0 = 17346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_0_01_RD_DELAY0_LEN = 17347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_0_01_RD_DELAY1 = 17348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_0_01_RD_DELAY1_LEN = 17349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_1_01_RD_DELAY0 = 17350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_1_01_RD_DELAY0_LEN = 17351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_1_01_RD_DELAY1 = 17352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_1_01_RD_DELAY1_LEN = 17353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0 = 17354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 17355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1 = 17356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 17357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0 = 17358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 17359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1 = 17360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 17361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_2_23_RD_DELAY0 = 17362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_2_23_RD_DELAY0_LEN = 17363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_2_23_RD_DELAY1 = 17364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_2_23_RD_DELAY1_LEN = 17365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_3_23_RD_DELAY0 = 17366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_3_23_RD_DELAY0_LEN = 17367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_3_23_RD_DELAY1 = 17368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_3_23_RD_DELAY1_LEN = 17369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_4_RD_DELAY0 = 17370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_4_RD_DELAY0_LEN = 17371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_4_RD_DELAY1 = 17372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P0_4_RD_DELAY1_LEN = 17373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_4_RD_DELAY0 = 17374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_4_RD_DELAY0_LEN = 17375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_4_RD_DELAY1 = 17376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR0_P1_4_RD_DELAY1_LEN = 17377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2 = 17378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 17379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3 = 17380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 17381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2 = 17382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 17383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3 = 17384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 17385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_0_01_RD_DELAY2 = 17386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_0_01_RD_DELAY2_LEN = 17387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_0_01_RD_DELAY3 = 17388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_0_01_RD_DELAY3_LEN = 17389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_1_01_RD_DELAY2 = 17390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_1_01_RD_DELAY2_LEN = 17391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_1_01_RD_DELAY3 = 17392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_1_01_RD_DELAY3_LEN = 17393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2 = 17394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 17395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3 = 17396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 17397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2 = 17398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 17399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3 = 17400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 17401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_2_23_RD_DELAY2 = 17402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_2_23_RD_DELAY2_LEN = 17403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_2_23_RD_DELAY3 = 17404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_2_23_RD_DELAY3_LEN = 17405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_3_23_RD_DELAY2 = 17406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_3_23_RD_DELAY2_LEN = 17407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_3_23_RD_DELAY3 = 17408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_3_23_RD_DELAY3_LEN = 17409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_4_RD_DELAY2 = 17410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_4_RD_DELAY2_LEN = 17411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_4_RD_DELAY3 = 17412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P0_4_RD_DELAY3_LEN = 17413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_4_RD_DELAY2 = 17414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_4_RD_DELAY2_LEN = 17415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_4_RD_DELAY3 = 17416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR1_P1_4_RD_DELAY3_LEN = 17417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4 = 17418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 17419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_0_01_RD = 17420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_LEN = 17421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4 = 17422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 17423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_1_01_RD = 17424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_LEN = 17425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_0_01_RD_DELAY4 = 17426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_0_01_RD_DELAY4_LEN = 17427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_0_01_RD = 17428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_0_01_RD_LEN = 17429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_1_01_RD_DELAY4 = 17430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_1_01_RD_DELAY4_LEN = 17431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_1_01_RD = 17432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_1_01_RD_LEN = 17433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4 = 17434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 17435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_2_23_RD = 17436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_LEN = 17437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4 = 17438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 17439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_3_23_RD = 17440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_LEN = 17441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_2_23_RD_DELAY4 = 17442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_2_23_RD_DELAY4_LEN = 17443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_2_23_RD = 17444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_2_23_RD_LEN = 17445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_3_23_RD_DELAY4 = 17446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_3_23_RD_DELAY4_LEN = 17447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_3_23_RD = 17448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_3_23_RD_LEN = 17449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_4_RD_DELAY4 = 17450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_4_RD_DELAY4_LEN = 17451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_4_RD = 17452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P0_4_RD_LEN = 17453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_4_RD_DELAY4 = 17454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_4_RD_DELAY4_LEN = 17455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_4_RD = 17456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR2_P1_4_RD_LEN = 17457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6 = 17458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 17459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7 = 17460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 17461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6 = 17462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 17463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7 = 17464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 17465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_0_01_RD_DELAY6 = 17466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_0_01_RD_DELAY6_LEN = 17467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_0_01_RD_DELAY7 = 17468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_0_01_RD_DELAY7_LEN = 17469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_1_01_RD_DELAY6 = 17470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_1_01_RD_DELAY6_LEN = 17471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_1_01_RD_DELAY7 = 17472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_1_01_RD_DELAY7_LEN = 17473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6 = 17474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 17475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7 = 17476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 17477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6 = 17478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 17479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7 = 17480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 17481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_2_23_RD_DELAY6 = 17482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_2_23_RD_DELAY6_LEN = 17483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_2_23_RD_DELAY7 = 17484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_2_23_RD_DELAY7_LEN = 17485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_3_23_RD_DELAY6 = 17486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_3_23_RD_DELAY6_LEN = 17487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_3_23_RD_DELAY7 = 17488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_3_23_RD_DELAY7_LEN = 17489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_4_RD_DELAY6 = 17490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_4_RD_DELAY6_LEN = 17491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_4_RD_DELAY7 = 17492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P0_4_RD_DELAY7_LEN = 17493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_4_RD_DELAY6 = 17494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_4_RD_DELAY6_LEN = 17495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_4_RD_DELAY7 = 17496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY5_RANK_PAIR3_P1_4_RD_DELAY7_LEN = 17497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0 = 17498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 17499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1 = 17500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 17501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0 = 17502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 17503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1 = 17504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 17505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_0_01_RD_DELAY0 = 17506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_0_01_RD_DELAY0_LEN = 17507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_0_01_RD_DELAY1 = 17508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_0_01_RD_DELAY1_LEN = 17509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_1_01_RD_DELAY0 = 17510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_1_01_RD_DELAY0_LEN = 17511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_1_01_RD_DELAY1 = 17512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_1_01_RD_DELAY1_LEN = 17513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0 = 17514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 17515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1 = 17516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 17517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0 = 17518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 17519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1 = 17520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 17521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_2_23_RD_DELAY0 = 17522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_2_23_RD_DELAY0_LEN = 17523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_2_23_RD_DELAY1 = 17524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_2_23_RD_DELAY1_LEN = 17525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_3_23_RD_DELAY0 = 17526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_3_23_RD_DELAY0_LEN = 17527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_3_23_RD_DELAY1 = 17528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_3_23_RD_DELAY1_LEN = 17529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_4_RD_DELAY0 = 17530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_4_RD_DELAY0_LEN = 17531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_4_RD_DELAY1 = 17532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P0_4_RD_DELAY1_LEN = 17533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_4_RD_DELAY0 = 17534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_4_RD_DELAY0_LEN = 17535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_4_RD_DELAY1 = 17536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR0_P1_4_RD_DELAY1_LEN = 17537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2 = 17538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 17539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3 = 17540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 17541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2 = 17542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 17543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3 = 17544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 17545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_0_01_RD_DELAY2 = 17546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_0_01_RD_DELAY2_LEN = 17547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_0_01_RD_DELAY3 = 17548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_0_01_RD_DELAY3_LEN = 17549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_1_01_RD_DELAY2 = 17550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_1_01_RD_DELAY2_LEN = 17551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_1_01_RD_DELAY3 = 17552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_1_01_RD_DELAY3_LEN = 17553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2 = 17554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 17555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3 = 17556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 17557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2 = 17558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 17559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3 = 17560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 17561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_2_23_RD_DELAY2 = 17562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_2_23_RD_DELAY2_LEN = 17563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_2_23_RD_DELAY3 = 17564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_2_23_RD_DELAY3_LEN = 17565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_3_23_RD_DELAY2 = 17566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_3_23_RD_DELAY2_LEN = 17567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_3_23_RD_DELAY3 = 17568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_3_23_RD_DELAY3_LEN = 17569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_4_RD_DELAY2 = 17570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_4_RD_DELAY2_LEN = 17571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_4_RD_DELAY3 = 17572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P0_4_RD_DELAY3_LEN = 17573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_4_RD_DELAY2 = 17574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_4_RD_DELAY2_LEN = 17575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_4_RD_DELAY3 = 17576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR1_P1_4_RD_DELAY3_LEN = 17577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4 = 17578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 17579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5 = 17580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 17581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4 = 17582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 17583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5 = 17584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 17585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_0_01_RD_DELAY4 = 17586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_0_01_RD_DELAY4_LEN = 17587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_0_01_RD_DELAY5 = 17588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_0_01_RD_DELAY5_LEN = 17589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_1_01_RD_DELAY4 = 17590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_1_01_RD_DELAY4_LEN = 17591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_1_01_RD_DELAY5 = 17592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_1_01_RD_DELAY5_LEN = 17593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4 = 17594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 17595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5 = 17596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 17597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4 = 17598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 17599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5 = 17600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 17601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_2_23_RD_DELAY4 = 17602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_2_23_RD_DELAY4_LEN = 17603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_2_23_RD_DELAY5 = 17604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_2_23_RD_DELAY5_LEN = 17605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_3_23_RD_DELAY4 = 17606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_3_23_RD_DELAY4_LEN = 17607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_3_23_RD_DELAY5 = 17608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_3_23_RD_DELAY5_LEN = 17609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_4_RD_DELAY4 = 17610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_4_RD_DELAY4_LEN = 17611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_4_RD_DELAY5 = 17612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P0_4_RD_DELAY5_LEN = 17613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_4_RD_DELAY4 = 17614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_4_RD_DELAY4_LEN = 17615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_4_RD_DELAY5 = 17616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR2_P1_4_RD_DELAY5_LEN = 17617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_0_01_RD = 17618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_LEN = 17619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7 = 17620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 17621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_1_01_RD = 17622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_LEN = 17623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7 = 17624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 17625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_0_01_RD = 17626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_0_01_RD_LEN = 17627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_0_01_RD_DELAY7 = 17628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_0_01_RD_DELAY7_LEN = 17629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_1_01_RD = 17630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_1_01_RD_LEN = 17631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_1_01_RD_DELAY7 = 17632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_1_01_RD_DELAY7_LEN = 17633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_2_23_RD = 17634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_LEN = 17635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7 = 17636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 17637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_3_23_RD = 17638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_LEN = 17639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7 = 17640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 17641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_2_23_RD = 17642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_2_23_RD_LEN = 17643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_2_23_RD_DELAY7 = 17644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_2_23_RD_DELAY7_LEN = 17645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_3_23_RD = 17646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_3_23_RD_LEN = 17647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_3_23_RD_DELAY7 = 17648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_3_23_RD_DELAY7_LEN = 17649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_4_RD = 17650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_4_RD_LEN = 17651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_4_RD_DELAY7 = 17652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P0_4_RD_DELAY7_LEN = 17653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_4_RD = 17654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_4_RD_LEN = 17655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_4_RD_DELAY7 = 17656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY6_RANK_PAIR3_P1_4_RD_DELAY7_LEN = 17657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0 = 17658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 17659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1 = 17660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 17661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0 = 17662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 17663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1 = 17664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 17665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_0_01_RD_DELAY0 = 17666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_0_01_RD_DELAY0_LEN = 17667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_0_01_RD_DELAY1 = 17668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_0_01_RD_DELAY1_LEN = 17669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_1_01_RD_DELAY0 = 17670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_1_01_RD_DELAY0_LEN = 17671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_1_01_RD_DELAY1 = 17672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_1_01_RD_DELAY1_LEN = 17673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0 = 17674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 17675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1 = 17676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 17677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0 = 17678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 17679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1 = 17680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 17681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_2_23_RD_DELAY0 = 17682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_2_23_RD_DELAY0_LEN = 17683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_2_23_RD_DELAY1 = 17684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_2_23_RD_DELAY1_LEN = 17685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_3_23_RD_DELAY0 = 17686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_3_23_RD_DELAY0_LEN = 17687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_3_23_RD_DELAY1 = 17688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_3_23_RD_DELAY1_LEN = 17689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_4_RD_DELAY0 = 17690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_4_RD_DELAY0_LEN = 17691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_4_RD_DELAY1 = 17692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P0_4_RD_DELAY1_LEN = 17693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_4_RD_DELAY0 = 17694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_4_RD_DELAY0_LEN = 17695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_4_RD_DELAY1 = 17696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR0_P1_4_RD_DELAY1_LEN = 17697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2 = 17698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 17699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3 = 17700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 17701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2 = 17702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 17703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3 = 17704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 17705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_0_01_RD_DELAY2 = 17706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_0_01_RD_DELAY2_LEN = 17707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_0_01_RD_DELAY3 = 17708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_0_01_RD_DELAY3_LEN = 17709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_1_01_RD_DELAY2 = 17710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_1_01_RD_DELAY2_LEN = 17711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_1_01_RD_DELAY3 = 17712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_1_01_RD_DELAY3_LEN = 17713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2 = 17714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 17715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3 = 17716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 17717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2 = 17718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 17719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3 = 17720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 17721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_2_23_RD_DELAY2 = 17722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_2_23_RD_DELAY2_LEN = 17723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_2_23_RD_DELAY3 = 17724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_2_23_RD_DELAY3_LEN = 17725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_3_23_RD_DELAY2 = 17726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_3_23_RD_DELAY2_LEN = 17727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_3_23_RD_DELAY3 = 17728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_3_23_RD_DELAY3_LEN = 17729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_4_RD_DELAY2 = 17730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_4_RD_DELAY2_LEN = 17731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_4_RD_DELAY3 = 17732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P0_4_RD_DELAY3_LEN = 17733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_4_RD_DELAY2 = 17734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_4_RD_DELAY2_LEN = 17735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_4_RD_DELAY3 = 17736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR1_P1_4_RD_DELAY3_LEN = 17737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4 = 17738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 17739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5 = 17740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 17741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4 = 17742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 17743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5 = 17744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 17745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_0_01_RD_DELAY4 = 17746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_0_01_RD_DELAY4_LEN = 17747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_0_01_RD_DELAY5 = 17748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_0_01_RD_DELAY5_LEN = 17749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_1_01_RD_DELAY4 = 17750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_1_01_RD_DELAY4_LEN = 17751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_1_01_RD_DELAY5 = 17752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_1_01_RD_DELAY5_LEN = 17753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4 = 17754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 17755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5 = 17756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 17757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4 = 17758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 17759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5 = 17760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 17761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_2_23_RD_DELAY4 = 17762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_2_23_RD_DELAY4_LEN = 17763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_2_23_RD_DELAY5 = 17764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_2_23_RD_DELAY5_LEN = 17765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_3_23_RD_DELAY4 = 17766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_3_23_RD_DELAY4_LEN = 17767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_3_23_RD_DELAY5 = 17768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_3_23_RD_DELAY5_LEN = 17769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_4_RD_DELAY4 = 17770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_4_RD_DELAY4_LEN = 17771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_4_RD_DELAY5 = 17772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P0_4_RD_DELAY5_LEN = 17773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_4_RD_DELAY4 = 17774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_4_RD_DELAY4_LEN = 17775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_4_RD_DELAY5 = 17776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR2_P1_4_RD_DELAY5_LEN = 17777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6 = 17778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 17779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_0_01_RD = 17780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_LEN = 17781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6 = 17782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 17783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_1_01_RD = 17784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_LEN = 17785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_0_01_RD_DELAY6 = 17786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_0_01_RD_DELAY6_LEN = 17787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_0_01_RD = 17788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_0_01_RD_LEN = 17789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_1_01_RD_DELAY6 = 17790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_1_01_RD_DELAY6_LEN = 17791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_1_01_RD = 17792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_1_01_RD_LEN = 17793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6 = 17794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 17795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_2_23_RD = 17796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_LEN = 17797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6 = 17798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 17799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_3_23_RD = 17800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_LEN = 17801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_2_23_RD_DELAY6 = 17802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_2_23_RD_DELAY6_LEN = 17803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_2_23_RD = 17804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_2_23_RD_LEN = 17805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_3_23_RD_DELAY6 = 17806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_3_23_RD_DELAY6_LEN = 17807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_3_23_RD = 17808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_3_23_RD_LEN = 17809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_4_RD_DELAY6 = 17810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_4_RD_DELAY6_LEN = 17811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_4_RD = 17812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P0_4_RD_LEN = 17813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_4_RD_DELAY6 = 17814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_4_RD_DELAY6_LEN = 17815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_4_RD = 17816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY7_RANK_PAIR3_P1_4_RD_LEN = 17817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01 = 17818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN = 17819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1 = 17820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN = 17821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01 = 17822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_LEN = 17823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1 = 17824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1_LEN = 17825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0_01 = 17826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0_01_LEN = 17827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0_01_OFFSET1 = 17828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0_01_OFFSET1_LEN = 17829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1_01 = 17830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1_01_LEN = 17831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1_01_OFFSET1 = 17832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1_01_OFFSET1_LEN = 17833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23 = 17834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_LEN = 17835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1 = 17836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1_LEN = 17837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23 = 17838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_LEN = 17839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1 = 17840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1_LEN = 17841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2_23 = 17842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2_23_LEN = 17843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2_23_OFFSET1 = 17844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2_23_OFFSET1_LEN = 17845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3_23 = 17846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3_23_LEN = 17847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3_23_OFFSET1 = 17848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3_23_OFFSET1_LEN = 17849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_OFFSET0 = 17850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_OFFSET0_LEN = 17851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_OFFSET1 = 17852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_OFFSET1_LEN = 17853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4_OFFSET0 = 17854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4_OFFSET0_LEN = 17855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4_OFFSET1 = 17856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4_OFFSET1_LEN = 17857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2 = 17858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2_LEN = 17859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3 = 17860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3_LEN = 17861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2 = 17862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2_LEN = 17863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3 = 17864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3_LEN = 17865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0_01_OFFSET2 = 17866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0_01_OFFSET2_LEN = 17867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0_01_OFFSET3 = 17868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0_01_OFFSET3_LEN = 17869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1_01_OFFSET2 = 17870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1_01_OFFSET2_LEN = 17871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1_01_OFFSET3 = 17872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1_01_OFFSET3_LEN = 17873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2 = 17874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2_LEN = 17875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3 = 17876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3_LEN = 17877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2 = 17878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2_LEN = 17879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3 = 17880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3_LEN = 17881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2_23_OFFSET2 = 17882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2_23_OFFSET2_LEN = 17883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2_23_OFFSET3 = 17884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2_23_OFFSET3_LEN = 17885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3_23_OFFSET2 = 17886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3_23_OFFSET2_LEN = 17887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3_23_OFFSET3 = 17888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3_23_OFFSET3_LEN = 17889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_OFFSET2 = 17890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_OFFSET2_LEN = 17891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_OFFSET3 = 17892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_OFFSET3_LEN = 17893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4_OFFSET2 = 17894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4_OFFSET2_LEN = 17895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4_OFFSET3 = 17896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4_OFFSET3_LEN = 17897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4 = 17898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4_LEN = 17899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5 = 17900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5_LEN = 17901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4 = 17902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4_LEN = 17903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5 = 17904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5_LEN = 17905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0_01_OFFSET4 = 17906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0_01_OFFSET4_LEN = 17907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0_01_OFFSET5 = 17908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0_01_OFFSET5_LEN = 17909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1_01_OFFSET4 = 17910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1_01_OFFSET4_LEN = 17911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1_01_OFFSET5 = 17912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1_01_OFFSET5_LEN = 17913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4 = 17914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4_LEN = 17915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5 = 17916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5_LEN = 17917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4 = 17918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4_LEN = 17919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5 = 17920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5_LEN = 17921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2_23_OFFSET4 = 17922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2_23_OFFSET4_LEN = 17923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2_23_OFFSET5 = 17924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2_23_OFFSET5_LEN = 17925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3_23_OFFSET4 = 17926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3_23_OFFSET4_LEN = 17927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3_23_OFFSET5 = 17928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3_23_OFFSET5_LEN = 17929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_OFFSET4 = 17930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_OFFSET4_LEN = 17931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_OFFSET5 = 17932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_OFFSET5_LEN = 17933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4_OFFSET4 = 17934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4_OFFSET4_LEN = 17935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4_OFFSET5 = 17936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4_OFFSET5_LEN = 17937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6 = 17938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6_LEN = 17939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7 = 17940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7_LEN = 17941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6 = 17942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6_LEN = 17943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7 = 17944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7_LEN = 17945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0_01_OFFSET6 = 17946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0_01_OFFSET6_LEN = 17947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0_01_OFFSET7 = 17948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0_01_OFFSET7_LEN = 17949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1_01_OFFSET6 = 17950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1_01_OFFSET6_LEN = 17951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1_01_OFFSET7 = 17952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1_01_OFFSET7_LEN = 17953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6 = 17954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6_LEN = 17955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7 = 17956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7_LEN = 17957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6 = 17958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6_LEN = 17959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7 = 17960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7_LEN = 17961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2_23_OFFSET6 = 17962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2_23_OFFSET6_LEN = 17963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2_23_OFFSET7 = 17964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2_23_OFFSET7_LEN = 17965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3_23_OFFSET6 = 17966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3_23_OFFSET6_LEN = 17967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3_23_OFFSET7 = 17968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3_23_OFFSET7_LEN = 17969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_OFFSET6 = 17970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_OFFSET6_LEN = 17971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_OFFSET7 = 17972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_OFFSET7_LEN = 17973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4_OFFSET6 = 17974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4_OFFSET6_LEN = 17975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4_OFFSET7 = 17976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4_OFFSET7_LEN = 17977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0 = 17978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0_LEN = 17979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01 = 17980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_LEN = 17981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0 = 17982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0_LEN = 17983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01 = 17984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_LEN = 17985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0_01_OFFSET0 = 17986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0_01_OFFSET0_LEN = 17987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0_01 = 17988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0_01_LEN = 17989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1_01_OFFSET0 = 17990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1_01_OFFSET0_LEN = 17991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1_01 = 17992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1_01_LEN = 17993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0 = 17994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0_LEN = 17995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23 = 17996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_LEN = 17997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0 = 17998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0_LEN = 17999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23 = 18000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_LEN = 18001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2_23_OFFSET0 = 18002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2_23_OFFSET0_LEN = 18003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2_23 = 18004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2_23_LEN = 18005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3_23_OFFSET0 = 18006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3_23_OFFSET0_LEN = 18007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3_23 = 18008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3_23_LEN = 18009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_OFFSET0 = 18010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_OFFSET0_LEN = 18011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_OFFSET1 = 18012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_OFFSET1_LEN = 18013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4_OFFSET0 = 18014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4_OFFSET0_LEN = 18015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4_OFFSET1 = 18016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4_OFFSET1_LEN = 18017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2 = 18018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2_LEN = 18019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3 = 18020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3_LEN = 18021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2 = 18022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2_LEN = 18023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3 = 18024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3_LEN = 18025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0_01_OFFSET2 = 18026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0_01_OFFSET2_LEN = 18027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0_01_OFFSET3 = 18028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0_01_OFFSET3_LEN = 18029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1_01_OFFSET2 = 18030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1_01_OFFSET2_LEN = 18031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1_01_OFFSET3 = 18032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1_01_OFFSET3_LEN = 18033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2 = 18034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2_LEN = 18035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3 = 18036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3_LEN = 18037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2 = 18038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2_LEN = 18039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3 = 18040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3_LEN = 18041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2_23_OFFSET2 = 18042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2_23_OFFSET2_LEN = 18043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2_23_OFFSET3 = 18044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2_23_OFFSET3_LEN = 18045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3_23_OFFSET2 = 18046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3_23_OFFSET2_LEN = 18047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3_23_OFFSET3 = 18048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3_23_OFFSET3_LEN = 18049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_OFFSET2 = 18050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_OFFSET2_LEN = 18051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_OFFSET3 = 18052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_OFFSET3_LEN = 18053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4_OFFSET2 = 18054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4_OFFSET2_LEN = 18055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4_OFFSET3 = 18056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4_OFFSET3_LEN = 18057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4 = 18058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4_LEN = 18059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5 = 18060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5_LEN = 18061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4 = 18062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4_LEN = 18063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5 = 18064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5_LEN = 18065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0_01_OFFSET4 = 18066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0_01_OFFSET4_LEN = 18067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0_01_OFFSET5 = 18068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0_01_OFFSET5_LEN = 18069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1_01_OFFSET4 = 18070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1_01_OFFSET4_LEN = 18071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1_01_OFFSET5 = 18072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1_01_OFFSET5_LEN = 18073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4 = 18074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4_LEN = 18075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5 = 18076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5_LEN = 18077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4 = 18078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4_LEN = 18079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5 = 18080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5_LEN = 18081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2_23_OFFSET4 = 18082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2_23_OFFSET4_LEN = 18083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2_23_OFFSET5 = 18084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2_23_OFFSET5_LEN = 18085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3_23_OFFSET4 = 18086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3_23_OFFSET4_LEN = 18087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3_23_OFFSET5 = 18088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3_23_OFFSET5_LEN = 18089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_OFFSET4 = 18090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_OFFSET4_LEN = 18091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_OFFSET5 = 18092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_OFFSET5_LEN = 18093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4_OFFSET4 = 18094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4_OFFSET4_LEN = 18095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4_OFFSET5 = 18096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4_OFFSET5_LEN = 18097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6 = 18098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6_LEN = 18099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7 = 18100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7_LEN = 18101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6 = 18102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6_LEN = 18103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7 = 18104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7_LEN = 18105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0_01_OFFSET6 = 18106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0_01_OFFSET6_LEN = 18107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0_01_OFFSET7 = 18108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0_01_OFFSET7_LEN = 18109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1_01_OFFSET6 = 18110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1_01_OFFSET6_LEN = 18111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1_01_OFFSET7 = 18112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1_01_OFFSET7_LEN = 18113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6 = 18114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6_LEN = 18115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7 = 18116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7_LEN = 18117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6 = 18118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6_LEN = 18119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7 = 18120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7_LEN = 18121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2_23_OFFSET6 = 18122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2_23_OFFSET6_LEN = 18123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2_23_OFFSET7 = 18124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2_23_OFFSET7_LEN = 18125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3_23_OFFSET6 = 18126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3_23_OFFSET6_LEN = 18127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3_23_OFFSET7 = 18128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3_23_OFFSET7_LEN = 18129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_OFFSET6 = 18130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_OFFSET6_LEN = 18131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_OFFSET7 = 18132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_OFFSET7_LEN = 18133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4_OFFSET6 = 18134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4_OFFSET6_LEN = 18135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4_OFFSET7 = 18136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4_OFFSET7_LEN = 18137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_0_01 = 18138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_0_01_LEN = 18139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_1_01 = 18140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_1_01_LEN = 18141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_0_01 = 18142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_0_01_LEN = 18143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_1_01 = 18144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_1_01_LEN = 18145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_2_23 = 18146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_2_23_LEN = 18147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_3_23 = 18148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_3_23_LEN = 18149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_2_23 = 18150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_2_23_LEN = 18151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_3_23 = 18152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_3_23_LEN = 18153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_4_REFERENCE = 18154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P0_4_REFERENCE_LEN = 18155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_4_REFERENCE = 18156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE_P1_4_REFERENCE_LEN = 18157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD = 18158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_LEN = 18159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1 = 18160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 18161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD = 18162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_LEN = 18163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1 = 18164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 18165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_0_01_RD = 18166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_0_01_RD_LEN = 18167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_0_01_RD_SIZE1 = 18168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 18169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_1_01_RD = 18170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_1_01_RD_LEN = 18171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_1_01_RD_SIZE1 = 18172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 18173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD = 18174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_LEN = 18175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1 = 18176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 18177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD = 18178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_LEN = 18179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1 = 18180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 18181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_2_23_RD = 18182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_2_23_RD_LEN = 18183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_2_23_RD_SIZE1 = 18184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 18185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_3_23_RD = 18186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_3_23_RD_LEN = 18187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_3_23_RD_SIZE1 = 18188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 18189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_4_RD = 18190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_4_RD_LEN = 18191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_4_RD_SIZE1 = 18192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 18193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_4_RD = 18194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_4_RD_LEN = 18195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_4_RD_SIZE1 = 18196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 18197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2 = 18198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 18199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3 = 18200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 18201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2 = 18202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 18203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3 = 18204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 18205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_0_01_RD_SIZE2 = 18206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 18207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_0_01_RD_SIZE3 = 18208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 18209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_1_01_RD_SIZE2 = 18210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 18211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_1_01_RD_SIZE3 = 18212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 18213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2 = 18214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 18215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3 = 18216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 18217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2 = 18218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 18219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3 = 18220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 18221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_2_23_RD_SIZE2 = 18222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 18223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_2_23_RD_SIZE3 = 18224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 18225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_3_23_RD_SIZE2 = 18226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 18227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_3_23_RD_SIZE3 = 18228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 18229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_4_RD_SIZE2 = 18230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 18231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_4_RD_SIZE3 = 18232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 18233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_4_RD_SIZE2 = 18234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 18235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_4_RD_SIZE3 = 18236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 18237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4 = 18238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 18239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5 = 18240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 18241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4 = 18242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 18243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5 = 18244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 18245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_0_01_RD_SIZE4 = 18246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 18247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_0_01_RD_SIZE5 = 18248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 18249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_1_01_RD_SIZE4 = 18250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 18251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_1_01_RD_SIZE5 = 18252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 18253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4 = 18254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 18255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5 = 18256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 18257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4 = 18258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 18259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5 = 18260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 18261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_2_23_RD_SIZE4 = 18262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 18263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_2_23_RD_SIZE5 = 18264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 18265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_3_23_RD_SIZE4 = 18266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 18267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_3_23_RD_SIZE5 = 18268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 18269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_4_RD_SIZE4 = 18270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 18271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_4_RD_SIZE5 = 18272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 18273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_4_RD_SIZE4 = 18274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 18275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_4_RD_SIZE5 = 18276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 18277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6 = 18278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 18279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7 = 18280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 18281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6 = 18282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 18283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7 = 18284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 18285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_0_01_RD_SIZE6 = 18286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 18287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_0_01_RD_SIZE7 = 18288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 18289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_1_01_RD_SIZE6 = 18290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 18291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_1_01_RD_SIZE7 = 18292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 18293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6 = 18294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 18295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7 = 18296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 18297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6 = 18298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 18299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7 = 18300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 18301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_2_23_RD_SIZE6 = 18302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 18303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_2_23_RD_SIZE7 = 18304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 18305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_3_23_RD_SIZE6 = 18306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 18307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_3_23_RD_SIZE7 = 18308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 18309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_4_RD_SIZE6 = 18310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 18311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_4_RD_SIZE7 = 18312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 18313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_4_RD_SIZE6 = 18314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 18315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_4_RD_SIZE7 = 18316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 18317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0 = 18318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 18319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1 = 18320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 18321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0 = 18322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 18323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1 = 18324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 18325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_0_01_RD_SIZE0 = 18326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 18327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_0_01_RD_SIZE1 = 18328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 18329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_1_01_RD_SIZE0 = 18330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 18331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_1_01_RD_SIZE1 = 18332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 18333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0 = 18334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 18335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1 = 18336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 18337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0 = 18338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 18339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1 = 18340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 18341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_2_23_RD_SIZE0 = 18342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 18343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_2_23_RD_SIZE1 = 18344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 18345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_3_23_RD_SIZE0 = 18346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 18347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_3_23_RD_SIZE1 = 18348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 18349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_4_RD_SIZE0 = 18350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 18351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_4_RD_SIZE1 = 18352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 18353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_4_RD_SIZE0 = 18354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 18355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_4_RD_SIZE1 = 18356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 18357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2 = 18358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 18359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3 = 18360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 18361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2 = 18362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 18363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3 = 18364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 18365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_0_01_RD_SIZE2 = 18366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 18367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_0_01_RD_SIZE3 = 18368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 18369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_1_01_RD_SIZE2 = 18370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 18371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_1_01_RD_SIZE3 = 18372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 18373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2 = 18374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 18375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3 = 18376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 18377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2 = 18378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 18379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3 = 18380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 18381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_2_23_RD_SIZE2 = 18382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 18383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_2_23_RD_SIZE3 = 18384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 18385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_3_23_RD_SIZE2 = 18386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 18387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_3_23_RD_SIZE3 = 18388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 18389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_4_RD_SIZE2 = 18390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 18391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_4_RD_SIZE3 = 18392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 18393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_4_RD_SIZE2 = 18394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 18395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_4_RD_SIZE3 = 18396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 18397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4 = 18398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 18399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5 = 18400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 18401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4 = 18402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 18403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5 = 18404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 18405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_0_01_RD_SIZE4 = 18406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 18407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_0_01_RD_SIZE5 = 18408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 18409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_1_01_RD_SIZE4 = 18410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 18411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_1_01_RD_SIZE5 = 18412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 18413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4 = 18414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 18415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5 = 18416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 18417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4 = 18418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 18419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5 = 18420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 18421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_2_23_RD_SIZE4 = 18422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 18423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_2_23_RD_SIZE5 = 18424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 18425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_3_23_RD_SIZE4 = 18426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 18427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_3_23_RD_SIZE5 = 18428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 18429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_4_RD_SIZE4 = 18430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 18431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_4_RD_SIZE5 = 18432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 18433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_4_RD_SIZE4 = 18434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 18435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_4_RD_SIZE5 = 18436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 18437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6 = 18438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 18439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7 = 18440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 18441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6 = 18442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 18443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7 = 18444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 18445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_0_01_RD_SIZE6 = 18446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 18447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_0_01_RD_SIZE7 = 18448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 18449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_1_01_RD_SIZE6 = 18450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 18451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_1_01_RD_SIZE7 = 18452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 18453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6 = 18454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 18455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7 = 18456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 18457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6 = 18458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 18459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7 = 18460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 18461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_2_23_RD_SIZE6 = 18462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 18463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_2_23_RD_SIZE7 = 18464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 18465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_3_23_RD_SIZE6 = 18466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 18467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_3_23_RD_SIZE7 = 18468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 18469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_4_RD_SIZE6 = 18470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 18471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_4_RD_SIZE7 = 18472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 18473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_4_RD_SIZE6 = 18474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 18475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_4_RD_SIZE7 = 18476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 18477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0 = 18478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 18479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1 = 18480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 18481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0 = 18482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 18483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1 = 18484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 18485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_0_01_RD_SIZE0 = 18486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 18487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_0_01_RD_SIZE1 = 18488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 18489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_1_01_RD_SIZE0 = 18490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 18491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_1_01_RD_SIZE1 = 18492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 18493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0 = 18494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 18495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1 = 18496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 18497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0 = 18498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 18499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1 = 18500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 18501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_2_23_RD_SIZE0 = 18502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 18503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_2_23_RD_SIZE1 = 18504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 18505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_3_23_RD_SIZE0 = 18506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 18507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_3_23_RD_SIZE1 = 18508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 18509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_4_RD_SIZE0 = 18510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 18511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_4_RD_SIZE1 = 18512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 18513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_4_RD_SIZE0 = 18514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 18515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_4_RD_SIZE1 = 18516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 18517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2 = 18518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 18519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3 = 18520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 18521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2 = 18522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 18523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3 = 18524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 18525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_0_01_RD_SIZE2 = 18526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 18527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_0_01_RD_SIZE3 = 18528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 18529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_1_01_RD_SIZE2 = 18530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 18531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_1_01_RD_SIZE3 = 18532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 18533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2 = 18534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 18535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3 = 18536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 18537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2 = 18538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 18539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3 = 18540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 18541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_2_23_RD_SIZE2 = 18542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 18543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_2_23_RD_SIZE3 = 18544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 18545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_3_23_RD_SIZE2 = 18546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 18547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_3_23_RD_SIZE3 = 18548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 18549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_4_RD_SIZE2 = 18550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 18551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_4_RD_SIZE3 = 18552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 18553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_4_RD_SIZE2 = 18554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 18555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_4_RD_SIZE3 = 18556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 18557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4 = 18558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 18559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5 = 18560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 18561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4 = 18562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 18563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5 = 18564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 18565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_0_01_RD_SIZE4 = 18566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 18567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_0_01_RD_SIZE5 = 18568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 18569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_1_01_RD_SIZE4 = 18570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 18571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_1_01_RD_SIZE5 = 18572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 18573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4 = 18574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 18575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5 = 18576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 18577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4 = 18578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 18579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5 = 18580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 18581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_2_23_RD_SIZE4 = 18582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 18583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_2_23_RD_SIZE5 = 18584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 18585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_3_23_RD_SIZE4 = 18586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 18587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_3_23_RD_SIZE5 = 18588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 18589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_4_RD_SIZE4 = 18590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 18591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_4_RD_SIZE5 = 18592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 18593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_4_RD_SIZE4 = 18594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 18595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_4_RD_SIZE5 = 18596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 18597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6 = 18598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 18599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7 = 18600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 18601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6 = 18602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 18603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7 = 18604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 18605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_0_01_RD_SIZE6 = 18606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 18607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_0_01_RD_SIZE7 = 18608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 18609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_1_01_RD_SIZE6 = 18610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 18611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_1_01_RD_SIZE7 = 18612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 18613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6 = 18614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 18615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7 = 18616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 18617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6 = 18618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 18619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7 = 18620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 18621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_2_23_RD_SIZE6 = 18622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 18623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_2_23_RD_SIZE7 = 18624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 18625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_3_23_RD_SIZE6 = 18626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 18627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_3_23_RD_SIZE7 = 18628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 18629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_4_RD_SIZE6 = 18630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 18631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_4_RD_SIZE7 = 18632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 18633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_4_RD_SIZE6 = 18634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 18635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_4_RD_SIZE7 = 18636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 18637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0 = 18638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 18639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD = 18640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_LEN = 18641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0 = 18642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 18643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD = 18644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_LEN = 18645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_0_01_RD_SIZE0 = 18646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 18647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_0_01_RD = 18648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_0_01_RD_LEN = 18649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_1_01_RD_SIZE0 = 18650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 18651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_1_01_RD = 18652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_1_01_RD_LEN = 18653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0 = 18654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 18655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD = 18656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_LEN = 18657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0 = 18658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 18659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD = 18660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_LEN = 18661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_2_23_RD_SIZE0 = 18662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 18663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_2_23_RD = 18664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_2_23_RD_LEN = 18665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_3_23_RD_SIZE0 = 18666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 18667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_3_23_RD = 18668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_3_23_RD_LEN = 18669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_4_RD_SIZE0 = 18670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 18671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_4_RD = 18672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P0_4_RD_LEN = 18673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_4_RD_SIZE0 = 18674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 18675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_4_RD = 18676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR0_P1_4_RD_LEN = 18677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2 = 18678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 18679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3 = 18680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 18681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2 = 18682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 18683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3 = 18684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 18685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_0_01_RD_SIZE2 = 18686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 18687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_0_01_RD_SIZE3 = 18688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 18689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_1_01_RD_SIZE2 = 18690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 18691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_1_01_RD_SIZE3 = 18692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 18693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2 = 18694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 18695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3 = 18696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 18697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2 = 18698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 18699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3 = 18700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 18701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_2_23_RD_SIZE2 = 18702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 18703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_2_23_RD_SIZE3 = 18704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 18705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_3_23_RD_SIZE2 = 18706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 18707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_3_23_RD_SIZE3 = 18708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 18709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_4_RD_SIZE2 = 18710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 18711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_4_RD_SIZE3 = 18712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 18713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_4_RD_SIZE2 = 18714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 18715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_4_RD_SIZE3 = 18716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 18717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4 = 18718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 18719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5 = 18720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 18721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4 = 18722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 18723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5 = 18724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 18725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_0_01_RD_SIZE4 = 18726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 18727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_0_01_RD_SIZE5 = 18728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 18729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_1_01_RD_SIZE4 = 18730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 18731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_1_01_RD_SIZE5 = 18732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 18733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4 = 18734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 18735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5 = 18736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 18737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4 = 18738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 18739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5 = 18740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 18741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_2_23_RD_SIZE4 = 18742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 18743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_2_23_RD_SIZE5 = 18744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 18745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_3_23_RD_SIZE4 = 18746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 18747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_3_23_RD_SIZE5 = 18748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 18749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_4_RD_SIZE4 = 18750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 18751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_4_RD_SIZE5 = 18752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 18753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_4_RD_SIZE4 = 18754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 18755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_4_RD_SIZE5 = 18756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 18757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6 = 18758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 18759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7 = 18760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 18761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6 = 18762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 18763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7 = 18764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 18765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_0_01_RD_SIZE6 = 18766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 18767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_0_01_RD_SIZE7 = 18768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 18769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_1_01_RD_SIZE6 = 18770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 18771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_1_01_RD_SIZE7 = 18772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 18773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6 = 18774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 18775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7 = 18776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 18777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6 = 18778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 18779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7 = 18780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 18781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_2_23_RD_SIZE6 = 18782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 18783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_2_23_RD_SIZE7 = 18784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 18785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_3_23_RD_SIZE6 = 18786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 18787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_3_23_RD_SIZE7 = 18788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 18789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_4_RD_SIZE6 = 18790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 18791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_4_RD_SIZE7 = 18792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 18793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_4_RD_SIZE6 = 18794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 18795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_4_RD_SIZE7 = 18796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 18797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0 = 18798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 18799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1 = 18800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 18801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0 = 18802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 18803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1 = 18804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 18805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_0_01_RD_SIZE0 = 18806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 18807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_0_01_RD_SIZE1 = 18808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 18809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_1_01_RD_SIZE0 = 18810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 18811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_1_01_RD_SIZE1 = 18812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 18813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0 = 18814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 18815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1 = 18816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 18817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0 = 18818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 18819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1 = 18820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 18821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_2_23_RD_SIZE0 = 18822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 18823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_2_23_RD_SIZE1 = 18824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 18825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_3_23_RD_SIZE0 = 18826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 18827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_3_23_RD_SIZE1 = 18828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 18829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_4_RD_SIZE0 = 18830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 18831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_4_RD_SIZE1 = 18832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 18833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_4_RD_SIZE0 = 18834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 18835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_4_RD_SIZE1 = 18836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 18837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD = 18838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_LEN = 18839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3 = 18840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 18841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD = 18842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_LEN = 18843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3 = 18844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 18845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_0_01_RD = 18846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_0_01_RD_LEN = 18847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_0_01_RD_SIZE3 = 18848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 18849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_1_01_RD = 18850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_1_01_RD_LEN = 18851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_1_01_RD_SIZE3 = 18852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 18853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD = 18854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_LEN = 18855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3 = 18856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 18857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD = 18858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_LEN = 18859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3 = 18860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 18861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_2_23_RD = 18862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_2_23_RD_LEN = 18863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_2_23_RD_SIZE3 = 18864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 18865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_3_23_RD = 18866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_3_23_RD_LEN = 18867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_3_23_RD_SIZE3 = 18868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 18869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_4_RD = 18870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_4_RD_LEN = 18871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_4_RD_SIZE3 = 18872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 18873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_4_RD = 18874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_4_RD_LEN = 18875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_4_RD_SIZE3 = 18876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 18877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4 = 18878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 18879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5 = 18880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 18881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4 = 18882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 18883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5 = 18884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 18885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_0_01_RD_SIZE4 = 18886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 18887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_0_01_RD_SIZE5 = 18888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 18889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_1_01_RD_SIZE4 = 18890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 18891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_1_01_RD_SIZE5 = 18892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 18893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4 = 18894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 18895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5 = 18896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 18897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4 = 18898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 18899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5 = 18900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 18901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_2_23_RD_SIZE4 = 18902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 18903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_2_23_RD_SIZE5 = 18904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 18905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_3_23_RD_SIZE4 = 18906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 18907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_3_23_RD_SIZE5 = 18908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 18909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_4_RD_SIZE4 = 18910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 18911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_4_RD_SIZE5 = 18912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 18913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_4_RD_SIZE4 = 18914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 18915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_4_RD_SIZE5 = 18916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 18917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6 = 18918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 18919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7 = 18920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 18921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6 = 18922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 18923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7 = 18924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 18925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_0_01_RD_SIZE6 = 18926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 18927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_0_01_RD_SIZE7 = 18928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 18929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_1_01_RD_SIZE6 = 18930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 18931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_1_01_RD_SIZE7 = 18932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 18933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6 = 18934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 18935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7 = 18936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 18937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6 = 18938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 18939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7 = 18940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 18941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_2_23_RD_SIZE6 = 18942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 18943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_2_23_RD_SIZE7 = 18944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 18945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_3_23_RD_SIZE6 = 18946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 18947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_3_23_RD_SIZE7 = 18948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 18949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_4_RD_SIZE6 = 18950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 18951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_4_RD_SIZE7 = 18952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 18953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_4_RD_SIZE6 = 18954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 18955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_4_RD_SIZE7 = 18956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 18957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0 = 18958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 18959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1 = 18960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 18961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0 = 18962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 18963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1 = 18964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 18965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_0_01_RD_SIZE0 = 18966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 18967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_0_01_RD_SIZE1 = 18968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 18969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_1_01_RD_SIZE0 = 18970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 18971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_1_01_RD_SIZE1 = 18972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 18973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0 = 18974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 18975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1 = 18976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 18977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0 = 18978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 18979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1 = 18980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 18981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_2_23_RD_SIZE0 = 18982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 18983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_2_23_RD_SIZE1 = 18984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 18985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_3_23_RD_SIZE0 = 18986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 18987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_3_23_RD_SIZE1 = 18988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 18989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_4_RD_SIZE0 = 18990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 18991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_4_RD_SIZE1 = 18992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 18993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_4_RD_SIZE0 = 18994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 18995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_4_RD_SIZE1 = 18996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 18997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2 = 18998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 18999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD = 19000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_LEN = 19001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2 = 19002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 19003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD = 19004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_LEN = 19005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_0_01_RD_SIZE2 = 19006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 19007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_0_01_RD = 19008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_0_01_RD_LEN = 19009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_1_01_RD_SIZE2 = 19010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 19011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_1_01_RD = 19012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_1_01_RD_LEN = 19013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2 = 19014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 19015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD = 19016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_LEN = 19017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2 = 19018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 19019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD = 19020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_LEN = 19021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_2_23_RD_SIZE2 = 19022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 19023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_2_23_RD = 19024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_2_23_RD_LEN = 19025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_3_23_RD_SIZE2 = 19026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 19027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_3_23_RD = 19028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_3_23_RD_LEN = 19029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_4_RD_SIZE2 = 19030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 19031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_4_RD = 19032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P0_4_RD_LEN = 19033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_4_RD_SIZE2 = 19034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 19035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_4_RD = 19036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR1_P1_4_RD_LEN = 19037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4 = 19038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 19039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5 = 19040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 19041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4 = 19042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 19043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5 = 19044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 19045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_0_01_RD_SIZE4 = 19046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 19047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_0_01_RD_SIZE5 = 19048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 19049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_1_01_RD_SIZE4 = 19050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 19051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_1_01_RD_SIZE5 = 19052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 19053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4 = 19054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 19055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5 = 19056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 19057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4 = 19058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 19059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5 = 19060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 19061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_2_23_RD_SIZE4 = 19062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 19063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_2_23_RD_SIZE5 = 19064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 19065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_3_23_RD_SIZE4 = 19066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 19067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_3_23_RD_SIZE5 = 19068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 19069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_4_RD_SIZE4 = 19070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 19071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_4_RD_SIZE5 = 19072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 19073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_4_RD_SIZE4 = 19074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 19075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_4_RD_SIZE5 = 19076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 19077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6 = 19078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 19079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7 = 19080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 19081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6 = 19082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 19083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7 = 19084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 19085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_0_01_RD_SIZE6 = 19086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 19087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_0_01_RD_SIZE7 = 19088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 19089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_1_01_RD_SIZE6 = 19090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 19091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_1_01_RD_SIZE7 = 19092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 19093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6 = 19094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 19095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7 = 19096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 19097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6 = 19098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 19099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7 = 19100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 19101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_2_23_RD_SIZE6 = 19102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 19103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_2_23_RD_SIZE7 = 19104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 19105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_3_23_RD_SIZE6 = 19106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 19107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_3_23_RD_SIZE7 = 19108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 19109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_4_RD_SIZE6 = 19110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 19111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_4_RD_SIZE7 = 19112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 19113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_4_RD_SIZE6 = 19114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 19115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_4_RD_SIZE7 = 19116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 19117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0 = 19118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 19119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1 = 19120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 19121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0 = 19122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 19123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1 = 19124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 19125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_0_01_RD_SIZE0 = 19126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 19127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_0_01_RD_SIZE1 = 19128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 19129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_1_01_RD_SIZE0 = 19130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 19131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_1_01_RD_SIZE1 = 19132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 19133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0 = 19134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 19135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1 = 19136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 19137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0 = 19138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 19139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1 = 19140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 19141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_2_23_RD_SIZE0 = 19142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 19143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_2_23_RD_SIZE1 = 19144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 19145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_3_23_RD_SIZE0 = 19146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 19147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_3_23_RD_SIZE1 = 19148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 19149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_4_RD_SIZE0 = 19150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 19151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_4_RD_SIZE1 = 19152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 19153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_4_RD_SIZE0 = 19154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 19155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_4_RD_SIZE1 = 19156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 19157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2 = 19158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 19159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3 = 19160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 19161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2 = 19162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 19163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3 = 19164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 19165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_0_01_RD_SIZE2 = 19166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 19167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_0_01_RD_SIZE3 = 19168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 19169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_1_01_RD_SIZE2 = 19170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 19171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_1_01_RD_SIZE3 = 19172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 19173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2 = 19174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 19175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3 = 19176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 19177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2 = 19178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 19179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3 = 19180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 19181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_2_23_RD_SIZE2 = 19182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 19183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_2_23_RD_SIZE3 = 19184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 19185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_3_23_RD_SIZE2 = 19186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 19187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_3_23_RD_SIZE3 = 19188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 19189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_4_RD_SIZE2 = 19190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 19191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_4_RD_SIZE3 = 19192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 19193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_4_RD_SIZE2 = 19194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 19195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_4_RD_SIZE3 = 19196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 19197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD = 19198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_LEN = 19199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5 = 19200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 19201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD = 19202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_LEN = 19203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5 = 19204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 19205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_0_01_RD = 19206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_0_01_RD_LEN = 19207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_0_01_RD_SIZE5 = 19208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 19209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_1_01_RD = 19210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_1_01_RD_LEN = 19211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_1_01_RD_SIZE5 = 19212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 19213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD = 19214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_LEN = 19215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5 = 19216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 19217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD = 19218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_LEN = 19219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5 = 19220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 19221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_2_23_RD = 19222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_2_23_RD_LEN = 19223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_2_23_RD_SIZE5 = 19224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 19225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_3_23_RD = 19226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_3_23_RD_LEN = 19227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_3_23_RD_SIZE5 = 19228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 19229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_4_RD = 19230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_4_RD_LEN = 19231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_4_RD_SIZE5 = 19232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 19233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_4_RD = 19234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_4_RD_LEN = 19235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_4_RD_SIZE5 = 19236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 19237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6 = 19238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 19239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7 = 19240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 19241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6 = 19242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 19243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7 = 19244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 19245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_0_01_RD_SIZE6 = 19246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 19247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_0_01_RD_SIZE7 = 19248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 19249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_1_01_RD_SIZE6 = 19250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 19251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_1_01_RD_SIZE7 = 19252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 19253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6 = 19254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 19255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7 = 19256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 19257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6 = 19258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 19259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7 = 19260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 19261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_2_23_RD_SIZE6 = 19262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 19263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_2_23_RD_SIZE7 = 19264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 19265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_3_23_RD_SIZE6 = 19266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 19267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_3_23_RD_SIZE7 = 19268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 19269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_4_RD_SIZE6 = 19270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 19271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_4_RD_SIZE7 = 19272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 19273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_4_RD_SIZE6 = 19274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 19275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_4_RD_SIZE7 = 19276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 19277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0 = 19278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 19279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1 = 19280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 19281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0 = 19282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 19283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1 = 19284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 19285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_0_01_RD_SIZE0 = 19286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 19287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_0_01_RD_SIZE1 = 19288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 19289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_1_01_RD_SIZE0 = 19290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 19291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_1_01_RD_SIZE1 = 19292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 19293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0 = 19294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 19295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1 = 19296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 19297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0 = 19298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 19299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1 = 19300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 19301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_2_23_RD_SIZE0 = 19302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 19303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_2_23_RD_SIZE1 = 19304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 19305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_3_23_RD_SIZE0 = 19306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 19307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_3_23_RD_SIZE1 = 19308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 19309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_4_RD_SIZE0 = 19310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 19311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_4_RD_SIZE1 = 19312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 19313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_4_RD_SIZE0 = 19314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 19315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_4_RD_SIZE1 = 19316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 19317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2 = 19318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 19319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3 = 19320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 19321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2 = 19322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 19323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3 = 19324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 19325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_0_01_RD_SIZE2 = 19326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 19327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_0_01_RD_SIZE3 = 19328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 19329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_1_01_RD_SIZE2 = 19330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 19331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_1_01_RD_SIZE3 = 19332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 19333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2 = 19334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 19335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3 = 19336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 19337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2 = 19338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 19339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3 = 19340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 19341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_2_23_RD_SIZE2 = 19342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 19343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_2_23_RD_SIZE3 = 19344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 19345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_3_23_RD_SIZE2 = 19346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 19347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_3_23_RD_SIZE3 = 19348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 19349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_4_RD_SIZE2 = 19350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 19351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_4_RD_SIZE3 = 19352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 19353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_4_RD_SIZE2 = 19354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 19355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_4_RD_SIZE3 = 19356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 19357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4 = 19358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 19359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD = 19360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_LEN = 19361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4 = 19362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 19363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD = 19364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_LEN = 19365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_0_01_RD_SIZE4 = 19366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 19367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_0_01_RD = 19368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_0_01_RD_LEN = 19369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_1_01_RD_SIZE4 = 19370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 19371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_1_01_RD = 19372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_1_01_RD_LEN = 19373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4 = 19374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 19375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD = 19376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_LEN = 19377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4 = 19378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 19379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD = 19380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_LEN = 19381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_2_23_RD_SIZE4 = 19382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 19383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_2_23_RD = 19384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_2_23_RD_LEN = 19385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_3_23_RD_SIZE4 = 19386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 19387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_3_23_RD = 19388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_3_23_RD_LEN = 19389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_4_RD_SIZE4 = 19390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 19391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_4_RD = 19392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P0_4_RD_LEN = 19393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_4_RD_SIZE4 = 19394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 19395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_4_RD = 19396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR2_P1_4_RD_LEN = 19397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6 = 19398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 19399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7 = 19400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 19401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6 = 19402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 19403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7 = 19404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 19405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_0_01_RD_SIZE6 = 19406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 19407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_0_01_RD_SIZE7 = 19408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 19409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_1_01_RD_SIZE6 = 19410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 19411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_1_01_RD_SIZE7 = 19412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 19413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6 = 19414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 19415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7 = 19416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 19417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6 = 19418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 19419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7 = 19420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 19421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_2_23_RD_SIZE6 = 19422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 19423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_2_23_RD_SIZE7 = 19424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 19425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_3_23_RD_SIZE6 = 19426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 19427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_3_23_RD_SIZE7 = 19428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 19429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_4_RD_SIZE6 = 19430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 19431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_4_RD_SIZE7 = 19432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 19433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_4_RD_SIZE6 = 19434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 19435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_4_RD_SIZE7 = 19436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 19437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0 = 19438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 19439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1 = 19440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 19441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0 = 19442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 19443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1 = 19444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 19445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_0_01_RD_SIZE0 = 19446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 19447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_0_01_RD_SIZE1 = 19448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 19449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_1_01_RD_SIZE0 = 19450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 19451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_1_01_RD_SIZE1 = 19452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 19453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0 = 19454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 19455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1 = 19456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 19457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0 = 19458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 19459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1 = 19460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 19461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_2_23_RD_SIZE0 = 19462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 19463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_2_23_RD_SIZE1 = 19464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 19465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_3_23_RD_SIZE0 = 19466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 19467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_3_23_RD_SIZE1 = 19468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 19469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_4_RD_SIZE0 = 19470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 19471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_4_RD_SIZE1 = 19472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 19473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_4_RD_SIZE0 = 19474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 19475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_4_RD_SIZE1 = 19476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 19477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2 = 19478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 19479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3 = 19480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 19481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2 = 19482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 19483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3 = 19484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 19485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_0_01_RD_SIZE2 = 19486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 19487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_0_01_RD_SIZE3 = 19488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 19489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_1_01_RD_SIZE2 = 19490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 19491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_1_01_RD_SIZE3 = 19492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 19493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2 = 19494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 19495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3 = 19496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 19497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2 = 19498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 19499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3 = 19500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 19501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_2_23_RD_SIZE2 = 19502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 19503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_2_23_RD_SIZE3 = 19504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 19505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_3_23_RD_SIZE2 = 19506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 19507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_3_23_RD_SIZE3 = 19508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 19509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_4_RD_SIZE2 = 19510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 19511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_4_RD_SIZE3 = 19512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 19513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_4_RD_SIZE2 = 19514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 19515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_4_RD_SIZE3 = 19516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 19517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4 = 19518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 19519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5 = 19520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 19521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4 = 19522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 19523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5 = 19524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 19525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_0_01_RD_SIZE4 = 19526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 19527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_0_01_RD_SIZE5 = 19528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 19529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_1_01_RD_SIZE4 = 19530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 19531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_1_01_RD_SIZE5 = 19532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 19533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4 = 19534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 19535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5 = 19536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 19537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4 = 19538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 19539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5 = 19540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 19541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_2_23_RD_SIZE4 = 19542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 19543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_2_23_RD_SIZE5 = 19544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 19545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_3_23_RD_SIZE4 = 19546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 19547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_3_23_RD_SIZE5 = 19548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 19549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_4_RD_SIZE4 = 19550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 19551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_4_RD_SIZE5 = 19552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 19553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_4_RD_SIZE4 = 19554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 19555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_4_RD_SIZE5 = 19556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 19557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD = 19558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_LEN = 19559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7 = 19560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 19561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD = 19562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_LEN = 19563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7 = 19564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 19565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_0_01_RD = 19566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_0_01_RD_LEN = 19567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_0_01_RD_SIZE7 = 19568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 19569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_1_01_RD = 19570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_1_01_RD_LEN = 19571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_1_01_RD_SIZE7 = 19572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 19573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD = 19574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_LEN = 19575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7 = 19576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 19577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD = 19578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_LEN = 19579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7 = 19580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 19581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_2_23_RD = 19582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_2_23_RD_LEN = 19583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_2_23_RD_SIZE7 = 19584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 19585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_3_23_RD = 19586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_3_23_RD_LEN = 19587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_3_23_RD_SIZE7 = 19588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 19589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_4_RD = 19590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_4_RD_LEN = 19591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_4_RD_SIZE7 = 19592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 19593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_4_RD = 19594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_4_RD_LEN = 19595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_4_RD_SIZE7 = 19596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 19597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0 = 19598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 19599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1 = 19600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 19601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0 = 19602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 19603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1 = 19604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 19605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_0_01_RD_SIZE0 = 19606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 19607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_0_01_RD_SIZE1 = 19608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 19609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_1_01_RD_SIZE0 = 19610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 19611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_1_01_RD_SIZE1 = 19612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 19613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0 = 19614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 19615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1 = 19616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 19617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0 = 19618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 19619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1 = 19620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 19621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_2_23_RD_SIZE0 = 19622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 19623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_2_23_RD_SIZE1 = 19624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 19625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_3_23_RD_SIZE0 = 19626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 19627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_3_23_RD_SIZE1 = 19628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 19629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_4_RD_SIZE0 = 19630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 19631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_4_RD_SIZE1 = 19632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 19633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_4_RD_SIZE0 = 19634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 19635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_4_RD_SIZE1 = 19636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 19637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2 = 19638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 19639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3 = 19640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 19641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2 = 19642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 19643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3 = 19644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 19645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_0_01_RD_SIZE2 = 19646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 19647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_0_01_RD_SIZE3 = 19648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 19649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_1_01_RD_SIZE2 = 19650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 19651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_1_01_RD_SIZE3 = 19652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 19653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2 = 19654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 19655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3 = 19656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 19657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2 = 19658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 19659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3 = 19660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 19661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_2_23_RD_SIZE2 = 19662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 19663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_2_23_RD_SIZE3 = 19664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 19665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_3_23_RD_SIZE2 = 19666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 19667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_3_23_RD_SIZE3 = 19668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 19669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_4_RD_SIZE2 = 19670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 19671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_4_RD_SIZE3 = 19672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 19673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_4_RD_SIZE2 = 19674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 19675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_4_RD_SIZE3 = 19676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 19677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4 = 19678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 19679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5 = 19680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 19681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4 = 19682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 19683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5 = 19684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 19685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_0_01_RD_SIZE4 = 19686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 19687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_0_01_RD_SIZE5 = 19688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 19689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_1_01_RD_SIZE4 = 19690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 19691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_1_01_RD_SIZE5 = 19692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 19693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4 = 19694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 19695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5 = 19696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 19697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4 = 19698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 19699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5 = 19700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 19701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_2_23_RD_SIZE4 = 19702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 19703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_2_23_RD_SIZE5 = 19704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 19705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_3_23_RD_SIZE4 = 19706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 19707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_3_23_RD_SIZE5 = 19708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 19709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_4_RD_SIZE4 = 19710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 19711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_4_RD_SIZE5 = 19712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 19713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_4_RD_SIZE4 = 19714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 19715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_4_RD_SIZE5 = 19716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 19717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6 = 19718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 19719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD = 19720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_LEN = 19721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6 = 19722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 19723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD = 19724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_LEN = 19725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_0_01_RD_SIZE6 = 19726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 19727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_0_01_RD = 19728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_0_01_RD_LEN = 19729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_1_01_RD_SIZE6 = 19730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 19731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_1_01_RD = 19732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_1_01_RD_LEN = 19733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6 = 19734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 19735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD = 19736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_LEN = 19737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6 = 19738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 19739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD = 19740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_LEN = 19741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_2_23_RD_SIZE6 = 19742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 19743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_2_23_RD = 19744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_2_23_RD_LEN = 19745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_3_23_RD_SIZE6 = 19746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 19747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_3_23_RD = 19748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_3_23_RD_LEN = 19749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_4_RD_SIZE6 = 19750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 19751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_4_RD = 19752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P0_4_RD_LEN = 19753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_4_RD_SIZE6 = 19754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 19755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_4_RD = 19756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR3_P1_4_RD_LEN = 19757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0 = 19758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 19759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1 = 19760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 19761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0 = 19762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 19763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1 = 19764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 19765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_0_01_RD_SIZE0 = 19766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 19767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_0_01_RD_SIZE1 = 19768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 19769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_1_01_RD_SIZE0 = 19770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 19771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_1_01_RD_SIZE1 = 19772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 19773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0 = 19774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 19775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1 = 19776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 19777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0 = 19778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 19779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1 = 19780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 19781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_2_23_RD_SIZE0 = 19782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 19783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_2_23_RD_SIZE1 = 19784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 19785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_3_23_RD_SIZE0 = 19786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 19787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_3_23_RD_SIZE1 = 19788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 19789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_4_RD_SIZE0 = 19790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 19791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_4_RD_SIZE1 = 19792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 19793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_4_RD_SIZE0 = 19794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 19795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_4_RD_SIZE1 = 19796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 19797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2 = 19798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 19799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3 = 19800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 19801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2 = 19802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 19803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3 = 19804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 19805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_0_01_RD_SIZE2 = 19806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 19807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_0_01_RD_SIZE3 = 19808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 19809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_1_01_RD_SIZE2 = 19810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 19811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_1_01_RD_SIZE3 = 19812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 19813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2 = 19814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 19815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3 = 19816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 19817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2 = 19818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 19819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3 = 19820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 19821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_2_23_RD_SIZE2 = 19822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 19823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_2_23_RD_SIZE3 = 19824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 19825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_3_23_RD_SIZE2 = 19826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 19827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_3_23_RD_SIZE3 = 19828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 19829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_4_RD_SIZE2 = 19830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 19831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_4_RD_SIZE3 = 19832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 19833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_4_RD_SIZE2 = 19834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 19835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_4_RD_SIZE3 = 19836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 19837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4 = 19838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 19839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5 = 19840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 19841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4 = 19842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 19843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5 = 19844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 19845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_0_01_RD_SIZE4 = 19846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 19847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_0_01_RD_SIZE5 = 19848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 19849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_1_01_RD_SIZE4 = 19850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 19851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_1_01_RD_SIZE5 = 19852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 19853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4 = 19854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 19855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5 = 19856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 19857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4 = 19858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 19859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5 = 19860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 19861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_2_23_RD_SIZE4 = 19862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 19863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_2_23_RD_SIZE5 = 19864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 19865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_3_23_RD_SIZE4 = 19866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 19867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_3_23_RD_SIZE5 = 19868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 19869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_4_RD_SIZE4 = 19870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 19871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_4_RD_SIZE5 = 19872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 19873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_4_RD_SIZE4 = 19874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 19875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_4_RD_SIZE5 = 19876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 19877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6 = 19878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 19879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7 = 19880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 19881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6 = 19882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 19883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7 = 19884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 19885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_0_01_RD_SIZE6 = 19886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 19887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_0_01_RD_SIZE7 = 19888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 19889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_1_01_RD_SIZE6 = 19890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 19891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_1_01_RD_SIZE7 = 19892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 19893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6 = 19894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 19895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7 = 19896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 19897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6 = 19898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 19899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7 = 19900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 19901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_2_23_RD_SIZE6 = 19902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 19903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_2_23_RD_SIZE7 = 19904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 19905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_3_23_RD_SIZE6 = 19906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 19907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_3_23_RD_SIZE7 = 19908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 19909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_4_RD_SIZE6 = 19910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 19911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_4_RD_SIZE7 = 19912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 19913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_4_RD_SIZE6 = 19914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 19915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_4_RD_SIZE7 = 19916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 19917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0 = 19918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 19919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1 = 19920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 19921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0 = 19922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 19923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1 = 19924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 19925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_0_01_RD_SIZE0 = 19926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_0_01_RD_SIZE0_LEN = 19927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_0_01_RD_SIZE1 = 19928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_0_01_RD_SIZE1_LEN = 19929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_1_01_RD_SIZE0 = 19930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_1_01_RD_SIZE0_LEN = 19931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_1_01_RD_SIZE1 = 19932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_1_01_RD_SIZE1_LEN = 19933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0 = 19934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 19935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1 = 19936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 19937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0 = 19938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 19939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1 = 19940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 19941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_2_23_RD_SIZE0 = 19942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_2_23_RD_SIZE0_LEN = 19943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_2_23_RD_SIZE1 = 19944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_2_23_RD_SIZE1_LEN = 19945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_3_23_RD_SIZE0 = 19946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_3_23_RD_SIZE0_LEN = 19947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_3_23_RD_SIZE1 = 19948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_3_23_RD_SIZE1_LEN = 19949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_4_RD_SIZE0 = 19950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_4_RD_SIZE0_LEN = 19951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_4_RD_SIZE1 = 19952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P0_4_RD_SIZE1_LEN = 19953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_4_RD_SIZE0 = 19954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_4_RD_SIZE0_LEN = 19955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_4_RD_SIZE1 = 19956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR0_P1_4_RD_SIZE1_LEN = 19957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2 = 19958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 19959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3 = 19960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 19961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2 = 19962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 19963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3 = 19964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 19965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_0_01_RD_SIZE2 = 19966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_0_01_RD_SIZE2_LEN = 19967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_0_01_RD_SIZE3 = 19968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_0_01_RD_SIZE3_LEN = 19969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_1_01_RD_SIZE2 = 19970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_1_01_RD_SIZE2_LEN = 19971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_1_01_RD_SIZE3 = 19972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_1_01_RD_SIZE3_LEN = 19973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2 = 19974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 19975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3 = 19976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 19977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2 = 19978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 19979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3 = 19980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 19981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_2_23_RD_SIZE2 = 19982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_2_23_RD_SIZE2_LEN = 19983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_2_23_RD_SIZE3 = 19984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_2_23_RD_SIZE3_LEN = 19985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_3_23_RD_SIZE2 = 19986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_3_23_RD_SIZE2_LEN = 19987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_3_23_RD_SIZE3 = 19988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_3_23_RD_SIZE3_LEN = 19989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_4_RD_SIZE2 = 19990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_4_RD_SIZE2_LEN = 19991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_4_RD_SIZE3 = 19992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P0_4_RD_SIZE3_LEN = 19993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_4_RD_SIZE2 = 19994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_4_RD_SIZE2_LEN = 19995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_4_RD_SIZE3 = 19996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR1_P1_4_RD_SIZE3_LEN = 19997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4 = 19998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 19999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5 = 20000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 20001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4 = 20002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 20003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5 = 20004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 20005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_0_01_RD_SIZE4 = 20006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_0_01_RD_SIZE4_LEN = 20007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_0_01_RD_SIZE5 = 20008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_0_01_RD_SIZE5_LEN = 20009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_1_01_RD_SIZE4 = 20010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_1_01_RD_SIZE4_LEN = 20011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_1_01_RD_SIZE5 = 20012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_1_01_RD_SIZE5_LEN = 20013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4 = 20014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 20015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5 = 20016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 20017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4 = 20018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 20019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5 = 20020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 20021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_2_23_RD_SIZE4 = 20022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_2_23_RD_SIZE4_LEN = 20023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_2_23_RD_SIZE5 = 20024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_2_23_RD_SIZE5_LEN = 20025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_3_23_RD_SIZE4 = 20026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_3_23_RD_SIZE4_LEN = 20027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_3_23_RD_SIZE5 = 20028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_3_23_RD_SIZE5_LEN = 20029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_4_RD_SIZE4 = 20030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_4_RD_SIZE4_LEN = 20031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_4_RD_SIZE5 = 20032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P0_4_RD_SIZE5_LEN = 20033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_4_RD_SIZE4 = 20034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_4_RD_SIZE4_LEN = 20035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_4_RD_SIZE5 = 20036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR2_P1_4_RD_SIZE5_LEN = 20037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6 = 20038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 20039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7 = 20040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 20041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6 = 20042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 20043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7 = 20044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 20045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_0_01_RD_SIZE6 = 20046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_0_01_RD_SIZE6_LEN = 20047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_0_01_RD_SIZE7 = 20048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_0_01_RD_SIZE7_LEN = 20049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_1_01_RD_SIZE6 = 20050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_1_01_RD_SIZE6_LEN = 20051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_1_01_RD_SIZE7 = 20052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_1_01_RD_SIZE7_LEN = 20053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6 = 20054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 20055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7 = 20056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 20057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6 = 20058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 20059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7 = 20060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 20061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_2_23_RD_SIZE6 = 20062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_2_23_RD_SIZE6_LEN = 20063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_2_23_RD_SIZE7 = 20064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_2_23_RD_SIZE7_LEN = 20065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_3_23_RD_SIZE6 = 20066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_3_23_RD_SIZE6_LEN = 20067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_3_23_RD_SIZE7 = 20068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_3_23_RD_SIZE7_LEN = 20069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_4_RD_SIZE6 = 20070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_4_RD_SIZE6_LEN = 20071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_4_RD_SIZE7 = 20072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P0_4_RD_SIZE7_LEN = 20073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_4_RD_SIZE6 = 20074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_4_RD_SIZE6_LEN = 20075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_4_RD_SIZE7 = 20076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR3_P1_4_RD_SIZE7_LEN = 20077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_01 = 20078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_01_LEN = 20079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1 = 20080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1_LEN = 20081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_01 = 20082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_01_LEN = 20083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1 = 20084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1_LEN = 20085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_01 = 20086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_01_LEN = 20087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_01_REFERENCE1 = 20088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_01_REFERENCE1_LEN = 20089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_01 = 20090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_01_LEN = 20091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_01_REFERENCE1 = 20092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_01_REFERENCE1_LEN = 20093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_23 = 20094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_23_LEN = 20095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1 = 20096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1_LEN = 20097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_23 = 20098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_23_LEN = 20099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1 = 20100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1_LEN = 20101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_23 = 20102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_23_LEN = 20103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_23_REFERENCE1 = 20104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_23_REFERENCE1_LEN = 20105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_23 = 20106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_23_LEN = 20107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_23_REFERENCE1 = 20108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_23_REFERENCE1_LEN = 20109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_REFERENCE0 = 20110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_REFERENCE0_LEN = 20111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_REFERENCE1 = 20112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_REFERENCE1_LEN = 20113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_REFERENCE0 = 20114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_REFERENCE0_LEN = 20115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_REFERENCE1 = 20116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_REFERENCE1_LEN = 20117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2 = 20118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2_LEN = 20119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3 = 20120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3_LEN = 20121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2 = 20122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2_LEN = 20123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3 = 20124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3_LEN = 20125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_01_REFERENCE2 = 20126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_01_REFERENCE2_LEN = 20127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_01_REFERENCE3 = 20128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_01_REFERENCE3_LEN = 20129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_01_REFERENCE2 = 20130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_01_REFERENCE2_LEN = 20131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_01_REFERENCE3 = 20132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_01_REFERENCE3_LEN = 20133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2 = 20134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2_LEN = 20135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3 = 20136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3_LEN = 20137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2 = 20138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2_LEN = 20139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3 = 20140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3_LEN = 20141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_23_REFERENCE2 = 20142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_23_REFERENCE2_LEN = 20143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_23_REFERENCE3 = 20144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_23_REFERENCE3_LEN = 20145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_23_REFERENCE2 = 20146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_23_REFERENCE2_LEN = 20147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_23_REFERENCE3 = 20148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_23_REFERENCE3_LEN = 20149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_REFERENCE2 = 20150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_REFERENCE2_LEN = 20151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_REFERENCE3 = 20152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_REFERENCE3_LEN = 20153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_REFERENCE2 = 20154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_REFERENCE2_LEN = 20155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_REFERENCE3 = 20156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_REFERENCE3_LEN = 20157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_CTL_SIDE0 = 20158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_CTL_SIDE0_LEN = 20159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_CTL_SIDE1 = 20160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_CTL_SIDE1_LEN = 20161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_SXMCVREF_3 = 20162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_SXMCVREF_3_LEN = 20163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_SXPODVREF = 20164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_DISABLE_TERMINATION = 20165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE = 20166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE_LEN = 20167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_CTL_SIDE0 = 20168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_CTL_SIDE0_LEN = 20169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_CTL_SIDE1 = 20170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_CTL_SIDE1_LEN = 20171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_SXMCVREF_0_3 = 20172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_SXMCVREF_0_3_LEN = 20173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_SXPODVREF = 20174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_DISABLE_TERMINATION = 20175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_READ_CENTERING_MODE = 20176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_1_01_READ_CENTERING_MODE_LEN = 20177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_CTL_SIDE0 = 20178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_CTL_SIDE0_LEN = 20179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_CTL_SIDE1 = 20180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_CTL_SIDE1_LEN = 20181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_SXMCVREF_3 = 20182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_SXMCVREF_3_LEN = 20183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_SXPODVREF = 20184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_DISABLE_TERMINATION = 20185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_READ_CENTERING_MODE = 20186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_0_01_READ_CENTERING_MODE_LEN = 20187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_CTL_SIDE0 = 20188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_CTL_SIDE0_LEN = 20189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_CTL_SIDE1 = 20190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_CTL_SIDE1_LEN = 20191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_SXMCVREF_0_3 = 20192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_SXMCVREF_0_3_LEN = 20193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_SXPODVREF = 20194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_DISABLE_TERMINATION = 20195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_READ_CENTERING_MODE = 20196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_1_01_READ_CENTERING_MODE_LEN = 20197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_CTL_SIDE0 = 20198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_CTL_SIDE0_LEN = 20199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_CTL_SIDE1 = 20200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_CTL_SIDE1_LEN = 20201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_SXMCVREF_0_3 = 20202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_SXMCVREF_0_3_LEN = 20203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_SXPODVREF = 20204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_DISABLE_TERMINATION = 20205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_READ_CENTERING_MODE = 20206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_2_23_READ_CENTERING_MODE_LEN = 20207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_CTL_SIDE0 = 20208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_CTL_SIDE0_LEN = 20209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_CTL_SIDE1 = 20210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_CTL_SIDE1_LEN = 20211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_SXMCVREF_0 = 20212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_SXMCVREF_0_LEN = 20213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_SXPODVREF = 20214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_DISABLE_TERMINATION = 20215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_READ_CENTERING_MODE = 20216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_3_23_READ_CENTERING_MODE_LEN = 20217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_CTL_SIDE0 = 20218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_CTL_SIDE0_LEN = 20219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_CTL_SIDE1 = 20220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_CTL_SIDE1_LEN = 20221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_SXMCVREF_0_3 = 20222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_SXMCVREF_0_3_LEN = 20223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_SXPODVREF = 20224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_DISABLE_TERMINATION = 20225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_READ_CENTERING_MODE = 20226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_2_23_READ_CENTERING_MODE_LEN = 20227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_CTL_SIDE0 = 20228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_CTL_SIDE0_LEN = 20229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_CTL_SIDE1 = 20230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_CTL_SIDE1_LEN = 20231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_SXMCVREF_0 = 20232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_SXMCVREF_0_LEN = 20233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_SXPODVREF = 20234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_DISABLE_TERMINATION = 20235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_READ_CENTERING_MODE = 20236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_3_23_READ_CENTERING_MODE_LEN = 20237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_CTL_SIDE0 = 20238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_CTL_SIDE0_LEN = 20239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_CTL_SIDE1 = 20240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_CTL_SIDE1_LEN = 20241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_SXMCVREF_0_3 = 20242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_SXMCVREF_0_3_LEN = 20243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_SXPODVREF = 20244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_DISABLE_TERMINATION = 20245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_READ_CENTERING_MODE = 20246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P0_4_READ_CENTERING_MODE_LEN = 20247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_CTL_SIDE0 = 20248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_CTL_SIDE0_LEN = 20249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_CTL_SIDE1 = 20250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_CTL_SIDE1_LEN = 20251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_SXMCVREF_0_3 = 20252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_SXMCVREF_0_3_LEN = 20253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_SXPODVREF = 20254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_DISABLE_TERMINATION = 20255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_READ_CENTERING_MODE = 20256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RX_PEAK_AMP_P1_4_READ_CENTERING_MODE_LEN = 20257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_0_01_ROT = 20258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_0_01_ROT_LEN = 20259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK = 20260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_1_01_ROT = 20261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_1_01_ROT_LEN = 20262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK = 20263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_0_01_ROT = 20264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_0_01_ROT_LEN = 20265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_0_01_BB_LOCK = 20266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_1_01_ROT = 20267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_1_01_ROT_LEN = 20268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_1_01_BB_LOCK = 20269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_2_23_ROT = 20270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_2_23_ROT_LEN = 20271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK = 20272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_3_23_ROT = 20273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_3_23_ROT_LEN = 20274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK = 20275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_2_23_ROT = 20276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_2_23_ROT_LEN = 20277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_2_23_BB_LOCK = 20278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_3_23_ROT = 20279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_3_23_ROT_LEN = 20280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_3_23_BB_LOCK = 20281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_4_ROT = 20282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_4_ROT_LEN = 20283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_4_BB_LOCK = 20284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_4_ROT = 20285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_4_ROT_LEN = 20286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_4_BB_LOCK = 20287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_ENABLE = 20288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_ROT_OVERRIDE = 20289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_ROT_OVERRIDE_LEN = 20290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_ROT_OVERRIDE_EN = 20291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_PHASE_ALIGN_RESET = 20292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_PHASE_CNTL_EN = 20293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_PHASE_DEFAULT_EN = 20294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_POS_EDGE_ALIGN = 20295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_0_01_CONTINUOUS_UPDATE = 20296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_ENABLE = 20297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_ROT_OVERRIDE = 20298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_ROT_OVERRIDE_LEN = 20299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_ROT_OVERRIDE_EN = 20300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_PHASE_ALIGN_RESET = 20301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_PHASE_CNTL_EN = 20302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_PHASE_DEFAULT_EN = 20303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_POS_EDGE_ALIGN = 20304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_1_01_CONTINUOUS_UPDATE = 20305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_ENABLE = 20306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_ROT_OVERRIDE = 20307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_ROT_OVERRIDE_LEN = 20308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_ROT_OVERRIDE_EN = 20309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_PHASE_ALIGN_RESET = 20310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_PHASE_CNTL_EN = 20311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_PHASE_DEFAULT_EN = 20312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_POS_EDGE_ALIGN = 20313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_0_01_CONTINUOUS_UPDATE = 20314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_ENABLE = 20315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_ROT_OVERRIDE = 20316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_ROT_OVERRIDE_LEN = 20317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_ROT_OVERRIDE_EN = 20318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_PHASE_ALIGN_RESET = 20319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_PHASE_CNTL_EN = 20320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_PHASE_DEFAULT_EN = 20321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_POS_EDGE_ALIGN = 20322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_1_01_CONTINUOUS_UPDATE = 20323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_ENABLE = 20324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_ROT_OVERRIDE = 20325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_ROT_OVERRIDE_LEN = 20326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_ROT_OVERRIDE_EN = 20327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_PHASE_ALIGN_RESET = 20328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_PHASE_CNTL_EN = 20329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_PHASE_DEFAULT_EN = 20330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_POS_EDGE_ALIGN = 20331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_2_23_CONTINUOUS_UPDATE = 20332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_ENABLE = 20333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_ROT_OVERRIDE = 20334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_ROT_OVERRIDE_LEN = 20335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_ROT_OVERRIDE_EN = 20336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_PHASE_ALIGN_RESET = 20337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_PHASE_CNTL_EN = 20338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_PHASE_DEFAULT_EN = 20339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_POS_EDGE_ALIGN = 20340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_3_23_CONTINUOUS_UPDATE = 20341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_ENABLE = 20342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_ROT_OVERRIDE = 20343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_ROT_OVERRIDE_LEN = 20344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_ROT_OVERRIDE_EN = 20345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_PHASE_ALIGN_RESET = 20346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_PHASE_CNTL_EN = 20347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_PHASE_DEFAULT_EN = 20348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_POS_EDGE_ALIGN = 20349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_2_23_CONTINUOUS_UPDATE = 20350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_ENABLE = 20351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_ROT_OVERRIDE = 20352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_ROT_OVERRIDE_LEN = 20353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_ROT_OVERRIDE_EN = 20354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_PHASE_ALIGN_RESET = 20355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_PHASE_CNTL_EN = 20356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_PHASE_DEFAULT_EN = 20357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_POS_EDGE_ALIGN = 20358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_3_23_CONTINUOUS_UPDATE = 20359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_ENABLE = 20360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_ROT_OVERRIDE = 20361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_ROT_OVERRIDE_LEN = 20362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_ROT_OVERRIDE_EN = 20363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_PHASE_ALIGN_RESET = 20364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_PHASE_CNTL_EN = 20365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_PHASE_DEFAULT_EN = 20366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_POS_EDGE_ALIGN = 20367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P0_4_CONTINUOUS_UPDATE = 20368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_ENABLE = 20369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_ROT_OVERRIDE = 20370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_ROT_OVERRIDE_LEN = 20371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_ROT_OVERRIDE_EN = 20372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_PHASE_ALIGN_RESET = 20373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_PHASE_CNTL_EN = 20374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_PHASE_DEFAULT_EN = 20375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_POS_EDGE_ALIGN = 20376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_SYSCLK_PR_P1_4_CONTINUOUS_UPDATE = 20377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16 = 20378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK16 = 20379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK16 = 20380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK16 = 20381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK18 = 20382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK18 = 20383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK20 = 20384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK20 = 20385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK22 = 20386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK22 = 20387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_CLK16_SINGLE_ENDED = 20388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_CLK18_SINGLE_ENDED = 20389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_CLK20_SINGLE_ENDED = 20390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_CLK22_SINGLE_ENDED = 20391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK18 = 20392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK18 = 20393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK16 = 20394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK16 = 20395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK16 = 20396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK16 = 20397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK18 = 20398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK18 = 20399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK20 = 20400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK20 = 20401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK22 = 20402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK22 = 20403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_CLK16_SINGLE_ENDED = 20404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_CLK18_SINGLE_ENDED = 20405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_CLK20_SINGLE_ENDED = 20406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_CLK22_SINGLE_ENDED = 20407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK18 = 20408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK18 = 20409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD0_CLK16 = 20410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD1_CLK16 = 20411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD2_CLK16 = 20412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD3_CLK16 = 20413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD0_CLK18 = 20414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD1_CLK18 = 20415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD2_CLK20 = 20416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD3_CLK20 = 20417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD2_CLK22 = 20418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD3_CLK22 = 20419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_CLK16_SINGLE_ENDED = 20420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_CLK18_SINGLE_ENDED = 20421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_CLK20_SINGLE_ENDED = 20422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_CLK22_SINGLE_ENDED = 20423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD2_CLK18 = 20424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_01_QUAD3_CLK18 = 20425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD0_CLK16 = 20426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD1_CLK16 = 20427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD2_CLK16 = 20428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD3_CLK16 = 20429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD0_CLK18 = 20430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD1_CLK18 = 20431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD2_CLK20 = 20432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD3_CLK20 = 20433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD2_CLK22 = 20434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD3_CLK22 = 20435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_CLK16_SINGLE_ENDED = 20436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_CLK18_SINGLE_ENDED = 20437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_CLK20_SINGLE_ENDED = 20438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_CLK22_SINGLE_ENDED = 20439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD2_CLK18 = 20440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_01_QUAD3_CLK18 = 20441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK16 = 20442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK16 = 20443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK16 = 20444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK16 = 20445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK18 = 20446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK18 = 20447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK20 = 20448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK20 = 20449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK22 = 20450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK22 = 20451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_CLK16_SINGLE_ENDED = 20452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_CLK18_SINGLE_ENDED = 20453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_CLK20_SINGLE_ENDED = 20454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_CLK22_SINGLE_ENDED = 20455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK18 = 20456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK18 = 20457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK16 = 20458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK16 = 20459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK16 = 20460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK16 = 20461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK18 = 20462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK18 = 20463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK20 = 20464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK20 = 20465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK22 = 20466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK22 = 20467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_CLK16_SINGLE_ENDED = 20468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_CLK18_SINGLE_ENDED = 20469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_CLK20_SINGLE_ENDED = 20470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_CLK22_SINGLE_ENDED = 20471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK18 = 20472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK18 = 20473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD0_CLK16 = 20474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD1_CLK16 = 20475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD2_CLK16 = 20476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD3_CLK16 = 20477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD0_CLK18 = 20478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD1_CLK18 = 20479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD2_CLK20 = 20480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD3_CLK20 = 20481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD2_CLK22 = 20482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD3_CLK22 = 20483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_CLK16_SINGLE_ENDED = 20484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_CLK18_SINGLE_ENDED = 20485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_CLK20_SINGLE_ENDED = 20486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_CLK22_SINGLE_ENDED = 20487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD2_CLK18 = 20488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_23_QUAD3_CLK18 = 20489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD0_CLK16 = 20490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD1_CLK16 = 20491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD2_CLK16 = 20492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD3_CLK16 = 20493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD0_CLK18 = 20494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD1_CLK18 = 20495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD2_CLK20 = 20496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD3_CLK20 = 20497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD2_CLK22 = 20498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD3_CLK22 = 20499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_CLK16_SINGLE_ENDED = 20500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_CLK18_SINGLE_ENDED = 20501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_CLK20_SINGLE_ENDED = 20502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_CLK22_SINGLE_ENDED = 20503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD2_CLK18 = 20504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_23_QUAD3_CLK18 = 20505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD0_CLK16 = 20506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD1_CLK16 = 20507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD2_CLK16 = 20508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD3_CLK16 = 20509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD0_CLK18 = 20510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD1_CLK18 = 20511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD2_CLK20 = 20512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD3_CLK20 = 20513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD2_CLK22 = 20514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD3_CLK22 = 20515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_CLK16_SINGLE_ENDED = 20516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_CLK18_SINGLE_ENDED = 20517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_CLK20_SINGLE_ENDED = 20518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_CLK22_SINGLE_ENDED = 20519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD2_CLK18 = 20520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_QUAD3_CLK18 = 20521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD0_CLK16 = 20522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD1_CLK16 = 20523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD2_CLK16 = 20524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD3_CLK16 = 20525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD0_CLK18 = 20526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD1_CLK18 = 20527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD2_CLK20 = 20528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD3_CLK20 = 20529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD2_CLK22 = 20530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD3_CLK22 = 20531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_CLK16_SINGLE_ENDED = 20532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_CLK18_SINGLE_ENDED = 20533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_CLK20_SINGLE_ENDED = 20534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_CLK22_SINGLE_ENDED = 20535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD2_CLK18 = 20536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_QUAD3_CLK18 = 20537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK16 = 20538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK16 = 20539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK16 = 20540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK16 = 20541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK18 = 20542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK18 = 20543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK20 = 20544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK20 = 20545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK22 = 20546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK22 = 20547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_CLK16_SINGLE_ENDED = 20548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_CLK18_SINGLE_ENDED = 20549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_CLK20_SINGLE_ENDED = 20550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_CLK22_SINGLE_ENDED = 20551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK18 = 20552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK18 = 20553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK16 = 20554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK16 = 20555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK16 = 20556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK16 = 20557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK18 = 20558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK18 = 20559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK20 = 20560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK20 = 20561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK22 = 20562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK22 = 20563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_CLK16_SINGLE_ENDED = 20564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_CLK18_SINGLE_ENDED = 20565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_CLK20_SINGLE_ENDED = 20566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_CLK22_SINGLE_ENDED = 20567;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK18 = 20568;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK18 = 20569;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD0_CLK16 = 20570;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD1_CLK16 = 20571;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD2_CLK16 = 20572;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD3_CLK16 = 20573;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD0_CLK18 = 20574;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD1_CLK18 = 20575;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD2_CLK20 = 20576;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD3_CLK20 = 20577;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD2_CLK22 = 20578;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD3_CLK22 = 20579;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_CLK16_SINGLE_ENDED = 20580;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_CLK18_SINGLE_ENDED = 20581;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_CLK20_SINGLE_ENDED = 20582;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_CLK22_SINGLE_ENDED = 20583;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD2_CLK18 = 20584;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_0_01_QUAD3_CLK18 = 20585;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD0_CLK16 = 20586;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD1_CLK16 = 20587;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD2_CLK16 = 20588;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD3_CLK16 = 20589;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD0_CLK18 = 20590;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD1_CLK18 = 20591;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD2_CLK20 = 20592;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD3_CLK20 = 20593;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD2_CLK22 = 20594;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD3_CLK22 = 20595;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_CLK16_SINGLE_ENDED = 20596;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_CLK18_SINGLE_ENDED = 20597;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_CLK20_SINGLE_ENDED = 20598;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_CLK22_SINGLE_ENDED = 20599;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD2_CLK18 = 20600;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_1_01_QUAD3_CLK18 = 20601;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK16 = 20602;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK16 = 20603;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK16 = 20604;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK16 = 20605;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK18 = 20606;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK18 = 20607;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK20 = 20608;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK20 = 20609;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK22 = 20610;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK22 = 20611;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_CLK16_SINGLE_ENDED = 20612;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_CLK18_SINGLE_ENDED = 20613;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_CLK20_SINGLE_ENDED = 20614;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_CLK22_SINGLE_ENDED = 20615;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK18 = 20616;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK18 = 20617;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK16 = 20618;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK16 = 20619;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK16 = 20620;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK16 = 20621;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK18 = 20622;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK18 = 20623;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK20 = 20624;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK20 = 20625;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK22 = 20626;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK22 = 20627;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_CLK16_SINGLE_ENDED = 20628;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_CLK18_SINGLE_ENDED = 20629;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_CLK20_SINGLE_ENDED = 20630;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_CLK22_SINGLE_ENDED = 20631;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK18 = 20632;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK18 = 20633;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD0_CLK16 = 20634;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD1_CLK16 = 20635;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD2_CLK16 = 20636;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD3_CLK16 = 20637;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD0_CLK18 = 20638;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD1_CLK18 = 20639;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD2_CLK20 = 20640;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD3_CLK20 = 20641;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD2_CLK22 = 20642;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD3_CLK22 = 20643;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_CLK16_SINGLE_ENDED = 20644;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_CLK18_SINGLE_ENDED = 20645;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_CLK20_SINGLE_ENDED = 20646;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_CLK22_SINGLE_ENDED = 20647;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD2_CLK18 = 20648;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_2_23_QUAD3_CLK18 = 20649;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD0_CLK16 = 20650;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD1_CLK16 = 20651;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD2_CLK16 = 20652;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD3_CLK16 = 20653;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD0_CLK18 = 20654;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD1_CLK18 = 20655;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD2_CLK20 = 20656;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD3_CLK20 = 20657;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD2_CLK22 = 20658;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD3_CLK22 = 20659;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_CLK16_SINGLE_ENDED = 20660;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_CLK18_SINGLE_ENDED = 20661;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_CLK20_SINGLE_ENDED = 20662;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_CLK22_SINGLE_ENDED = 20663;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD2_CLK18 = 20664;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_3_23_QUAD3_CLK18 = 20665;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD0_CLK16 = 20666;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD1_CLK16 = 20667;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD2_CLK16 = 20668;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD3_CLK16 = 20669;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD0_CLK18 = 20670;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD1_CLK18 = 20671;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD2_CLK20 = 20672;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD3_CLK20 = 20673;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD2_CLK22 = 20674;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD3_CLK22 = 20675;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_CLK16_SINGLE_ENDED = 20676;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_CLK18_SINGLE_ENDED = 20677;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_CLK20_SINGLE_ENDED = 20678;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_CLK22_SINGLE_ENDED = 20679;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD2_CLK18 = 20680;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P0_4_QUAD3_CLK18 = 20681;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD0_CLK16 = 20682;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD1_CLK16 = 20683;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD2_CLK16 = 20684;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD3_CLK16 = 20685;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD0_CLK18 = 20686;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD1_CLK18 = 20687;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD2_CLK20 = 20688;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD3_CLK20 = 20689;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD2_CLK22 = 20690;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD3_CLK22 = 20691;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_CLK16_SINGLE_ENDED = 20692;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_CLK18_SINGLE_ENDED = 20693;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_CLK20_SINGLE_ENDED = 20694;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_CLK22_SINGLE_ENDED = 20695;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD2_CLK18 = 20696;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP1_P1_4_QUAD3_CLK18 = 20697;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK16 = 20698;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK16 = 20699;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK16 = 20700;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK16 = 20701;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK18 = 20702;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK18 = 20703;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK20 = 20704;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK20 = 20705;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK22 = 20706;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK22 = 20707;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_CLK16_SINGLE_ENDED = 20708;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_CLK18_SINGLE_ENDED = 20709;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_CLK20_SINGLE_ENDED = 20710;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_CLK22_SINGLE_ENDED = 20711;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK18 = 20712;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK18 = 20713;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK16 = 20714;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK16 = 20715;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK16 = 20716;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK16 = 20717;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK18 = 20718;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK18 = 20719;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK20 = 20720;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK20 = 20721;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK22 = 20722;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK22 = 20723;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_CLK16_SINGLE_ENDED = 20724;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_CLK18_SINGLE_ENDED = 20725;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_CLK20_SINGLE_ENDED = 20726;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_CLK22_SINGLE_ENDED = 20727;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK18 = 20728;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK18 = 20729;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD0_CLK16 = 20730;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD1_CLK16 = 20731;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD2_CLK16 = 20732;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD3_CLK16 = 20733;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD0_CLK18 = 20734;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD1_CLK18 = 20735;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD2_CLK20 = 20736;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD3_CLK20 = 20737;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD2_CLK22 = 20738;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD3_CLK22 = 20739;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_CLK16_SINGLE_ENDED = 20740;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_CLK18_SINGLE_ENDED = 20741;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_CLK20_SINGLE_ENDED = 20742;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_CLK22_SINGLE_ENDED = 20743;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD2_CLK18 = 20744;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_0_01_QUAD3_CLK18 = 20745;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD0_CLK16 = 20746;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD1_CLK16 = 20747;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD2_CLK16 = 20748;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD3_CLK16 = 20749;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD0_CLK18 = 20750;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD1_CLK18 = 20751;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD2_CLK20 = 20752;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD3_CLK20 = 20753;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD2_CLK22 = 20754;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD3_CLK22 = 20755;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_CLK16_SINGLE_ENDED = 20756;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_CLK18_SINGLE_ENDED = 20757;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_CLK20_SINGLE_ENDED = 20758;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_CLK22_SINGLE_ENDED = 20759;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD2_CLK18 = 20760;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_1_01_QUAD3_CLK18 = 20761;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK16 = 20762;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK16 = 20763;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK16 = 20764;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK16 = 20765;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK18 = 20766;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK18 = 20767;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK20 = 20768;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK20 = 20769;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK22 = 20770;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK22 = 20771;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_CLK16_SINGLE_ENDED = 20772;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_CLK18_SINGLE_ENDED = 20773;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_CLK20_SINGLE_ENDED = 20774;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_CLK22_SINGLE_ENDED = 20775;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK18 = 20776;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK18 = 20777;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK16 = 20778;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK16 = 20779;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK16 = 20780;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK16 = 20781;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK18 = 20782;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK18 = 20783;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK20 = 20784;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK20 = 20785;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK22 = 20786;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK22 = 20787;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_CLK16_SINGLE_ENDED = 20788;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_CLK18_SINGLE_ENDED = 20789;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_CLK20_SINGLE_ENDED = 20790;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_CLK22_SINGLE_ENDED = 20791;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK18 = 20792;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK18 = 20793;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD0_CLK16 = 20794;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD1_CLK16 = 20795;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD2_CLK16 = 20796;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD3_CLK16 = 20797;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD0_CLK18 = 20798;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD1_CLK18 = 20799;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD2_CLK20 = 20800;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD3_CLK20 = 20801;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD2_CLK22 = 20802;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD3_CLK22 = 20803;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_CLK16_SINGLE_ENDED = 20804;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_CLK18_SINGLE_ENDED = 20805;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_CLK20_SINGLE_ENDED = 20806;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_CLK22_SINGLE_ENDED = 20807;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD2_CLK18 = 20808;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_2_23_QUAD3_CLK18 = 20809;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD0_CLK16 = 20810;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD1_CLK16 = 20811;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD2_CLK16 = 20812;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD3_CLK16 = 20813;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD0_CLK18 = 20814;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD1_CLK18 = 20815;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD2_CLK20 = 20816;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD3_CLK20 = 20817;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD2_CLK22 = 20818;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD3_CLK22 = 20819;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_CLK16_SINGLE_ENDED = 20820;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_CLK18_SINGLE_ENDED = 20821;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_CLK20_SINGLE_ENDED = 20822;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_CLK22_SINGLE_ENDED = 20823;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD2_CLK18 = 20824;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_3_23_QUAD3_CLK18 = 20825;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD0_CLK16 = 20826;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD1_CLK16 = 20827;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD2_CLK16 = 20828;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD3_CLK16 = 20829;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD0_CLK18 = 20830;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD1_CLK18 = 20831;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD2_CLK20 = 20832;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD3_CLK20 = 20833;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD2_CLK22 = 20834;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD3_CLK22 = 20835;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_CLK16_SINGLE_ENDED = 20836;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_CLK18_SINGLE_ENDED = 20837;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_CLK20_SINGLE_ENDED = 20838;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_CLK22_SINGLE_ENDED = 20839;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD2_CLK18 = 20840;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P0_4_QUAD3_CLK18 = 20841;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD0_CLK16 = 20842;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD1_CLK16 = 20843;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD2_CLK16 = 20844;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD3_CLK16 = 20845;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD0_CLK18 = 20846;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD1_CLK18 = 20847;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD2_CLK20 = 20848;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD3_CLK20 = 20849;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD2_CLK22 = 20850;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD3_CLK22 = 20851;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_CLK16_SINGLE_ENDED = 20852;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_CLK18_SINGLE_ENDED = 20853;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_CLK20_SINGLE_ENDED = 20854;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_CLK22_SINGLE_ENDED = 20855;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD2_CLK18 = 20856;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP2_P1_4_QUAD3_CLK18 = 20857;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK16 = 20858;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK16 = 20859;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK16 = 20860;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK16 = 20861;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK18 = 20862;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK18 = 20863;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK20 = 20864;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK20 = 20865;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK22 = 20866;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK22 = 20867;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_CLK16_SINGLE_ENDED = 20868;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_CLK18_SINGLE_ENDED = 20869;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_CLK20_SINGLE_ENDED = 20870;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_CLK22_SINGLE_ENDED = 20871;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK18 = 20872;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK18 = 20873;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK16 = 20874;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK16 = 20875;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK16 = 20876;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK16 = 20877;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK18 = 20878;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK18 = 20879;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK20 = 20880;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK20 = 20881;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK22 = 20882;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK22 = 20883;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_CLK16_SINGLE_ENDED = 20884;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_CLK18_SINGLE_ENDED = 20885;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_CLK20_SINGLE_ENDED = 20886;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_CLK22_SINGLE_ENDED = 20887;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK18 = 20888;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK18 = 20889;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD0_CLK16 = 20890;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD1_CLK16 = 20891;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD2_CLK16 = 20892;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD3_CLK16 = 20893;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD0_CLK18 = 20894;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD1_CLK18 = 20895;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD2_CLK20 = 20896;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD3_CLK20 = 20897;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD2_CLK22 = 20898;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD3_CLK22 = 20899;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_CLK16_SINGLE_ENDED = 20900;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_CLK18_SINGLE_ENDED = 20901;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_CLK20_SINGLE_ENDED = 20902;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_CLK22_SINGLE_ENDED = 20903;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD2_CLK18 = 20904;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_0_01_QUAD3_CLK18 = 20905;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD0_CLK16 = 20906;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD1_CLK16 = 20907;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD2_CLK16 = 20908;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD3_CLK16 = 20909;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD0_CLK18 = 20910;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD1_CLK18 = 20911;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD2_CLK20 = 20912;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD3_CLK20 = 20913;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD2_CLK22 = 20914;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD3_CLK22 = 20915;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_CLK16_SINGLE_ENDED = 20916;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_CLK18_SINGLE_ENDED = 20917;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_CLK20_SINGLE_ENDED = 20918;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_CLK22_SINGLE_ENDED = 20919;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD2_CLK18 = 20920;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_1_01_QUAD3_CLK18 = 20921;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK16 = 20922;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK16 = 20923;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK16 = 20924;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK16 = 20925;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK18 = 20926;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK18 = 20927;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK20 = 20928;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK20 = 20929;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK22 = 20930;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK22 = 20931;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_CLK16_SINGLE_ENDED = 20932;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_CLK18_SINGLE_ENDED = 20933;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_CLK20_SINGLE_ENDED = 20934;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_CLK22_SINGLE_ENDED = 20935;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK18 = 20936;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK18 = 20937;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK16 = 20938;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK16 = 20939;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK16 = 20940;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK16 = 20941;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK18 = 20942;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK18 = 20943;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK20 = 20944;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK20 = 20945;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK22 = 20946;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK22 = 20947;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_CLK16_SINGLE_ENDED = 20948;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_CLK18_SINGLE_ENDED = 20949;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_CLK20_SINGLE_ENDED = 20950;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_CLK22_SINGLE_ENDED = 20951;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK18 = 20952;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK18 = 20953;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD0_CLK16 = 20954;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD1_CLK16 = 20955;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD2_CLK16 = 20956;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD3_CLK16 = 20957;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD0_CLK18 = 20958;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD1_CLK18 = 20959;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD2_CLK20 = 20960;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD3_CLK20 = 20961;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD2_CLK22 = 20962;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD3_CLK22 = 20963;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_CLK16_SINGLE_ENDED = 20964;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_CLK18_SINGLE_ENDED = 20965;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_CLK20_SINGLE_ENDED = 20966;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_CLK22_SINGLE_ENDED = 20967;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD2_CLK18 = 20968;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_2_23_QUAD3_CLK18 = 20969;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD0_CLK16 = 20970;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD1_CLK16 = 20971;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD2_CLK16 = 20972;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD3_CLK16 = 20973;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD0_CLK18 = 20974;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD1_CLK18 = 20975;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD2_CLK20 = 20976;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD3_CLK20 = 20977;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD2_CLK22 = 20978;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD3_CLK22 = 20979;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_CLK16_SINGLE_ENDED = 20980;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_CLK18_SINGLE_ENDED = 20981;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_CLK20_SINGLE_ENDED = 20982;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_CLK22_SINGLE_ENDED = 20983;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD2_CLK18 = 20984;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_3_23_QUAD3_CLK18 = 20985;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD0_CLK16 = 20986;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD1_CLK16 = 20987;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD2_CLK16 = 20988;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD3_CLK16 = 20989;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD0_CLK18 = 20990;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD1_CLK18 = 20991;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD2_CLK20 = 20992;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD3_CLK20 = 20993;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD2_CLK22 = 20994;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD3_CLK22 = 20995;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_CLK16_SINGLE_ENDED = 20996;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_CLK18_SINGLE_ENDED = 20997;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_CLK20_SINGLE_ENDED = 20998;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_CLK22_SINGLE_ENDED = 20999;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD2_CLK18 = 21000;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P0_4_QUAD3_CLK18 = 21001;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD0_CLK16 = 21002;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD1_CLK16 = 21003;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD2_CLK16 = 21004;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD3_CLK16 = 21005;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD0_CLK18 = 21006;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD1_CLK18 = 21007;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD2_CLK20 = 21008;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD3_CLK20 = 21009;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD2_CLK22 = 21010;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD3_CLK22 = 21011;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_CLK16_SINGLE_ENDED = 21012;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_CLK18_SINGLE_ENDED = 21013;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_CLK20_SINGLE_ENDED = 21014;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_CLK22_SINGLE_ENDED = 21015;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD2_CLK18 = 21016;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_EN_RP3_P1_4_QUAD3_CLK18 = 21017;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_0_01_TSYS = 21018;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_0_01_TSYS_LEN = 21019;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_1_01_TSYS = 21020;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_1_01_TSYS_LEN = 21021;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_0_01_TSYS = 21022;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_0_01_TSYS_LEN = 21023;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_1_01_TSYS = 21024;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_1_01_TSYS_LEN = 21025;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_2_23_TSYS = 21026;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_2_23_TSYS_LEN = 21027;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_3_23_TSYS = 21028;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_3_23_TSYS_LEN = 21029;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_2_23_TSYS = 21030;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_2_23_TSYS_LEN = 21031;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_3_23_TSYS = 21032;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_3_23_TSYS_LEN = 21033;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_4_TSYS = 21034;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P0_4_TSYS_LEN = 21035;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_4_TSYS = 21036;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WRCLK_PR_P1_4_TSYS_LEN = 21037;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED = 21038;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED_LEN = 21039;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_LEFT = 21040;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_BIG_STEP_RIGHT = 21041;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_MATCH_STEP_RIGHT = 21042;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_JUMP_BACK_RIGHT = 21043;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_RIGHT = 21044;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_0_01_DONE = 21045;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED = 21046;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED_LEN = 21047;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_LEFT = 21048;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_BIG_STEP_RIGHT = 21049;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_MATCH_STEP_RIGHT = 21050;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_JUMP_BACK_RIGHT = 21051;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_RIGHT = 21052;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_1_01_DONE = 21053;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_BIT_CENTERED = 21054;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_BIT_CENTERED_LEN = 21055;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_SMALL_STEP_LEFT = 21056;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_BIG_STEP_RIGHT = 21057;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_MATCH_STEP_RIGHT = 21058;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_JUMP_BACK_RIGHT = 21059;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_SMALL_STEP_RIGHT = 21060;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_0_01_DONE = 21061;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_BIT_CENTERED = 21062;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_BIT_CENTERED_LEN = 21063;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_SMALL_STEP_LEFT = 21064;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_BIG_STEP_RIGHT = 21065;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_MATCH_STEP_RIGHT = 21066;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_JUMP_BACK_RIGHT = 21067;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_SMALL_STEP_RIGHT = 21068;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_1_01_DONE = 21069;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED = 21070;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED_LEN = 21071;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_LEFT = 21072;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_BIG_STEP_RIGHT = 21073;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_MATCH_STEP_RIGHT = 21074;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_JUMP_BACK_RIGHT = 21075;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_RIGHT = 21076;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_2_23_DONE = 21077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED = 21078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED_LEN = 21079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_LEFT = 21080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_BIG_STEP_RIGHT = 21081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_MATCH_STEP_RIGHT = 21082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_JUMP_BACK_RIGHT = 21083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_RIGHT = 21084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_3_23_DONE = 21085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_BIT_CENTERED = 21086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_BIT_CENTERED_LEN = 21087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_SMALL_STEP_LEFT = 21088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_BIG_STEP_RIGHT = 21089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_MATCH_STEP_RIGHT = 21090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_JUMP_BACK_RIGHT = 21091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_SMALL_STEP_RIGHT = 21092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_2_23_DONE = 21093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_BIT_CENTERED = 21094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_BIT_CENTERED_LEN = 21095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_SMALL_STEP_LEFT = 21096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_BIG_STEP_RIGHT = 21097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_MATCH_STEP_RIGHT = 21098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_JUMP_BACK_RIGHT = 21099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_SMALL_STEP_RIGHT = 21100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_3_23_DONE = 21101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_BIT_CENTERED = 21102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_BIT_CENTERED_LEN = 21103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_SMALL_STEP_LEFT = 21104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_BIG_STEP_RIGHT = 21105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_MATCH_STEP_RIGHT = 21106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_JUMP_BACK_RIGHT = 21107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_SMALL_STEP_RIGHT = 21108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P0_4_DONE = 21109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_BIT_CENTERED = 21110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_BIT_CENTERED_LEN = 21111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_SMALL_STEP_LEFT = 21112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_BIG_STEP_RIGHT = 21113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_MATCH_STEP_RIGHT = 21114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_JUMP_BACK_RIGHT = 21115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_SMALL_STEP_RIGHT = 21116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS0_P1_4_DONE = 21117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE = 21118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE_LEN = 21119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE = 21120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE_LEN = 21121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_0_01_FW_LEFT_SIDE = 21122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_0_01_FW_LEFT_SIDE_LEN = 21123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_1_01_FW_LEFT_SIDE = 21124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_1_01_FW_LEFT_SIDE_LEN = 21125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE = 21126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE_LEN = 21127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE = 21128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE_LEN = 21129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_2_23_FW_LEFT_SIDE = 21130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_2_23_FW_LEFT_SIDE_LEN = 21131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_3_23_FW_LEFT_SIDE = 21132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_3_23_FW_LEFT_SIDE_LEN = 21133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_4_FW_LEFT_SIDE = 21134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P0_4_FW_LEFT_SIDE_LEN = 21135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_4_FW_LEFT_SIDE = 21136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS1_P1_4_FW_LEFT_SIDE_LEN = 21137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE = 21138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE_LEN = 21139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE = 21140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE_LEN = 21141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_0_01_FW_RIGHT_SIDE = 21142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_0_01_FW_RIGHT_SIDE_LEN = 21143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_1_01_FW_RIGHT_SIDE = 21144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_1_01_FW_RIGHT_SIDE_LEN = 21145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE = 21146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE_LEN = 21147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE = 21148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE_LEN = 21149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_2_23_FW_RIGHT_SIDE = 21150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_2_23_FW_RIGHT_SIDE_LEN = 21151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_3_23_FW_RIGHT_SIDE = 21152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_3_23_FW_RIGHT_SIDE_LEN = 21153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_4_FW_RIGHT_SIDE = 21154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P0_4_FW_RIGHT_SIDE_LEN = 21155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_4_FW_RIGHT_SIDE = 21156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_CNTR_STATUS2_P1_4_FW_RIGHT_SIDE_LEN = 21157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_WL_ERR_CLK16 = 21158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_WL_ERR_CLK18 = 21159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_WL_ERR_CLK20 = 21160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_WL_ERR_CLK22 = 21161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_VALID_NS_BIG_L = 21162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_L = 21163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_VALID_NS_BIG_R = 21164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_INVALID_NS_BIG_R = 21165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_VALID_NS_JUMP_BACK = 21166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_R = 21167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_0_01_OFFSET_ERR = 21168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_WL_ERR_CLK16 = 21169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_WL_ERR_CLK18 = 21170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_WL_ERR_CLK20 = 21171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_WL_ERR_CLK22 = 21172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_VALID_NS_BIG_L = 21173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_L = 21174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_VALID_NS_BIG_R = 21175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_INVALID_NS_BIG_R = 21176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_VALID_NS_JUMP_BACK = 21177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_R = 21178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_1_01_OFFSET_ERR = 21179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_WL_ERR_CLK16 = 21180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_WL_ERR_CLK18 = 21181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_WL_ERR_CLK20 = 21182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_WL_ERR_CLK22 = 21183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_VALID_NS_BIG_L = 21184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_INVALID_NS_SMALL_L = 21185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_VALID_NS_BIG_R = 21186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_INVALID_NS_BIG_R = 21187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_VALID_NS_JUMP_BACK = 21188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_INVALID_NS_SMALL_R = 21189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_0_01_OFFSET_ERR = 21190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_WL_ERR_CLK16 = 21191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_WL_ERR_CLK18 = 21192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_WL_ERR_CLK20 = 21193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_WL_ERR_CLK22 = 21194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_VALID_NS_BIG_L = 21195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_INVALID_NS_SMALL_L = 21196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_VALID_NS_BIG_R = 21197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_INVALID_NS_BIG_R = 21198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_VALID_NS_JUMP_BACK = 21199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_INVALID_NS_SMALL_R = 21200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_1_01_OFFSET_ERR = 21201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_WL_ERR_CLK16 = 21202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_WL_ERR_CLK18 = 21203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_WL_ERR_CLK20 = 21204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_WL_ERR_CLK22 = 21205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_VALID_NS_BIG_L = 21206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_L = 21207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_VALID_NS_BIG_R = 21208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_INVALID_NS_BIG_R = 21209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_VALID_NS_JUMP_BACK = 21210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_R = 21211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_2_23_OFFSET_ERR = 21212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_WL_ERR_CLK16 = 21213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_WL_ERR_CLK18 = 21214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_WL_ERR_CLK20 = 21215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_WL_ERR_CLK22 = 21216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_VALID_NS_BIG_L = 21217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_L = 21218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_VALID_NS_BIG_R = 21219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_INVALID_NS_BIG_R = 21220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_VALID_NS_JUMP_BACK = 21221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_R = 21222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_3_23_OFFSET_ERR = 21223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_WL_ERR_CLK16 = 21224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_WL_ERR_CLK18 = 21225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_WL_ERR_CLK20 = 21226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_WL_ERR_CLK22 = 21227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_VALID_NS_BIG_L = 21228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_INVALID_NS_SMALL_L = 21229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_VALID_NS_BIG_R = 21230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_INVALID_NS_BIG_R = 21231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_VALID_NS_JUMP_BACK = 21232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_INVALID_NS_SMALL_R = 21233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_2_23_OFFSET_ERR = 21234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_WL_ERR_CLK16 = 21235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_WL_ERR_CLK18 = 21236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_WL_ERR_CLK20 = 21237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_WL_ERR_CLK22 = 21238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_VALID_NS_BIG_L = 21239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_INVALID_NS_SMALL_L = 21240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_VALID_NS_BIG_R = 21241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_INVALID_NS_BIG_R = 21242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_VALID_NS_JUMP_BACK = 21243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_INVALID_NS_SMALL_R = 21244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_3_23_OFFSET_ERR = 21245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_WL_ERR_CLK16 = 21246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_WL_ERR_CLK18 = 21247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_WL_ERR_CLK20 = 21248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_WL_ERR_CLK22 = 21249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_VALID_NS_BIG_L = 21250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_INVALID_NS_SMALL_L = 21251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_VALID_NS_BIG_R = 21252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_INVALID_NS_BIG_R = 21253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_VALID_NS_JUMP_BACK = 21254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_INVALID_NS_SMALL_R = 21255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P0_4_OFFSET_ERR = 21256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_WL_ERR_CLK16 = 21257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_WL_ERR_CLK18 = 21258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_WL_ERR_CLK20 = 21259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_WL_ERR_CLK22 = 21260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_VALID_NS_BIG_L = 21261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_INVALID_NS_SMALL_L = 21262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_VALID_NS_BIG_R = 21263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_INVALID_NS_BIG_R = 21264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_VALID_NS_JUMP_BACK = 21265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_INVALID_NS_SMALL_R = 21266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR0_P1_4_OFFSET_ERR = 21267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK16_MASK = 21268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK18_MASK = 21269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK20_MASK = 21270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_ERR_CLK22_MASK = 21271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_L_MASK = 21272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_L_MASK = 21273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_R_MASK = 21274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_INVALID_NS_BIG_R_MASK = 21275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_VALID_NS_JUMP_BACK_MASK = 21276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_R_MASK = 21277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_OFFSET_ERR_MASK = 21278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_0_01_ADVANCE_PR_VALUE = 21279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK16_MASK = 21280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK18_MASK = 21281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK20_MASK = 21282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_ERR_CLK22_MASK = 21283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_L_MASK = 21284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_L_MASK = 21285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_R_MASK = 21286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_INVALID_NS_BIG_R_MASK = 21287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_VALID_NS_JUMP_BACK_MASK = 21288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_R_MASK = 21289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_OFFSET_ERR_MASK = 21290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_1_01_ADVANCE_PR_VALUE = 21291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_WL_ERR_CLK16_MASK = 21292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_WL_ERR_CLK18_MASK = 21293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_WL_ERR_CLK20_MASK = 21294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_ERR_CLK22_MASK = 21295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_VALID_NS_BIG_L_MASK = 21296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_INVALID_NS_SMALL_L_MASK = 21297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_VALID_NS_BIG_R_MASK = 21298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_INVALID_NS_BIG_R_MASK = 21299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_VALID_NS_JUMP_BACK_MASK = 21300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_INVALID_NS_SMALL_R_MASK = 21301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_OFFSET_ERR_MASK = 21302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_0_01_ADVANCE_PR_VALUE = 21303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_WL_ERR_CLK16_MASK = 21304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_WL_ERR_CLK18_MASK = 21305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_WL_ERR_CLK20_MASK = 21306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_ERR_CLK22_MASK = 21307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_VALID_NS_BIG_L_MASK = 21308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_INVALID_NS_SMALL_L_MASK = 21309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_VALID_NS_BIG_R_MASK = 21310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_INVALID_NS_BIG_R_MASK = 21311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_VALID_NS_JUMP_BACK_MASK = 21312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_INVALID_NS_SMALL_R_MASK = 21313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_OFFSET_ERR_MASK = 21314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_1_01_ADVANCE_PR_VALUE = 21315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK16_MASK = 21316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK18_MASK = 21317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK20_MASK = 21318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_ERR_CLK22_MASK = 21319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_L_MASK = 21320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_L_MASK = 21321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_R_MASK = 21322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_INVALID_NS_BIG_R_MASK = 21323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_VALID_NS_JUMP_BACK_MASK = 21324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_R_MASK = 21325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_OFFSET_ERR_MASK = 21326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_2_23_ADVANCE_PR_VALUE = 21327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK16_MASK = 21328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK18_MASK = 21329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK20_MASK = 21330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_ERR_CLK22_MASK = 21331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_L_MASK = 21332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_L_MASK = 21333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_R_MASK = 21334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_INVALID_NS_BIG_R_MASK = 21335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_VALID_NS_JUMP_BACK_MASK = 21336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_R_MASK = 21337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_OFFSET_ERR_MASK = 21338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_3_23_ADVANCE_PR_VALUE = 21339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_WL_ERR_CLK16_MASK = 21340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_WL_ERR_CLK18_MASK = 21341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_WL_ERR_CLK20_MASK = 21342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_ERR_CLK22_MASK = 21343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_VALID_NS_BIG_L_MASK = 21344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_INVALID_NS_SMALL_L_MASK = 21345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_VALID_NS_BIG_R_MASK = 21346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_INVALID_NS_BIG_R_MASK = 21347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_VALID_NS_JUMP_BACK_MASK = 21348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_INVALID_NS_SMALL_R_MASK = 21349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_OFFSET_ERR_MASK = 21350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_2_23_ADVANCE_PR_VALUE = 21351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_WL_ERR_CLK16_MASK = 21352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_WL_ERR_CLK18_MASK = 21353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_WL_ERR_CLK20_MASK = 21354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_ERR_CLK22_MASK = 21355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_VALID_NS_BIG_L_MASK = 21356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_INVALID_NS_SMALL_L_MASK = 21357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_VALID_NS_BIG_R_MASK = 21358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_INVALID_NS_BIG_R_MASK = 21359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_VALID_NS_JUMP_BACK_MASK = 21360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_INVALID_NS_SMALL_R_MASK = 21361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_OFFSET_ERR_MASK = 21362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_3_23_ADVANCE_PR_VALUE = 21363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_WL_ERR_CLK16_MASK = 21364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_WL_ERR_CLK18_MASK = 21365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_WL_ERR_CLK20_MASK = 21366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_ERR_CLK22_MASK = 21367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_VALID_NS_BIG_L_MASK = 21368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_INVALID_NS_SMALL_L_MASK = 21369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_VALID_NS_BIG_R_MASK = 21370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_INVALID_NS_BIG_R_MASK = 21371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_VALID_NS_JUMP_BACK_MASK = 21372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_INVALID_NS_SMALL_R_MASK = 21373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_OFFSET_ERR_MASK = 21374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P0_4_ADVANCE_PR_VALUE = 21375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_WL_ERR_CLK16_MASK = 21376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_WL_ERR_CLK18_MASK = 21377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_WL_ERR_CLK20_MASK = 21378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_ERR_CLK22_MASK = 21379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_VALID_NS_BIG_L_MASK = 21380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_INVALID_NS_SMALL_L_MASK = 21381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_VALID_NS_BIG_R_MASK = 21382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_INVALID_NS_BIG_R_MASK = 21383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_VALID_NS_JUMP_BACK_MASK = 21384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_INVALID_NS_SMALL_R_MASK = 21385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_OFFSET_ERR_MASK = 21386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_ERROR_MASK0_P1_4_ADVANCE_PR_VALUE = 21387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL = 21388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL_LEN = 21389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_FINE_STEPPING = 21390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_DONE = 21391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK16 = 21392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK18 = 21393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK20 = 21394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK22 = 21395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_0_01_ZERO_DETECTED = 21396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL = 21397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL_LEN = 21398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_FINE_STEPPING = 21399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_DONE = 21400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK16 = 21401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK18 = 21402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK20 = 21403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK22 = 21404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_1_01_ZERO_DETECTED = 21405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_CLK_LEVEL = 21406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_CLK_LEVEL_LEN = 21407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_FINE_STEPPING = 21408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_DONE = 21409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_WL_ERR_CLK16 = 21410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_WL_ERR_CLK18 = 21411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_WL_ERR_CLK20 = 21412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_WL_ERR_CLK22 = 21413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_0_01_ZERO_DETECTED = 21414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_CLK_LEVEL = 21415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_CLK_LEVEL_LEN = 21416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_FINE_STEPPING = 21417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_DONE = 21418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_WL_ERR_CLK16 = 21419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_WL_ERR_CLK18 = 21420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_WL_ERR_CLK20 = 21421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_WL_ERR_CLK22 = 21422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_1_01_ZERO_DETECTED = 21423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL = 21424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL_LEN = 21425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_FINE_STEPPING = 21426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_DONE = 21427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK16 = 21428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK18 = 21429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK20 = 21430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK22 = 21431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_2_23_ZERO_DETECTED = 21432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL = 21433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL_LEN = 21434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_FINE_STEPPING = 21435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_DONE = 21436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK16 = 21437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK18 = 21438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK20 = 21439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK22 = 21440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_3_23_ZERO_DETECTED = 21441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_CLK_LEVEL = 21442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_CLK_LEVEL_LEN = 21443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_FINE_STEPPING = 21444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_DONE = 21445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_WL_ERR_CLK16 = 21446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_WL_ERR_CLK18 = 21447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_WL_ERR_CLK20 = 21448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_WL_ERR_CLK22 = 21449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_2_23_ZERO_DETECTED = 21450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_CLK_LEVEL = 21451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_CLK_LEVEL_LEN = 21452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_FINE_STEPPING = 21453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_DONE = 21454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_WL_ERR_CLK16 = 21455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_WL_ERR_CLK18 = 21456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_WL_ERR_CLK20 = 21457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_WL_ERR_CLK22 = 21458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_3_23_ZERO_DETECTED = 21459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_CLK_LEVEL = 21460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_CLK_LEVEL_LEN = 21461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_FINE_STEPPING = 21462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_DONE = 21463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_WL_ERR_CLK16 = 21464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_WL_ERR_CLK18 = 21465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_WL_ERR_CLK20 = 21466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_WL_ERR_CLK22 = 21467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P0_4_ZERO_DETECTED = 21468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_CLK_LEVEL = 21469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_CLK_LEVEL_LEN = 21470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_FINE_STEPPING = 21471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_DONE = 21472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_WL_ERR_CLK16 = 21473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_WL_ERR_CLK18 = 21474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_WL_ERR_CLK20 = 21475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_WL_ERR_CLK22 = 21476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_WR_LVL_STATUS0_P1_4_ZERO_DETECTED = 21477;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG = 21478;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG_LEN = 21479;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_1_01_DELAYG = 21480;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_1_01_DELAYG_LEN = 21481;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_0_01_DELAYG = 21482;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_0_01_DELAYG_LEN = 21483;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_1_01_DELAYG = 21484;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_1_01_DELAYG_LEN = 21485;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_2_23_DELAYG = 21486;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_2_23_DELAYG_LEN = 21487;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_3_23_DELAYG = 21488;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_3_23_DELAYG_LEN = 21489;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_2_23_DELAYG = 21490;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_2_23_DELAYG_LEN = 21491;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_3_23_DELAYG = 21492;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_3_23_DELAYG_LEN = 21493;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_4_DELAYG = 21494;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_4_DELAYG_LEN = 21495;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_4_DELAYG = 21496;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP0_REG_P1_4_DELAYG_LEN = 21497;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_0_01_DELAYG = 21498;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_0_01_DELAYG_LEN = 21499;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_1_01_DELAYG = 21500;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_1_01_DELAYG_LEN = 21501;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_0_01_DELAYG = 21502;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_0_01_DELAYG_LEN = 21503;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_1_01_DELAYG = 21504;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_1_01_DELAYG_LEN = 21505;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_2_23_DELAYG = 21506;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_2_23_DELAYG_LEN = 21507;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_3_23_DELAYG = 21508;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_3_23_DELAYG_LEN = 21509;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_2_23_DELAYG = 21510;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_2_23_DELAYG_LEN = 21511;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_3_23_DELAYG = 21512;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_3_23_DELAYG_LEN = 21513;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_4_DELAYG = 21514;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P0_4_DELAYG_LEN = 21515;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_4_DELAYG = 21516;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP1_REG_P1_4_DELAYG_LEN = 21517;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_0_01_DELAYG = 21518;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_0_01_DELAYG_LEN = 21519;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_1_01_DELAYG = 21520;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_1_01_DELAYG_LEN = 21521;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_0_01_DELAYG = 21522;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_0_01_DELAYG_LEN = 21523;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_1_01_DELAYG = 21524;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_1_01_DELAYG_LEN = 21525;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_2_23_DELAYG = 21526;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_2_23_DELAYG_LEN = 21527;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_3_23_DELAYG = 21528;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_3_23_DELAYG_LEN = 21529;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_2_23_DELAYG = 21530;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_2_23_DELAYG_LEN = 21531;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_3_23_DELAYG = 21532;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_3_23_DELAYG_LEN = 21533;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_4_DELAYG = 21534;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P0_4_DELAYG_LEN = 21535;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_4_DELAYG = 21536;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP2_REG_P1_4_DELAYG_LEN = 21537;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_0_01_DELAYG = 21538;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_0_01_DELAYG_LEN = 21539;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_1_01_DELAYG = 21540;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_1_01_DELAYG_LEN = 21541;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_0_01_DELAYG = 21542;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_0_01_DELAYG_LEN = 21543;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_1_01_DELAYG = 21544;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_1_01_DELAYG_LEN = 21545;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_2_23_DELAYG = 21546;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_2_23_DELAYG_LEN = 21547;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_3_23_DELAYG = 21548;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_3_23_DELAYG_LEN = 21549;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_2_23_DELAYG = 21550;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_2_23_DELAYG_LEN = 21551;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_3_23_DELAYG = 21552;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_3_23_DELAYG_LEN = 21553;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_4_DELAYG = 21554;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P0_4_DELAYG_LEN = 21555;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_4_DELAYG = 21556;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_0_RP3_REG_P1_4_DELAYG_LEN = 21557;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_0_01_DELAYG = 21558;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_0_01_DELAYG_LEN = 21559;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_1_01_DELAYG = 21560;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_1_01_DELAYG_LEN = 21561;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_0_01_DELAYG = 21562;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_0_01_DELAYG_LEN = 21563;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_1_01_DELAYG = 21564;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_1_01_DELAYG_LEN = 21565;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_2_23_DELAYG = 21566;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_2_23_DELAYG_LEN = 21567;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_3_23_DELAYG = 21568;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_3_23_DELAYG_LEN = 21569;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_2_23_DELAYG = 21570;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_2_23_DELAYG_LEN = 21571;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_3_23_DELAYG = 21572;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_3_23_DELAYG_LEN = 21573;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_4_DELAYG = 21574;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P0_4_DELAYG_LEN = 21575;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_4_DELAYG = 21576;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP0_REG_P1_4_DELAYG_LEN = 21577;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_0_01_DELAYG = 21578;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_0_01_DELAYG_LEN = 21579;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_1_01_DELAYG = 21580;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_1_01_DELAYG_LEN = 21581;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_0_01_DELAYG = 21582;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_0_01_DELAYG_LEN = 21583;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_1_01_DELAYG = 21584;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_1_01_DELAYG_LEN = 21585;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_2_23_DELAYG = 21586;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_2_23_DELAYG_LEN = 21587;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_3_23_DELAYG = 21588;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_3_23_DELAYG_LEN = 21589;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_2_23_DELAYG = 21590;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_2_23_DELAYG_LEN = 21591;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_3_23_DELAYG = 21592;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_3_23_DELAYG_LEN = 21593;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_4_DELAYG = 21594;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P0_4_DELAYG_LEN = 21595;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_4_DELAYG = 21596;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP1_REG_P1_4_DELAYG_LEN = 21597;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_0_01_DELAYG = 21598;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_0_01_DELAYG_LEN = 21599;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_1_01_DELAYG = 21600;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_1_01_DELAYG_LEN = 21601;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_0_01_DELAYG = 21602;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_0_01_DELAYG_LEN = 21603;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_1_01_DELAYG = 21604;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_1_01_DELAYG_LEN = 21605;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_2_23_DELAYG = 21606;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_2_23_DELAYG_LEN = 21607;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_3_23_DELAYG = 21608;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_3_23_DELAYG_LEN = 21609;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_2_23_DELAYG = 21610;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_2_23_DELAYG_LEN = 21611;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_3_23_DELAYG = 21612;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_3_23_DELAYG_LEN = 21613;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_4_DELAYG = 21614;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P0_4_DELAYG_LEN = 21615;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_4_DELAYG = 21616;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP2_REG_P1_4_DELAYG_LEN = 21617;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_0_01_DELAYG = 21618;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_0_01_DELAYG_LEN = 21619;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_1_01_DELAYG = 21620;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_1_01_DELAYG_LEN = 21621;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_0_01_DELAYG = 21622;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_0_01_DELAYG_LEN = 21623;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_1_01_DELAYG = 21624;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_1_01_DELAYG_LEN = 21625;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_2_23_DELAYG = 21626;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_2_23_DELAYG_LEN = 21627;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_3_23_DELAYG = 21628;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_3_23_DELAYG_LEN = 21629;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_2_23_DELAYG = 21630;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_2_23_DELAYG_LEN = 21631;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_3_23_DELAYG = 21632;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_3_23_DELAYG_LEN = 21633;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_4_DELAYG = 21634;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P0_4_DELAYG_LEN = 21635;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_4_DELAYG = 21636;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_10_RP3_REG_P1_4_DELAYG_LEN = 21637;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_0_01_DELAYG = 21638;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_0_01_DELAYG_LEN = 21639;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_1_01_DELAYG = 21640;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_1_01_DELAYG_LEN = 21641;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_0_01_DELAYG = 21642;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_0_01_DELAYG_LEN = 21643;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_1_01_DELAYG = 21644;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_1_01_DELAYG_LEN = 21645;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_2_23_DELAYG = 21646;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_2_23_DELAYG_LEN = 21647;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_3_23_DELAYG = 21648;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_3_23_DELAYG_LEN = 21649;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_2_23_DELAYG = 21650;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_2_23_DELAYG_LEN = 21651;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_3_23_DELAYG = 21652;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_3_23_DELAYG_LEN = 21653;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_4_DELAYG = 21654;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P0_4_DELAYG_LEN = 21655;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_4_DELAYG = 21656;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP0_REG_P1_4_DELAYG_LEN = 21657;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_0_01_DELAYG = 21658;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_0_01_DELAYG_LEN = 21659;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_1_01_DELAYG = 21660;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_1_01_DELAYG_LEN = 21661;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_0_01_DELAYG = 21662;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_0_01_DELAYG_LEN = 21663;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_1_01_DELAYG = 21664;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_1_01_DELAYG_LEN = 21665;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_2_23_DELAYG = 21666;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_2_23_DELAYG_LEN = 21667;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_3_23_DELAYG = 21668;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_3_23_DELAYG_LEN = 21669;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_2_23_DELAYG = 21670;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_2_23_DELAYG_LEN = 21671;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_3_23_DELAYG = 21672;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_3_23_DELAYG_LEN = 21673;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_4_DELAYG = 21674;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P0_4_DELAYG_LEN = 21675;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_4_DELAYG = 21676;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP1_REG_P1_4_DELAYG_LEN = 21677;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_0_01_DELAYG = 21678;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_0_01_DELAYG_LEN = 21679;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_1_01_DELAYG = 21680;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_1_01_DELAYG_LEN = 21681;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_0_01_DELAYG = 21682;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_0_01_DELAYG_LEN = 21683;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_1_01_DELAYG = 21684;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_1_01_DELAYG_LEN = 21685;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_2_23_DELAYG = 21686;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_2_23_DELAYG_LEN = 21687;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_3_23_DELAYG = 21688;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_3_23_DELAYG_LEN = 21689;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_2_23_DELAYG = 21690;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_2_23_DELAYG_LEN = 21691;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_3_23_DELAYG = 21692;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_3_23_DELAYG_LEN = 21693;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_4_DELAYG = 21694;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P0_4_DELAYG_LEN = 21695;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_4_DELAYG = 21696;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP2_REG_P1_4_DELAYG_LEN = 21697;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_0_01_DELAYG = 21698;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_0_01_DELAYG_LEN = 21699;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_1_01_DELAYG = 21700;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_1_01_DELAYG_LEN = 21701;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_0_01_DELAYG = 21702;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_0_01_DELAYG_LEN = 21703;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_1_01_DELAYG = 21704;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_1_01_DELAYG_LEN = 21705;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_2_23_DELAYG = 21706;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_2_23_DELAYG_LEN = 21707;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_3_23_DELAYG = 21708;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_3_23_DELAYG_LEN = 21709;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_2_23_DELAYG = 21710;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_2_23_DELAYG_LEN = 21711;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_3_23_DELAYG = 21712;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_3_23_DELAYG_LEN = 21713;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_4_DELAYG = 21714;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P0_4_DELAYG_LEN = 21715;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_4_DELAYG = 21716;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_11_RP3_REG_P1_4_DELAYG_LEN = 21717;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_0_01_DELAYG = 21718;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_0_01_DELAYG_LEN = 21719;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_1_01_DELAYG = 21720;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_1_01_DELAYG_LEN = 21721;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_0_01_DELAYG = 21722;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_0_01_DELAYG_LEN = 21723;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_1_01_DELAYG = 21724;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_1_01_DELAYG_LEN = 21725;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_2_23_DELAYG = 21726;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_2_23_DELAYG_LEN = 21727;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_3_23_DELAYG = 21728;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_3_23_DELAYG_LEN = 21729;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_2_23_DELAYG = 21730;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_2_23_DELAYG_LEN = 21731;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_3_23_DELAYG = 21732;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_3_23_DELAYG_LEN = 21733;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_4_DELAYG = 21734;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P0_4_DELAYG_LEN = 21735;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_4_DELAYG = 21736;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP0_REG_P1_4_DELAYG_LEN = 21737;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_0_01_DELAYG = 21738;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_0_01_DELAYG_LEN = 21739;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_1_01_DELAYG = 21740;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_1_01_DELAYG_LEN = 21741;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_0_01_DELAYG = 21742;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_0_01_DELAYG_LEN = 21743;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_1_01_DELAYG = 21744;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_1_01_DELAYG_LEN = 21745;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_2_23_DELAYG = 21746;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_2_23_DELAYG_LEN = 21747;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_3_23_DELAYG = 21748;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_3_23_DELAYG_LEN = 21749;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_2_23_DELAYG = 21750;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_2_23_DELAYG_LEN = 21751;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_3_23_DELAYG = 21752;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_3_23_DELAYG_LEN = 21753;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_4_DELAYG = 21754;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P0_4_DELAYG_LEN = 21755;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_4_DELAYG = 21756;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP1_REG_P1_4_DELAYG_LEN = 21757;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_0_01_DELAYG = 21758;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_0_01_DELAYG_LEN = 21759;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_1_01_DELAYG = 21760;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_1_01_DELAYG_LEN = 21761;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_0_01_DELAYG = 21762;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_0_01_DELAYG_LEN = 21763;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_1_01_DELAYG = 21764;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_1_01_DELAYG_LEN = 21765;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_2_23_DELAYG = 21766;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_2_23_DELAYG_LEN = 21767;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_3_23_DELAYG = 21768;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_3_23_DELAYG_LEN = 21769;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_2_23_DELAYG = 21770;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_2_23_DELAYG_LEN = 21771;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_3_23_DELAYG = 21772;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_3_23_DELAYG_LEN = 21773;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_4_DELAYG = 21774;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P0_4_DELAYG_LEN = 21775;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_4_DELAYG = 21776;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP2_REG_P1_4_DELAYG_LEN = 21777;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_0_01_DELAYG = 21778;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_0_01_DELAYG_LEN = 21779;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_1_01_DELAYG = 21780;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_1_01_DELAYG_LEN = 21781;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_0_01_DELAYG = 21782;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_0_01_DELAYG_LEN = 21783;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_1_01_DELAYG = 21784;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_1_01_DELAYG_LEN = 21785;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_2_23_DELAYG = 21786;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_2_23_DELAYG_LEN = 21787;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_3_23_DELAYG = 21788;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_3_23_DELAYG_LEN = 21789;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_2_23_DELAYG = 21790;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_2_23_DELAYG_LEN = 21791;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_3_23_DELAYG = 21792;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_3_23_DELAYG_LEN = 21793;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_4_DELAYG = 21794;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P0_4_DELAYG_LEN = 21795;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_4_DELAYG = 21796;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_12_RP3_REG_P1_4_DELAYG_LEN = 21797;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_0_01_DELAYG = 21798;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_0_01_DELAYG_LEN = 21799;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_1_01_DELAYG = 21800;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_1_01_DELAYG_LEN = 21801;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_0_01_DELAYG = 21802;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_0_01_DELAYG_LEN = 21803;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_1_01_DELAYG = 21804;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_1_01_DELAYG_LEN = 21805;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_2_23_DELAYG = 21806;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_2_23_DELAYG_LEN = 21807;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_3_23_DELAYG = 21808;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_3_23_DELAYG_LEN = 21809;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_2_23_DELAYG = 21810;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_2_23_DELAYG_LEN = 21811;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_3_23_DELAYG = 21812;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_3_23_DELAYG_LEN = 21813;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_4_DELAYG = 21814;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P0_4_DELAYG_LEN = 21815;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_4_DELAYG = 21816;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP0_REG_P1_4_DELAYG_LEN = 21817;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_0_01_DELAYG = 21818;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_0_01_DELAYG_LEN = 21819;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_1_01_DELAYG = 21820;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_1_01_DELAYG_LEN = 21821;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_0_01_DELAYG = 21822;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_0_01_DELAYG_LEN = 21823;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_1_01_DELAYG = 21824;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_1_01_DELAYG_LEN = 21825;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_2_23_DELAYG = 21826;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_2_23_DELAYG_LEN = 21827;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_3_23_DELAYG = 21828;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_3_23_DELAYG_LEN = 21829;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_2_23_DELAYG = 21830;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_2_23_DELAYG_LEN = 21831;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_3_23_DELAYG = 21832;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_3_23_DELAYG_LEN = 21833;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_4_DELAYG = 21834;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P0_4_DELAYG_LEN = 21835;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_4_DELAYG = 21836;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP1_REG_P1_4_DELAYG_LEN = 21837;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_0_01_DELAYG = 21838;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_0_01_DELAYG_LEN = 21839;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_1_01_DELAYG = 21840;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_1_01_DELAYG_LEN = 21841;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_0_01_DELAYG = 21842;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_0_01_DELAYG_LEN = 21843;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_1_01_DELAYG = 21844;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_1_01_DELAYG_LEN = 21845;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_2_23_DELAYG = 21846;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_2_23_DELAYG_LEN = 21847;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_3_23_DELAYG = 21848;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_3_23_DELAYG_LEN = 21849;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_2_23_DELAYG = 21850;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_2_23_DELAYG_LEN = 21851;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_3_23_DELAYG = 21852;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_3_23_DELAYG_LEN = 21853;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_4_DELAYG = 21854;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P0_4_DELAYG_LEN = 21855;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_4_DELAYG = 21856;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP2_REG_P1_4_DELAYG_LEN = 21857;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_0_01_DELAYG = 21858;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_0_01_DELAYG_LEN = 21859;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_1_01_DELAYG = 21860;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_1_01_DELAYG_LEN = 21861;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_0_01_DELAYG = 21862;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_0_01_DELAYG_LEN = 21863;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_1_01_DELAYG = 21864;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_1_01_DELAYG_LEN = 21865;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_2_23_DELAYG = 21866;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_2_23_DELAYG_LEN = 21867;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_3_23_DELAYG = 21868;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_3_23_DELAYG_LEN = 21869;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_2_23_DELAYG = 21870;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_2_23_DELAYG_LEN = 21871;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_3_23_DELAYG = 21872;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_3_23_DELAYG_LEN = 21873;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_4_DELAYG = 21874;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P0_4_DELAYG_LEN = 21875;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_4_DELAYG = 21876;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_13_RP3_REG_P1_4_DELAYG_LEN = 21877;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_0_01_DELAYG = 21878;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_0_01_DELAYG_LEN = 21879;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_1_01_DELAYG = 21880;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_1_01_DELAYG_LEN = 21881;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_0_01_DELAYG = 21882;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_0_01_DELAYG_LEN = 21883;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_1_01_DELAYG = 21884;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_1_01_DELAYG_LEN = 21885;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_2_23_DELAYG = 21886;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_2_23_DELAYG_LEN = 21887;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_3_23_DELAYG = 21888;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_3_23_DELAYG_LEN = 21889;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_2_23_DELAYG = 21890;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_2_23_DELAYG_LEN = 21891;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_3_23_DELAYG = 21892;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_3_23_DELAYG_LEN = 21893;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_4_DELAYG = 21894;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P0_4_DELAYG_LEN = 21895;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_4_DELAYG = 21896;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP0_REG_P1_4_DELAYG_LEN = 21897;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_0_01_DELAYG = 21898;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_0_01_DELAYG_LEN = 21899;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_1_01_DELAYG = 21900;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_1_01_DELAYG_LEN = 21901;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_0_01_DELAYG = 21902;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_0_01_DELAYG_LEN = 21903;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_1_01_DELAYG = 21904;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_1_01_DELAYG_LEN = 21905;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_2_23_DELAYG = 21906;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_2_23_DELAYG_LEN = 21907;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_3_23_DELAYG = 21908;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_3_23_DELAYG_LEN = 21909;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_2_23_DELAYG = 21910;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_2_23_DELAYG_LEN = 21911;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_3_23_DELAYG = 21912;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_3_23_DELAYG_LEN = 21913;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_4_DELAYG = 21914;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P0_4_DELAYG_LEN = 21915;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_4_DELAYG = 21916;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP1_REG_P1_4_DELAYG_LEN = 21917;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_0_01_DELAYG = 21918;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_0_01_DELAYG_LEN = 21919;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_1_01_DELAYG = 21920;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_1_01_DELAYG_LEN = 21921;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_0_01_DELAYG = 21922;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_0_01_DELAYG_LEN = 21923;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_1_01_DELAYG = 21924;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_1_01_DELAYG_LEN = 21925;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_2_23_DELAYG = 21926;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_2_23_DELAYG_LEN = 21927;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_3_23_DELAYG = 21928;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_3_23_DELAYG_LEN = 21929;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_2_23_DELAYG = 21930;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_2_23_DELAYG_LEN = 21931;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_3_23_DELAYG = 21932;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_3_23_DELAYG_LEN = 21933;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_4_DELAYG = 21934;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P0_4_DELAYG_LEN = 21935;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_4_DELAYG = 21936;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP2_REG_P1_4_DELAYG_LEN = 21937;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_0_01_DELAYG = 21938;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_0_01_DELAYG_LEN = 21939;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_1_01_DELAYG = 21940;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_1_01_DELAYG_LEN = 21941;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_0_01_DELAYG = 21942;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_0_01_DELAYG_LEN = 21943;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_1_01_DELAYG = 21944;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_1_01_DELAYG_LEN = 21945;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_2_23_DELAYG = 21946;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_2_23_DELAYG_LEN = 21947;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_3_23_DELAYG = 21948;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_3_23_DELAYG_LEN = 21949;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_2_23_DELAYG = 21950;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_2_23_DELAYG_LEN = 21951;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_3_23_DELAYG = 21952;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_3_23_DELAYG_LEN = 21953;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_4_DELAYG = 21954;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P0_4_DELAYG_LEN = 21955;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_4_DELAYG = 21956;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_14_RP3_REG_P1_4_DELAYG_LEN = 21957;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_0_01_DELAYG = 21958;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_0_01_DELAYG_LEN = 21959;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_1_01_DELAYG = 21960;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_1_01_DELAYG_LEN = 21961;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_0_01_DELAYG = 21962;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_0_01_DELAYG_LEN = 21963;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_1_01_DELAYG = 21964;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_1_01_DELAYG_LEN = 21965;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_2_23_DELAYG = 21966;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_2_23_DELAYG_LEN = 21967;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_3_23_DELAYG = 21968;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_3_23_DELAYG_LEN = 21969;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_2_23_DELAYG = 21970;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_2_23_DELAYG_LEN = 21971;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_3_23_DELAYG = 21972;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_3_23_DELAYG_LEN = 21973;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_4_DELAYG = 21974;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P0_4_DELAYG_LEN = 21975;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_4_DELAYG = 21976;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP0_REG_P1_4_DELAYG_LEN = 21977;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_0_01_DELAYG = 21978;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_0_01_DELAYG_LEN = 21979;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_1_01_DELAYG = 21980;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_1_01_DELAYG_LEN = 21981;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_0_01_DELAYG = 21982;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_0_01_DELAYG_LEN = 21983;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_1_01_DELAYG = 21984;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_1_01_DELAYG_LEN = 21985;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_2_23_DELAYG = 21986;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_2_23_DELAYG_LEN = 21987;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_3_23_DELAYG = 21988;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_3_23_DELAYG_LEN = 21989;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_2_23_DELAYG = 21990;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_2_23_DELAYG_LEN = 21991;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_3_23_DELAYG = 21992;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_3_23_DELAYG_LEN = 21993;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_4_DELAYG = 21994;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P0_4_DELAYG_LEN = 21995;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_4_DELAYG = 21996;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP1_REG_P1_4_DELAYG_LEN = 21997;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_0_01_DELAYG = 21998;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_0_01_DELAYG_LEN = 21999;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_1_01_DELAYG = 22000;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_1_01_DELAYG_LEN = 22001;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_0_01_DELAYG = 22002;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_0_01_DELAYG_LEN = 22003;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_1_01_DELAYG = 22004;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_1_01_DELAYG_LEN = 22005;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_2_23_DELAYG = 22006;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_2_23_DELAYG_LEN = 22007;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_3_23_DELAYG = 22008;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_3_23_DELAYG_LEN = 22009;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_2_23_DELAYG = 22010;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_2_23_DELAYG_LEN = 22011;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_3_23_DELAYG = 22012;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_3_23_DELAYG_LEN = 22013;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_4_DELAYG = 22014;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P0_4_DELAYG_LEN = 22015;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_4_DELAYG = 22016;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP2_REG_P1_4_DELAYG_LEN = 22017;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_0_01_DELAYG = 22018;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_0_01_DELAYG_LEN = 22019;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_1_01_DELAYG = 22020;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_1_01_DELAYG_LEN = 22021;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_0_01_DELAYG = 22022;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_0_01_DELAYG_LEN = 22023;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_1_01_DELAYG = 22024;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_1_01_DELAYG_LEN = 22025;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_2_23_DELAYG = 22026;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_2_23_DELAYG_LEN = 22027;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_3_23_DELAYG = 22028;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_3_23_DELAYG_LEN = 22029;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_2_23_DELAYG = 22030;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_2_23_DELAYG_LEN = 22031;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_3_23_DELAYG = 22032;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_3_23_DELAYG_LEN = 22033;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_4_DELAYG = 22034;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P0_4_DELAYG_LEN = 22035;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_4_DELAYG = 22036;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_15_RP3_REG_P1_4_DELAYG_LEN = 22037;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_0_01_DELAYG = 22038;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_0_01_DELAYG_LEN = 22039;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_1_01_DELAYG = 22040;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_1_01_DELAYG_LEN = 22041;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_0_01_DELAYG = 22042;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_0_01_DELAYG_LEN = 22043;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_1_01_DELAYG = 22044;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_1_01_DELAYG_LEN = 22045;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_2_23_DELAYG = 22046;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_2_23_DELAYG_LEN = 22047;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_3_23_DELAYG = 22048;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_3_23_DELAYG_LEN = 22049;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_2_23_DELAYG = 22050;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_2_23_DELAYG_LEN = 22051;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_3_23_DELAYG = 22052;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_3_23_DELAYG_LEN = 22053;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_4_DELAYG = 22054;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P0_4_DELAYG_LEN = 22055;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_4_DELAYG = 22056;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP0_REG_P1_4_DELAYG_LEN = 22057;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_0_01_DELAYG = 22058;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_0_01_DELAYG_LEN = 22059;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_1_01_DELAYG = 22060;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_1_01_DELAYG_LEN = 22061;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_0_01_DELAYG = 22062;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_0_01_DELAYG_LEN = 22063;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_1_01_DELAYG = 22064;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_1_01_DELAYG_LEN = 22065;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_2_23_DELAYG = 22066;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_2_23_DELAYG_LEN = 22067;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_3_23_DELAYG = 22068;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_3_23_DELAYG_LEN = 22069;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_2_23_DELAYG = 22070;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_2_23_DELAYG_LEN = 22071;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_3_23_DELAYG = 22072;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_3_23_DELAYG_LEN = 22073;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_4_DELAYG = 22074;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P0_4_DELAYG_LEN = 22075;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_4_DELAYG = 22076;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP1_REG_P1_4_DELAYG_LEN = 22077;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_0_01_DELAYG = 22078;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_0_01_DELAYG_LEN = 22079;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_1_01_DELAYG = 22080;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_1_01_DELAYG_LEN = 22081;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_0_01_DELAYG = 22082;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_0_01_DELAYG_LEN = 22083;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_1_01_DELAYG = 22084;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_1_01_DELAYG_LEN = 22085;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_2_23_DELAYG = 22086;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_2_23_DELAYG_LEN = 22087;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_3_23_DELAYG = 22088;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_3_23_DELAYG_LEN = 22089;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_2_23_DELAYG = 22090;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_2_23_DELAYG_LEN = 22091;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_3_23_DELAYG = 22092;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_3_23_DELAYG_LEN = 22093;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_4_DELAYG = 22094;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P0_4_DELAYG_LEN = 22095;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_4_DELAYG = 22096;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP2_REG_P1_4_DELAYG_LEN = 22097;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_0_01_DELAYG = 22098;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_0_01_DELAYG_LEN = 22099;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_1_01_DELAYG = 22100;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_1_01_DELAYG_LEN = 22101;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_0_01_DELAYG = 22102;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_0_01_DELAYG_LEN = 22103;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_1_01_DELAYG = 22104;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_1_01_DELAYG_LEN = 22105;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_2_23_DELAYG = 22106;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_2_23_DELAYG_LEN = 22107;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_3_23_DELAYG = 22108;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_3_23_DELAYG_LEN = 22109;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_2_23_DELAYG = 22110;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_2_23_DELAYG_LEN = 22111;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_3_23_DELAYG = 22112;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_3_23_DELAYG_LEN = 22113;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_4_DELAYG = 22114;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P0_4_DELAYG_LEN = 22115;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_4_DELAYG = 22116;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_16_RP3_REG_P1_4_DELAYG_LEN = 22117;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_0_01_DELAYG = 22118;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_0_01_DELAYG_LEN = 22119;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_1_01_DELAYG = 22120;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_1_01_DELAYG_LEN = 22121;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_0_01_DELAYG = 22122;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_0_01_DELAYG_LEN = 22123;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_1_01_DELAYG = 22124;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_1_01_DELAYG_LEN = 22125;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_2_23_DELAYG = 22126;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_2_23_DELAYG_LEN = 22127;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_3_23_DELAYG = 22128;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_3_23_DELAYG_LEN = 22129;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_2_23_DELAYG = 22130;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_2_23_DELAYG_LEN = 22131;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_3_23_DELAYG = 22132;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_3_23_DELAYG_LEN = 22133;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_4_DELAYG = 22134;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P0_4_DELAYG_LEN = 22135;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_4_DELAYG = 22136;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP0_REG_P1_4_DELAYG_LEN = 22137;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_0_01_DELAYG = 22138;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_0_01_DELAYG_LEN = 22139;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_1_01_DELAYG = 22140;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_1_01_DELAYG_LEN = 22141;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_0_01_DELAYG = 22142;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_0_01_DELAYG_LEN = 22143;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_1_01_DELAYG = 22144;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_1_01_DELAYG_LEN = 22145;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_2_23_DELAYG = 22146;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_2_23_DELAYG_LEN = 22147;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_3_23_DELAYG = 22148;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_3_23_DELAYG_LEN = 22149;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_2_23_DELAYG = 22150;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_2_23_DELAYG_LEN = 22151;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_3_23_DELAYG = 22152;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_3_23_DELAYG_LEN = 22153;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_4_DELAYG = 22154;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P0_4_DELAYG_LEN = 22155;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_4_DELAYG = 22156;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP1_REG_P1_4_DELAYG_LEN = 22157;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_0_01_DELAYG = 22158;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_0_01_DELAYG_LEN = 22159;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_1_01_DELAYG = 22160;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_1_01_DELAYG_LEN = 22161;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_0_01_DELAYG = 22162;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_0_01_DELAYG_LEN = 22163;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_1_01_DELAYG = 22164;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_1_01_DELAYG_LEN = 22165;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_2_23_DELAYG = 22166;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_2_23_DELAYG_LEN = 22167;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_3_23_DELAYG = 22168;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_3_23_DELAYG_LEN = 22169;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_2_23_DELAYG = 22170;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_2_23_DELAYG_LEN = 22171;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_3_23_DELAYG = 22172;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_3_23_DELAYG_LEN = 22173;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_4_DELAYG = 22174;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P0_4_DELAYG_LEN = 22175;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_4_DELAYG = 22176;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP2_REG_P1_4_DELAYG_LEN = 22177;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_0_01_DELAYG = 22178;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_0_01_DELAYG_LEN = 22179;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_1_01_DELAYG = 22180;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_1_01_DELAYG_LEN = 22181;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_0_01_DELAYG = 22182;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_0_01_DELAYG_LEN = 22183;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_1_01_DELAYG = 22184;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_1_01_DELAYG_LEN = 22185;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_2_23_DELAYG = 22186;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_2_23_DELAYG_LEN = 22187;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_3_23_DELAYG = 22188;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_3_23_DELAYG_LEN = 22189;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_2_23_DELAYG = 22190;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_2_23_DELAYG_LEN = 22191;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_3_23_DELAYG = 22192;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_3_23_DELAYG_LEN = 22193;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_4_DELAYG = 22194;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P0_4_DELAYG_LEN = 22195;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_4_DELAYG = 22196;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_18_RP3_REG_P1_4_DELAYG_LEN = 22197;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_0_01_DELAYG = 22198;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_0_01_DELAYG_LEN = 22199;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_1_01_DELAYG = 22200;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_1_01_DELAYG_LEN = 22201;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_0_01_DELAYG = 22202;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_0_01_DELAYG_LEN = 22203;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_1_01_DELAYG = 22204;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_1_01_DELAYG_LEN = 22205;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_2_23_DELAYG = 22206;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_2_23_DELAYG_LEN = 22207;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_3_23_DELAYG = 22208;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_3_23_DELAYG_LEN = 22209;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_2_23_DELAYG = 22210;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_2_23_DELAYG_LEN = 22211;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_3_23_DELAYG = 22212;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_3_23_DELAYG_LEN = 22213;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_4_DELAYG = 22214;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P0_4_DELAYG_LEN = 22215;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_4_DELAYG = 22216;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP0_REG_P1_4_DELAYG_LEN = 22217;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_0_01_DELAYG = 22218;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_0_01_DELAYG_LEN = 22219;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_1_01_DELAYG = 22220;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_1_01_DELAYG_LEN = 22221;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_0_01_DELAYG = 22222;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_0_01_DELAYG_LEN = 22223;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_1_01_DELAYG = 22224;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_1_01_DELAYG_LEN = 22225;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_2_23_DELAYG = 22226;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_2_23_DELAYG_LEN = 22227;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_3_23_DELAYG = 22228;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_3_23_DELAYG_LEN = 22229;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_2_23_DELAYG = 22230;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_2_23_DELAYG_LEN = 22231;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_3_23_DELAYG = 22232;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_3_23_DELAYG_LEN = 22233;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_4_DELAYG = 22234;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P0_4_DELAYG_LEN = 22235;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_4_DELAYG = 22236;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP1_REG_P1_4_DELAYG_LEN = 22237;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_0_01_DELAYG = 22238;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_0_01_DELAYG_LEN = 22239;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_1_01_DELAYG = 22240;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_1_01_DELAYG_LEN = 22241;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_0_01_DELAYG = 22242;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_0_01_DELAYG_LEN = 22243;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_1_01_DELAYG = 22244;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_1_01_DELAYG_LEN = 22245;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_2_23_DELAYG = 22246;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_2_23_DELAYG_LEN = 22247;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_3_23_DELAYG = 22248;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_3_23_DELAYG_LEN = 22249;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_2_23_DELAYG = 22250;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_2_23_DELAYG_LEN = 22251;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_3_23_DELAYG = 22252;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_3_23_DELAYG_LEN = 22253;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_4_DELAYG = 22254;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P0_4_DELAYG_LEN = 22255;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_4_DELAYG = 22256;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP2_REG_P1_4_DELAYG_LEN = 22257;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_0_01_DELAYG = 22258;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_0_01_DELAYG_LEN = 22259;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_1_01_DELAYG = 22260;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_1_01_DELAYG_LEN = 22261;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_0_01_DELAYG = 22262;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_0_01_DELAYG_LEN = 22263;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_1_01_DELAYG = 22264;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_1_01_DELAYG_LEN = 22265;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_2_23_DELAYG = 22266;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_2_23_DELAYG_LEN = 22267;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_3_23_DELAYG = 22268;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_3_23_DELAYG_LEN = 22269;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_2_23_DELAYG = 22270;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_2_23_DELAYG_LEN = 22271;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_3_23_DELAYG = 22272;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_3_23_DELAYG_LEN = 22273;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_4_DELAYG = 22274;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P0_4_DELAYG_LEN = 22275;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_4_DELAYG = 22276;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_1_RP3_REG_P1_4_DELAYG_LEN = 22277;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_0_01_DELAYG = 22278;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_0_01_DELAYG_LEN = 22279;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_1_01_DELAYG = 22280;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_1_01_DELAYG_LEN = 22281;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_0_01_DELAYG = 22282;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_0_01_DELAYG_LEN = 22283;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_1_01_DELAYG = 22284;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_1_01_DELAYG_LEN = 22285;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_2_23_DELAYG = 22286;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_2_23_DELAYG_LEN = 22287;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_3_23_DELAYG = 22288;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_3_23_DELAYG_LEN = 22289;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_2_23_DELAYG = 22290;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_2_23_DELAYG_LEN = 22291;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_3_23_DELAYG = 22292;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_3_23_DELAYG_LEN = 22293;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_4_DELAYG = 22294;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P0_4_DELAYG_LEN = 22295;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_4_DELAYG = 22296;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP0_REG_P1_4_DELAYG_LEN = 22297;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_0_01_DELAYG = 22298;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_0_01_DELAYG_LEN = 22299;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_1_01_DELAYG = 22300;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_1_01_DELAYG_LEN = 22301;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_0_01_DELAYG = 22302;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_0_01_DELAYG_LEN = 22303;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_1_01_DELAYG = 22304;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_1_01_DELAYG_LEN = 22305;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_2_23_DELAYG = 22306;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_2_23_DELAYG_LEN = 22307;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_3_23_DELAYG = 22308;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_3_23_DELAYG_LEN = 22309;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_2_23_DELAYG = 22310;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_2_23_DELAYG_LEN = 22311;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_3_23_DELAYG = 22312;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_3_23_DELAYG_LEN = 22313;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_4_DELAYG = 22314;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P0_4_DELAYG_LEN = 22315;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_4_DELAYG = 22316;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP1_REG_P1_4_DELAYG_LEN = 22317;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_0_01_DELAYG = 22318;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_0_01_DELAYG_LEN = 22319;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_1_01_DELAYG = 22320;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_1_01_DELAYG_LEN = 22321;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_0_01_DELAYG = 22322;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_0_01_DELAYG_LEN = 22323;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_1_01_DELAYG = 22324;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_1_01_DELAYG_LEN = 22325;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_2_23_DELAYG = 22326;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_2_23_DELAYG_LEN = 22327;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_3_23_DELAYG = 22328;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_3_23_DELAYG_LEN = 22329;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_2_23_DELAYG = 22330;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_2_23_DELAYG_LEN = 22331;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_3_23_DELAYG = 22332;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_3_23_DELAYG_LEN = 22333;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_4_DELAYG = 22334;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P0_4_DELAYG_LEN = 22335;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_4_DELAYG = 22336;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP2_REG_P1_4_DELAYG_LEN = 22337;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_0_01_DELAYG = 22338;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_0_01_DELAYG_LEN = 22339;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_1_01_DELAYG = 22340;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_1_01_DELAYG_LEN = 22341;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_0_01_DELAYG = 22342;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_0_01_DELAYG_LEN = 22343;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_1_01_DELAYG = 22344;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_1_01_DELAYG_LEN = 22345;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_2_23_DELAYG = 22346;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_2_23_DELAYG_LEN = 22347;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_3_23_DELAYG = 22348;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_3_23_DELAYG_LEN = 22349;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_2_23_DELAYG = 22350;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_2_23_DELAYG_LEN = 22351;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_3_23_DELAYG = 22352;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_3_23_DELAYG_LEN = 22353;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_4_DELAYG = 22354;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P0_4_DELAYG_LEN = 22355;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_4_DELAYG = 22356;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_20_RP3_REG_P1_4_DELAYG_LEN = 22357;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_0_01_DELAYG = 22358;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_0_01_DELAYG_LEN = 22359;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_1_01_DELAYG = 22360;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_1_01_DELAYG_LEN = 22361;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_0_01_DELAYG = 22362;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_0_01_DELAYG_LEN = 22363;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_1_01_DELAYG = 22364;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_1_01_DELAYG_LEN = 22365;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_2_23_DELAYG = 22366;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_2_23_DELAYG_LEN = 22367;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_3_23_DELAYG = 22368;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_3_23_DELAYG_LEN = 22369;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_2_23_DELAYG = 22370;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_2_23_DELAYG_LEN = 22371;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_3_23_DELAYG = 22372;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_3_23_DELAYG_LEN = 22373;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_4_DELAYG = 22374;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P0_4_DELAYG_LEN = 22375;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_4_DELAYG = 22376;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP0_REG_P1_4_DELAYG_LEN = 22377;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_0_01_DELAYG = 22378;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_0_01_DELAYG_LEN = 22379;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_1_01_DELAYG = 22380;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_1_01_DELAYG_LEN = 22381;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_0_01_DELAYG = 22382;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_0_01_DELAYG_LEN = 22383;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_1_01_DELAYG = 22384;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_1_01_DELAYG_LEN = 22385;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_2_23_DELAYG = 22386;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_2_23_DELAYG_LEN = 22387;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_3_23_DELAYG = 22388;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_3_23_DELAYG_LEN = 22389;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_2_23_DELAYG = 22390;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_2_23_DELAYG_LEN = 22391;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_3_23_DELAYG = 22392;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_3_23_DELAYG_LEN = 22393;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_4_DELAYG = 22394;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P0_4_DELAYG_LEN = 22395;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_4_DELAYG = 22396;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP1_REG_P1_4_DELAYG_LEN = 22397;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_0_01_DELAYG = 22398;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_0_01_DELAYG_LEN = 22399;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_1_01_DELAYG = 22400;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_1_01_DELAYG_LEN = 22401;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_0_01_DELAYG = 22402;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_0_01_DELAYG_LEN = 22403;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_1_01_DELAYG = 22404;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_1_01_DELAYG_LEN = 22405;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_2_23_DELAYG = 22406;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_2_23_DELAYG_LEN = 22407;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_3_23_DELAYG = 22408;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_3_23_DELAYG_LEN = 22409;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_2_23_DELAYG = 22410;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_2_23_DELAYG_LEN = 22411;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_3_23_DELAYG = 22412;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_3_23_DELAYG_LEN = 22413;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_4_DELAYG = 22414;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P0_4_DELAYG_LEN = 22415;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_4_DELAYG = 22416;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP2_REG_P1_4_DELAYG_LEN = 22417;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_0_01_DELAYG = 22418;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_0_01_DELAYG_LEN = 22419;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_1_01_DELAYG = 22420;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_1_01_DELAYG_LEN = 22421;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_0_01_DELAYG = 22422;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_0_01_DELAYG_LEN = 22423;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_1_01_DELAYG = 22424;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_1_01_DELAYG_LEN = 22425;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_2_23_DELAYG = 22426;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_2_23_DELAYG_LEN = 22427;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_3_23_DELAYG = 22428;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_3_23_DELAYG_LEN = 22429;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_2_23_DELAYG = 22430;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_2_23_DELAYG_LEN = 22431;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_3_23_DELAYG = 22432;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_3_23_DELAYG_LEN = 22433;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_4_DELAYG = 22434;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P0_4_DELAYG_LEN = 22435;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_4_DELAYG = 22436;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_22_RP3_REG_P1_4_DELAYG_LEN = 22437;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_0_01_DELAYG = 22438;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_0_01_DELAYG_LEN = 22439;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_1_01_DELAYG = 22440;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_1_01_DELAYG_LEN = 22441;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_0_01_DELAYG = 22442;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_0_01_DELAYG_LEN = 22443;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_1_01_DELAYG = 22444;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_1_01_DELAYG_LEN = 22445;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_2_23_DELAYG = 22446;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_2_23_DELAYG_LEN = 22447;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_3_23_DELAYG = 22448;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_3_23_DELAYG_LEN = 22449;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_2_23_DELAYG = 22450;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_2_23_DELAYG_LEN = 22451;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_3_23_DELAYG = 22452;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_3_23_DELAYG_LEN = 22453;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_4_DELAYG = 22454;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P0_4_DELAYG_LEN = 22455;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_4_DELAYG = 22456;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP0_REG_P1_4_DELAYG_LEN = 22457;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_0_01_DELAYG = 22458;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_0_01_DELAYG_LEN = 22459;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_1_01_DELAYG = 22460;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_1_01_DELAYG_LEN = 22461;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_0_01_DELAYG = 22462;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_0_01_DELAYG_LEN = 22463;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_1_01_DELAYG = 22464;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_1_01_DELAYG_LEN = 22465;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_2_23_DELAYG = 22466;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_2_23_DELAYG_LEN = 22467;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_3_23_DELAYG = 22468;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_3_23_DELAYG_LEN = 22469;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_2_23_DELAYG = 22470;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_2_23_DELAYG_LEN = 22471;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_3_23_DELAYG = 22472;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_3_23_DELAYG_LEN = 22473;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_4_DELAYG = 22474;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P0_4_DELAYG_LEN = 22475;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_4_DELAYG = 22476;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP1_REG_P1_4_DELAYG_LEN = 22477;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_0_01_DELAYG = 22478;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_0_01_DELAYG_LEN = 22479;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_1_01_DELAYG = 22480;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_1_01_DELAYG_LEN = 22481;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_0_01_DELAYG = 22482;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_0_01_DELAYG_LEN = 22483;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_1_01_DELAYG = 22484;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_1_01_DELAYG_LEN = 22485;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_2_23_DELAYG = 22486;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_2_23_DELAYG_LEN = 22487;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_3_23_DELAYG = 22488;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_3_23_DELAYG_LEN = 22489;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_2_23_DELAYG = 22490;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_2_23_DELAYG_LEN = 22491;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_3_23_DELAYG = 22492;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_3_23_DELAYG_LEN = 22493;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_4_DELAYG = 22494;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P0_4_DELAYG_LEN = 22495;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_4_DELAYG = 22496;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP2_REG_P1_4_DELAYG_LEN = 22497;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_0_01_DELAYG = 22498;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_0_01_DELAYG_LEN = 22499;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_1_01_DELAYG = 22500;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_1_01_DELAYG_LEN = 22501;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_0_01_DELAYG = 22502;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_0_01_DELAYG_LEN = 22503;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_1_01_DELAYG = 22504;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_1_01_DELAYG_LEN = 22505;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_2_23_DELAYG = 22506;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_2_23_DELAYG_LEN = 22507;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_3_23_DELAYG = 22508;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_3_23_DELAYG_LEN = 22509;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_2_23_DELAYG = 22510;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_2_23_DELAYG_LEN = 22511;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_3_23_DELAYG = 22512;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_3_23_DELAYG_LEN = 22513;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_4_DELAYG = 22514;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P0_4_DELAYG_LEN = 22515;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_4_DELAYG = 22516;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_2_RP3_REG_P1_4_DELAYG_LEN = 22517;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_0_01_DELAYG = 22518;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_0_01_DELAYG_LEN = 22519;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_1_01_DELAYG = 22520;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_1_01_DELAYG_LEN = 22521;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_0_01_DELAYG = 22522;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_0_01_DELAYG_LEN = 22523;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_1_01_DELAYG = 22524;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_1_01_DELAYG_LEN = 22525;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_2_23_DELAYG = 22526;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_2_23_DELAYG_LEN = 22527;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_3_23_DELAYG = 22528;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_3_23_DELAYG_LEN = 22529;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_2_23_DELAYG = 22530;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_2_23_DELAYG_LEN = 22531;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_3_23_DELAYG = 22532;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_3_23_DELAYG_LEN = 22533;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_4_DELAYG = 22534;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P0_4_DELAYG_LEN = 22535;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_4_DELAYG = 22536;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP0_REG_P1_4_DELAYG_LEN = 22537;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_0_01_DELAYG = 22538;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_0_01_DELAYG_LEN = 22539;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_1_01_DELAYG = 22540;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_1_01_DELAYG_LEN = 22541;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_0_01_DELAYG = 22542;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_0_01_DELAYG_LEN = 22543;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_1_01_DELAYG = 22544;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_1_01_DELAYG_LEN = 22545;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_2_23_DELAYG = 22546;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_2_23_DELAYG_LEN = 22547;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_3_23_DELAYG = 22548;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_3_23_DELAYG_LEN = 22549;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_2_23_DELAYG = 22550;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_2_23_DELAYG_LEN = 22551;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_3_23_DELAYG = 22552;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_3_23_DELAYG_LEN = 22553;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_4_DELAYG = 22554;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P0_4_DELAYG_LEN = 22555;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_4_DELAYG = 22556;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP1_REG_P1_4_DELAYG_LEN = 22557;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_0_01_DELAYG = 22558;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_0_01_DELAYG_LEN = 22559;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_1_01_DELAYG = 22560;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_1_01_DELAYG_LEN = 22561;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_0_01_DELAYG = 22562;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_0_01_DELAYG_LEN = 22563;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_1_01_DELAYG = 22564;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_1_01_DELAYG_LEN = 22565;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_2_23_DELAYG = 22566;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_2_23_DELAYG_LEN = 22567;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_3_23_DELAYG = 22568;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_3_23_DELAYG_LEN = 22569;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_2_23_DELAYG = 22570;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_2_23_DELAYG_LEN = 22571;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_3_23_DELAYG = 22572;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_3_23_DELAYG_LEN = 22573;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_4_DELAYG = 22574;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P0_4_DELAYG_LEN = 22575;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_4_DELAYG = 22576;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP2_REG_P1_4_DELAYG_LEN = 22577;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_0_01_DELAYG = 22578;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_0_01_DELAYG_LEN = 22579;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_1_01_DELAYG = 22580;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_1_01_DELAYG_LEN = 22581;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_0_01_DELAYG = 22582;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_0_01_DELAYG_LEN = 22583;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_1_01_DELAYG = 22584;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_1_01_DELAYG_LEN = 22585;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_2_23_DELAYG = 22586;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_2_23_DELAYG_LEN = 22587;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_3_23_DELAYG = 22588;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_3_23_DELAYG_LEN = 22589;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_2_23_DELAYG = 22590;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_2_23_DELAYG_LEN = 22591;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_3_23_DELAYG = 22592;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_3_23_DELAYG_LEN = 22593;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_4_DELAYG = 22594;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P0_4_DELAYG_LEN = 22595;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_4_DELAYG = 22596;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_3_RP3_REG_P1_4_DELAYG_LEN = 22597;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_0_01_DELAYG = 22598;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_0_01_DELAYG_LEN = 22599;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_1_01_DELAYG = 22600;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_1_01_DELAYG_LEN = 22601;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_0_01_DELAYG = 22602;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_0_01_DELAYG_LEN = 22603;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_1_01_DELAYG = 22604;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_1_01_DELAYG_LEN = 22605;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_2_23_DELAYG = 22606;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_2_23_DELAYG_LEN = 22607;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_3_23_DELAYG = 22608;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_3_23_DELAYG_LEN = 22609;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_2_23_DELAYG = 22610;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_2_23_DELAYG_LEN = 22611;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_3_23_DELAYG = 22612;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_3_23_DELAYG_LEN = 22613;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_4_DELAYG = 22614;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P0_4_DELAYG_LEN = 22615;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_4_DELAYG = 22616;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP0_REG_P1_4_DELAYG_LEN = 22617;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_0_01_DELAYG = 22618;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_0_01_DELAYG_LEN = 22619;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_1_01_DELAYG = 22620;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_1_01_DELAYG_LEN = 22621;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_0_01_DELAYG = 22622;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_0_01_DELAYG_LEN = 22623;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_1_01_DELAYG = 22624;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_1_01_DELAYG_LEN = 22625;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_2_23_DELAYG = 22626;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_2_23_DELAYG_LEN = 22627;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_3_23_DELAYG = 22628;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_3_23_DELAYG_LEN = 22629;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_2_23_DELAYG = 22630;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_2_23_DELAYG_LEN = 22631;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_3_23_DELAYG = 22632;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_3_23_DELAYG_LEN = 22633;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_4_DELAYG = 22634;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P0_4_DELAYG_LEN = 22635;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_4_DELAYG = 22636;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP1_REG_P1_4_DELAYG_LEN = 22637;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_0_01_DELAYG = 22638;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_0_01_DELAYG_LEN = 22639;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_1_01_DELAYG = 22640;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_1_01_DELAYG_LEN = 22641;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_0_01_DELAYG = 22642;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_0_01_DELAYG_LEN = 22643;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_1_01_DELAYG = 22644;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_1_01_DELAYG_LEN = 22645;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_2_23_DELAYG = 22646;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_2_23_DELAYG_LEN = 22647;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_3_23_DELAYG = 22648;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_3_23_DELAYG_LEN = 22649;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_2_23_DELAYG = 22650;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_2_23_DELAYG_LEN = 22651;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_3_23_DELAYG = 22652;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_3_23_DELAYG_LEN = 22653;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_4_DELAYG = 22654;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P0_4_DELAYG_LEN = 22655;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_4_DELAYG = 22656;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP2_REG_P1_4_DELAYG_LEN = 22657;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_0_01_DELAYG = 22658;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_0_01_DELAYG_LEN = 22659;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_1_01_DELAYG = 22660;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_1_01_DELAYG_LEN = 22661;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_0_01_DELAYG = 22662;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_0_01_DELAYG_LEN = 22663;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_1_01_DELAYG = 22664;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_1_01_DELAYG_LEN = 22665;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_2_23_DELAYG = 22666;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_2_23_DELAYG_LEN = 22667;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_3_23_DELAYG = 22668;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_3_23_DELAYG_LEN = 22669;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_2_23_DELAYG = 22670;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_2_23_DELAYG_LEN = 22671;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_3_23_DELAYG = 22672;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_3_23_DELAYG_LEN = 22673;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_4_DELAYG = 22674;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P0_4_DELAYG_LEN = 22675;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_4_DELAYG = 22676;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_4_RP3_REG_P1_4_DELAYG_LEN = 22677;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_0_01_DELAYG = 22678;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_0_01_DELAYG_LEN = 22679;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_1_01_DELAYG = 22680;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_1_01_DELAYG_LEN = 22681;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_0_01_DELAYG = 22682;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_0_01_DELAYG_LEN = 22683;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_1_01_DELAYG = 22684;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_1_01_DELAYG_LEN = 22685;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_2_23_DELAYG = 22686;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_2_23_DELAYG_LEN = 22687;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_3_23_DELAYG = 22688;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_3_23_DELAYG_LEN = 22689;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_2_23_DELAYG = 22690;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_2_23_DELAYG_LEN = 22691;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_3_23_DELAYG = 22692;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_3_23_DELAYG_LEN = 22693;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_4_DELAYG = 22694;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P0_4_DELAYG_LEN = 22695;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_4_DELAYG = 22696;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP0_REG_P1_4_DELAYG_LEN = 22697;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_0_01_DELAYG = 22698;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_0_01_DELAYG_LEN = 22699;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_1_01_DELAYG = 22700;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_1_01_DELAYG_LEN = 22701;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_0_01_DELAYG = 22702;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_0_01_DELAYG_LEN = 22703;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_1_01_DELAYG = 22704;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_1_01_DELAYG_LEN = 22705;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_2_23_DELAYG = 22706;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_2_23_DELAYG_LEN = 22707;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_3_23_DELAYG = 22708;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_3_23_DELAYG_LEN = 22709;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_2_23_DELAYG = 22710;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_2_23_DELAYG_LEN = 22711;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_3_23_DELAYG = 22712;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_3_23_DELAYG_LEN = 22713;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_4_DELAYG = 22714;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P0_4_DELAYG_LEN = 22715;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_4_DELAYG = 22716;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP1_REG_P1_4_DELAYG_LEN = 22717;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_0_01_DELAYG = 22718;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_0_01_DELAYG_LEN = 22719;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_1_01_DELAYG = 22720;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_1_01_DELAYG_LEN = 22721;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_0_01_DELAYG = 22722;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_0_01_DELAYG_LEN = 22723;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_1_01_DELAYG = 22724;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_1_01_DELAYG_LEN = 22725;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_2_23_DELAYG = 22726;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_2_23_DELAYG_LEN = 22727;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_3_23_DELAYG = 22728;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_3_23_DELAYG_LEN = 22729;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_2_23_DELAYG = 22730;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_2_23_DELAYG_LEN = 22731;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_3_23_DELAYG = 22732;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_3_23_DELAYG_LEN = 22733;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_4_DELAYG = 22734;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P0_4_DELAYG_LEN = 22735;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_4_DELAYG = 22736;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP2_REG_P1_4_DELAYG_LEN = 22737;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_0_01_DELAYG = 22738;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_0_01_DELAYG_LEN = 22739;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_1_01_DELAYG = 22740;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_1_01_DELAYG_LEN = 22741;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_0_01_DELAYG = 22742;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_0_01_DELAYG_LEN = 22743;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_1_01_DELAYG = 22744;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_1_01_DELAYG_LEN = 22745;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_2_23_DELAYG = 22746;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_2_23_DELAYG_LEN = 22747;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_3_23_DELAYG = 22748;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_3_23_DELAYG_LEN = 22749;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_2_23_DELAYG = 22750;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_2_23_DELAYG_LEN = 22751;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_3_23_DELAYG = 22752;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_3_23_DELAYG_LEN = 22753;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_4_DELAYG = 22754;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P0_4_DELAYG_LEN = 22755;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_4_DELAYG = 22756;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_5_RP3_REG_P1_4_DELAYG_LEN = 22757;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_0_01_DELAYG = 22758;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_0_01_DELAYG_LEN = 22759;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_1_01_DELAYG = 22760;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_1_01_DELAYG_LEN = 22761;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_0_01_DELAYG = 22762;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_0_01_DELAYG_LEN = 22763;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_1_01_DELAYG = 22764;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_1_01_DELAYG_LEN = 22765;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_2_23_DELAYG = 22766;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_2_23_DELAYG_LEN = 22767;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_3_23_DELAYG = 22768;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_3_23_DELAYG_LEN = 22769;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_2_23_DELAYG = 22770;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_2_23_DELAYG_LEN = 22771;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_3_23_DELAYG = 22772;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_3_23_DELAYG_LEN = 22773;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_4_DELAYG = 22774;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P0_4_DELAYG_LEN = 22775;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_4_DELAYG = 22776;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP0_REG_P1_4_DELAYG_LEN = 22777;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_0_01_DELAYG = 22778;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_0_01_DELAYG_LEN = 22779;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_1_01_DELAYG = 22780;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_1_01_DELAYG_LEN = 22781;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_0_01_DELAYG = 22782;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_0_01_DELAYG_LEN = 22783;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_1_01_DELAYG = 22784;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_1_01_DELAYG_LEN = 22785;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_2_23_DELAYG = 22786;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_2_23_DELAYG_LEN = 22787;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_3_23_DELAYG = 22788;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_3_23_DELAYG_LEN = 22789;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_2_23_DELAYG = 22790;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_2_23_DELAYG_LEN = 22791;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_3_23_DELAYG = 22792;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_3_23_DELAYG_LEN = 22793;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_4_DELAYG = 22794;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P0_4_DELAYG_LEN = 22795;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_4_DELAYG = 22796;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP1_REG_P1_4_DELAYG_LEN = 22797;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_0_01_DELAYG = 22798;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_0_01_DELAYG_LEN = 22799;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_1_01_DELAYG = 22800;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_1_01_DELAYG_LEN = 22801;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_0_01_DELAYG = 22802;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_0_01_DELAYG_LEN = 22803;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_1_01_DELAYG = 22804;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_1_01_DELAYG_LEN = 22805;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_2_23_DELAYG = 22806;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_2_23_DELAYG_LEN = 22807;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_3_23_DELAYG = 22808;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_3_23_DELAYG_LEN = 22809;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_2_23_DELAYG = 22810;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_2_23_DELAYG_LEN = 22811;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_3_23_DELAYG = 22812;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_3_23_DELAYG_LEN = 22813;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_4_DELAYG = 22814;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P0_4_DELAYG_LEN = 22815;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_4_DELAYG = 22816;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP2_REG_P1_4_DELAYG_LEN = 22817;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_0_01_DELAYG = 22818;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_0_01_DELAYG_LEN = 22819;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_1_01_DELAYG = 22820;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_1_01_DELAYG_LEN = 22821;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_0_01_DELAYG = 22822;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_0_01_DELAYG_LEN = 22823;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_1_01_DELAYG = 22824;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_1_01_DELAYG_LEN = 22825;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_2_23_DELAYG = 22826;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_2_23_DELAYG_LEN = 22827;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_3_23_DELAYG = 22828;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_3_23_DELAYG_LEN = 22829;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_2_23_DELAYG = 22830;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_2_23_DELAYG_LEN = 22831;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_3_23_DELAYG = 22832;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_3_23_DELAYG_LEN = 22833;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_4_DELAYG = 22834;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P0_4_DELAYG_LEN = 22835;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_4_DELAYG = 22836;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_6_RP3_REG_P1_4_DELAYG_LEN = 22837;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_0_01_DELAYG = 22838;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_0_01_DELAYG_LEN = 22839;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_1_01_DELAYG = 22840;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_1_01_DELAYG_LEN = 22841;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_0_01_DELAYG = 22842;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_0_01_DELAYG_LEN = 22843;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_1_01_DELAYG = 22844;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_1_01_DELAYG_LEN = 22845;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_2_23_DELAYG = 22846;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_2_23_DELAYG_LEN = 22847;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_3_23_DELAYG = 22848;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_3_23_DELAYG_LEN = 22849;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_2_23_DELAYG = 22850;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_2_23_DELAYG_LEN = 22851;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_3_23_DELAYG = 22852;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_3_23_DELAYG_LEN = 22853;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_4_DELAYG = 22854;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P0_4_DELAYG_LEN = 22855;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_4_DELAYG = 22856;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP0_REG_P1_4_DELAYG_LEN = 22857;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_0_01_DELAYG = 22858;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_0_01_DELAYG_LEN = 22859;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_1_01_DELAYG = 22860;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_1_01_DELAYG_LEN = 22861;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_0_01_DELAYG = 22862;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_0_01_DELAYG_LEN = 22863;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_1_01_DELAYG = 22864;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_1_01_DELAYG_LEN = 22865;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_2_23_DELAYG = 22866;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_2_23_DELAYG_LEN = 22867;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_3_23_DELAYG = 22868;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_3_23_DELAYG_LEN = 22869;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_2_23_DELAYG = 22870;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_2_23_DELAYG_LEN = 22871;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_3_23_DELAYG = 22872;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_3_23_DELAYG_LEN = 22873;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_4_DELAYG = 22874;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P0_4_DELAYG_LEN = 22875;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_4_DELAYG = 22876;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP1_REG_P1_4_DELAYG_LEN = 22877;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_0_01_DELAYG = 22878;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_0_01_DELAYG_LEN = 22879;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_1_01_DELAYG = 22880;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_1_01_DELAYG_LEN = 22881;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_0_01_DELAYG = 22882;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_0_01_DELAYG_LEN = 22883;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_1_01_DELAYG = 22884;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_1_01_DELAYG_LEN = 22885;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_2_23_DELAYG = 22886;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_2_23_DELAYG_LEN = 22887;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_3_23_DELAYG = 22888;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_3_23_DELAYG_LEN = 22889;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_2_23_DELAYG = 22890;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_2_23_DELAYG_LEN = 22891;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_3_23_DELAYG = 22892;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_3_23_DELAYG_LEN = 22893;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_4_DELAYG = 22894;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P0_4_DELAYG_LEN = 22895;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_4_DELAYG = 22896;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP2_REG_P1_4_DELAYG_LEN = 22897;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_0_01_DELAYG = 22898;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_0_01_DELAYG_LEN = 22899;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_1_01_DELAYG = 22900;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_1_01_DELAYG_LEN = 22901;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_0_01_DELAYG = 22902;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_0_01_DELAYG_LEN = 22903;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_1_01_DELAYG = 22904;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_1_01_DELAYG_LEN = 22905;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_2_23_DELAYG = 22906;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_2_23_DELAYG_LEN = 22907;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_3_23_DELAYG = 22908;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_3_23_DELAYG_LEN = 22909;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_2_23_DELAYG = 22910;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_2_23_DELAYG_LEN = 22911;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_3_23_DELAYG = 22912;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_3_23_DELAYG_LEN = 22913;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_4_DELAYG = 22914;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P0_4_DELAYG_LEN = 22915;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_4_DELAYG = 22916;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_7_RP3_REG_P1_4_DELAYG_LEN = 22917;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_0_01_DELAYG = 22918;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_0_01_DELAYG_LEN = 22919;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_1_01_DELAYG = 22920;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_1_01_DELAYG_LEN = 22921;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_0_01_DELAYG = 22922;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_0_01_DELAYG_LEN = 22923;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_1_01_DELAYG = 22924;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_1_01_DELAYG_LEN = 22925;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_2_23_DELAYG = 22926;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_2_23_DELAYG_LEN = 22927;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_3_23_DELAYG = 22928;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_3_23_DELAYG_LEN = 22929;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_2_23_DELAYG = 22930;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_2_23_DELAYG_LEN = 22931;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_3_23_DELAYG = 22932;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_3_23_DELAYG_LEN = 22933;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_4_DELAYG = 22934;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P0_4_DELAYG_LEN = 22935;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_4_DELAYG = 22936;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP0_REG_P1_4_DELAYG_LEN = 22937;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_0_01_DELAYG = 22938;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_0_01_DELAYG_LEN = 22939;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_1_01_DELAYG = 22940;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_1_01_DELAYG_LEN = 22941;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_0_01_DELAYG = 22942;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_0_01_DELAYG_LEN = 22943;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_1_01_DELAYG = 22944;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_1_01_DELAYG_LEN = 22945;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_2_23_DELAYG = 22946;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_2_23_DELAYG_LEN = 22947;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_3_23_DELAYG = 22948;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_3_23_DELAYG_LEN = 22949;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_2_23_DELAYG = 22950;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_2_23_DELAYG_LEN = 22951;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_3_23_DELAYG = 22952;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_3_23_DELAYG_LEN = 22953;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_4_DELAYG = 22954;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P0_4_DELAYG_LEN = 22955;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_4_DELAYG = 22956;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP1_REG_P1_4_DELAYG_LEN = 22957;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_0_01_DELAYG = 22958;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_0_01_DELAYG_LEN = 22959;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_1_01_DELAYG = 22960;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_1_01_DELAYG_LEN = 22961;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_0_01_DELAYG = 22962;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_0_01_DELAYG_LEN = 22963;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_1_01_DELAYG = 22964;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_1_01_DELAYG_LEN = 22965;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_2_23_DELAYG = 22966;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_2_23_DELAYG_LEN = 22967;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_3_23_DELAYG = 22968;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_3_23_DELAYG_LEN = 22969;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_2_23_DELAYG = 22970;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_2_23_DELAYG_LEN = 22971;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_3_23_DELAYG = 22972;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_3_23_DELAYG_LEN = 22973;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_4_DELAYG = 22974;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P0_4_DELAYG_LEN = 22975;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_4_DELAYG = 22976;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP2_REG_P1_4_DELAYG_LEN = 22977;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_0_01_DELAYG = 22978;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_0_01_DELAYG_LEN = 22979;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_1_01_DELAYG = 22980;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_1_01_DELAYG_LEN = 22981;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_0_01_DELAYG = 22982;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_0_01_DELAYG_LEN = 22983;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_1_01_DELAYG = 22984;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_1_01_DELAYG_LEN = 22985;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_2_23_DELAYG = 22986;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_2_23_DELAYG_LEN = 22987;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_3_23_DELAYG = 22988;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_3_23_DELAYG_LEN = 22989;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_2_23_DELAYG = 22990;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_2_23_DELAYG_LEN = 22991;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_3_23_DELAYG = 22992;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_3_23_DELAYG_LEN = 22993;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_4_DELAYG = 22994;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P0_4_DELAYG_LEN = 22995;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_4_DELAYG = 22996;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_8_RP3_REG_P1_4_DELAYG_LEN = 22997;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_0_01_DELAYG = 22998;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_0_01_DELAYG_LEN = 22999;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_1_01_DELAYG = 23000;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_1_01_DELAYG_LEN = 23001;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_0_01_DELAYG = 23002;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_0_01_DELAYG_LEN = 23003;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_1_01_DELAYG = 23004;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_1_01_DELAYG_LEN = 23005;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_2_23_DELAYG = 23006;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_2_23_DELAYG_LEN = 23007;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_3_23_DELAYG = 23008;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_3_23_DELAYG_LEN = 23009;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_2_23_DELAYG = 23010;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_2_23_DELAYG_LEN = 23011;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_3_23_DELAYG = 23012;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_3_23_DELAYG_LEN = 23013;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_4_DELAYG = 23014;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P0_4_DELAYG_LEN = 23015;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_4_DELAYG = 23016;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP0_REG_P1_4_DELAYG_LEN = 23017;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_0_01_DELAYG = 23018;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_0_01_DELAYG_LEN = 23019;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_1_01_DELAYG = 23020;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_1_01_DELAYG_LEN = 23021;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_0_01_DELAYG = 23022;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_0_01_DELAYG_LEN = 23023;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_1_01_DELAYG = 23024;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_1_01_DELAYG_LEN = 23025;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_2_23_DELAYG = 23026;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_2_23_DELAYG_LEN = 23027;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_3_23_DELAYG = 23028;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_3_23_DELAYG_LEN = 23029;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_2_23_DELAYG = 23030;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_2_23_DELAYG_LEN = 23031;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_3_23_DELAYG = 23032;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_3_23_DELAYG_LEN = 23033;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_4_DELAYG = 23034;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P0_4_DELAYG_LEN = 23035;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_4_DELAYG = 23036;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP1_REG_P1_4_DELAYG_LEN = 23037;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_0_01_DELAYG = 23038;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_0_01_DELAYG_LEN = 23039;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_1_01_DELAYG = 23040;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_1_01_DELAYG_LEN = 23041;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_0_01_DELAYG = 23042;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_0_01_DELAYG_LEN = 23043;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_1_01_DELAYG = 23044;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_1_01_DELAYG_LEN = 23045;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_2_23_DELAYG = 23046;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_2_23_DELAYG_LEN = 23047;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_3_23_DELAYG = 23048;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_3_23_DELAYG_LEN = 23049;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_2_23_DELAYG = 23050;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_2_23_DELAYG_LEN = 23051;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_3_23_DELAYG = 23052;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_3_23_DELAYG_LEN = 23053;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_4_DELAYG = 23054;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P0_4_DELAYG_LEN = 23055;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_4_DELAYG = 23056;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP2_REG_P1_4_DELAYG_LEN = 23057;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_0_01_DELAYG = 23058;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_0_01_DELAYG_LEN = 23059;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_1_01_DELAYG = 23060;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_1_01_DELAYG_LEN = 23061;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_0_01_DELAYG = 23062;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_0_01_DELAYG_LEN = 23063;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_1_01_DELAYG = 23064;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_1_01_DELAYG_LEN = 23065;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_2_23_DELAYG = 23066;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_2_23_DELAYG_LEN = 23067;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_3_23_DELAYG = 23068;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_3_23_DELAYG_LEN = 23069;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_2_23_DELAYG = 23070;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_2_23_DELAYG_LEN = 23071;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_3_23_DELAYG = 23072;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_3_23_DELAYG_LEN = 23073;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_4_DELAYG = 23074;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P0_4_DELAYG_LEN = 23075;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_4_DELAYG = 23076;
static const uint64_t IDX_CEN_MBA_DP18_WR_DELAY_VALUE_9_RP3_REG_P1_4_DELAYG_LEN = 23077;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD0 = 23078;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD0_LEN = 23079;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD1 = 23080;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD1_LEN = 23081;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD2 = 23082;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD2_LEN = 23083;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD3 = 23084;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_QUAD3_LEN = 23085;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD0 = 23086;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD0_LEN = 23087;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD1 = 23088;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD1_LEN = 23089;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD2 = 23090;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD2_LEN = 23091;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD3 = 23092;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_QUAD3_LEN = 23093;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD0 = 23094;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD0_LEN = 23095;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD1 = 23096;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD1_LEN = 23097;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD2 = 23098;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD2_LEN = 23099;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD3 = 23100;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_QUAD3_LEN = 23101;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD0 = 23102;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD0_LEN = 23103;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD1 = 23104;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD1_LEN = 23105;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD2 = 23106;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD2_LEN = 23107;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD3 = 23108;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_QUAD3_LEN = 23109;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD0 = 23110;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD0_LEN = 23111;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD1 = 23112;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD1_LEN = 23113;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD2 = 23114;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD2_LEN = 23115;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD3 = 23116;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_QUAD3_LEN = 23117;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD0 = 23118;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD0_LEN = 23119;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD1 = 23120;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD1_LEN = 23121;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD2 = 23122;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD2_LEN = 23123;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD3 = 23124;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_QUAD3_LEN = 23125;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD0 = 23126;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD0_LEN = 23127;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD1 = 23128;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD1_LEN = 23129;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD2 = 23130;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD2_LEN = 23131;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD3 = 23132;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_QUAD3_LEN = 23133;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD0 = 23134;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD0_LEN = 23135;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD1 = 23136;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD1_LEN = 23137;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD2 = 23138;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD2_LEN = 23139;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD3 = 23140;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_QUAD3_LEN = 23141;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD0 = 23142;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD0_LEN = 23143;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD1 = 23144;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD1_LEN = 23145;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD2 = 23146;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD2_LEN = 23147;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD3 = 23148;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_QUAD3_LEN = 23149;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD0 = 23150;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD0_LEN = 23151;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD1 = 23152;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD1_LEN = 23153;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD2 = 23154;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD2_LEN = 23155;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD3 = 23156;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_QUAD3_LEN = 23157;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_0_DESIRED_EDGE_CNTR_TARGET_HIGH = 23158;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_0_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23159;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_0_DESIRED_EDGE_CNTR_TARGET_LOW = 23160;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_0_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23161;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_1_DESIRED_EDGE_CNTR_TARGET_HIGH = 23162;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_1_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23163;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_1_DESIRED_EDGE_CNTR_TARGET_LOW = 23164;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_1_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23165;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_0_DESIRED_EDGE_CNTR_TARGET_HIGH = 23166;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_0_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23167;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_0_DESIRED_EDGE_CNTR_TARGET_LOW = 23168;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_0_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23169;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_1_DESIRED_EDGE_CNTR_TARGET_HIGH = 23170;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_1_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23171;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_1_DESIRED_EDGE_CNTR_TARGET_LOW = 23172;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_1_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23173;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_2_DESIRED_EDGE_CNTR_TARGET_HIGH = 23174;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_2_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23175;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_2_DESIRED_EDGE_CNTR_TARGET_LOW = 23176;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_2_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23177;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_3_DESIRED_EDGE_CNTR_TARGET_HIGH = 23178;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_3_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23179;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_3_DESIRED_EDGE_CNTR_TARGET_LOW = 23180;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_3_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23181;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_2_DESIRED_EDGE_CNTR_TARGET_HIGH = 23182;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_2_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23183;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_2_DESIRED_EDGE_CNTR_TARGET_LOW = 23184;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_2_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23185;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_3_DESIRED_EDGE_CNTR_TARGET_HIGH = 23186;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_3_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23187;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_3_DESIRED_EDGE_CNTR_TARGET_LOW = 23188;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_3_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23189;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 23190;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23191;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_4_DESIRED_EDGE_CNTR_TARGET_LOW = 23192;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P0_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23193;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 23194;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 23195;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_4_DESIRED_EDGE_CNTR_TARGET_LOW = 23196;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG3_P1_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 23197;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P0_0_DQS_ALIGN_FIX_DIS = 23198;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P0_1_DQS_ALIGN_FIX_DIS = 23199;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P1_0_DQS_ALIGN_FIX_DIS = 23200;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P1_1_DQS_ALIGN_FIX_DIS = 23201;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P0_2_DQS_ALIGN_FIX_DIS = 23202;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P0_3_DQS_ALIGN_FIX_DIS = 23203;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P1_2_DQS_ALIGN_FIX_DIS = 23204;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P1_3_DQS_ALIGN_FIX_DIS = 23205;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P0_4_DQS_ALIGN_FIX_DIS = 23206;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG4_P1_4_DQS_ALIGN_FIX_DIS = 23207;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DYN_POWER_CNTL_EN = 23208;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DYN_MCTERM_CNTL_EN = 23209;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DYN_RX_GATE_CNTL_EN = 23210;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_CALGATE_ON = 23211;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_PER_CAL_UPDATE_DISABLE = 23212;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DQS_PIPE_FIX_DIS = 23213;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DQS_PIPE_FIX_DIS_LEN = 23214;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DD2_DQS_FIX_DIS = 23215;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DL_FORCE_ON = 23216;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_BLFIFO_DIS = 23217;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_WTRFL_AVE_DIS = 23218;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_PERCAL_PWR_DIS = 23219;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_LOOPBACK_FIX_EN = 23220;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_LOOPBACK_DLY12 = 23221;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_DD2_WTRFL_SYNC_DIS = 23222;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_FORCE_FIFO_CAPTURE = 23223;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DYN_POWER_CNTL_EN = 23224;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DYN_MCTERM_CNTL_EN = 23225;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DYN_RX_GATE_CNTL_EN = 23226;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_CALGATE_ON = 23227;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_PER_CAL_UPDATE_DISABLE = 23228;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DQS_PIPE_FIX_DIS = 23229;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DQS_PIPE_FIX_DIS_LEN = 23230;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DD2_DQS_FIX_DIS = 23231;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DL_FORCE_ON = 23232;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_BLFIFO_DIS = 23233;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_WTRFL_AVE_DIS = 23234;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_PERCAL_PWR_DIS = 23235;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_LOOPBACK_FIX_EN = 23236;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_LOOPBACK_DLY12 = 23237;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_DD2_WTRFL_SYNC_DIS = 23238;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_FORCE_FIFO_CAPTURE = 23239;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DYN_POWER_CNTL_EN = 23240;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DYN_MCTERM_CNTL_EN = 23241;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DYN_RX_GATE_CNTL_EN = 23242;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_CALGATE_ON = 23243;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_PER_CAL_UPDATE_DISABLE = 23244;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DQS_PIPE_FIX_DIS = 23245;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DQS_PIPE_FIX_DIS_LEN = 23246;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DD2_DQS_FIX_DIS = 23247;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DL_FORCE_ON = 23248;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_BLFIFO_DIS = 23249;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_WTRFL_AVE_DIS = 23250;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_PERCAL_PWR_DIS = 23251;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_LOOPBACK_FIX_EN = 23252;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_LOOPBACK_DLY12 = 23253;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_DD2_WTRFL_SYNC_DIS = 23254;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_FORCE_FIFO_CAPTURE = 23255;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DYN_POWER_CNTL_EN = 23256;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DYN_MCTERM_CNTL_EN = 23257;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DYN_RX_GATE_CNTL_EN = 23258;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_CALGATE_ON = 23259;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_PER_CAL_UPDATE_DISABLE = 23260;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DQS_PIPE_FIX_DIS = 23261;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DQS_PIPE_FIX_DIS_LEN = 23262;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DD2_DQS_FIX_DIS = 23263;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DL_FORCE_ON = 23264;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_BLFIFO_DIS = 23265;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_WTRFL_AVE_DIS = 23266;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_PERCAL_PWR_DIS = 23267;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_LOOPBACK_FIX_EN = 23268;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_LOOPBACK_DLY12 = 23269;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_DD2_WTRFL_SYNC_DIS = 23270;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_FORCE_FIFO_CAPTURE = 23271;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DYN_POWER_CNTL_EN = 23272;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DYN_MCTERM_CNTL_EN = 23273;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DYN_RX_GATE_CNTL_EN = 23274;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_CALGATE_ON = 23275;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_PER_CAL_UPDATE_DISABLE = 23276;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DQS_PIPE_FIX_DIS = 23277;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DQS_PIPE_FIX_DIS_LEN = 23278;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DD2_DQS_FIX_DIS = 23279;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DL_FORCE_ON = 23280;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_BLFIFO_DIS = 23281;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_WTRFL_AVE_DIS = 23282;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_PERCAL_PWR_DIS = 23283;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_LOOPBACK_FIX_EN = 23284;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_LOOPBACK_DLY12 = 23285;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_DD2_WTRFL_SYNC_DIS = 23286;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_FORCE_FIFO_CAPTURE = 23287;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DYN_POWER_CNTL_EN = 23288;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DYN_MCTERM_CNTL_EN = 23289;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DYN_RX_GATE_CNTL_EN = 23290;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_CALGATE_ON = 23291;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_PER_CAL_UPDATE_DISABLE = 23292;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DQS_PIPE_FIX_DIS = 23293;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DQS_PIPE_FIX_DIS_LEN = 23294;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DD2_DQS_FIX_DIS = 23295;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DL_FORCE_ON = 23296;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_BLFIFO_DIS = 23297;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_WTRFL_AVE_DIS = 23298;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_PERCAL_PWR_DIS = 23299;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_LOOPBACK_FIX_EN = 23300;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_LOOPBACK_DLY12 = 23301;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_DD2_WTRFL_SYNC_DIS = 23302;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_FORCE_FIFO_CAPTURE = 23303;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DYN_POWER_CNTL_EN = 23304;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DYN_MCTERM_CNTL_EN = 23305;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DYN_RX_GATE_CNTL_EN = 23306;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_CALGATE_ON = 23307;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_PER_CAL_UPDATE_DISABLE = 23308;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DQS_PIPE_FIX_DIS = 23309;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DQS_PIPE_FIX_DIS_LEN = 23310;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DD2_DQS_FIX_DIS = 23311;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DL_FORCE_ON = 23312;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_BLFIFO_DIS = 23313;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_WTRFL_AVE_DIS = 23314;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_PERCAL_PWR_DIS = 23315;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_LOOPBACK_FIX_EN = 23316;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_LOOPBACK_DLY12 = 23317;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_DD2_WTRFL_SYNC_DIS = 23318;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_FORCE_FIFO_CAPTURE = 23319;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DYN_POWER_CNTL_EN = 23320;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DYN_MCTERM_CNTL_EN = 23321;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DYN_RX_GATE_CNTL_EN = 23322;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_CALGATE_ON = 23323;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_PER_CAL_UPDATE_DISABLE = 23324;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DQS_PIPE_FIX_DIS = 23325;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DQS_PIPE_FIX_DIS_LEN = 23326;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DD2_DQS_FIX_DIS = 23327;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DL_FORCE_ON = 23328;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_BLFIFO_DIS = 23329;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_WTRFL_AVE_DIS = 23330;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_PERCAL_PWR_DIS = 23331;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_LOOPBACK_FIX_EN = 23332;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_LOOPBACK_DLY12 = 23333;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_DD2_WTRFL_SYNC_DIS = 23334;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_FORCE_FIFO_CAPTURE = 23335;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DYN_POWER_CNTL_EN = 23336;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DYN_MCTERM_CNTL_EN = 23337;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DYN_RX_GATE_CNTL_EN = 23338;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_CALGATE_ON = 23339;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_PER_CAL_UPDATE_DISABLE = 23340;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DQS_PIPE_FIX_DIS = 23341;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DQS_PIPE_FIX_DIS_LEN = 23342;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DD2_DQS_FIX_DIS = 23343;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DL_FORCE_ON = 23344;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_BLFIFO_DIS = 23345;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_WTRFL_AVE_DIS = 23346;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_PERCAL_PWR_DIS = 23347;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_LOOPBACK_FIX_EN = 23348;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_LOOPBACK_DLY12 = 23349;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_DD2_WTRFL_SYNC_DIS = 23350;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_FORCE_FIFO_CAPTURE = 23351;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DYN_POWER_CNTL_EN = 23352;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DYN_MCTERM_CNTL_EN = 23353;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DYN_RX_GATE_CNTL_EN = 23354;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_CALGATE_ON = 23355;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_PER_CAL_UPDATE_DISABLE = 23356;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DQS_PIPE_FIX_DIS = 23357;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DQS_PIPE_FIX_DIS_LEN = 23358;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DD2_DQS_FIX_DIS = 23359;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DL_FORCE_ON = 23360;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_BLFIFO_DIS = 23361;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_WTRFL_AVE_DIS = 23362;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_PERCAL_PWR_DIS = 23363;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_LOOPBACK_FIX_EN = 23364;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_LOOPBACK_DLY12 = 23365;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_DD2_WTRFL_SYNC_DIS = 23366;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_FORCE_FIFO_CAPTURE = 23367;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_0_SYSCLK_DQSCLK_OFFSET = 23368;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_0_SYSCLK_DQSCLK_OFFSET_LEN = 23369;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_0_SYSCLK_RDCLK_OFFSET = 23370;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_0_SYSCLK_RDCLK_OFFSET_LEN = 23371;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_1_SYSCLK_DQSCLK_OFFSET = 23372;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_1_SYSCLK_DQSCLK_OFFSET_LEN = 23373;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_1_SYSCLK_RDCLK_OFFSET = 23374;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_1_SYSCLK_RDCLK_OFFSET_LEN = 23375;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_0_SYSCLK_DQSCLK_OFFSET = 23376;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_0_SYSCLK_DQSCLK_OFFSET_LEN = 23377;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_0_SYSCLK_RDCLK_OFFSET = 23378;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_0_SYSCLK_RDCLK_OFFSET_LEN = 23379;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_1_SYSCLK_DQSCLK_OFFSET = 23380;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_1_SYSCLK_DQSCLK_OFFSET_LEN = 23381;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_1_SYSCLK_RDCLK_OFFSET = 23382;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_1_SYSCLK_RDCLK_OFFSET_LEN = 23383;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_2_SYSCLK_DQSCLK_OFFSET = 23384;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_2_SYSCLK_DQSCLK_OFFSET_LEN = 23385;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_2_SYSCLK_RDCLK_OFFSET = 23386;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_2_SYSCLK_RDCLK_OFFSET_LEN = 23387;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_3_SYSCLK_DQSCLK_OFFSET = 23388;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_3_SYSCLK_DQSCLK_OFFSET_LEN = 23389;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_3_SYSCLK_RDCLK_OFFSET = 23390;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_3_SYSCLK_RDCLK_OFFSET_LEN = 23391;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_2_SYSCLK_DQSCLK_OFFSET = 23392;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_2_SYSCLK_DQSCLK_OFFSET_LEN = 23393;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_2_SYSCLK_RDCLK_OFFSET = 23394;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_2_SYSCLK_RDCLK_OFFSET_LEN = 23395;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_3_SYSCLK_DQSCLK_OFFSET = 23396;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_3_SYSCLK_DQSCLK_OFFSET_LEN = 23397;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_3_SYSCLK_RDCLK_OFFSET = 23398;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_3_SYSCLK_RDCLK_OFFSET_LEN = 23399;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_4_SYSCLK_DQSCLK_OFFSET = 23400;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_4_SYSCLK_DQSCLK_OFFSET_LEN = 23401;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_4_SYSCLK_RDCLK_OFFSET = 23402;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P0_4_SYSCLK_RDCLK_OFFSET_LEN = 23403;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_4_SYSCLK_DQSCLK_OFFSET = 23404;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_4_SYSCLK_DQSCLK_OFFSET_LEN = 23405;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_4_SYSCLK_RDCLK_OFFSET = 23406;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG0_P1_4_SYSCLK_RDCLK_OFFSET_LEN = 23407;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_0_DQS_ALIGN_SM = 23408;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_0_DQS_ALIGN_SM_LEN = 23409;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_0_DQS_ALIGN_CNTR = 23410;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_0_DQS_ALIGN_CNTR_LEN = 23411;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_0_DQS_ALIGN_ITR_CNTR = 23412;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_0_DQS_ALIGN_ITR_CNTR_LEN = 23413;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_1_DQS_ALIGN_SM = 23414;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_1_DQS_ALIGN_SM_LEN = 23415;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_1_DQS_ALIGN_CNTR = 23416;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_1_DQS_ALIGN_CNTR_LEN = 23417;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_1_DQS_ALIGN_ITR_CNTR = 23418;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_1_DQS_ALIGN_ITR_CNTR_LEN = 23419;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_0_DQS_ALIGN_SM = 23420;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_0_DQS_ALIGN_SM_LEN = 23421;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_0_DQS_ALIGN_CNTR = 23422;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_0_DQS_ALIGN_CNTR_LEN = 23423;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_0_DQS_ALIGN_ITR_CNTR = 23424;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_0_DQS_ALIGN_ITR_CNTR_LEN = 23425;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_1_DQS_ALIGN_SM = 23426;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_1_DQS_ALIGN_SM_LEN = 23427;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_1_DQS_ALIGN_CNTR = 23428;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_1_DQS_ALIGN_CNTR_LEN = 23429;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_1_DQS_ALIGN_ITR_CNTR = 23430;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_1_DQS_ALIGN_ITR_CNTR_LEN = 23431;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_2_DQS_ALIGN_SM = 23432;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_2_DQS_ALIGN_SM_LEN = 23433;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_2_DQS_ALIGN_CNTR = 23434;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_2_DQS_ALIGN_CNTR_LEN = 23435;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_2_DQS_ALIGN_ITR_CNTR = 23436;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_2_DQS_ALIGN_ITR_CNTR_LEN = 23437;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_3_DQS_ALIGN_SM = 23438;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_3_DQS_ALIGN_SM_LEN = 23439;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_3_DQS_ALIGN_CNTR = 23440;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_3_DQS_ALIGN_CNTR_LEN = 23441;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_3_DQS_ALIGN_ITR_CNTR = 23442;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_3_DQS_ALIGN_ITR_CNTR_LEN = 23443;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_2_DQS_ALIGN_SM = 23444;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_2_DQS_ALIGN_SM_LEN = 23445;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_2_DQS_ALIGN_CNTR = 23446;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_2_DQS_ALIGN_CNTR_LEN = 23447;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_2_DQS_ALIGN_ITR_CNTR = 23448;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_2_DQS_ALIGN_ITR_CNTR_LEN = 23449;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_3_DQS_ALIGN_SM = 23450;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_3_DQS_ALIGN_SM_LEN = 23451;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_3_DQS_ALIGN_CNTR = 23452;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_3_DQS_ALIGN_CNTR_LEN = 23453;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_3_DQS_ALIGN_ITR_CNTR = 23454;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_3_DQS_ALIGN_ITR_CNTR_LEN = 23455;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_4_DQS_ALIGN_SM = 23456;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_4_DQS_ALIGN_SM_LEN = 23457;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_4_DQS_ALIGN_CNTR = 23458;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_4_DQS_ALIGN_CNTR_LEN = 23459;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_4_DQS_ALIGN_ITR_CNTR = 23460;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P0_4_DQS_ALIGN_ITR_CNTR_LEN = 23461;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_4_DQS_ALIGN_SM = 23462;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_4_DQS_ALIGN_SM_LEN = 23463;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_4_DQS_ALIGN_CNTR = 23464;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_4_DQS_ALIGN_CNTR_LEN = 23465;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_4_DQS_ALIGN_ITR_CNTR = 23466;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG1_P1_4_DQS_ALIGN_ITR_CNTR_LEN = 23467;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_CALIBRATE_BIT = 23468;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_CALIBRATE_BIT_LEN = 23469;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_DQS_ALIGN_QUAD = 23470;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_DQS_ALIGN_QUAD_LEN = 23471;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_OPERATE_MODE = 23472;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_OPERATE_MODE_LEN = 23473;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_EN_DQS_OFFSET = 23474;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_DQS_ALIGN_JITTER = 23475;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_DIS_CLK_GATE = 23476;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_0_MAX_DQS_ITER = 23477;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_CALIBRATE_BIT = 23478;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_CALIBRATE_BIT_LEN = 23479;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_DQS_ALIGN_QUAD = 23480;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_DQS_ALIGN_QUAD_LEN = 23481;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_OPERATE_MODE = 23482;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_OPERATE_MODE_LEN = 23483;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_EN_DQS_OFFSET = 23484;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_DQS_ALIGN_JITTER = 23485;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_DIS_CLK_GATE = 23486;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_1_MAX_DQS_ITER = 23487;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_CALIBRATE_BIT = 23488;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_CALIBRATE_BIT_LEN = 23489;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_DQS_ALIGN_QUAD = 23490;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_DQS_ALIGN_QUAD_LEN = 23491;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_OPERATE_MODE = 23492;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_OPERATE_MODE_LEN = 23493;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_EN_DQS_OFFSET = 23494;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_DQS_ALIGN_JITTER = 23495;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_DIS_CLK_GATE = 23496;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_0_MAX_DQS_ITER = 23497;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_CALIBRATE_BIT = 23498;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_CALIBRATE_BIT_LEN = 23499;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_DQS_ALIGN_QUAD = 23500;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_DQS_ALIGN_QUAD_LEN = 23501;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_OPERATE_MODE = 23502;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_OPERATE_MODE_LEN = 23503;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_EN_DQS_OFFSET = 23504;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_DQS_ALIGN_JITTER = 23505;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_DIS_CLK_GATE = 23506;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_1_MAX_DQS_ITER = 23507;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_CALIBRATE_BIT = 23508;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_CALIBRATE_BIT_LEN = 23509;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_DQS_ALIGN_QUAD = 23510;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_DQS_ALIGN_QUAD_LEN = 23511;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_OPERATE_MODE = 23512;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_OPERATE_MODE_LEN = 23513;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_EN_DQS_OFFSET = 23514;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_DQS_ALIGN_JITTER = 23515;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_DIS_CLK_GATE = 23516;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_2_MAX_DQS_ITER = 23517;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_CALIBRATE_BIT = 23518;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_CALIBRATE_BIT_LEN = 23519;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_DQS_ALIGN_QUAD = 23520;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_DQS_ALIGN_QUAD_LEN = 23521;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_OPERATE_MODE = 23522;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_OPERATE_MODE_LEN = 23523;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_EN_DQS_OFFSET = 23524;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_DQS_ALIGN_JITTER = 23525;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_DIS_CLK_GATE = 23526;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_3_MAX_DQS_ITER = 23527;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_CALIBRATE_BIT = 23528;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_CALIBRATE_BIT_LEN = 23529;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_DQS_ALIGN_QUAD = 23530;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_DQS_ALIGN_QUAD_LEN = 23531;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_OPERATE_MODE = 23532;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_OPERATE_MODE_LEN = 23533;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_EN_DQS_OFFSET = 23534;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_DQS_ALIGN_JITTER = 23535;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_DIS_CLK_GATE = 23536;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_2_MAX_DQS_ITER = 23537;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_CALIBRATE_BIT = 23538;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_CALIBRATE_BIT_LEN = 23539;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_DQS_ALIGN_QUAD = 23540;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_DQS_ALIGN_QUAD_LEN = 23541;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_OPERATE_MODE = 23542;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_OPERATE_MODE_LEN = 23543;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_EN_DQS_OFFSET = 23544;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_DQS_ALIGN_JITTER = 23545;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_DIS_CLK_GATE = 23546;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_3_MAX_DQS_ITER = 23547;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_CALIBRATE_BIT = 23548;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_CALIBRATE_BIT_LEN = 23549;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_DQS_ALIGN_QUAD = 23550;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_DQS_ALIGN_QUAD_LEN = 23551;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_OPERATE_MODE = 23552;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_OPERATE_MODE_LEN = 23553;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_EN_DQS_OFFSET = 23554;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_DQS_ALIGN_JITTER = 23555;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_DIS_CLK_GATE = 23556;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P0_4_MAX_DQS_ITER = 23557;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_CALIBRATE_BIT = 23558;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_CALIBRATE_BIT_LEN = 23559;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_DQS_ALIGN_QUAD = 23560;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_DQS_ALIGN_QUAD_LEN = 23561;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_OPERATE_MODE = 23562;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_OPERATE_MODE_LEN = 23563;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_EN_DQS_OFFSET = 23564;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_DQS_ALIGN_JITTER = 23565;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_DIS_CLK_GATE = 23566;
static const uint64_t IDX_CEN_MBA_DDRPHY_DP18_RD_DIA_CONFIG2_P1_4_MAX_DQS_ITER = 23567;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11 = 23568;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11_LEN = 23569;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_12_15 = 23570;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_12_15_LEN = 23571;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11 = 23572;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11_LEN = 23573;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_12_15 = 23574;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_12_15_LEN = 23575;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR0_01_0_11 = 23576;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR0_01_0_11_LEN = 23577;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR0_01_12_15 = 23578;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR0_01_12_15_LEN = 23579;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR1_01_0_11 = 23580;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR1_01_0_11_LEN = 23581;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR1_01_12_15 = 23582;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR1_01_12_15_LEN = 23583;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11 = 23584;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11_LEN = 23585;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_12_15 = 23586;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_12_15_LEN = 23587;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11 = 23588;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11_LEN = 23589;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15 = 23590;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15_LEN = 23591;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR2_23_0_11 = 23592;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR2_23_0_11_LEN = 23593;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR2_23_12_15 = 23594;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR2_23_12_15_LEN = 23595;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR3_23_0_11 = 23596;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR3_23_0_11_LEN = 23597;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR3_23_12_15 = 23598;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_BIT_ENABLE_P1_ADR3_23_12_15_LEN = 23599;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR0_01 = 23600;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR0_01_LEN = 23601;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1 = 23602;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1_LEN = 23603;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR1_01 = 23604;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR1_01_LEN = 23605;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1 = 23606;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1_LEN = 23607;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR0_01 = 23608;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR0_01_LEN = 23609;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR0_01_DELAY1 = 23610;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR0_01_DELAY1_LEN = 23611;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR1_01 = 23612;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR1_01_LEN = 23613;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR1_01_DELAY1 = 23614;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR1_01_DELAY1_LEN = 23615;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR2_23 = 23616;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR2_23_LEN = 23617;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1 = 23618;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1_LEN = 23619;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR3_23 = 23620;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR3_23_LEN = 23621;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1 = 23622;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1_LEN = 23623;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR2_23 = 23624;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR2_23_LEN = 23625;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR2_23_DELAY1 = 23626;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR2_23_DELAY1_LEN = 23627;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR3_23 = 23628;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR3_23_LEN = 23629;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR3_23_DELAY1 = 23630;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY0_P1_ADR3_23_DELAY1_LEN = 23631;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2 = 23632;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2_LEN = 23633;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3 = 23634;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3_LEN = 23635;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2 = 23636;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2_LEN = 23637;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3 = 23638;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3_LEN = 23639;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR0_01_DELAY2 = 23640;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR0_01_DELAY2_LEN = 23641;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR0_01_DELAY3 = 23642;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR0_01_DELAY3_LEN = 23643;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR1_01_DELAY2 = 23644;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR1_01_DELAY2_LEN = 23645;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR1_01_DELAY3 = 23646;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR1_01_DELAY3_LEN = 23647;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2 = 23648;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2_LEN = 23649;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3 = 23650;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3_LEN = 23651;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2 = 23652;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2_LEN = 23653;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3 = 23654;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3_LEN = 23655;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR2_23_DELAY2 = 23656;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR2_23_DELAY2_LEN = 23657;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR2_23_DELAY3 = 23658;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR2_23_DELAY3_LEN = 23659;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR3_23_DELAY2 = 23660;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR3_23_DELAY2_LEN = 23661;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR3_23_DELAY3 = 23662;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY1_P1_ADR3_23_DELAY3_LEN = 23663;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4 = 23664;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4_LEN = 23665;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5 = 23666;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5_LEN = 23667;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4 = 23668;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4_LEN = 23669;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5 = 23670;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5_LEN = 23671;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR0_01_DELAY4 = 23672;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR0_01_DELAY4_LEN = 23673;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR0_01_DELAY5 = 23674;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR0_01_DELAY5_LEN = 23675;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR1_01_DELAY4 = 23676;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR1_01_DELAY4_LEN = 23677;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR1_01_DELAY5 = 23678;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR1_01_DELAY5_LEN = 23679;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4 = 23680;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4_LEN = 23681;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5 = 23682;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5_LEN = 23683;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4 = 23684;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4_LEN = 23685;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5 = 23686;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5_LEN = 23687;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR2_23_DELAY4 = 23688;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR2_23_DELAY4_LEN = 23689;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR2_23_DELAY5 = 23690;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR2_23_DELAY5_LEN = 23691;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR3_23_DELAY4 = 23692;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR3_23_DELAY4_LEN = 23693;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR3_23_DELAY5 = 23694;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY2_P1_ADR3_23_DELAY5_LEN = 23695;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6 = 23696;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6_LEN = 23697;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7 = 23698;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7_LEN = 23699;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6 = 23700;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6_LEN = 23701;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7 = 23702;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7_LEN = 23703;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR0_01_DELAY6 = 23704;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR0_01_DELAY6_LEN = 23705;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR0_01_DELAY7 = 23706;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR0_01_DELAY7_LEN = 23707;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR1_01_DELAY6 = 23708;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR1_01_DELAY6_LEN = 23709;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR1_01_DELAY7 = 23710;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR1_01_DELAY7_LEN = 23711;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6 = 23712;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6_LEN = 23713;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7 = 23714;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7_LEN = 23715;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6 = 23716;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6_LEN = 23717;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7 = 23718;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7_LEN = 23719;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR2_23_DELAY6 = 23720;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR2_23_DELAY6_LEN = 23721;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR2_23_DELAY7 = 23722;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR2_23_DELAY7_LEN = 23723;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR3_23_DELAY6 = 23724;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR3_23_DELAY6_LEN = 23725;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR3_23_DELAY7 = 23726;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY3_P1_ADR3_23_DELAY7_LEN = 23727;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8 = 23728;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8_LEN = 23729;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9 = 23730;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9_LEN = 23731;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8 = 23732;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8_LEN = 23733;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9 = 23734;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9_LEN = 23735;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR0_01_DELAY8 = 23736;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR0_01_DELAY8_LEN = 23737;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR0_01_DELAY9 = 23738;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR0_01_DELAY9_LEN = 23739;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR1_01_DELAY8 = 23740;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR1_01_DELAY8_LEN = 23741;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR1_01_DELAY9 = 23742;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR1_01_DELAY9_LEN = 23743;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8 = 23744;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8_LEN = 23745;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9 = 23746;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9_LEN = 23747;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8 = 23748;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8_LEN = 23749;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9 = 23750;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9_LEN = 23751;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR2_23_DELAY8 = 23752;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR2_23_DELAY8_LEN = 23753;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR2_23_DELAY9 = 23754;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR2_23_DELAY9_LEN = 23755;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR3_23_DELAY8 = 23756;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR3_23_DELAY8_LEN = 23757;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR3_23_DELAY9 = 23758;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY4_P1_ADR3_23_DELAY9_LEN = 23759;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10 = 23760;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10_LEN = 23761;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11 = 23762;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11_LEN = 23763;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10 = 23764;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10_LEN = 23765;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11 = 23766;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11_LEN = 23767;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR0_01_DELAY10 = 23768;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR0_01_DELAY10_LEN = 23769;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR0_01_DELAY11 = 23770;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR0_01_DELAY11_LEN = 23771;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR1_01_DELAY10 = 23772;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR1_01_DELAY10_LEN = 23773;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR1_01_DELAY11 = 23774;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR1_01_DELAY11_LEN = 23775;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10 = 23776;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10_LEN = 23777;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11 = 23778;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11_LEN = 23779;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10 = 23780;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10_LEN = 23781;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11 = 23782;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11_LEN = 23783;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR2_23_DELAY10 = 23784;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR2_23_DELAY10_LEN = 23785;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR2_23_DELAY11 = 23786;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR2_23_DELAY11_LEN = 23787;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR3_23_DELAY10 = 23788;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR3_23_DELAY10_LEN = 23789;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR3_23_DELAY11 = 23790;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY5_P1_ADR3_23_DELAY11_LEN = 23791;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12 = 23792;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12_LEN = 23793;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13 = 23794;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13_LEN = 23795;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12 = 23796;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12_LEN = 23797;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13 = 23798;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13_LEN = 23799;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR0_01_DELAY12 = 23800;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR0_01_DELAY12_LEN = 23801;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR0_01_DELAY13 = 23802;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR0_01_DELAY13_LEN = 23803;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR1_01_DELAY12 = 23804;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR1_01_DELAY12_LEN = 23805;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR1_01_DELAY13 = 23806;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR1_01_DELAY13_LEN = 23807;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12 = 23808;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12_LEN = 23809;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13 = 23810;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13_LEN = 23811;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12 = 23812;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12_LEN = 23813;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13 = 23814;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13_LEN = 23815;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR2_23_DELAY12 = 23816;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR2_23_DELAY12_LEN = 23817;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR2_23_DELAY13 = 23818;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR2_23_DELAY13_LEN = 23819;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR3_23_DELAY12 = 23820;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR3_23_DELAY12_LEN = 23821;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR3_23_DELAY13 = 23822;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY6_P1_ADR3_23_DELAY13_LEN = 23823;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14 = 23824;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14_LEN = 23825;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15 = 23826;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15_LEN = 23827;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14 = 23828;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14_LEN = 23829;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15 = 23830;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15_LEN = 23831;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR0_01_DELAY14 = 23832;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR0_01_DELAY14_LEN = 23833;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR0_01_DELAY15 = 23834;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR0_01_DELAY15_LEN = 23835;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR1_01_DELAY14 = 23836;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR1_01_DELAY14_LEN = 23837;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR1_01_DELAY15 = 23838;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR1_01_DELAY15_LEN = 23839;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14 = 23840;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14_LEN = 23841;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15 = 23842;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15_LEN = 23843;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14 = 23844;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14_LEN = 23845;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15 = 23846;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15_LEN = 23847;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR2_23_DELAY14 = 23848;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR2_23_DELAY14_LEN = 23849;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR2_23_DELAY15 = 23850;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR2_23_DELAY15_LEN = 23851;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR3_23_DELAY14 = 23852;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR3_23_DELAY14_LEN = 23853;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR3_23_DELAY15 = 23854;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DELAY7_P1_ADR3_23_DELAY15_LEN = 23855;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL = 23856;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL_LEN = 23857;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_DATA_EN = 23858;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE = 23859;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE_LEN = 23860;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_4TO1_MODE = 23861;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_RESET = 23862;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_GEN_EN = 23863;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CLEAR_ERROR = 23864;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CHECK_EN = 23865;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL = 23866;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL_LEN = 23867;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_DATA_EN = 23868;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE = 23869;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE_LEN = 23870;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_4TO1_MODE = 23871;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_RESET = 23872;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_GEN_EN = 23873;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CLEAR_ERROR = 23874;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CHECK_EN = 23875;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_LANE_PAIR_FAIL = 23876;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_LANE_PAIR_FAIL_LEN = 23877;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_DATA_EN = 23878;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_MODE = 23879;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_MODE_LEN = 23880;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_4TO1_MODE = 23881;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_RESET = 23882;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_GEN_EN = 23883;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_CLEAR_ERROR = 23884;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0_01_TEST_CHECK_EN = 23885;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_LANE_PAIR_FAIL = 23886;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_LANE_PAIR_FAIL_LEN = 23887;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_DATA_EN = 23888;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_MODE = 23889;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_MODE_LEN = 23890;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_4TO1_MODE = 23891;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_RESET = 23892;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_GEN_EN = 23893;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_CLEAR_ERROR = 23894;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1_01_TEST_CHECK_EN = 23895;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL = 23896;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL_LEN = 23897;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_DATA_EN = 23898;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE = 23899;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE_LEN = 23900;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_4TO1_MODE = 23901;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_RESET = 23902;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_GEN_EN = 23903;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CLEAR_ERROR = 23904;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CHECK_EN = 23905;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL = 23906;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL_LEN = 23907;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_DATA_EN = 23908;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE = 23909;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE_LEN = 23910;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_4TO1_MODE = 23911;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_RESET = 23912;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_GEN_EN = 23913;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CLEAR_ERROR = 23914;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CHECK_EN = 23915;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_LANE_PAIR_FAIL = 23916;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_LANE_PAIR_FAIL_LEN = 23917;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_DATA_EN = 23918;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_MODE = 23919;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_MODE_LEN = 23920;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_4TO1_MODE = 23921;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_RESET = 23922;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_GEN_EN = 23923;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_CLEAR_ERROR = 23924;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2_23_TEST_CHECK_EN = 23925;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_LANE_PAIR_FAIL = 23926;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_LANE_PAIR_FAIL_LEN = 23927;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_DATA_EN = 23928;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_MODE = 23929;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_MODE_LEN = 23930;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_4TO1_MODE = 23931;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_RESET = 23932;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_GEN_EN = 23933;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_CLEAR_ERROR = 23934;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3_23_TEST_CHECK_EN = 23935;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR1 = 23936;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR2_ADR3 = 23937;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR4_ADR5 = 23938;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR6_ADR7 = 23939;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR8_ADR9 = 23940;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR10_ADR11 = 23941;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR12_ADR13 = 23942;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR14_ADR15 = 23943;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR0 = 23944;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR2_ADR3 = 23945;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR4_ADR5 = 23946;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR6_ADR7 = 23947;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR8_ADR9 = 23948;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR10_ADR11 = 23949;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR12_ADR13 = 23950;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR14_ADR15 = 23951;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR1 = 23952;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR2_ADR3 = 23953;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR4_ADR5 = 23954;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR6_ADR7 = 23955;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR8_ADR9 = 23956;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR10_ADR11 = 23957;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR12_ADR13 = 23958;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0_01_DI_ADR14_ADR15 = 23959;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR0 = 23960;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR2_ADR3 = 23961;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR4_ADR5 = 23962;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR6_ADR7 = 23963;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR8_ADR9 = 23964;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR10_ADR11 = 23965;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR12_ADR13 = 23966;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1_01_DI_ADR14_ADR15 = 23967;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR0_ADR1 = 23968;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR3 = 23969;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR4_ADR5 = 23970;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR6_ADR7 = 23971;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR8_ADR9 = 23972;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR10_ADR11 = 23973;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR12_ADR13 = 23974;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR14_ADR15 = 23975;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR0_ADR1 = 23976;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR2 = 23977;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR4_ADR5 = 23978;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR6_ADR7 = 23979;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR8_ADR9 = 23980;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR10_ADR11 = 23981;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR12_ADR13 = 23982;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR14_ADR15 = 23983;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR0_ADR1 = 23984;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR3 = 23985;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR4_ADR5 = 23986;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR6_ADR7 = 23987;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR8_ADR9 = 23988;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR10_ADR11 = 23989;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR12_ADR13 = 23990;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2_23_DI_ADR14_ADR15 = 23991;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR0_ADR1 = 23992;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR2 = 23993;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR4_ADR5 = 23994;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR6_ADR7 = 23995;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR8_ADR9 = 23996;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR10_ADR11 = 23997;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR12_ADR13 = 23998;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3_23_DI_ADR14_ADR15 = 23999;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL0 = 24000;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL0_LEN = 24001;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1 = 24002;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1_LEN = 24003;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2 = 24004;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2_LEN = 24005;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3 = 24006;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3_LEN = 24007;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4 = 24008;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4_LEN = 24009;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5 = 24010;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5_LEN = 24011;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6 = 24012;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6_LEN = 24013;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7 = 24014;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7_LEN = 24015;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL0 = 24016;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL0_LEN = 24017;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1 = 24018;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1_LEN = 24019;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2 = 24020;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2_LEN = 24021;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3 = 24022;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3_LEN = 24023;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4 = 24024;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4_LEN = 24025;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5 = 24026;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5_LEN = 24027;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6 = 24028;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6_LEN = 24029;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7 = 24030;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7_LEN = 24031;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL0 = 24032;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL0_LEN = 24033;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL1 = 24034;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL1_LEN = 24035;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL2 = 24036;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL2_LEN = 24037;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL3 = 24038;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL3_LEN = 24039;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL4 = 24040;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL4_LEN = 24041;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL5 = 24042;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL5_LEN = 24043;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL6 = 24044;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL6_LEN = 24045;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL7 = 24046;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_01_SEL7_LEN = 24047;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL0 = 24048;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL0_LEN = 24049;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL1 = 24050;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL1_LEN = 24051;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL2 = 24052;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL2_LEN = 24053;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL3 = 24054;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL3_LEN = 24055;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL4 = 24056;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL4_LEN = 24057;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL5 = 24058;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL5_LEN = 24059;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL6 = 24060;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL6_LEN = 24061;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL7 = 24062;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_01_SEL7_LEN = 24063;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL0 = 24064;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL0_LEN = 24065;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1 = 24066;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1_LEN = 24067;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2 = 24068;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2_LEN = 24069;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3 = 24070;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3_LEN = 24071;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4 = 24072;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4_LEN = 24073;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5 = 24074;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5_LEN = 24075;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6 = 24076;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6_LEN = 24077;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7 = 24078;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7_LEN = 24079;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL0 = 24080;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL0_LEN = 24081;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1 = 24082;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1_LEN = 24083;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2 = 24084;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2_LEN = 24085;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3 = 24086;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3_LEN = 24087;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4 = 24088;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4_LEN = 24089;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5 = 24090;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5_LEN = 24091;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6 = 24092;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6_LEN = 24093;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7 = 24094;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7_LEN = 24095;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL0 = 24096;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL0_LEN = 24097;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL1 = 24098;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL1_LEN = 24099;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL2 = 24100;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL2_LEN = 24101;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL3 = 24102;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL3_LEN = 24103;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL4 = 24104;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL4_LEN = 24105;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL5 = 24106;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL5_LEN = 24107;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL6 = 24108;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL6_LEN = 24109;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL7 = 24110;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_23_SEL7_LEN = 24111;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL0 = 24112;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL0_LEN = 24113;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL1 = 24114;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL1_LEN = 24115;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL2 = 24116;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL2_LEN = 24117;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL3 = 24118;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL3_LEN = 24119;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL4 = 24120;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL4_LEN = 24121;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL5 = 24122;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL5_LEN = 24123;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL6 = 24124;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL6_LEN = 24125;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL7 = 24126;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_23_SEL7_LEN = 24127;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL8 = 24128;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL8_LEN = 24129;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9 = 24130;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9_LEN = 24131;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10 = 24132;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10_LEN = 24133;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11 = 24134;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11_LEN = 24135;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12 = 24136;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12_LEN = 24137;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13 = 24138;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13_LEN = 24139;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14 = 24140;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14_LEN = 24141;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15 = 24142;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15_LEN = 24143;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL8 = 24144;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL8_LEN = 24145;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9 = 24146;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9_LEN = 24147;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10 = 24148;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10_LEN = 24149;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11 = 24150;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11_LEN = 24151;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12 = 24152;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12_LEN = 24153;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13 = 24154;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13_LEN = 24155;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14 = 24156;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14_LEN = 24157;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15 = 24158;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15_LEN = 24159;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL8 = 24160;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL8_LEN = 24161;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL9 = 24162;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL9_LEN = 24163;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL10 = 24164;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL10_LEN = 24165;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL11 = 24166;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL11_LEN = 24167;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL12 = 24168;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL12_LEN = 24169;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL13 = 24170;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL13_LEN = 24171;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL14 = 24172;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL14_LEN = 24173;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL15 = 24174;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_01_SEL15_LEN = 24175;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL8 = 24176;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL8_LEN = 24177;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL9 = 24178;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL9_LEN = 24179;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL10 = 24180;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL10_LEN = 24181;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL11 = 24182;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL11_LEN = 24183;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL12 = 24184;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL12_LEN = 24185;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL13 = 24186;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL13_LEN = 24187;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL14 = 24188;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL14_LEN = 24189;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL15 = 24190;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_01_SEL15_LEN = 24191;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL8 = 24192;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL8_LEN = 24193;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9 = 24194;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9_LEN = 24195;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10 = 24196;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10_LEN = 24197;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11 = 24198;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11_LEN = 24199;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12 = 24200;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12_LEN = 24201;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13 = 24202;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13_LEN = 24203;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14 = 24204;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14_LEN = 24205;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15 = 24206;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15_LEN = 24207;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL8 = 24208;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL8_LEN = 24209;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9 = 24210;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9_LEN = 24211;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10 = 24212;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10_LEN = 24213;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11 = 24214;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11_LEN = 24215;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12 = 24216;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12_LEN = 24217;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13 = 24218;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13_LEN = 24219;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14 = 24220;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14_LEN = 24221;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15 = 24222;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15_LEN = 24223;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL8 = 24224;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL8_LEN = 24225;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL9 = 24226;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL9_LEN = 24227;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL10 = 24228;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL10_LEN = 24229;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL11 = 24230;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL11_LEN = 24231;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL12 = 24232;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL12_LEN = 24233;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL13 = 24234;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL13_LEN = 24235;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL14 = 24236;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL14_LEN = 24237;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL15 = 24238;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_23_SEL15_LEN = 24239;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL8 = 24240;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL8_LEN = 24241;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL9 = 24242;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL9_LEN = 24243;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL10 = 24244;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL10_LEN = 24245;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL11 = 24246;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL11_LEN = 24247;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL12 = 24248;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL12_LEN = 24249;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL13 = 24250;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL13_LEN = 24251;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL14 = 24252;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL14_LEN = 24253;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL15 = 24254;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_23_SEL15_LEN = 24255;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL0 = 24256;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL0_LEN = 24257;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL1 = 24258;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL1_LEN = 24259;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL2 = 24260;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL2_LEN = 24261;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL3 = 24262;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL3_LEN = 24263;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL4 = 24264;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL4_LEN = 24265;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL5 = 24266;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL5_LEN = 24267;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL6 = 24268;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL6_LEN = 24269;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL7 = 24270;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL7_LEN = 24271;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL0 = 24272;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL0_LEN = 24273;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL1 = 24274;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL1_LEN = 24275;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL2 = 24276;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL2_LEN = 24277;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL3 = 24278;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL3_LEN = 24279;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL4 = 24280;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL4_LEN = 24281;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL5 = 24282;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL5_LEN = 24283;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL6 = 24284;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL6_LEN = 24285;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL7 = 24286;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL7_LEN = 24287;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL0 = 24288;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL0_LEN = 24289;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL1 = 24290;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL1_LEN = 24291;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL2 = 24292;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL2_LEN = 24293;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL3 = 24294;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL3_LEN = 24295;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL4 = 24296;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL4_LEN = 24297;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL5 = 24298;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL5_LEN = 24299;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL6 = 24300;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL6_LEN = 24301;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL7 = 24302;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0_01_SEL7_LEN = 24303;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL0 = 24304;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL0_LEN = 24305;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL1 = 24306;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL1_LEN = 24307;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL2 = 24308;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL2_LEN = 24309;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL3 = 24310;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL3_LEN = 24311;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL4 = 24312;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL4_LEN = 24313;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL5 = 24314;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL5_LEN = 24315;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL6 = 24316;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL6_LEN = 24317;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL7 = 24318;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1_01_SEL7_LEN = 24319;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL0 = 24320;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL0_LEN = 24321;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL1 = 24322;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL1_LEN = 24323;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL2 = 24324;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL2_LEN = 24325;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL3 = 24326;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL3_LEN = 24327;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL4 = 24328;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL4_LEN = 24329;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL5 = 24330;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL5_LEN = 24331;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL6 = 24332;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL6_LEN = 24333;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL7 = 24334;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL7_LEN = 24335;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL0 = 24336;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL0_LEN = 24337;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL1 = 24338;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL1_LEN = 24339;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL2 = 24340;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL2_LEN = 24341;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL3 = 24342;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL3_LEN = 24343;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL4 = 24344;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL4_LEN = 24345;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL5 = 24346;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL5_LEN = 24347;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL6 = 24348;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL6_LEN = 24349;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL7 = 24350;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL7_LEN = 24351;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL0 = 24352;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL0_LEN = 24353;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL1 = 24354;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL1_LEN = 24355;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL2 = 24356;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL2_LEN = 24357;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL3 = 24358;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL3_LEN = 24359;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL4 = 24360;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL4_LEN = 24361;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL5 = 24362;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL5_LEN = 24363;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL6 = 24364;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL6_LEN = 24365;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL7 = 24366;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2_23_SEL7_LEN = 24367;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL0 = 24368;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL0_LEN = 24369;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL1 = 24370;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL1_LEN = 24371;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL2 = 24372;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL2_LEN = 24373;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL3 = 24374;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL3_LEN = 24375;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL4 = 24376;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL4_LEN = 24377;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL5 = 24378;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL5_LEN = 24379;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL6 = 24380;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL6_LEN = 24381;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL7 = 24382;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3_23_SEL7_LEN = 24383;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL8 = 24384;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL8_LEN = 24385;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL9 = 24386;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL9_LEN = 24387;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL10 = 24388;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL10_LEN = 24389;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL11 = 24390;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL11_LEN = 24391;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL12 = 24392;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL12_LEN = 24393;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL13 = 24394;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL13_LEN = 24395;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL14 = 24396;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL14_LEN = 24397;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL15 = 24398;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL15_LEN = 24399;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL8 = 24400;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL8_LEN = 24401;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL9 = 24402;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL9_LEN = 24403;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL10 = 24404;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL10_LEN = 24405;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL11 = 24406;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL11_LEN = 24407;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL12 = 24408;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL12_LEN = 24409;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL13 = 24410;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL13_LEN = 24411;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL14 = 24412;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL14_LEN = 24413;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL15 = 24414;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL15_LEN = 24415;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL8 = 24416;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL8_LEN = 24417;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL9 = 24418;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL9_LEN = 24419;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL10 = 24420;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL10_LEN = 24421;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL11 = 24422;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL11_LEN = 24423;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL12 = 24424;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL12_LEN = 24425;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL13 = 24426;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL13_LEN = 24427;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL14 = 24428;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL14_LEN = 24429;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL15 = 24430;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0_01_SEL15_LEN = 24431;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL8 = 24432;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL8_LEN = 24433;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL9 = 24434;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL9_LEN = 24435;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL10 = 24436;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL10_LEN = 24437;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL11 = 24438;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL11_LEN = 24439;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL12 = 24440;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL12_LEN = 24441;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL13 = 24442;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL13_LEN = 24443;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL14 = 24444;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL14_LEN = 24445;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL15 = 24446;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1_01_SEL15_LEN = 24447;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL8 = 24448;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL8_LEN = 24449;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL9 = 24450;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL9_LEN = 24451;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL10 = 24452;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL10_LEN = 24453;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL11 = 24454;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL11_LEN = 24455;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL12 = 24456;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL12_LEN = 24457;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL13 = 24458;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL13_LEN = 24459;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL14 = 24460;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL14_LEN = 24461;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL15 = 24462;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL15_LEN = 24463;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL8 = 24464;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL8_LEN = 24465;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL9 = 24466;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL9_LEN = 24467;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL10 = 24468;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL10_LEN = 24469;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL11 = 24470;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL11_LEN = 24471;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL12 = 24472;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL12_LEN = 24473;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL13 = 24474;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL13_LEN = 24475;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL14 = 24476;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL14_LEN = 24477;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL15 = 24478;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL15_LEN = 24479;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL8 = 24480;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL8_LEN = 24481;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL9 = 24482;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL9_LEN = 24483;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL10 = 24484;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL10_LEN = 24485;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL11 = 24486;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL11_LEN = 24487;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL12 = 24488;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL12_LEN = 24489;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL13 = 24490;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL13_LEN = 24491;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL14 = 24492;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL14_LEN = 24493;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL15 = 24494;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2_23_SEL15_LEN = 24495;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL8 = 24496;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL8_LEN = 24497;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL9 = 24498;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL9_LEN = 24499;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL10 = 24500;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL10_LEN = 24501;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL11 = 24502;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL11_LEN = 24503;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL12 = 24504;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL12_LEN = 24505;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL13 = 24506;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL13_LEN = 24507;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL14 = 24508;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL14_LEN = 24509;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL15 = 24510;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3_23_SEL15_LEN = 24511;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL0 = 24512;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL0_LEN = 24513;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL1 = 24514;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL1_LEN = 24515;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL2 = 24516;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL2_LEN = 24517;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL3 = 24518;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_01_CTL3_LEN = 24519;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL0 = 24520;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL0_LEN = 24521;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL1 = 24522;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL1_LEN = 24523;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL2 = 24524;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL2_LEN = 24525;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL3 = 24526;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_01_CTL3_LEN = 24527;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL0 = 24528;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL0_LEN = 24529;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL1 = 24530;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL1_LEN = 24531;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL2 = 24532;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL2_LEN = 24533;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL3 = 24534;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_01_CTL3_LEN = 24535;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL0 = 24536;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL0_LEN = 24537;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL1 = 24538;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL1_LEN = 24539;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL2 = 24540;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL2_LEN = 24541;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL3 = 24542;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_01_CTL3_LEN = 24543;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL0 = 24544;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL0_LEN = 24545;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL1 = 24546;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL1_LEN = 24547;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL2 = 24548;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL2_LEN = 24549;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL3 = 24550;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_23_CTL3_LEN = 24551;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL0 = 24552;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL0_LEN = 24553;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL1 = 24554;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL1_LEN = 24555;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL2 = 24556;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL2_LEN = 24557;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL3 = 24558;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_23_CTL3_LEN = 24559;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL0 = 24560;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL0_LEN = 24561;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL1 = 24562;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL1_LEN = 24563;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL2 = 24564;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL2_LEN = 24565;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL3 = 24566;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_23_CTL3_LEN = 24567;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL0 = 24568;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL0_LEN = 24569;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL1 = 24570;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL1_LEN = 24571;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL2 = 24572;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL2_LEN = 24573;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL3 = 24574;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_23_CTL3_LEN = 24575;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS = 24576;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS_LEN = 24577;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS = 24578;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS_LEN = 24579;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S0_ADR0_TSYS = 24580;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S0_ADR0_TSYS_LEN = 24581;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S1_ADR1_TSYS = 24582;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S1_ADR1_TSYS_LEN = 24583;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE = 24584;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE_LEN = 24585;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE = 24586;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE_LEN = 24587;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S0_ADR0_VALUE = 24588;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S0_ADR0_VALUE_LEN = 24589;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S1_ADR1_VALUE = 24590;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S1_ADR1_VALUE_LEN = 24591;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE = 24592;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE_LEN = 24593;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE = 24594;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE_LEN = 24595;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S0_ADR0_VALUE = 24596;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S0_ADR0_VALUE_LEN = 24597;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S1_ADR1_VALUE = 24598;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S1_ADR1_VALUE_LEN = 24599;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_FLUSH = 24600;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_EN = 24601;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_TOXDRV_HIBERNATE = 24602;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATEST1CTL_EN = 24603;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL = 24604;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_LEN = 24605;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL = 24606;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_LEN = 24607;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATEST1CTL0 = 24608;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATEST1CTL1 = 24609;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATEST1CTL2 = 24610;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATEST1CTL3 = 24611;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_FLUSH = 24612;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_EN = 24613;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_TOXDRV_HIBERNATE = 24614;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATEST1CTL_EN = 24615;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL = 24616;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_LEN = 24617;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL = 24618;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_LEN = 24619;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATEST1CTL0 = 24620;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATEST1CTL1 = 24621;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATEST1CTL2 = 24622;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATEST1CTL3 = 24623;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_FLUSH = 24624;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_EN = 24625;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_TOXDRV_HIBERNATE = 24626;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_ATEST1CTL_EN = 24627;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_HS_PROBE_A_SEL = 24628;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_HS_PROBE_A_SEL_LEN = 24629;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_HS_PROBE_B_SEL = 24630;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_HS_PROBE_B_SEL_LEN = 24631;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_ATEST1CTL0 = 24632;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_ATEST1CTL1 = 24633;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_ATEST1CTL2 = 24634;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_ADR0_ATEST1CTL3 = 24635;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_FLUSH = 24636;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_EN = 24637;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_TOXDRV_HIBERNATE = 24638;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_ATEST1CTL_EN = 24639;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_HS_PROBE_A_SEL = 24640;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_HS_PROBE_A_SEL_LEN = 24641;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_HS_PROBE_B_SEL = 24642;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_HS_PROBE_B_SEL_LEN = 24643;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_ATEST1CTL0 = 24644;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_ATEST1CTL1 = 24645;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_ATEST1CTL2 = 24646;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_ADR1_ATEST1CTL3 = 24647;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNE_2 = 24648;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNE_2_LEN = 24649;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNECP_2 = 24650;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNECP_2_LEN = 24651;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNEF_5 = 24652;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNEF_5_LEN = 24653;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNEVCO_1 = 24654;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_TUNEVCO_1_LEN = 24655;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_PLLXTR_1 = 24656;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_ADR0_PLLXTR_1_LEN = 24657;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNE_2 = 24658;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNE_2_LEN = 24659;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNECP_2 = 24660;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNECP_2_LEN = 24661;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNEF_5 = 24662;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNEF_5_LEN = 24663;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNEVCO_1 = 24664;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_TUNEVCO_1_LEN = 24665;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_PLLXTR_1 = 24666;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_ADR1_PLLXTR_1_LEN = 24667;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNE_2 = 24668;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNE_2_LEN = 24669;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNECP_2 = 24670;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNECP_2_LEN = 24671;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNEF_5 = 24672;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNEF_5_LEN = 24673;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNEVCO_1 = 24674;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_TUNEVCO_1_LEN = 24675;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_PLLXTR_1 = 24676;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_ADR0_PLLXTR_1_LEN = 24677;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNE_2 = 24678;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNE_2_LEN = 24679;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNECP_2 = 24680;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNECP_2_LEN = 24681;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNEF_5 = 24682;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNEF_5_LEN = 24683;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNEVCO_1 = 24684;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_TUNEVCO_1_LEN = 24685;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_PLLXTR_1 = 24686;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_ADR1_PLLXTR_1_LEN = 24687;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_TUNETDIV_0_2 = 24688;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_TUNETDIV_0_2_LEN = 24689;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_TUNEMDIV_0 = 24690;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_TUNEMDIV_0_LEN = 24691;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_TUNEATST = 24692;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_RANGE_0 = 24693;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_RANGE_0_LEN = 24694;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_VCCTUNE_0 = 24695;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_VCCTUNE_0_LEN = 24696;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3 = 24697;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3_LEN = 24698;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ANALOG_WRAPON = 24699;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_TUNETDIV_0_2 = 24700;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_TUNETDIV_0_2_LEN = 24701;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_TUNEMDIV_0 = 24702;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_TUNEMDIV_0_LEN = 24703;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_TUNEATST = 24704;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_RANGE_0 = 24705;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_RANGE_0_LEN = 24706;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_VCCTUNE_0 = 24707;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_VCCTUNE_0_LEN = 24708;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3 = 24709;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3_LEN = 24710;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ANALOG_WRAPON = 24711;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_TUNETDIV_0_2 = 24712;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_TUNETDIV_0_2_LEN = 24713;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_TUNEMDIV_0 = 24714;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_TUNEMDIV_0_LEN = 24715;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_TUNEATST = 24716;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_RANGE_0 = 24717;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_RANGE_0_LEN = 24718;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_VCCTUNE_0 = 24719;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_VCCTUNE_0_LEN = 24720;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3 = 24721;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3_LEN = 24722;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_ADR0_ANALOG_WRAPON = 24723;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_TUNETDIV_0_2 = 24724;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_TUNETDIV_0_2_LEN = 24725;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_TUNEMDIV_0 = 24726;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_TUNEMDIV_0_LEN = 24727;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_TUNEATST = 24728;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_RANGE_0 = 24729;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_RANGE_0_LEN = 24730;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_VCCTUNE_0 = 24731;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_VCCTUNE_0_LEN = 24732;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3 = 24733;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3_LEN = 24734;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_ADR1_ANALOG_WRAPON = 24735;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_11_PD = 24736;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_11_PD_LEN = 24737;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD = 24738;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD_LEN = 24739;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_11_PD = 24740;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_11_PD_LEN = 24741;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD = 24742;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD_LEN = 24743;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR0_01_LANE__0_11_PD = 24744;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR0_01_LANE__0_11_PD_LEN = 24745;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR0_01_LANE__12_15_PD = 24746;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR0_01_LANE__12_15_PD_LEN = 24747;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR1_01_LANE__0_11_PD = 24748;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR1_01_LANE__0_11_PD_LEN = 24749;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR1_01_LANE__12_15_PD = 24750;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR1_01_LANE__12_15_PD_LEN = 24751;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_11_PD = 24752;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_11_PD_LEN = 24753;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD = 24754;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD_LEN = 24755;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_11_PD = 24756;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_11_PD_LEN = 24757;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD = 24758;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD_LEN = 24759;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR2_23_LANE__0_11_PD = 24760;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR2_23_LANE__0_11_PD_LEN = 24761;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR2_23_LANE__12_15_PD = 24762;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR2_23_LANE__12_15_PD_LEN = 24763;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR3_23_LANE__0_11_PD = 24764;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR3_23_LANE__0_11_PD_LEN = 24765;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR3_23_LANE__12_15_PD = 24766;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_POWERDOWN_2_P1_ADR3_23_LANE__12_15_PD_LEN = 24767;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_ENABLE = 24768;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_START = 24769;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE_EN = 24770;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE = 24771;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE_LEN = 24772;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_TARGET_PR_OFFSET = 24773;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_TARGET_PR_OFFSET_LEN = 24774;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_ENABLE = 24775;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_START = 24776;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE_EN = 24777;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE = 24778;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE_LEN = 24779;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET = 24780;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET_LEN = 24781;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_ADR0_ENABLE = 24782;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_ADR0_START = 24783;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_ADR0_OVERRIDE_EN = 24784;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_ADR0_OVERRIDE = 24785;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_ADR0_OVERRIDE_LEN = 24786;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_ADR0_TARGET_PR_OFFSET = 24787;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_ADR0_TARGET_PR_OFFSET_LEN = 24788;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_ADR1_ENABLE = 24789;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_ADR1_START = 24790;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_ADR1_OVERRIDE_EN = 24791;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_ADR1_OVERRIDE = 24792;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_ADR1_OVERRIDE_LEN = 24793;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_ADR1_TARGET_PR_OFFSET = 24794;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_ADR1_TARGET_PR_OFFSET_LEN = 24795;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ENABLE = 24796;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE = 24797;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_LEN = 24798;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_EN = 24799;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_ALIGN_RESET = 24800;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_EN = 24801;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_DEFAULT_EN = 24802;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_POS_EDGE_ALIGN = 24803;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CONTINUOUS_UPDATE = 24804;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CE0DLTVCC = 24805;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CE0DLTVCC_LEN = 24806;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ENABLE = 24807;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE = 24808;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_LEN = 24809;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_EN = 24810;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_ALIGN_RESET = 24811;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_EN = 24812;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_DEFAULT_EN = 24813;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_POS_EDGE_ALIGN = 24814;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_CONTINUOUS_UPDATE = 24815;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_CE0DLTVCC = 24816;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_CE0DLTVCC_LEN = 24817;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_ENABLE = 24818;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_ROT_OVERRIDE = 24819;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_ROT_OVERRIDE_LEN = 24820;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_ROT_OVERRIDE_EN = 24821;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_PHASE_ALIGN_RESET = 24822;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_PHASE_EN = 24823;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_PHASE_DEFAULT_EN = 24824;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_POS_EDGE_ALIGN = 24825;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_CONTINUOUS_UPDATE = 24826;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_CE0DLTVCC = 24827;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_ADR0_CE0DLTVCC_LEN = 24828;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_ENABLE = 24829;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_ROT_OVERRIDE = 24830;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_ROT_OVERRIDE_LEN = 24831;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_ROT_OVERRIDE_EN = 24832;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_PHASE_ALIGN_RESET = 24833;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_PHASE_EN = 24834;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_PHASE_DEFAULT_EN = 24835;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_POS_EDGE_ALIGN = 24836;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_CONTINUOUS_UPDATE = 24837;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_CE0DLTVCC = 24838;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_ADR1_CE0DLTVCC_LEN = 24839;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_LATE_SAMPLE = 24840;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT = 24841;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT_LEN = 24842;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK = 24843;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_EARLY_SAMPLE = 24844;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS = 24845;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS_LEN = 24846;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_CNTL = 24847;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_CNTL_LEN = 24848;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_LATE_SAMPLE = 24849;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT = 24850;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT_LEN = 24851;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_BB_LOCK = 24852;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_EARLY_SAMPLE = 24853;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS = 24854;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS_LEN = 24855;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_CNTL = 24856;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_CNTL_LEN = 24857;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_SLEW_LATE_SAMPLE = 24858;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_ROT = 24859;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_ROT_LEN = 24860;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_BB_LOCK = 24861;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_SLEW_EARLY_SAMPLE = 24862;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_SLEW_DONE_STATUS = 24863;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_SLEW_DONE_STATUS_LEN = 24864;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_SLEW_CNTL = 24865;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_ADR0_SLEW_CNTL_LEN = 24866;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_SLEW_LATE_SAMPLE = 24867;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_ROT = 24868;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_ROT_LEN = 24869;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_BB_LOCK = 24870;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_SLEW_EARLY_SAMPLE = 24871;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_SLEW_DONE_STATUS = 24872;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_SLEW_DONE_STATUS_LEN = 24873;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_SLEW_CNTL = 24874;
static const uint64_t IDX_CEN_MBA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_ADR1_SLEW_CNTL_LEN = 24875;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION0_REG_DDR0 = 24876;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION0_REG_DDR0_LEN = 24877;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION0_REG_DDR1 = 24878;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION0_REG_DDR1_LEN = 24879;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION1_REG_DDR0 = 24880;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION1_REG_DDR0_LEN = 24881;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION1_REG_DDR1 = 24882;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_ACTION1_REG_DDR1_LEN = 24883;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR0_FSM_CKSTP = 24884;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR0_PARITY_CKSTP = 24885;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR0_CALIBRATION_ERROR = 24886;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR0_FSM_ERR = 24887;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR0_PARITY_ERR = 24888;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR01_PARITY_ERR = 24889;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR1_FSM_CKSTP = 24890;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR1_PARITY_CKSTP = 24891;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR1_CALIBRATION_ERROR = 24892;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR1_FSM_ERR = 24893;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_MASK_REG_DDR1_PARITY_ERR = 24894;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR0_FSM_CKSTP = 24895;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR0_PARITY_CKSTP = 24896;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR0_CALIBRATION_ERROR = 24897;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR0_FSM_ERR = 24898;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR0_PARITY_ERR = 24899;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR01_PARITY_ERR = 24900;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR1_FSM_CKSTP = 24901;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR1_PARITY_CKSTP = 24902;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR1_CALIBRATION_ERROR = 24903;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR1_FSM_ERR = 24904;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_REG_DDR1_PARITY_ERR = 24905;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_WOF_REG_DDR0 = 24906;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_WOF_REG_DDR0_LEN = 24907;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_WOF_REG_DDR1 = 24908;
static const uint64_t IDX_CEN_MBA_PHY01_DDRPHY_FIR_WOF_REG_DDR1_LEN = 24909;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_ISLE_XSTOP_MASK_B = 24910;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_PCB_XSTOP_MASK_B = 24911;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_CLKSTP_EN = 24912;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_EDRAM_XSTOP_MASK_B = 24913;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_PLL_XSTOP_MASK_B = 24914;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_LOCAL_XSTOP_MASK_B = 24915;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_DISABLE_PCB_ITR = 24916;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_USE_FOR_SCAN = 24917;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_KEEP_EDRAM_ON_XSTOP = 24918;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_TRIGGER_OPCG_ON_XSTOP = 24919;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_SEL_EXT_OPCG_TRIGGER = 24920;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_LISTEN_TO_PULSE = 24921;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_CLK_START_ENABLE = 24922;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_CLK_STOP_ENABLE = 24923;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_CHIP_PROTECTION_ENABLE = 24924;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_SPARE15 = 24925;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_SPARE16 = 24926;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_SPARE17 = 24927;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_SPARE18 = 24928;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_SPARE19 = 24929;
static const uint64_t IDX_CEN_TCM_SYNC_CONFIG_SPARE20 = 24930;
static const uint64_t IDX_CEN_TCM_PHASE_SHADOW_COUNT_Q = 24931;
static const uint64_t IDX_CEN_TCM_PHASE_SHADOW_COUNT_Q_LEN = 24932;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_RUNN_MODE = 24933;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_GO = 24934;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_RUN_SCAN0 = 24935;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_SCAN0_MODE = 24936;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_SCAN_RATIO = 24937;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_SCAN_RATIO_LEN = 24938;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_INOP_FORCE_SG = 24939;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_INOP_ALIGN = 24940;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_INOP_ALIGN_LEN = 24941;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_INOP_WAIT = 24942;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_INOP_WAIT_LEN = 24943;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_SNOP_ALIGN = 24944;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_SNOP_ALIGN_LEN = 24945;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_SNOP_WAIT = 24946;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_SNOP_WAIT_LEN = 24947;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_ENOP_ALIGN = 24948;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_ENOP_ALIGN_LEN = 24949;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_ENOP_WAIT = 24950;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_ENOP_WAIT_LEN = 24951;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_ENOP_FORCE_SG = 24952;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_LOOP_COUNT = 24953;
static const uint64_t IDX_CEN_TCM_OPCG_REG0_LOOP_COUNT_LEN = 24954;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_COUNT = 24955;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_COUNT_LEN = 24956;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ01_01F = 24957;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ01_01F_LEN = 24958;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ02_02F = 24959;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ02_02F_LEN = 24960;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ03_03F = 24961;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ03_03F_LEN = 24962;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ04_04F = 24963;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ04_04F_LEN = 24964;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ05_05F = 24965;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ05_05F_LEN = 24966;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ06_06F = 24967;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ06_06F_LEN = 24968;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ07_07F = 24969;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ07_07F_LEN = 24970;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ08_08F = 24971;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ08_08F_LEN = 24972;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ09_01FBY2 = 24973;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ09_01FBY2_LEN = 24974;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ10_02FBY2 = 24975;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ10_02FBY2_LEN = 24976;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ11_03FBY2 = 24977;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ11_03FBY2_LEN = 24978;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ12_04FBY2 = 24979;
static const uint64_t IDX_CEN_TCM_OPCG_REG1_FUNC_CAPT_SEQ12_04FBY2_LEN = 24980;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_SCAN_COUNT = 24981;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_SCAN_COUNT_LEN = 24982;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_MISR_A_VAL = 24983;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_MISR_A_VAL_LEN = 24984;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_MISR_B_VAL = 24985;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_MISR_B_VAL_LEN = 24986;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_MISR_INIT_WAIT = 24987;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_MISR_INIT_WAIT_LEN = 24988;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_SUPPRESS_EVEN_CLK = 24989;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_PAD_VALUE = 24990;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_PAD_VALUE_LEN = 24991;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_USE_F_AND_FDIV2 = 24992;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_USE_ARY_CLK_DURING_FILL = 24993;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_SG_HIGH_DURING_FILL = 24994;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_RTIM_THOLD_FORCE = 24995;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_LBIST_SKITTER_CTL = 24996;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_MISR_MODE = 24997;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_INFINITE_MODE = 24998;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_NSL_FILL_COUNT = 24999;
static const uint64_t IDX_CEN_TCM_OPCG_REG2_NSL_FILL_COUNT_LEN = 25000;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_GO2 = 25001;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_RUN_ON_UPDATE_DR = 25002;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_RUN_ON_CAPTURE_DR = 25003;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_ALIGN_SOURCE_SELECT = 25004;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_ALIGN_SOURCE_SELECT_LEN = 25005;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_WEIGHTING = 25006;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_WEIGHTING_LEN = 25007;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_VALUE = 25008;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_VALUE_LEN = 25009;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_EXTEND_INOPW_ENOPW = 25010;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_EXTEND_SNOPW = 25011;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_FORCE_SG_HIGH_DURING_SNOP = 25012;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_CHKSW = 25013;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_CHKSW_LEN = 25014;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_A_VAL = 25015;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_A_VAL_LEN = 25016;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_B_VAL = 25017;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_B_VAL_LEN = 25018;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_PRPG_MODE = 25019;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_SCAN_CLK_USE_EVEN = 25020;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_SPARE3 = 25021;
static const uint64_t IDX_CEN_TCM_OPCG_REG3_SPARE3_LEN = 25022;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_CMD = 25023;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_CMD_LEN = 25024;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_PERV = 25025;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_FASTUNIT0 = 25026;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_FASTUNIT1 = 25027;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_UNIT2 = 25028;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_UNIT3 = 25029;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_UNIT4 = 25030;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_UNIT5 = 25031;
static const uint64_t IDX_CEN_TCM_CLK_REGION_CLOCK_PLL = 25032;
static const uint64_t IDX_CEN_TCM_CLK_REGION_SEL_THOLD_SL = 25033;
static const uint64_t IDX_CEN_TCM_CLK_REGION_SEL_THOLD_NSL = 25034;
static const uint64_t IDX_CEN_TCM_CLK_REGION_SEL_THOLD_ARY = 25035;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_VITL = 25036;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_PERV = 25037;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_FASTUNIT0 = 25038;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_FASTUNIT1 = 25039;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_UNIT2 = 25040;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_UNIT3 = 25041;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_UNIT4 = 25042;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_UNIT5 = 25043;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CLK_PLL = 25044;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_FUNC = 25045;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CFG = 25046;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CCFG_GPTR = 25047;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_REGF = 25048;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_LBIST = 25049;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_ABIST = 25050;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_REPR = 25051;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_TIME = 25052;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_BNDY_FARY = 25053;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_FARR = 25054;
static const uint64_t IDX_CEN_TCM_SCANSELQ_SCANSEL_CMSK = 25055;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_PERV_FUNC_SL = 25056;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_PERV_FUNC_NSL = 25057;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_PERV_ARY_NSL = 25058;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT0_ODD_FUNC_SL = 25059;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT0_EVEN_FUNC_SL = 25060;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT0_ODD_FUNC_NSL = 25061;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT0_EVEN_FUNC_NSL = 25062;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT0_ODD_ARY_NSL = 25063;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT0_EVEN_ARY_NSL = 25064;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT1_ODD_FUNC_SL = 25065;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT1_EVEN_FUNC_SL = 25066;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT1_ODD_FUNC_NSL = 25067;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT1_EVEN_FUNC_NSL = 25068;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT1_ODD_ARY_NSL = 25069;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_FASTUNIT1_EVEN_ARY_NSL = 25070;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT2_FUNC_SL = 25071;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT2_FUNC_NSL = 25072;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT2_ARY_NSL = 25073;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT3_FUNC_SL = 25074;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT3_FUNC_NSL = 25075;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT3_ARY_NSL = 25076;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT4_FUNC_SL = 25077;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT4_FUNC_NSL = 25078;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT4_ARY_NSL = 25079;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT5_FUNC_SL = 25080;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT5_FUNC_NSL = 25081;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_UNIT5_ARY_NSL = 25082;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_PLL_FUNC_SL = 25083;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_PLL_FUNC_NSL = 25084;
static const uint64_t IDX_CEN_TCM_CLOCK_STAT_STATUS_PLL_ARY_NSL = 25085;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED = 25086;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_READ_NOT_ALLOWED = 25087;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_PARITY_ERR_ON_CMD = 25088;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_ADDRESS_NOT_VALID = 25089;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_PARITY_ADDR_ERR = 25090;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_PARITY_DATA_ERR = 25091;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID = 25092;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_PARITY_SPCIF_ERR = 25093;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PCB_WRITE_AND_OPCG = 25094;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_CLOCK_CMD_CONFLICT = 25095;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_SCAN_COLLISION = 25096;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_OPCG_TRIGGER = 25097;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_OPCG_PARITY = 25098;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_PHASE_CNT_CORRUPTED = 25099;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_CC_PAR_ERR = 25100;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_CC_PAR_ERR_LEN = 25101;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_GPIO_PAR_ERR = 25102;
static const uint64_t IDX_CEN_TCM_ERROR_STATUS_SECURITY_VIOLATION = 25103;
static const uint64_t IDX_CEN_TCM_CC_PROTECT_MODE_REG_READ_ENABLE = 25104;
static const uint64_t IDX_CEN_TCM_CC_PROTECT_MODE_REG_WRITE_ENABLE = 25105;
static const uint64_t IDX_CEN_TCM_CC_ATOMIC_LOCK_REG_ENABLE = 25106;
static const uint64_t IDX_CEN_TCM_CC_ATOMIC_LOCK_REG_ID = 25107;
static const uint64_t IDX_CEN_TCM_CC_ATOMIC_LOCK_REG_ID_LEN = 25108;
static const uint64_t IDX_CEN_TCM_GP0_TC_UNIT_ABSTCLK_MUXSEL_DC = 25109;
static const uint64_t IDX_CEN_TCM_GP0_TC_UNIT_SYNCCLK_MUXSEL_DC = 25110;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_FLUSHMODE_INH_DC_OUT = 25111;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_FORCEALIGN = 25112;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_AVP_MODE_DC_OUT = 25113;
static const uint64_t IDX_CEN_TCM_GP0_TC_ASIC_CORE_FORCETOKNOWN_DC = 25114;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_CC_SCAN_DIS_DC_B_OUT = 25115;
static const uint64_t IDX_CEN_TCM_GP0_TC_SKIT_MODE_BIST_DC = 25116;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_LBIST_EN_DC_OUT = 25117;
static const uint64_t IDX_CEN_TCM_GP0_TC_UNIT_LBIST_AC_MODE_DC = 25118;
static const uint64_t IDX_CEN_TCM_GP0_TC_UNIT_LBIST_ARY_WRT_THRU_DC = 25119;
static const uint64_t IDX_CEN_TCM_GP0_TC_ABIST_MODE_DC = 25120;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_ABIST_START_TEST_DC_OUT = 25121;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED0 = 25122;
static const uint64_t IDX_CEN_TCM_GP0_TC_UNIT_ATPG_EN_DC = 25123;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_SCAN_PROTECT_DC_OUT = 25124;
static const uint64_t IDX_CEN_TCM_GP0_TC_ASIC_CORE_FORCETOKNOWN2_DC = 25125;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED2 = 25126;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED3 = 25127;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED4 = 25128;
static const uint64_t IDX_CEN_TCM_GP0_TP_GPIO_TRACE_START = 25129;
static const uint64_t IDX_CEN_TCM_GP0_TP_GPIO_TRACE_STOP = 25130;
static const uint64_t IDX_CEN_TCM_GP0_TP_GPIO_TRACE_RESET = 25131;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED5 = 25132;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_CLKDIV_SEL_DC = 25133;
static const uint64_t IDX_CEN_TCM_GP0_TC_GPIO_CLKDIV_SEL_DC_LEN = 25134;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED6 = 25135;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED7 = 25136;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED8 = 25137;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED8_LEN = 25138;
static const uint64_t IDX_CEN_TCM_GP0_TC_PSRO_SEL_DC = 25139;
static const uint64_t IDX_CEN_TCM_GP0_TC_PSRO_SEL_DC_LEN = 25140;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED10 = 25141;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED10_LEN = 25142;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED11 = 25143;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED11_LEN = 25144;
static const uint64_t IDX_CEN_TCM_GP0_TC_PLLMEMIO_PADTEST_T_K = 25145;
static const uint64_t IDX_CEN_TCM_GP0_TC_PLLMEMIO_PADTEST_C_K = 25146;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED12 = 25147;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED13 = 25148;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED14 = 25149;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED15 = 25150;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED16 = 25151;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED17 = 25152;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED18 = 25153;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED19 = 25154;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED20 = 25155;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED21 = 25156;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED22 = 25157;
static const uint64_t IDX_CEN_TCM_GP0_NOT_USED23 = 25158;
static const uint64_t IDX_CEN_TCM_GP0_TC_MASK_CC_PCB_ERR_DC = 25159;
static const uint64_t IDX_CEN_TCM_GP0_TC_MASK_CC_SCAN_OPCG_ERR_DC = 25160;
static const uint64_t IDX_CEN_TCM_GP0_TC_CC_LCC_EDGE_DELAYED_DC = 25161;
static const uint64_t IDX_CEN_TCM_GP0_TC_FENCE_PERV_DC = 25162;
static const uint64_t IDX_CEN_TCM_GP1_MEMN_ABIST_DONE = 25163;
static const uint64_t IDX_CEN_TCM_GP1_MEMS_ABIST_DONE = 25164;
static const uint64_t IDX_CEN_TCM_GP1_TRA_ABIST_DONE = 25165;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED1 = 25166;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED9 = 25167;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED25 = 25168;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED26 = 25169;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED27 = 25170;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED28 = 25171;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED29 = 25172;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED30 = 25173;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED31 = 25174;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED32 = 25175;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED33 = 25176;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED34 = 25177;
static const uint64_t IDX_CEN_TCM_GP1_TC_OPCG_DONE_DC = 25178;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED35 = 25179;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED36 = 25180;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED37 = 25181;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED38 = 25182;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED39 = 25183;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED40 = 25184;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED41 = 25185;
static const uint64_t IDX_CEN_TCM_GP1_NOT_USED42 = 25186;
static const uint64_t IDX_CEN_TCM_GP2_GPIN_MASKING = 25187;
static const uint64_t IDX_CEN_TCM_GP2_GPIN_MASKING_LEN = 25188;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE0_SEL_DC = 25189;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE0_SEL_DC_LEN = 25190;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED43 = 25191;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED43_LEN = 25192;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE1_SEL_DC = 25193;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE1_SEL_DC_LEN = 25194;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED44 = 25195;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED44_LEN = 25196;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE2_SEL_DC = 25197;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE2_SEL_DC_LEN = 25198;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED45 = 25199;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED45_LEN = 25200;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE3_SEL_DC = 25201;
static const uint64_t IDX_CEN_TCM_GP4_TC_PROBE3_SEL_DC_LEN = 25202;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED46 = 25203;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED47 = 25204;
static const uint64_t IDX_CEN_TCM_GP4_TC_NBTI0_RING_SEL_DC_00 = 25205;
static const uint64_t IDX_CEN_TCM_GP4_TC_NBTI0_RING_SEL_DC_01 = 25206;
static const uint64_t IDX_CEN_TCM_GP4_TC_NBTI0_RING_SEL_DC_02 = 25207;
static const uint64_t IDX_CEN_TCM_GP4_TC_NBTI0_RING_SEL_DC_03 = 25208;
static const uint64_t IDX_CEN_TCM_GP4_TC_NBTI0_HDR_ENABLE_DC_B = 25209;
static const uint64_t IDX_CEN_TCM_GP4_TC_NBTI0_ACDC_STRESS_SELECT_DC = 25210;
static const uint64_t IDX_CEN_TCM_GP4_TC_NBTI0_STRESS_DC = 25211;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED48 = 25212;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED49 = 25213;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED50 = 25214;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED51 = 25215;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED52 = 25216;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED53 = 25217;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED54 = 25218;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED55 = 25219;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED56 = 25220;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED57 = 25221;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED58 = 25222;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED59 = 25223;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED60 = 25224;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED61 = 25225;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED62 = 25226;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED63 = 25227;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED64 = 25228;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED65 = 25229;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED66 = 25230;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED67 = 25231;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED68 = 25232;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED69 = 25233;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED70 = 25234;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED71 = 25235;
static const uint64_t IDX_CEN_TCM_GP4_NOT_USED72 = 25236;
static const uint64_t IDX_CEN_TCM_GPIO_PROTECT_MODE_REG_READ_ENABLE = 25237;
static const uint64_t IDX_CEN_TCM_GPIO_PROTECT_MODE_REG_WRITE_ENABLE = 25238;
static const uint64_t IDX_CEN_TCM_GPIO_ATOMIC_LOCK_REG_ENABLE = 25239;
static const uint64_t IDX_CEN_TCM_GPIO_ATOMIC_LOCK_REG_ID = 25240;
static const uint64_t IDX_CEN_TCM_GPIO_ATOMIC_LOCK_REG_ID_LEN = 25241;
static const uint64_t IDX_CEN_TCM_XFIR_IN0 = 25242;
static const uint64_t IDX_CEN_TCM_XFIR_IN1 = 25243;
static const uint64_t IDX_CEN_TCM_XFIR_IN2 = 25244;
static const uint64_t IDX_CEN_TCM_XFIR_IN3 = 25245;
static const uint64_t IDX_CEN_TCM_XFIR_IN4 = 25246;
static const uint64_t IDX_CEN_TCM_XFIR_IN5 = 25247;
static const uint64_t IDX_CEN_TCM_XFIR_IN6 = 25248;
static const uint64_t IDX_CEN_TCM_XFIR_IN7 = 25249;
static const uint64_t IDX_CEN_TCM_XFIR_IN8 = 25250;
static const uint64_t IDX_CEN_TCM_XFIR_IN9 = 25251;
static const uint64_t IDX_CEN_TCM_XFIR_IN10 = 25252;
static const uint64_t IDX_CEN_TCM_XFIR_IN11 = 25253;
static const uint64_t IDX_CEN_TCM_XFIR_IN12 = 25254;
static const uint64_t IDX_CEN_TCM_XFIR_IN13 = 25255;
static const uint64_t IDX_CEN_TCM_XFIR_IN14 = 25256;
static const uint64_t IDX_CEN_TCM_XFIR_IN15 = 25257;
static const uint64_t IDX_CEN_TCM_XFIR_IN15_LEN = 25258;
static const uint64_t IDX_CEN_TCM_XFIR_IN26 = 25259;
static const uint64_t IDX_CEN_TCM_RFIR_IN0 = 25260;
static const uint64_t IDX_CEN_TCM_RFIR_LFIR_RECOV_ERR = 25261;
static const uint64_t IDX_CEN_TCM_RFIR_IN = 25262;
static const uint64_t IDX_CEN_TCM_RFIR_IN_LEN = 25263;
static const uint64_t IDX_CEN_TCM_FIR_MASK_IN0 = 25264;
static const uint64_t IDX_CEN_TCM_FIR_MASK_IN1 = 25265;
static const uint64_t IDX_CEN_TCM_FIR_MASK_IN2 = 25266;
static const uint64_t IDX_CEN_TCM_FIR_MASK_IN3 = 25267;
static const uint64_t IDX_CEN_TCM_FIR_MASK_IN4 = 25268;
static const uint64_t IDX_CEN_TCM_FIR_MASK_IN4_LEN = 25269;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN0 = 25270;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN1 = 25271;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN2 = 25272;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN3 = 25273;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN4 = 25274;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN5 = 25275;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN6 = 25276;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN7 = 25277;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN8 = 25278;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN9 = 25279;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN10 = 25280;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN11 = 25281;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN12 = 25282;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN13 = 25283;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN14 = 25284;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN15 = 25285;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN15_LEN = 25286;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_IN40 = 25287;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 25288;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 25289;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR = 25290;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 25291;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_WATCHDOG_ENABLE = 25292;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 25293;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 25294;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_FORCE_ALL_RINGS = 25295;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 25296;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_RESERVED_LT = 25297;
static const uint64_t IDX_CEN_TCM_PSCOM_MODE_REG_RESERVED_LT_LEN = 25298;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 25299;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 25300;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 25301;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 25302;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 25303;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 25304;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 25305;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 25306;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 25307;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 25308;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 25309;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 25310;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 25311;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 25312;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 25313;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 25314;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 25315;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 25316;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 25317;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 25318;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 25319;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 25320;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 25321;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 25322;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 25323;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25324;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 25325;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 25326;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 25327;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 25328;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 25329;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 25330;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 25331;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 25332;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 25333;
static const uint64_t IDX_CEN_TCM_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 25334;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 25335;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 25336;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 25337;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_DL_RETURN_P0 = 25338;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 25339;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_UL_P0 = 25340;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 25341;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 25342;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 25343;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 25344;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 25345;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_MASK_PARALLEL_WRITE_NVLD = 25346;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_MASK_PARALLEL_READ_NVLD = 25347;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_MASK_PARALLEL_ADDR_INVALID = 25348;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 25349;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 25350;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 25351;
static const uint64_t IDX_CEN_TCM_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 25352;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 25353;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 25354;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 25355;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_RESERVED_LAST_LT = 25356;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 25357;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 25358;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 25359;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 25360;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 25361;
static const uint64_t IDX_CEN_TCM_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 25362;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN = 25363;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_TRACE_STATE_LAT = 25364;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN = 25365;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_TRACE_FREEZE = 25366;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_COND3_STATE_LT = 25367;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_COND3_STATE_LT_LEN = 25368;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_COND5_STATE_LT = 25369;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_COND5_STATE_LT_LEN = 25370;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT = 25371;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT = 25372;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT = 25373;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT = 25374;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT = 25375;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT = 25376;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_RESERVED_TCDBG_LT = 25377;
static const uint64_t IDX_CEN_TCM_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN = 25378;
static const uint64_t IDX_CEN_TCM_PSCOM_WRITE_PROTECT_REG_ENABLE_SERIAL_RING = 25379;
static const uint64_t IDX_CEN_TCM_PSCOM_WRITE_PROTECT_REG_RESERVED = 25380;
static const uint64_t IDX_CEN_TCM_ATOMIC_LOCK_REG_ENABLE = 25381;
static const uint64_t IDX_CEN_TCM_ATOMIC_LOCK_REG_ID = 25382;
static const uint64_t IDX_CEN_TCM_ATOMIC_LOCK_REG_ID_LEN = 25383;
static const uint64_t IDX_CEN_TCM_SPATTN_IN0 = 25384;
static const uint64_t IDX_CEN_TCM_SPATTN_IN1 = 25385;
static const uint64_t IDX_CEN_TCM_SPATTN_IN2 = 25386;
static const uint64_t IDX_CEN_TCM_SPATTN_IN2_LEN = 25387;
static const uint64_t IDX_CEN_TCM_SPA_MASK_IN = 25388;
static const uint64_t IDX_CEN_TCM_SPA_MASK_IN_LEN = 25389;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN0 = 25390;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN1 = 25391;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN2 = 25392;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN3 = 25393;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN4 = 25394;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN5 = 25395;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN6 = 25396;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN7 = 25397;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN8 = 25398;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN9 = 25399;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN10 = 25400;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN11 = 25401;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN = 25402;
static const uint64_t IDX_CEN_TCM_MODE_REG_IN_LEN = 25403;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_ACTION0_IN = 25404;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_ACTION0_IN_LEN = 25405;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_ACTION1_IN = 25406;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_ACTION1_IN_LEN = 25407;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_MASK_LFIR_IN = 25408;
static const uint64_t IDX_CEN_TCM_LOCAL_FIR_MASK_LFIR_IN_LEN = 25409;
static const uint64_t IDX_CEN_TCM_DTS_RESULT0_0_RESULT = 25410;
static const uint64_t IDX_CEN_TCM_DTS_RESULT0_0_RESULT_LEN = 25411;
static const uint64_t IDX_CEN_TCM_DTS_RESULT0_1_RESULT = 25412;
static const uint64_t IDX_CEN_TCM_DTS_RESULT0_1_RESULT_LEN = 25413;
static const uint64_t IDX_CEN_TCM_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 25414;
static const uint64_t IDX_CEN_TCM_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 25415;
static const uint64_t IDX_CEN_TCM_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 25416;
static const uint64_t IDX_CEN_TCM_DTS_TRC_RESULT_0_RESULT = 25417;
static const uint64_t IDX_CEN_TCM_DTS_TRC_RESULT_0_RESULT_LEN = 25418;
static const uint64_t IDX_CEN_TCM_ENC_CPM_RESULT0_DTS_0_RESULT = 25419;
static const uint64_t IDX_CEN_TCM_ENC_CPM_RESULT0_DTS_0_RESULT_LEN = 25420;
static const uint64_t IDX_CEN_TCM_ENC_CPM_RESULT0_DTS_1_RESULT = 25421;
static const uint64_t IDX_CEN_TCM_ENC_CPM_RESULT0_DTS_1_RESULT_LEN = 25422;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 25423;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_FORCE_THRES_ACT = 25424;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_THRES_TRIP_ENA = 25425;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 25426;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DTS_SAMPLE_ENA = 25427;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_SAMPLE_PULSE_CNT = 25428;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 25429;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_THRES_ENA = 25430;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_THRES_ENA_LEN = 25431;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DTS_TRIGGER = 25432;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DTS_TRIGGER_SEL = 25433;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_UNUSED = 25434;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_UNUSED_LEN = 25435;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DTS_READ_SEL = 25436;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DTS_READ_SEL_LEN = 25437;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DTS_ENABLE = 25438;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_DTS_ENABLE_LEN = 25439;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_CPM_ENABLE = 25440;
static const uint64_t IDX_CEN_TCM_THERM_MODE_REG_CPM_ENABLE_LEN = 25441;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_HOLD_SAMPLE = 25442;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_DISABLE_STICKINESS = 25443;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_UNUSED1 = 25444;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_UNUSED1_LEN = 25445;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 25446;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 25447;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_RESET_TRIG_SEL = 25448;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 25449;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_SAMPLE_GUTS = 25450;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 25451;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 25452;
static const uint64_t IDX_CEN_TCM_SKITTER_MODE_REG_DATA_V_LT = 25453;
static const uint64_t IDX_CEN_TCM_SKITTER_CLKSRC_REG_SKITTER0 = 25454;
static const uint64_t IDX_CEN_TCM_SKITTER_CLKSRC_REG_SKITTER0_LEN = 25455;
static const uint64_t IDX_CEN_TCM_INJECT_REG_THERM_TRIP = 25456;
static const uint64_t IDX_CEN_TCM_INJECT_REG_THERM_TRIP_LEN = 25457;
static const uint64_t IDX_CEN_TCM_INJECT_REG_THERM_MODE = 25458;
static const uint64_t IDX_CEN_TCM_INJECT_REG_THERM_MODE_LEN = 25459;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 25460;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 25461;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 25462;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 25463;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_MASK = 25464;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 25465;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_COUNT_STATE_MASK = 25466;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_RUN_STATE_MASK = 25467;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_THRES_STATE_MASK = 25468;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_OVERFLOW_MASK = 25469;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 25470;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_SHIFTER_VALID_MASK = 25471;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_TIMEOUT_MASK = 25472;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_F_SKITTER_READ_MASK = 25473;
static const uint64_t IDX_CEN_TCM_ERR_STATUS_REG_PCB_MASK = 25474;
static const uint64_t IDX_CEN_TCM_SKITTER_FORCE_REG_F_READ = 25475;
static const uint64_t IDX_CEN_TCM_VOLT_MODE_REG_MEASURE_ENA = 25476;
static const uint64_t IDX_CEN_TCM_VOLT_MODE_REG_TRIP_ENA = 25477;
static const uint64_t IDX_CEN_TCM_VOLT_MODE_REG_ENABLE = 25478;
static const uint64_t IDX_CEN_TCM_VOLT_MODE_REG_ENABLE_LEN = 25479;
static const uint64_t IDX_CEN_TCM_TIMESTAMP_COUNTER_READ_VALUE = 25480;
static const uint64_t IDX_CEN_TCM_TIMESTAMP_COUNTER_READ_VALUE_LEN = 25481;
static const uint64_t IDX_CEN_TCM_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 25482;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_GLB_BRCST = 25483;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_GLB_BRCST_LEN = 25484;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_TRACE_SEL = 25485;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_TRACE_SEL_LEN = 25486;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_TRIG_SEL = 25487;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_TRIG_SEL_LEN = 25488;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 25489;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 25490;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 25491;
static const uint64_t IDX_CEN_TCM_DBG_MODE_REG_FREEZE_SEL = 25492;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND1_SEL_A = 25493;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 25494;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND1_SEL_B = 25495;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 25496;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND2_SEL_A = 25497;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 25498;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND2_SEL_B = 25499;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 25500;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 25501;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 25502;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 25503;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 25504;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 = 25505;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN = 25506;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 25507;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 25508;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 25509;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 25510;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 = 25511;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN = 25512;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 25513;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 25514;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 25515;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 25516;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 25517;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 25518;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_C1_COUNT_LT = 25519;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 25520;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_C2_COUNT_LT = 25521;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 25522;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 25523;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 25524;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_1_A = 25525;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_1_A_LEN = 25526;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 25527;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 25528;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_A = 25529;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_A_LEN = 25530;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_B = 25531;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_B_LEN = 25532;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_SP_COUNT_LT = 25533;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN = 25534;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE = 25535;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN = 25536;
static const uint64_t IDX_CEN_TCM_DBG_INST1_COND_REG_2_FORCE_TEST_MODE = 25537;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND1_SEL_A = 25538;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 25539;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND1_SEL_B = 25540;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 25541;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND2_SEL_A = 25542;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 25543;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND2_SEL_B = 25544;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 25545;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 25546;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 25547;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 25548;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 25549;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 = 25550;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN = 25551;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 25552;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 25553;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 25554;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 25555;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 = 25556;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN = 25557;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 25558;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 25559;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 25560;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 25561;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 25562;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 25563;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_C1_COUNT_LT = 25564;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 25565;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_C2_COUNT_LT = 25566;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 25567;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 25568;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 25569;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_1_A = 25570;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_1_A_LEN = 25571;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 25572;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 25573;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_A = 25574;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_A_LEN = 25575;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_B = 25576;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_B_LEN = 25577;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_SP_COUNT_LT = 25578;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN = 25579;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE = 25580;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN = 25581;
static const uint64_t IDX_CEN_TCM_DBG_INST2_COND_REG_2_FORCE_TEST_MODE = 25582;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 25583;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 25584;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 25585;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 25586;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 25587;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 25588;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 25589;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 25590;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 25591;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 25592;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 25593;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 25594;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 25595;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 25596;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 25597;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 25598;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 25599;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 25600;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 25601;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 25602;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 25603;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 25604;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 25605;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 25606;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 25607;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 25608;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 25609;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 25610;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_ARM_SEL = 25611;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_ARM_SEL_LEN = 25612;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 25613;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 25614;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 25615;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 25616;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 25617;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 25618;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 25619;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 25620;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 25621;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 25622;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 25623;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 25624;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 25625;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 25626;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 25627;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 25628;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 25629;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25630;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 25631;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 25632;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 25633;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 25634;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 25635;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 25636;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 25637;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 25638;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 25639;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 25640;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 25641;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 25642;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 25643;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 25644;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 25645;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 25646;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 25647;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 25648;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 25649;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 25650;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 25651;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_FORCE_TEST = 25652;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 25653;
static const uint64_t IDX_CEN_TCM_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON = 25654;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 25655;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 25656;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE = 25657;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN = 25658;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_BANK_MODE = 25659;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_ENH_MODE = 25660;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL = 25661;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN = 25662;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 25663;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 25664;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 25665;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 25666;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_2_PATTERNA = 25667;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 25668;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_2_PATTERNB = 25669;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 25670;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_3_PATTERNC = 25671;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 25672;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_3_PATTERND = 25673;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 25674;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_4_MASKA = 25675;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 25676;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_4_MASKB = 25677;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 25678;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_5_MASKC = 25679;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 25680;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_5_MASKD = 25681;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 25682;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 25683;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 25684;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 25685;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 25686;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 25687;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 25688;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 25689;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 25690;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 25691;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 25692;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 25693;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 25694;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 25695;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 25696;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 25697;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 25698;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 25699;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 25700;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 25701;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 25702;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 25703;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 25704;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_HI_DATA_REG_DATA = 25705;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_HI_DATA_REG_DATA_LEN = 25706;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_DATA = 25707;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_DATA_LEN = 25708;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_ADDRESS = 25709;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_ADDRESS_LEN = 25710;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_LAST_BANK = 25711;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_LAST_BANK_LEN = 25712;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_LAST_BANK_VALID = 25713;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_WRITE_ON_RUN = 25714;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_RUNNING = 25715;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_HOLD_ADDRESS = 25716;
static const uint64_t IDX_CEN_MBA_TCM_TRA_MBA01TRA_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 25717;
static const uint64_t IDX_CEN_FSISCRPD_FSI_SCRATCH_PAD = 25718;
static const uint64_t IDX_CEN_FSISCRPD_FSI_SCRATCH_PAD_LEN = 25719;
static const uint64_t IDX_CEN_DATA_REGISTER_0_REG_0 = 25720;
static const uint64_t IDX_CEN_DATA_REGISTER_0_REG_0_LEN = 25721;
static const uint64_t IDX_CEN_DATA_REGISTER_1_REG_1 = 25722;
static const uint64_t IDX_CEN_DATA_REGISTER_1_REG_1_LEN = 25723;
static const uint64_t IDX_CEN_COMMAND_REGISTER_CMD_REG = 25724;
static const uint64_t IDX_CEN_COMMAND_REGISTER_CMD_REG_LEN = 25725;
static const uint64_t IDX_CEN_INTERRUPT_STATUS_REG = 25726;
static const uint64_t IDX_CEN_INTERRUPT_STATUS_REG_LEN = 25727;
static const uint64_t IDX_CEN_COMPLEMENT_MASK_REG = 25728;
static const uint64_t IDX_CEN_COMPLEMENT_MASK_REG_LEN = 25729;
static const uint64_t IDX_CEN_TRUE_MASK_REG = 25730;
static const uint64_t IDX_CEN_TRUE_MASK_REG_LEN = 25731;
static const uint64_t IDX_CEN_FSIGP4_TPFSI_PLLMEM_ALTREFCLK_ENABLE = 25732;
static const uint64_t IDX_CEN_FSIGP4_TPFSI_CLKSTOP_DPHY23_GRID_ENABLE = 25733;
static const uint64_t IDX_CEN_FSIGP4_TPFSI_MEMRST_B = 25734;
static const uint64_t IDX_CEN_FSIGP4_TPFSI_FORCE_MCLK_OFF = 25735;
static const uint64_t IDX_CEN_FSIGP4_TP_CHIP_DPHY_PLLRESET_B = 25736;
static const uint64_t IDX_CEN_FSIGP4_TP_CHIP_DPHY_RESET_ALL = 25737;
static const uint64_t IDX_CEN_FSIGP4_TP_CHIP_PADTEST_ENABLE = 25738;
static const uint64_t IDX_CEN_FSIGP4_TPFSI_TP_PLLMEM_ALTREFCLK_ENABLE = 25739;
static const uint64_t IDX_CEN_FSIGP4_TCN_DMI_TERM_DC = 25740;
static const uint64_t IDX_CEN_FSIGP4_TCN_DMI_TERM_DC_LEN = 25741;
static const uint64_t IDX_CEN_FSIGP4_TCM_DDR_TERM_DC = 25742;
static const uint64_t IDX_CEN_FSIGP4_TCM_DDR_TERM_DC_LEN = 25743;
static const uint64_t IDX_CEN_FSIGP4_GLBCK_RELAY_STRENGTH_DC = 25744;
static const uint64_t IDX_CEN_FSIGP4_GLBCK_RELAY_STRENGTH_DC_LEN = 25745;
static const uint64_t IDX_CEN_FSIGP4_TP_PLL_DIV_BYPASS_EN_DC = 25746;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_17_20 = 25747;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_17_20_LEN = 25748;
static const uint64_t IDX_CEN_FSIGP4_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 25749;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_22_23 = 25750;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_22_23_LEN = 25751;
static const uint64_t IDX_CEN_FSIGP4_TPFSI_TP_PLL_TEST_ENABLE_DC = 25752;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_25_27 = 25753;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_25_27_LEN = 25754;
static const uint64_t IDX_CEN_FSIGP4_TP_RI_DC_B = 25755;
static const uint64_t IDX_CEN_FSIGP4_TP_DI1_DC_B = 25756;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_30 = 25757;
static const uint64_t IDX_CEN_FSIGP4_GP4_UNUSED_31 = 25758;
static const uint64_t IDX_CEN_FSIGP3_GP3_UNUSED_0_19 = 25759;
static const uint64_t IDX_CEN_FSIGP3_GP3_UNUSED_0_19_LEN = 25760;
static const uint64_t IDX_CEN_FSIGP3_USE_PIB2PCB_MUX_DC = 25761;
static const uint64_t IDX_CEN_FSIGP3_OOB_MUX_DC = 25762;
static const uint64_t IDX_CEN_FSIGP3_PCB_RESET_DC = 25763;
static const uint64_t IDX_CEN_FSIGP3_FENCE2_DC = 25764;
static const uint64_t IDX_CEN_FSIGP3_FENCE3_DC = 25765;
static const uint64_t IDX_CEN_FSIGP3_FENCE4_DC = 25766;
static const uint64_t IDX_CEN_FSIGP3_FENCE5_DC = 25767;
static const uint64_t IDX_CEN_FSIGP3_VDD2VIO_LVL_FENCE = 25768;
static const uint64_t IDX_CEN_FSIGP3_PLL_RESET_DC = 25769;
static const uint64_t IDX_CEN_FSIGP3_PLL_OUT_EN_DC = 25770;
static const uint64_t IDX_CEN_FSIGP3_GP3_UNUSED_30 = 25771;
static const uint64_t IDX_CEN_FSIGP3_GLOBAL_EP_RESET_DC = 25772;
static const uint64_t IDX_CEN_FSIGP5_PROBE0_SEL_DC = 25773;
static const uint64_t IDX_CEN_FSIGP5_PROBE0_SEL_DC_LEN = 25774;
static const uint64_t IDX_CEN_FSIGP5_PROBE1_SEL_DC = 25775;
static const uint64_t IDX_CEN_FSIGP5_PROBE1_SEL_DC_LEN = 25776;
static const uint64_t IDX_CEN_FSIGP5_PROBE_MESH_SEL_DC = 25777;
static const uint64_t IDX_CEN_FSIGP5_PROBE_DRV_EN_DC = 25778;
static const uint64_t IDX_CEN_FSIGP5_BURNIN_MODE_DC = 25779;
static const uint64_t IDX_CEN_FSIGP5_GP5_UNUSED_11 = 25780;
static const uint64_t IDX_CEN_FSIGP5_GP5_UNUSED_12_15 = 25781;
static const uint64_t IDX_CEN_FSIGP5_GP5_UNUSED_12_15_LEN = 25782;
static const uint64_t IDX_CEN_FSIGP5_FSI_PROBE_SEL_DC = 25783;
static const uint64_t IDX_CEN_FSIGP5_FSI_PROBE_SEL_DC_LEN = 25784;
static const uint64_t IDX_CEN_FSIGP5_GP5_UNUSED_18_22 = 25785;
static const uint64_t IDX_CEN_FSIGP5_GP5_UNUSED_18_22_LEN = 25786;
static const uint64_t IDX_CEN_FSIGP5_PLL_DRV_EN_DC = 25787;
static const uint64_t IDX_CEN_FSIGP5_DBG_PCB_ASYNC_EN_DC = 25788;
static const uint64_t IDX_CEN_FSIGP5_DBG_PCB_DATA_PAR_DIS_DC = 25789;
static const uint64_t IDX_CEN_FSIGP5_DBG_PCB_TYPE_PAR_DIS_DC = 25790;
static const uint64_t IDX_CEN_FSIGP5_PCB_GSD_LATCHED_MODE_DC = 25791;
static const uint64_t IDX_CEN_FSIGP5_PIB_DISABLE_PARITY_DC = 25792;
static const uint64_t IDX_CEN_FSIGP5_GPIO_PIB_TIMEOUT = 25793;
static const uint64_t IDX_CEN_FSIGP5_GPIO_PIB_TIMEOUT_LEN = 25794;
static const uint64_t IDX_CEN_FSIGP6_GP6_UNUSED_0_31 = 25795;
static const uint64_t IDX_CEN_FSIGP6_GP6_UNUSED_0_31_LEN = 25796;
static const uint64_t IDX_CEN_FSIGP7_DPHYN_PROGDLY_SETTING_DC = 25797;
static const uint64_t IDX_CEN_FSIGP7_DPHYN_PROGDLY_SETTING_DC_LEN = 25798;
static const uint64_t IDX_CEN_FSIGP7_DPHYS_PROGDLY_SETTING_DC = 25799;
static const uint64_t IDX_CEN_FSIGP7_DPHYS_PROGDLY_SETTING_DC_LEN = 25800;
static const uint64_t IDX_CEN_FSIGP7_MBC_PROGDLY_SETTING_DC = 25801;
static const uint64_t IDX_CEN_FSIGP7_MBC_PROGDLY_SETTING_DC_LEN = 25802;
static const uint64_t IDX_CEN_FSIGP7_MEM_PROGDLY_SETTING_DC = 25803;
static const uint64_t IDX_CEN_FSIGP7_MEM_PROGDLY_SETTING_DC_LEN = 25804;
static const uint64_t IDX_CEN_FSIGP7_NEST_PROGDLY_SETTING_DC = 25805;
static const uint64_t IDX_CEN_FSIGP7_NEST_PROGDLY_SETTING_DC_LEN = 25806;
static const uint64_t IDX_CEN_FSIGP7_GP7_UNUSED_20_31 = 25807;
static const uint64_t IDX_CEN_FSIGP7_GP7_UNUSED_20_31_LEN = 25808;
static const uint64_t IDX_CEN_GPWRP_MAGIC_COOKIE = 25809;
static const uint64_t IDX_CEN_GPWRP_MAGIC_COOKIE_LEN = 25810;
static const uint64_t IDX_CEN_GPWRP_EN_OR_DIS_WRITE_PROTECTION = 25811;
static const uint64_t IDX_CEN_GPWRP_EN_OR_DIS_WRITE_PROTECTION_LEN = 25812;
static const uint64_t IDX_CEN_SNS1LTH_SNS1_UNUSED_0_31 = 25813;
static const uint64_t IDX_CEN_SNS1LTH_SNS1_UNUSED_0_31_LEN = 25814;
static const uint64_t IDX_CEN_SNS2LTH_SNS2_UNUSED_0_31 = 25815;
static const uint64_t IDX_CEN_SNS2LTH_SNS2_UNUSED_0_31_LEN = 25816;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_EN_DC = 25817;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_PCB_EP_RESET_DC = 25818;
static const uint64_t IDX_CEN_PERV_GP3_UNUSED_2_4 = 25819;
static const uint64_t IDX_CEN_PERV_GP3_UNUSED_2_4_LEN = 25820;
static const uint64_t IDX_CEN_PERV_GP3_TP_PLLNST_BYPASS_EN_DC = 25821;
static const uint64_t IDX_CEN_PERV_GP3_UNUSED_6_10 = 25822;
static const uint64_t IDX_CEN_PERV_GP3_UNUSED_6_10_LEN = 25823;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_VTL_D_MODE_DC = 25824;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_VTL_ACT_DIS_DC = 25825;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_VTL_MPW2_DC_B = 25826;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_VTL_MPW1_DC_B = 25827;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_VTL_DELAY_LCLKR_DC = 25828;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_VTL_CLKOFF_DC = 25829;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_PLL_BYPASS_EN_DC = 25830;
static const uint64_t IDX_CEN_PERV_GP3_TP_CHIPLET_FENCE_EN_DC = 25831;
static const uint64_t IDX_CEN_PERV_GP3_UNUSED_19_31 = 25832;
static const uint64_t IDX_CEN_PERV_GP3_UNUSED_19_31_LEN = 25833;
static const uint64_t IDX_CEN_I2_DATA_REGISTER_0_REG_0 = 25834;
static const uint64_t IDX_CEN_I2_DATA_REGISTER_0_REG_0_LEN = 25835;
static const uint64_t IDX_CEN_I2_DATA_REGISTER_1_REG_1 = 25836;
static const uint64_t IDX_CEN_I2_DATA_REGISTER_1_REG_1_LEN = 25837;
static const uint64_t IDX_CEN_I2_COMMAND_REGISTER_CMD_REG = 25838;
static const uint64_t IDX_CEN_I2_COMMAND_REGISTER_CMD_REG_LEN = 25839;
static const uint64_t IDX_CEN_I2_INTERRUPT_STATUS_REG = 25840;
static const uint64_t IDX_CEN_I2_INTERRUPT_STATUS_REG_LEN = 25841;
static const uint64_t IDX_CEN_I2_COMPLEMENT_MASK_REG = 25842;
static const uint64_t IDX_CEN_I2_COMPLEMENT_MASK_REG_LEN = 25843;
static const uint64_t IDX_CEN_I2_TRUE_MASK_REG = 25844;
static const uint64_t IDX_CEN_I2_TRUE_MASK_REG_LEN = 25845;
static const uint64_t IDX_CEN_FSI_SHIFT_COMMAND_REGISTER_CMD_REG = 25846;
static const uint64_t IDX_CEN_FSI_SHIFT_COMMAND_REGISTER_CMD_REG_LEN = 25847;
static const uint64_t IDX_CEN_FSI_SHIFT_READ_BUFFER_REG = 25848;
static const uint64_t IDX_CEN_FSI_SHIFT_READ_BUFFER_REG_LEN = 25849;
static const uint64_t IDX_CEN_FSI_SHIFT_STATUS_4 = 25850;
static const uint64_t IDX_CEN_FSI_SHIFT_STATUS_4_LEN = 25851;
static const uint64_t IDX_CEN_FSI_SHIFT_COMPLEMENT_MASK_REG = 25852;
static const uint64_t IDX_CEN_FSI_SHIFT_COMPLEMENT_MASK_REG_LEN = 25853;
static const uint64_t IDX_CEN_FSI_SHIFT_TRUE_MASK_REG = 25854;
static const uint64_t IDX_CEN_FSI_SHIFT_TRUE_MASK_REG_LEN = 25855;
static const uint64_t IDX_CEN_FSI_SHIFT_SHIFT_CONTROL_REGISTER_2_CONTROL_REGISTER = 25856;
static const uint64_t IDX_CEN_FSI_SHIFT_SHIFT_CONTROL_REGISTER_2_CONTROL_REGISTER_LEN = 25857;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_MODE_REGISTER_REG_ENABLE = 25858;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_MODE_REGISTER_REG_FIFO_SIZE_EQ_1 = 25859;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_MODE_REGISTER_REG_UNUSED = 25860;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_MODE_REGISTER_REG_UNUSED_LEN = 25861;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_STAT_COMP_MASK_REGISTER_REG = 25862;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_STAT_COMP_MASK_REGISTER_REG_LEN = 25863;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE = 25864;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE_LEN = 25865;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE = 25866;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE_LEN = 25867;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS = 25868;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS_LEN = 25869;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0 = 25870;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN = 25871;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0 = 25872;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0_LEN = 25873;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0 = 25874;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN = 25875;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1 = 25876;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1_LEN = 25877;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_ERROR_PTR_REGISTER_REG = 25878;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_ERROR_PTR_REGISTER_REG_LEN = 25879;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_SCOM_CMD_REGISTER_REG = 25880;
static const uint64_t IDX_CEN_FSI_SHIFT_DMA_SCOM_CMD_REGISTER_REG_LEN = 25881;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG = 25882;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG_LEN = 25883;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG = 25884;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG_LEN = 25885;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG = 25886;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG_LEN = 25887;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG = 25888;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG_LEN = 25889;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG = 25890;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG_LEN = 25891;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG = 25892;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG_LEN = 25893;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG = 25894;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG_LEN = 25895;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG = 25896;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG_LEN = 25897;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG = 25898;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG_LEN = 25899;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG = 25900;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG_LEN = 25901;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG = 25902;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG_LEN = 25903;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG = 25904;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG_LEN = 25905;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG = 25906;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG_LEN = 25907;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG = 25908;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG_LEN = 25909;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG = 25910;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG_LEN = 25911;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG = 25912;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG_LEN = 25913;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS = 25914;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS_LEN = 25915;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS = 25916;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS_LEN = 25917;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS = 25918;
static const uint64_t IDX_CEN_FSI_SHIFT_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS_LEN = 25919;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG = 25920;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG_LEN = 25921;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG = 25922;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG_LEN = 25923;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG = 25924;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG_LEN = 25925;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG = 25926;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG_LEN = 25927;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG = 25928;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG_LEN = 25929;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG = 25930;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG_LEN = 25931;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG = 25932;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG_LEN = 25933;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG = 25934;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG_LEN = 25935;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG = 25936;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG_LEN = 25937;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG = 25938;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG_LEN = 25939;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG = 25940;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG_LEN = 25941;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG = 25942;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG_LEN = 25943;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG = 25944;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG_LEN = 25945;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG = 25946;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG_LEN = 25947;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG = 25948;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG_LEN = 25949;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG = 25950;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG_LEN = 25951;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS = 25952;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS_LEN = 25953;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS = 25954;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS_LEN = 25955;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS = 25956;
static const uint64_t IDX_CEN_FSI2PIB_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS_LEN = 25957;
static const uint64_t IDX_CEN_FSI_I2C_COMMAND_REGISTER_CMD_REG = 25958;
static const uint64_t IDX_CEN_FSI_I2C_COMMAND_REGISTER_CMD_REG_LEN = 25959;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_BIT_RATE_DIVISOR = 25960;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_BIT_RATE_DIVISOR_LEN = 25961;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_PORT_NUMBER = 25962;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_PORT_NUMBER_LEN = 25963;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_FGAT = 25964;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_DIAG = 25965;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_PACING_ALLOW = 25966;
static const uint64_t IDX_CEN_FSI_I2C_MODE_REGISTER_WRAP = 25967;
static const uint64_t IDX_CEN_FSI_I2C_WATER_MARK_REGISTER_WATERMARK_REG = 25968;
static const uint64_t IDX_CEN_FSI_I2C_WATER_MARK_REGISTER_WATERMARK_REG_LEN = 25969;
static const uint64_t IDX_CEN_FSI_I2C_INTERRUPT_MASK_REGISTER_INT = 25970;
static const uint64_t IDX_CEN_FSI_I2C_INTERRUPT_MASK_REGISTER_INT_LEN = 25971;
static const uint64_t IDX_CEN_GPIO_INPUT_REGISTER_READ_DATA = 25972;
static const uint64_t IDX_CEN_GPIO_INPUT_REGISTER_READ_DATA_LEN = 25973;
static const uint64_t IDX_CEN_GPIO_OUPUT_REGISTER_OUTPUT_REGISTER_READ_WRITE_DATA = 25974;
static const uint64_t IDX_CEN_GPIO_OUPUT_REGISTER_OUTPUT_REGISTER_READ_WRITE_DATA_LEN = 25975;
static const uint64_t IDX_CEN_GPIO_OUPUT_ENABLE_REGISTER_OUTPUT_ENABLE_REGISTER_READ_WRITE_DATA = 25976;
static const uint64_t IDX_CEN_GPIO_OUPUT_ENABLE_REGISTER_OUTPUT_ENABLE_REGISTER_READ_WRITE_DATA_LEN = 25977;
static const uint64_t IDX_CEN_GPIO_INTERRUPT_REGISTER_READ_DATA = 25978;
static const uint64_t IDX_CEN_GPIO_INTERRUPT_REGISTER_READ_DATA_LEN = 25979;
static const uint64_t IDX_CEN_GPIO_POLARITY_REGISTER_READ_WRITE_DATA = 25980;
static const uint64_t IDX_CEN_GPIO_POLARITY_REGISTER_READ_WRITE_DATA_LEN = 25981;
static const uint64_t IDX_CEN_GPIO_INTERRUPT_ENABLE_REGISTER_READ_WRITE_DATA = 25982;
static const uint64_t IDX_CEN_GPIO_INTERRUPT_ENABLE_REGISTER_READ_WRITE_DATA_LEN = 25983;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG = 25984;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG_LEN = 25985;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG = 25986;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG_LEN = 25987;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG = 25988;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG_LEN = 25989;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG = 25990;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG_LEN = 25991;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG = 25992;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG_LEN = 25993;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG = 25994;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG_LEN = 25995;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG = 25996;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG_LEN = 25997;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG = 25998;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG_LEN = 25999;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG = 26000;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG_LEN = 26001;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG = 26002;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG_LEN = 26003;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG = 26004;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG_LEN = 26005;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG = 26006;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG_LEN = 26007;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG = 26008;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG_LEN = 26009;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG = 26010;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG_LEN = 26011;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG = 26012;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG_LEN = 26013;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG = 26014;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG_LEN = 26015;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS = 26016;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS_LEN = 26017;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS = 26018;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS_LEN = 26019;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS = 26020;
static const uint64_t IDX_CEN_FSI2PIB2_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS_LEN = 26021;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_COMMAND_REGISTER_CMD_REG = 26022;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_COMMAND_REGISTER_CMD_REG_LEN = 26023;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_FRONTEND_REGISTER_REG = 26024;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_FRONTEND_REGISTER_REG_LEN = 26025;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_CMDVAL_REGISTER_REG = 26026;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_CMDVAL_REGISTER_REG_LEN = 26027;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_STATUS_REGISTER_REG = 26028;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_STATUS_REGISTER_REG_LEN = 26029;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_ECCTRAP_REGISTER_REG = 26030;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_ECCTRAP_REGISTER_REG_LEN = 26031;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_CONFIG_REGISTER_REG = 26032;
static const uint64_t IDX_CEN_RLDCOMP_RLDLOG_CONFIG_REGISTER_REG_LEN = 26033;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG = 26034;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG_LEN = 26035;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG = 26036;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG_LEN = 26037;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG = 26038;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG_LEN = 26039;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG = 26040;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG_LEN = 26041;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG = 26042;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG_LEN = 26043;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG = 26044;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG_LEN = 26045;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG = 26046;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG_LEN = 26047;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG = 26048;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG_LEN = 26049;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG = 26050;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG_LEN = 26051;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG = 26052;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG_LEN = 26053;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG = 26054;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG_LEN = 26055;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG = 26056;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG_LEN = 26057;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG = 26058;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG_LEN = 26059;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG = 26060;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG_LEN = 26061;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG = 26062;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG_LEN = 26063;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG = 26064;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG_LEN = 26065;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS = 26066;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS_LEN = 26067;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS = 26068;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS_LEN = 26069;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS = 26070;
static const uint64_t IDX_CEN_RLDCOMP_PIBMST_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS_LEN = 26071;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_BIT_WITHSTART = 26072;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_BIT_WITHADDR = 26073;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_BIT_READCONT = 26074;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_BIT_WITHSTOP = 26075;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_LENGTH = 26076;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_LENGTH_LEN = 26077;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_ADDR = 26078;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_ADDR_LEN = 26079;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_BIT_RNW = 26080;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_SPEED = 26081;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_SPEED_LEN = 26082;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_PORT_NUMBER = 26083;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_PORT_NUMBER_LEN = 26084;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_REG_ADDR_LEN = 26085;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_REG_ADDR_LEN_LEN = 26086;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_ENH_MODE = 26087;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_UNUSED = 26088;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_UNUSED_LEN = 26089;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_1 = 26090;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_1_LEN = 26091;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_2 = 26092;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_2_LEN = 26093;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_3 = 26094;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_3_LEN = 26095;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_4 = 26096;
static const uint64_t IDX_CEN_I2CM_CONTROL_REGISTER_0_PIB_CNTR_REG_DATA_4_LEN = 26097;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_ADDR_NVLD_0 = 26098;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_WRITE_NVLD_0 = 26099;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_READ_NVLD_0 = 26100;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_ADDR_P_ERR_0 = 26101;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_PAR_ERR_0 = 26102;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_LB_PARITY_ERROR_0 = 26103;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT = 26104;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT_LEN = 26105;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT_1 = 26106;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT_1_LEN = 26107;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT_2 = 26108;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT_2_LEN = 26109;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT_3 = 26110;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_PIB_REG_DATA_ACT_3_LEN = 26111;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_BUSY_0 = 26112;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_INVALID_COMMAND_0 = 26113;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_PARITY_ERROR_0 = 26114;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_BACK_END_OVERRUN_ERROR_0 = 26115;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_BACK_END_ACCESS_ERROR_0 = 26116;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_ARBITRATION_LOST_ERROR_0 = 26117;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_NACK_RECEIVED_ERROR_0 = 26118;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_DATA_REQUEST_0 = 26119;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_COMMAND_COMPLETE_0 = 26120;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_STOP_ERROR_0 = 26121;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_I2C_PORT_BUSY_0 = 26122;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_I2C_INTERFACE_BUSY_0 = 26123;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_FIFO_ENTRY_COUNT_0 = 26124;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_0_BUS_FIFO_ENTRY_COUNT_0_LEN = 26125;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_0 = 26126;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_0_LEN = 26127;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_1_0 = 26128;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_1_0_LEN = 26129;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_2_0 = 26130;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_2_0_LEN = 26131;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_3_0 = 26132;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_3_0_LEN = 26133;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_4_0 = 26134;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_4_0_LEN = 26135;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_5_0 = 26136;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_5_0_LEN = 26137;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_6_0 = 26138;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_6_0_LEN = 26139;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_7_0 = 26140;
static const uint64_t IDX_CEN_I2CM_DATA_REGISTER_0_PIB_REG_ACT_7_0_LEN = 26141;
static const uint64_t IDX_CEN_I2CM_FIFO1_REGISTER_READ_0_FIFO_BITS_READ0 = 26142;
static const uint64_t IDX_CEN_I2CM_FIFO1_REGISTER_READ_0_FIFO_BITS_READ0_LEN = 26143;
static const uint64_t IDX_CEN_I2CM_FIFO1_REGISTER_READ_0_PEEK_DATA1 = 26144;
static const uint64_t IDX_CEN_I2CM_FIFO1_REGISTER_READ_0_PEEK_DATA1_LEN = 26145;
static const uint64_t IDX_CEN_I2CM_FIFO1_REGISTER_READ_0_LBUS_PARITY_ERR1 = 26146;
static const uint64_t IDX_CEN_I2CM_FIFO4_REGISTER_READ_0_FIFO_BITS_READ0 = 26147;
static const uint64_t IDX_CEN_I2CM_FIFO4_REGISTER_READ_0_FIFO_BITS_READ0_LEN = 26148;
static const uint64_t IDX_CEN_I2CM_FIFO4_REGISTER_READ_0_PEEK_DATA1 = 26149;
static const uint64_t IDX_CEN_I2CM_FIFO4_REGISTER_READ_0_PEEK_DATA1_LEN = 26150;
static const uint64_t IDX_CEN_I2CM_FIFO4_REGISTER_READ_0_LBUS_PARITY_ERR1 = 26151;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_WITH_START = 26152;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_WITH_ADDRESS = 26153;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_READ_CONTINUE = 26154;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_WITH_STOP = 26155;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_NOT_USED = 26156;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_NOT_USED_LEN = 26157;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_DEVICE_ADDRESS = 26158;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_DEVICE_ADDRESS_LEN = 26159;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_READ_NOT_WRITE = 26160;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_LENGTH_IN_BYTES = 26161;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_LENGTH_IN_BYTES_LEN = 26162;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_PEEK_DATA1 = 26163;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_PEEK_DATA1_LEN = 26164;
static const uint64_t IDX_CEN_I2CM_COMMAND_REGISTER_0_LBUS_PARITY_ERR1 = 26165;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_BIT_RATE_DIVISOR = 26166;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_BIT_RATE_DIVISOR_LEN = 26167;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_PORT_NUMBER = 26168;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_PORT_NUMBER_LEN = 26169;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_CHKSW_I2C_BUSY = 26170;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_FGAT_0 = 26171;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_DIAG_0 = 26172;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_PACING_ALLOW_0 = 26173;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_WRAP_0 = 26174;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_PEEK_DATA1 = 26175;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_PEEK_DATA1_LEN = 26176;
static const uint64_t IDX_CEN_I2CM_MODE_REGISTER_0_LBUS_PARITY_ERR1 = 26177;
static const uint64_t IDX_CEN_I2CM_WATER_MARK_REGISTER_0_WATERMARK_REG = 26178;
static const uint64_t IDX_CEN_I2CM_WATER_MARK_REGISTER_0_WATERMARK_REG_LEN = 26179;
static const uint64_t IDX_CEN_I2CM_WATER_MARK_REGISTER_0_PEEK_DATA1 = 26180;
static const uint64_t IDX_CEN_I2CM_WATER_MARK_REGISTER_0_PEEK_DATA1_LEN = 26181;
static const uint64_t IDX_CEN_I2CM_WATER_MARK_REGISTER_0_LBUS_PARITY_ERR1 = 26182;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_MASK_REGISTER_READ_0_INT_0 = 26183;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_MASK_REGISTER_READ_0_INT_0_LEN = 26184;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_MASK_REGISTER_READ_0_PEEK_DATA1 = 26185;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_MASK_REGISTER_READ_0_PEEK_DATA1_LEN = 26186;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_MASK_REGISTER_READ_0_LBUS_PARITY_ERR1 = 26187;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_MASK_REGISTER_0_INT_0 = 26188;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_MASK_REGISTER_0_INT_0_LEN = 26189;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_INVALID_CMD = 26190;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_LBUS_PARITY_ERROR = 26191;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_BE_OV_ERROR = 26192;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_BE_ACC_ERROR = 26193;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_ARBITRATION_LOST_ERROR = 26194;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_NACK_RECEIVED_ERROR = 26195;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_DATA_REQUEST = 26196;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_STOP_ERROR = 26197;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_busy = 26198;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_SELF_BUSY = 26199;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_FIFO_ENTRY_COUNT = 26200;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_FIFO_ENTRY_COUNT_LEN = 26201;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_PEEK_DATA1 = 26202;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_PEEK_DATA1_LEN = 26203;
static const uint64_t IDX_CEN_I2CM_STATUS_REGISTER_ENGINE_0_LBUS_PARITY_ERR1 = 26204;
static const uint64_t IDX_CEN_I2CM_RESIDUAL_FRONT_END_BACK_END_LENGTH_0_RESID_FE_LEN = 26205;
static const uint64_t IDX_CEN_I2CM_RESIDUAL_FRONT_END_BACK_END_LENGTH_0_RESID_FE_LEN_LEN = 26206;
static const uint64_t IDX_CEN_I2CM_RESIDUAL_FRONT_END_BACK_END_LENGTH_0_PEEK_DATA1 = 26207;
static const uint64_t IDX_CEN_I2CM_RESIDUAL_FRONT_END_BACK_END_LENGTH_0_PEEK_DATA1_LEN = 26208;
static const uint64_t IDX_CEN_I2CM_RESIDUAL_FRONT_END_BACK_END_LENGTH_0_LBUS_PARITY_ERR1 = 26209;
static const uint64_t IDX_CEN_I2CM_EXTENDED_STATUS_0_MSM_CURR_STATE = 26210;
static const uint64_t IDX_CEN_I2CM_EXTENDED_STATUS_0_MSM_CURR_STATE_LEN = 26211;
static const uint64_t IDX_CEN_I2CM_EXTENDED_STATUS_0_SELF_BUSY = 26212;
static const uint64_t IDX_CEN_I2CM_EXTENDED_STATUS_0_PEEK_DATA1 = 26213;
static const uint64_t IDX_CEN_I2CM_EXTENDED_STATUS_0_PEEK_DATA1_LEN = 26214;
static const uint64_t IDX_CEN_I2CM_EXTENDED_STATUS_0_LBUS_PARITY_ERR1 = 26215;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_INVALID_CMD = 26216;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_LBUS_PARITY_ERROR = 26217;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_BE_OV_ERROR = 26218;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_BE_ACC_ERROR = 26219;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_ARBITRATION_LOST_ERROR = 26220;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_NACK_RECEIVED_ERROR = 26221;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_DATA_REQUEST = 26222;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_STOP_ERROR = 26223;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_PEEK_DATA1 = 26224;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_PEEK_DATA1_LEN = 26225;
static const uint64_t IDX_CEN_I2CM_INTERRUPT_COND_0_LBUS_PARITY_ERR1 = 26226;
static const uint64_t IDX_CEN_I2CM_INTERRUPTS_0_PEEK_DATA1 = 26227;
static const uint64_t IDX_CEN_I2CM_INTERRUPTS_0_PEEK_DATA1_LEN = 26228;
static const uint64_t IDX_CEN_I2CM_INTERRUPTS_0_LBUS_PARITY_ERR1 = 26229;
static const uint64_t IDX_CEN_I2CM_I2C_BUSY_REGISTER_0_PEEK_DATA1 = 26230;
static const uint64_t IDX_CEN_I2CM_I2C_BUSY_REGISTER_0_PEEK_DATA1_LEN = 26231;
static const uint64_t IDX_CEN_I2CM_I2C_BUSY_REGISTER_0_LBUS_PARITY_ERR1 = 26232;
static const uint64_t IDX_CEN_MCAST_GRP_0_SLAVES_REG_SLAVES_GROUP_0 = 26233;
static const uint64_t IDX_CEN_MCAST_GRP_0_SLAVES_REG_SLAVES_GROUP_0_LEN = 26234;
static const uint64_t IDX_CEN_MCAST_GRP_1_SLAVES_REG_SLAVES_GROUP_1 = 26235;
static const uint64_t IDX_CEN_MCAST_GRP_1_SLAVES_REG_SLAVES_GROUP_1_LEN = 26236;
static const uint64_t IDX_CEN_MCAST_GRP_2_SLAVES_REG_SLAVES_GROUP_2 = 26237;
static const uint64_t IDX_CEN_MCAST_GRP_2_SLAVES_REG_SLAVES_GROUP_2_LEN = 26238;
static const uint64_t IDX_CEN_MCAST_GRP_3_SLAVES_REG_SLAVES_GROUP_3 = 26239;
static const uint64_t IDX_CEN_MCAST_GRP_3_SLAVES_REG_SLAVES_GROUP_3_LEN = 26240;
static const uint64_t IDX_CEN_MCAST_GRP_4_SLAVES_REG_SLAVES_GROUP_4 = 26241;
static const uint64_t IDX_CEN_MCAST_GRP_4_SLAVES_REG_SLAVES_GROUP_4_LEN = 26242;
static const uint64_t IDX_CEN_MCAST_GRP_5_SLAVES_REG_SLAVES_GROUP_5 = 26243;
static const uint64_t IDX_CEN_MCAST_GRP_5_SLAVES_REG_SLAVES_GROUP_5_LEN = 26244;
static const uint64_t IDX_CEN_MCAST_GRP_6_SLAVES_REG_SLAVES_GROUP_6 = 26245;
static const uint64_t IDX_CEN_MCAST_GRP_6_SLAVES_REG_SLAVES_GROUP_6_LEN = 26246;
static const uint64_t IDX_CEN_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB = 26247;
static const uint64_t IDX_CEN_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB_LEN = 26248;
static const uint64_t IDX_CEN_BIT_SEL_REG_3_SELECT_REGISTER_FSISHIFT = 26249;
static const uint64_t IDX_CEN_BIT_SEL_REG_3_SELECT_REGISTER_FSISHIFT_LEN = 26250;
static const uint64_t IDX_CEN_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER = 26251;
static const uint64_t IDX_CEN_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 26252;
static const uint64_t IDX_CEN_REC_ERR_REG0_MASTER_RESPONSE_BIT = 26253;
static const uint64_t IDX_CEN_REC_ERR_REG0_MASTER_ERROR_CODE = 26254;
static const uint64_t IDX_CEN_REC_ERR_REG0_MASTER_ERROR_CODE_LEN = 26255;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE1_RESPONSE_BIT = 26256;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE1_ERROR_CODE = 26257;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE1_ERROR_CODE_LEN = 26258;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE2_RESPONSE_BIT = 26259;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE2_ERROR_CODE = 26260;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE2_ERROR_CODE_LEN = 26261;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE3_RESPONSE_BIT = 26262;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE3_ERROR_CODE = 26263;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE3_ERROR_CODE_LEN = 26264;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE4_RESPONSE_BIT = 26265;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE4_ERROR_CODE = 26266;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE4_ERROR_CODE_LEN = 26267;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE5_RESPONSE_BIT = 26268;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE5_ERROR_CODE = 26269;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE5_ERROR_CODE_LEN = 26270;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE6_RESPONSE_BIT = 26271;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE6_ERROR_CODE = 26272;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE6_ERROR_CODE_LEN = 26273;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE7_RESPONSE_BIT = 26274;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE7_ERROR_CODE = 26275;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE7_ERROR_CODE_LEN = 26276;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE8_RESPONSE_BIT = 26277;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE8_ERROR_CODE = 26278;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE8_ERROR_CODE_LEN = 26279;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE9_RESPONSE_BIT = 26280;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE9_ERROR_CODE = 26281;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE9_ERROR_CODE_LEN = 26282;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE10_RESPONSE_BIT = 26283;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE10_ERROR_CODE = 26284;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE10_ERROR_CODE_LEN = 26285;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE11_RESPONSE_BIT = 26286;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE11_ERROR_CODE = 26287;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE11_ERROR_CODE_LEN = 26288;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE12_RESPONSE_BIT = 26289;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE12_ERROR_CODE = 26290;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE12_ERROR_CODE_LEN = 26291;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE13_RESPONSE_BIT = 26292;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE13_ERROR_CODE = 26293;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE13_ERROR_CODE_LEN = 26294;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE14_RESPONSE_BIT = 26295;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE14_ERROR_CODE = 26296;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE14_ERROR_CODE_LEN = 26297;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE15_RESPONSE_BIT = 26298;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE15_ERROR_CODE = 26299;
static const uint64_t IDX_CEN_REC_ERR_REG0_SLAVE15_ERROR_CODE_LEN = 26300;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE16_RESPONSE_BIT = 26301;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE16_ERROR_CODE = 26302;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE16_ERROR_CODE_LEN = 26303;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE17_RESPONSE_BIT = 26304;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE17_ERROR_CODE = 26305;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE17_ERROR_CODE_LEN = 26306;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE18_RESPONSE_BIT = 26307;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE18_ERROR_CODE = 26308;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE18_ERROR_CODE_LEN = 26309;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE19_RESPONSE_BIT = 26310;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE19_ERROR_CODE = 26311;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE19_ERROR_CODE_LEN = 26312;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE20_RESPONSE_BIT = 26313;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE20_ERROR_CODE = 26314;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE20_ERROR_CODE_LEN = 26315;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE21_RESPONSE_BIT = 26316;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE21_ERROR_CODE = 26317;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE21_ERROR_CODE_LEN = 26318;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE22_RESPONSE_BIT = 26319;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE22_ERROR_CODE = 26320;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE22_ERROR_CODE_LEN = 26321;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE23_RESPONSE_BIT = 26322;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE23_ERROR_CODE = 26323;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE23_ERROR_CODE_LEN = 26324;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE24_RESPONSE_BIT = 26325;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE24_ERROR_CODE = 26326;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE24_ERROR_CODE_LEN = 26327;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE25_RESPONSE_BIT = 26328;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE25_ERROR_CODE = 26329;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE25_ERROR_CODE_LEN = 26330;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE26_RESPONSE_BIT = 26331;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE26_ERROR_CODE = 26332;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE26_ERROR_CODE_LEN = 26333;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE27_RESPONSE_BIT = 26334;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE27_ERROR_CODE = 26335;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE27_ERROR_CODE_LEN = 26336;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE28_RESPONSE_BIT = 26337;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE28_ERROR_CODE = 26338;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE28_ERROR_CODE_LEN = 26339;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE29_RESPONSE_BIT = 26340;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE29_ERROR_CODE = 26341;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE29_ERROR_CODE_LEN = 26342;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE30_RESPONSE_BIT = 26343;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE30_ERROR_CODE = 26344;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE30_ERROR_CODE_LEN = 26345;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE31_RESPONSE_BIT = 26346;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE31_ERROR_CODE = 26347;
static const uint64_t IDX_CEN_REC_ERR_REG1_SLAVE31_ERROR_CODE_LEN = 26348;
static const uint64_t IDX_CEN_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER = 26349;
static const uint64_t IDX_CEN_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER_LEN = 26350;
static const uint64_t IDX_CEN_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER = 26351;
static const uint64_t IDX_CEN_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 26352;
static const uint64_t IDX_CEN_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER = 26353;
static const uint64_t IDX_CEN_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER_LEN = 26354;
static const uint64_t IDX_CEN_FIRST_REPLY_REG_REGISTER = 26355;
static const uint64_t IDX_CEN_FIRST_REPLY_REG_REGISTER_LEN = 26356;
static const uint64_t IDX_CEN_TIMEOUT_REG_REGISTER = 26357;
static const uint64_t IDX_CEN_TIMEOUT_REG_REGISTER_LEN = 26358;
static const uint64_t IDX_CEN_INTERRUPT_TYPE_REG_ATTENTION = 26359;
static const uint64_t IDX_CEN_INTERRUPT_TYPE_REG_RECOVERABLE_ERROR = 26360;
static const uint64_t IDX_CEN_INTERRUPT_TYPE_REG_CHECKSTOP = 26361;
static const uint64_t IDX_CEN_ERROR_REG_TIMEOUT_ACTIVE = 26362;
static const uint64_t IDX_CEN_ERROR_REG_PARITY_ERR = 26363;
static const uint64_t IDX_CEN_ERROR_REG_BEAT_NUM_ERR = 26364;
static const uint64_t IDX_CEN_ERROR_REG_BEAT_REC_ERR = 26365;
static const uint64_t IDX_CEN_ERROR_REG_RECEIVED = 26366;
static const uint64_t IDX_CEN_ERROR_REG_RX_PCB_DATA_P_ERR = 26367;
static const uint64_t IDX_CEN_ERROR_REG_PIB_ADDR_P_ERR = 26368;
static const uint64_t IDX_CEN_ERROR_REG_PIB_DATA_P_ERR = 26369;
static const uint64_t IDX_CEN_FIRST_ERR_REG_TIMEOUT_ACTIVE = 26370;
static const uint64_t IDX_CEN_FIRST_ERR_REG_PARITY = 26371;
static const uint64_t IDX_CEN_FIRST_ERR_REG_BEAT_NUM = 26372;
static const uint64_t IDX_CEN_FIRST_ERR_REG_BEAT_REC = 26373;
static const uint64_t IDX_CEN_FIRST_ERR_REG_RECEIVED_ERROR = 26374;
static const uint64_t IDX_CEN_FIRST_ERR_REG_RX_PCB_DATA_P = 26375;
static const uint64_t IDX_CEN_FIRST_ERR_REG_PIB_ADDR_P = 26376;
static const uint64_t IDX_CEN_FIRST_ERR_REG_PIB_DATA_P = 26377;
static const uint64_t IDX_CEN_RESET_REG_PCB = 26378;
static const uint64_t IDX_CEN_RESET_REG_ENDPOINTS = 26379;
static const uint64_t IDX_CEN_RESET_REG_TIMEOUT_EN = 26380;
static const uint64_t IDX_CEN_IGNORE_PAR_REG_PARITY_REG = 26381;
static const uint64_t IDX_CEN_IGNORE_PAR_REG_DISABLE_ECC_CORRECTION = 26382;
static const uint64_t IDX_CEN_IGNORE_PAR_REG_ECC_S_BIT_ERROR = 26383;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG = 26384;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG_LEN = 26385;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG = 26386;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG_LEN = 26387;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG = 26388;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG_LEN = 26389;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG = 26390;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG_LEN = 26391;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG = 26392;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG_LEN = 26393;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG = 26394;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG_LEN = 26395;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG = 26396;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG_LEN = 26397;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG = 26398;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG_LEN = 26399;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG = 26400;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG_LEN = 26401;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG = 26402;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG_LEN = 26403;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG = 26404;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG_LEN = 26405;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG = 26406;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG_LEN = 26407;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG = 26408;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG_LEN = 26409;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG = 26410;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG_LEN = 26411;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG = 26412;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG_LEN = 26413;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG = 26414;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG_LEN = 26415;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS = 26416;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS_LEN = 26417;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS = 26418;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS_LEN = 26419;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS = 26420;
static const uint64_t IDX_CEN_JTAG2PIB_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS_LEN = 26421;
static const uint64_t IDX_CEN_SYNC_CONFIG_ISLE_XSTOP_MASK_B = 26422;
static const uint64_t IDX_CEN_SYNC_CONFIG_PCB_XSTOP_MASK_B = 26423;
static const uint64_t IDX_CEN_SYNC_CONFIG_CLKSTP_EN = 26424;
static const uint64_t IDX_CEN_SYNC_CONFIG_EDRAM_XSTOP_MASK_B = 26425;
static const uint64_t IDX_CEN_SYNC_CONFIG_PLL_XSTOP_MASK_B = 26426;
static const uint64_t IDX_CEN_SYNC_CONFIG_LOCAL_XSTOP_MASK_B = 26427;
static const uint64_t IDX_CEN_SYNC_CONFIG_DISABLE_PCB_ITR = 26428;
static const uint64_t IDX_CEN_SYNC_CONFIG_USE_FOR_SCAN = 26429;
static const uint64_t IDX_CEN_SYNC_CONFIG_KEEP_EDRAM_ON_XSTOP = 26430;
static const uint64_t IDX_CEN_SYNC_CONFIG_TRIGGER_OPCG_ON_XSTOP = 26431;
static const uint64_t IDX_CEN_SYNC_CONFIG_SEL_EXT_OPCG_TRIGGER = 26432;
static const uint64_t IDX_CEN_SYNC_CONFIG_LISTEN_TO_PULSE = 26433;
static const uint64_t IDX_CEN_SYNC_CONFIG_CLK_START_ENABLE = 26434;
static const uint64_t IDX_CEN_SYNC_CONFIG_CLK_STOP_ENABLE = 26435;
static const uint64_t IDX_CEN_SYNC_CONFIG_CHIP_PROTECTION_ENABLE = 26436;
static const uint64_t IDX_CEN_SYNC_CONFIG_SPARE15 = 26437;
static const uint64_t IDX_CEN_SYNC_CONFIG_SPARE16 = 26438;
static const uint64_t IDX_CEN_SYNC_CONFIG_SPARE17 = 26439;
static const uint64_t IDX_CEN_SYNC_CONFIG_SPARE18 = 26440;
static const uint64_t IDX_CEN_SYNC_CONFIG_SPARE19 = 26441;
static const uint64_t IDX_CEN_SYNC_CONFIG_SPARE20 = 26442;
static const uint64_t IDX_CEN_PHASE_SHADOW_COUNT_Q = 26443;
static const uint64_t IDX_CEN_PHASE_SHADOW_COUNT_Q_LEN = 26444;
static const uint64_t IDX_CEN_OPCG_REG0_RUNN_MODE = 26445;
static const uint64_t IDX_CEN_OPCG_REG0_GO = 26446;
static const uint64_t IDX_CEN_OPCG_REG0_RUN_SCAN0 = 26447;
static const uint64_t IDX_CEN_OPCG_REG0_SCAN0_MODE = 26448;
static const uint64_t IDX_CEN_OPCG_REG0_SCAN_RATIO = 26449;
static const uint64_t IDX_CEN_OPCG_REG0_SCAN_RATIO_LEN = 26450;
static const uint64_t IDX_CEN_OPCG_REG0_INOP_FORCE_SG = 26451;
static const uint64_t IDX_CEN_OPCG_REG0_INOP_ALIGN = 26452;
static const uint64_t IDX_CEN_OPCG_REG0_INOP_ALIGN_LEN = 26453;
static const uint64_t IDX_CEN_OPCG_REG0_INOP_WAIT = 26454;
static const uint64_t IDX_CEN_OPCG_REG0_INOP_WAIT_LEN = 26455;
static const uint64_t IDX_CEN_OPCG_REG0_SNOP_ALIGN = 26456;
static const uint64_t IDX_CEN_OPCG_REG0_SNOP_ALIGN_LEN = 26457;
static const uint64_t IDX_CEN_OPCG_REG0_SNOP_WAIT = 26458;
static const uint64_t IDX_CEN_OPCG_REG0_SNOP_WAIT_LEN = 26459;
static const uint64_t IDX_CEN_OPCG_REG0_ENOP_ALIGN = 26460;
static const uint64_t IDX_CEN_OPCG_REG0_ENOP_ALIGN_LEN = 26461;
static const uint64_t IDX_CEN_OPCG_REG0_ENOP_WAIT = 26462;
static const uint64_t IDX_CEN_OPCG_REG0_ENOP_WAIT_LEN = 26463;
static const uint64_t IDX_CEN_OPCG_REG0_ENOP_FORCE_SG = 26464;
static const uint64_t IDX_CEN_OPCG_REG0_LOOP_COUNT = 26465;
static const uint64_t IDX_CEN_OPCG_REG0_LOOP_COUNT_LEN = 26466;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_COUNT = 26467;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_COUNT_LEN = 26468;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ01_01F = 26469;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ01_01F_LEN = 26470;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ02_02F = 26471;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ02_02F_LEN = 26472;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ03_03F = 26473;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ03_03F_LEN = 26474;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ04_04F = 26475;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ04_04F_LEN = 26476;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ05_05F = 26477;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ05_05F_LEN = 26478;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ06_06F = 26479;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ06_06F_LEN = 26480;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ07_07F = 26481;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ07_07F_LEN = 26482;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ08_08F = 26483;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ08_08F_LEN = 26484;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ09_01FBY2 = 26485;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ09_01FBY2_LEN = 26486;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ10_02FBY2 = 26487;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ10_02FBY2_LEN = 26488;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ11_03FBY2 = 26489;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ11_03FBY2_LEN = 26490;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ12_04FBY2 = 26491;
static const uint64_t IDX_CEN_OPCG_REG1_FUNC_CAPT_SEQ12_04FBY2_LEN = 26492;
static const uint64_t IDX_CEN_OPCG_REG2_SCAN_COUNT = 26493;
static const uint64_t IDX_CEN_OPCG_REG2_SCAN_COUNT_LEN = 26494;
static const uint64_t IDX_CEN_OPCG_REG2_MISR_A_VAL = 26495;
static const uint64_t IDX_CEN_OPCG_REG2_MISR_A_VAL_LEN = 26496;
static const uint64_t IDX_CEN_OPCG_REG2_MISR_B_VAL = 26497;
static const uint64_t IDX_CEN_OPCG_REG2_MISR_B_VAL_LEN = 26498;
static const uint64_t IDX_CEN_OPCG_REG2_MISR_INIT_WAIT = 26499;
static const uint64_t IDX_CEN_OPCG_REG2_MISR_INIT_WAIT_LEN = 26500;
static const uint64_t IDX_CEN_OPCG_REG2_SUPPRESS_EVEN_CLK = 26501;
static const uint64_t IDX_CEN_OPCG_REG2_PAD_VALUE = 26502;
static const uint64_t IDX_CEN_OPCG_REG2_PAD_VALUE_LEN = 26503;
static const uint64_t IDX_CEN_OPCG_REG2_USE_F_AND_FDIV2 = 26504;
static const uint64_t IDX_CEN_OPCG_REG2_USE_ARY_CLK_DURING_FILL = 26505;
static const uint64_t IDX_CEN_OPCG_REG2_SG_HIGH_DURING_FILL = 26506;
static const uint64_t IDX_CEN_OPCG_REG2_RTIM_THOLD_FORCE = 26507;
static const uint64_t IDX_CEN_OPCG_REG2_LBIST_SKITTER_CTL = 26508;
static const uint64_t IDX_CEN_OPCG_REG2_MISR_MODE = 26509;
static const uint64_t IDX_CEN_OPCG_REG2_INFINITE_MODE = 26510;
static const uint64_t IDX_CEN_OPCG_REG2_NSL_FILL_COUNT = 26511;
static const uint64_t IDX_CEN_OPCG_REG2_NSL_FILL_COUNT_LEN = 26512;
static const uint64_t IDX_CEN_OPCG_REG3_GO2 = 26513;
static const uint64_t IDX_CEN_OPCG_REG3_RUN_ON_UPDATE_DR = 26514;
static const uint64_t IDX_CEN_OPCG_REG3_RUN_ON_CAPTURE_DR = 26515;
static const uint64_t IDX_CEN_OPCG_REG3_ALIGN_SOURCE_SELECT = 26516;
static const uint64_t IDX_CEN_OPCG_REG3_ALIGN_SOURCE_SELECT_LEN = 26517;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_WEIGHTING = 26518;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_WEIGHTING_LEN = 26519;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_VALUE = 26520;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_VALUE_LEN = 26521;
static const uint64_t IDX_CEN_OPCG_REG3_EXTEND_INOPW_ENOPW = 26522;
static const uint64_t IDX_CEN_OPCG_REG3_EXTEND_SNOPW = 26523;
static const uint64_t IDX_CEN_OPCG_REG3_FORCE_SG_HIGH_DURING_SNOP = 26524;
static const uint64_t IDX_CEN_OPCG_REG3_CHKSW = 26525;
static const uint64_t IDX_CEN_OPCG_REG3_CHKSW_LEN = 26526;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_A_VAL = 26527;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_A_VAL_LEN = 26528;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_B_VAL = 26529;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_B_VAL_LEN = 26530;
static const uint64_t IDX_CEN_OPCG_REG3_PRPG_MODE = 26531;
static const uint64_t IDX_CEN_OPCG_REG3_SCAN_CLK_USE_EVEN = 26532;
static const uint64_t IDX_CEN_OPCG_REG3_AUTO_SCAN0 = 26533;
static const uint64_t IDX_CEN_OPCG_REG3_SPARE3 = 26534;
static const uint64_t IDX_CEN_OPCG_REG3_SPARE3_LEN = 26535;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_CMD = 26536;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_CMD_LEN = 26537;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_PERV = 26538;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_UNIT0 = 26539;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_UNIT1 = 26540;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_UNIT2 = 26541;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_UNIT3 = 26542;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_UNIT4 = 26543;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_UNIT5 = 26544;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_PLL = 26545;
static const uint64_t IDX_CEN_CLK_REGION_CLOCK_OSCSW = 26546;
static const uint64_t IDX_CEN_CLK_REGION_SEL_THOLD_SL = 26547;
static const uint64_t IDX_CEN_CLK_REGION_SEL_THOLD_NSL = 26548;
static const uint64_t IDX_CEN_CLK_REGION_SEL_THOLD_ARY = 26549;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_VITL = 26550;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_PERV = 26551;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_UNIT0 = 26552;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_UNIT1 = 26553;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_UNIT2 = 26554;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_UNIT3 = 26555;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_UNIT4 = 26556;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_UNIT5 = 26557;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_PLL = 26558;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CLK_OSCSW = 26559;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_FUNC = 26560;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CFG = 26561;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CCFG_GPTR = 26562;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_REGF = 26563;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_LBIST = 26564;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_ABIST = 26565;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_REPR = 26566;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_TIME = 26567;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_BNDY = 26568;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_FARR = 26569;
static const uint64_t IDX_CEN_SCANSELQ_SCANSEL_CMSK = 26570;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_PERV_FUNC_SL = 26571;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_PERV_FUNC_NSL = 26572;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_PERV_ARY_NSL = 26573;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT0_FUNC_SL = 26574;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT0_FUNC_NSL = 26575;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT0_ARY_NSL = 26576;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT1_FUNC_SL = 26577;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT1_FUNC_NSL = 26578;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT1_ARY_NSL = 26579;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT2_FUNC_SL = 26580;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT2_FUNC_NSL = 26581;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT2_ARY_NSL = 26582;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT3_FUNC_SL = 26583;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT3_FUNC_NSL = 26584;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT3_ARY_NSL = 26585;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT4_FUNC_SL = 26586;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT4_FUNC_NSL = 26587;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT4_ARY_NSL = 26588;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT5_FUNC_SL = 26589;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT5_FUNC_NSL = 26590;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_UNIT5_ARY_NSL = 26591;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_PLL_FUNC_SL = 26592;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_PLL_FUNC_NSL = 26593;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_PLL_ARY_NSL = 26594;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_OSCSW_FUNC_SL = 26595;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_OSCSW_FUNC_NSL = 26596;
static const uint64_t IDX_CEN_CLOCK_STAT_STATUS_OSCSW_ARY_NSL = 26597;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED = 26598;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_READ_NOT_ALLOWED = 26599;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_PARITY_ERR_ON_CMD = 26600;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_ADDRESS_NOT_VALID = 26601;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_PARITY_ADDR_ERR = 26602;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_PARITY_DATA_ERR = 26603;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID = 26604;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_PARITY_SPCIF_ERR = 26605;
static const uint64_t IDX_CEN_ERROR_STATUS_PCB_WRITE_AND_OPCG = 26606;
static const uint64_t IDX_CEN_ERROR_STATUS_CLOCK_CMD_CONFLICT = 26607;
static const uint64_t IDX_CEN_ERROR_STATUS_SCAN_COLLISION = 26608;
static const uint64_t IDX_CEN_ERROR_STATUS_OPCG_TRIGGER = 26609;
static const uint64_t IDX_CEN_ERROR_STATUS_OPCG_PARITY = 26610;
static const uint64_t IDX_CEN_ERROR_STATUS_PHASE_CNT_CORRUPTED = 26611;
static const uint64_t IDX_CEN_ERROR_STATUS_CC_PAR_ERR = 26612;
static const uint64_t IDX_CEN_ERROR_STATUS_CC_PAR_ERR_LEN = 26613;
static const uint64_t IDX_CEN_ERROR_STATUS_GPIO_PAR_ERR = 26614;
static const uint64_t IDX_CEN_ERROR_STATUS_SECURITY_VIOLATION = 26615;
static const uint64_t IDX_CEN_CC_PROTECT_MODE_REG_READ_ENABLE = 26616;
static const uint64_t IDX_CEN_CC_PROTECT_MODE_REG_WRITE_ENABLE = 26617;
static const uint64_t IDX_CEN_CC_ATOMIC_LOCK_REG_ENABLE = 26618;
static const uint64_t IDX_CEN_CC_ATOMIC_LOCK_REG_ID = 26619;
static const uint64_t IDX_CEN_CC_ATOMIC_LOCK_REG_ID_LEN = 26620;
static const uint64_t IDX_CEN_GP0_NOT_USED0 = 26621;
static const uint64_t IDX_CEN_GP0_NOT_USED1 = 26622;
static const uint64_t IDX_CEN_GP0_TC_GPIO_FLUSHMODE_INH_DC_OUT = 26623;
static const uint64_t IDX_CEN_GP0_TC_GPIO_FORCEALIGN = 26624;
static const uint64_t IDX_CEN_GP0_TC_GPIO_AVP_MODE_DC_OUT = 26625;
static const uint64_t IDX_CEN_GP0_NOT_USED3 = 26626;
static const uint64_t IDX_CEN_GP0_TC_GPIO_CC_SCAN_DIS_DC_B_OUT = 26627;
static const uint64_t IDX_CEN_GP0_NOT_USED2 = 26628;
static const uint64_t IDX_CEN_GP0_TC_GPIO_LBIST_EN_DC_OUT = 26629;
static const uint64_t IDX_CEN_GP0_TC_UNIT_LBIST_AC_MODE_DC = 26630;
static const uint64_t IDX_CEN_GP0_TC_UNIT_LBIST_ARY_WRT_THRU_DC = 26631;
static const uint64_t IDX_CEN_GP0_TC_ABIST_MODE_DC = 26632;
static const uint64_t IDX_CEN_GP0_TC_GPIO_ABIST_START_TEST_DC_OUT = 26633;
static const uint64_t IDX_CEN_GP0_NOT_USED4 = 26634;
static const uint64_t IDX_CEN_GP0_NOT_USED5 = 26635;
static const uint64_t IDX_CEN_GP0_TC_GPIO_SCAN_PROTECT_DC_OUT = 26636;
static const uint64_t IDX_CEN_GP0_NOT_USED6 = 26637;
static const uint64_t IDX_CEN_GP0_NOT_USED7 = 26638;
static const uint64_t IDX_CEN_GP0_NOT_USED8 = 26639;
static const uint64_t IDX_CEN_GP0_NOT_USED9 = 26640;
static const uint64_t IDX_CEN_GP0_TP_GPIO_TRACE_START = 26641;
static const uint64_t IDX_CEN_GP0_TP_GPIO_TRACE_STOP = 26642;
static const uint64_t IDX_CEN_GP0_TP_GPIO_TRACE_RESET = 26643;
static const uint64_t IDX_CEN_GP0_TP_PIB_TRACE_MODE_DATA = 26644;
static const uint64_t IDX_CEN_GP0_TC_GPIO_CLKDIV_SEL_DC = 26645;
static const uint64_t IDX_CEN_GP0_TC_GPIO_CLKDIV_SEL_DC_LEN = 26646;
static const uint64_t IDX_CEN_GP0_NOT_USED10 = 26647;
static const uint64_t IDX_CEN_GP0_NOT_USED11 = 26648;
static const uint64_t IDX_CEN_GP0_NOT_USED12 = 26649;
static const uint64_t IDX_CEN_GP0_NOT_USED12_LEN = 26650;
static const uint64_t IDX_CEN_GP0_TC_PSRO_SEL_DC = 26651;
static const uint64_t IDX_CEN_GP0_TC_PSRO_SEL_DC_LEN = 26652;
static const uint64_t IDX_CEN_GP0_NOT_USED13 = 26653;
static const uint64_t IDX_CEN_GP0_NOT_USED13_LEN = 26654;
static const uint64_t IDX_CEN_GP0_NOT_USED14 = 26655;
static const uint64_t IDX_CEN_GP0_NOT_USED14_LEN = 26656;
static const uint64_t IDX_CEN_GP0_TC_BSC_WRAPSEL_DC = 26657;
static const uint64_t IDX_CEN_GP0_TC_BSC_INTMODE_DC = 26658;
static const uint64_t IDX_CEN_GP0_TC_BSC_INV_DC = 26659;
static const uint64_t IDX_CEN_GP0_TC_BSC_EXTMODE_DC = 26660;
static const uint64_t IDX_CEN_GP0_NOT_USED15 = 26661;
static const uint64_t IDX_CEN_GP0_NOT_USED16 = 26662;
static const uint64_t IDX_CEN_GP0_NOT_USED17 = 26663;
static const uint64_t IDX_CEN_GP0_NOT_USED18 = 26664;
static const uint64_t IDX_CEN_GP0_NOT_USED19 = 26665;
static const uint64_t IDX_CEN_GP0_NOT_USED20 = 26666;
static const uint64_t IDX_CEN_GP0_NOT_USED21 = 26667;
static const uint64_t IDX_CEN_GP0_NOT_USED22 = 26668;
static const uint64_t IDX_CEN_GP0_NOT_USED23 = 26669;
static const uint64_t IDX_CEN_GP0_NOT_USED24 = 26670;
static const uint64_t IDX_CEN_GP0_TC_MASK_CC_PCB_ERR_DC = 26671;
static const uint64_t IDX_CEN_GP0_TC_MASK_CC_SCAN_OPCG_ERR_DC = 26672;
static const uint64_t IDX_CEN_GP0_NOT_USED25 = 26673;
static const uint64_t IDX_CEN_GP0_TC_FENCE_PERV_DC = 26674;
static const uint64_t IDX_CEN_GP1_TRA_ABIST_DONE = 26675;
static const uint64_t IDX_CEN_GP1_NOT_USED26 = 26676;
static const uint64_t IDX_CEN_GP1_NOT_USED27 = 26677;
static const uint64_t IDX_CEN_GP1_NOT_USED28 = 26678;
static const uint64_t IDX_CEN_GP1_NOT_USED29 = 26679;
static const uint64_t IDX_CEN_GP1_NOT_USED30 = 26680;
static const uint64_t IDX_CEN_GP1_NOT_USED31 = 26681;
static const uint64_t IDX_CEN_GP1_NOT_USED32 = 26682;
static const uint64_t IDX_CEN_GP1_NOT_USED33 = 26683;
static const uint64_t IDX_CEN_GP1_NOT_USED34 = 26684;
static const uint64_t IDX_CEN_GP1_NOT_USED35 = 26685;
static const uint64_t IDX_CEN_GP1_NOT_USED36 = 26686;
static const uint64_t IDX_CEN_GP1_NOT_USED37 = 26687;
static const uint64_t IDX_CEN_GP1_NOT_USED38 = 26688;
static const uint64_t IDX_CEN_GP1_NOT_USED39 = 26689;
static const uint64_t IDX_CEN_GP1_TC_OPCG_DONE_DC = 26690;
static const uint64_t IDX_CEN_GP1_NOT_USED40 = 26691;
static const uint64_t IDX_CEN_GP1_NOT_USED41 = 26692;
static const uint64_t IDX_CEN_GP1_NOT_USED42 = 26693;
static const uint64_t IDX_CEN_GP1_NOT_USED43 = 26694;
static const uint64_t IDX_CEN_GP1_NOT_USED44 = 26695;
static const uint64_t IDX_CEN_GP1_NOT_USED45 = 26696;
static const uint64_t IDX_CEN_GP1_NOT_USED46 = 26697;
static const uint64_t IDX_CEN_GP1_NOT_USED47 = 26698;
static const uint64_t IDX_CEN_GP2_GPIN_MASKING = 26699;
static const uint64_t IDX_CEN_GP2_GPIN_MASKING_LEN = 26700;
static const uint64_t IDX_CEN_GP4_TC_PROBE0_SEL_DC = 26701;
static const uint64_t IDX_CEN_GP4_TC_PROBE0_SEL_DC_LEN = 26702;
static const uint64_t IDX_CEN_GP4_NOT_USED48 = 26703;
static const uint64_t IDX_CEN_GP4_NOT_USED48_LEN = 26704;
static const uint64_t IDX_CEN_GP4_TC_PROBE1_SEL_DC = 26705;
static const uint64_t IDX_CEN_GP4_TC_PROBE1_SEL_DC_LEN = 26706;
static const uint64_t IDX_CEN_GP4_NOT_USED49 = 26707;
static const uint64_t IDX_CEN_GP4_NOT_USED49_LEN = 26708;
static const uint64_t IDX_CEN_GP4_TC_PROBE2_SEL_DC = 26709;
static const uint64_t IDX_CEN_GP4_TC_PROBE2_SEL_DC_LEN = 26710;
static const uint64_t IDX_CEN_GP4_NOT_USED50 = 26711;
static const uint64_t IDX_CEN_GP4_NOT_USED50_LEN = 26712;
static const uint64_t IDX_CEN_GP4_TC_PROBE3_SEL_DC = 26713;
static const uint64_t IDX_CEN_GP4_TC_PROBE3_SEL_DC_LEN = 26714;
static const uint64_t IDX_CEN_GP4_NOT_USED51 = 26715;
static const uint64_t IDX_CEN_GP4_NOT_USED52 = 26716;
static const uint64_t IDX_CEN_GP4_NOT_USED53 = 26717;
static const uint64_t IDX_CEN_GP4_NOT_USED54 = 26718;
static const uint64_t IDX_CEN_GP4_NOT_USED55 = 26719;
static const uint64_t IDX_CEN_GP4_NOT_USED56 = 26720;
static const uint64_t IDX_CEN_GP4_NOT_USED57 = 26721;
static const uint64_t IDX_CEN_GP4_NOT_USED58 = 26722;
static const uint64_t IDX_CEN_GP4_NOT_USED59 = 26723;
static const uint64_t IDX_CEN_GP4_NOT_USED60 = 26724;
static const uint64_t IDX_CEN_GP4_NOT_USED61 = 26725;
static const uint64_t IDX_CEN_GP4_NOT_USED62 = 26726;
static const uint64_t IDX_CEN_GP4_NOT_USED63 = 26727;
static const uint64_t IDX_CEN_GP4_NOT_USED64 = 26728;
static const uint64_t IDX_CEN_GP4_NOT_USED65 = 26729;
static const uint64_t IDX_CEN_GP4_NOT_USED66 = 26730;
static const uint64_t IDX_CEN_GP4_NOT_USED67 = 26731;
static const uint64_t IDX_CEN_GP4_NOT_USED68 = 26732;
static const uint64_t IDX_CEN_GP4_NOT_USED69 = 26733;
static const uint64_t IDX_CEN_GP4_NOT_USED70 = 26734;
static const uint64_t IDX_CEN_GP4_NOT_USED71 = 26735;
static const uint64_t IDX_CEN_GP4_NOT_USED72 = 26736;
static const uint64_t IDX_CEN_GP4_NOT_USED73 = 26737;
static const uint64_t IDX_CEN_GP4_NOT_USED74 = 26738;
static const uint64_t IDX_CEN_GP4_NOT_USED75 = 26739;
static const uint64_t IDX_CEN_GP4_NOT_USED76 = 26740;
static const uint64_t IDX_CEN_GP4_NOT_USED77 = 26741;
static const uint64_t IDX_CEN_GP4_NOT_USED78 = 26742;
static const uint64_t IDX_CEN_GP4_NOT_USED79 = 26743;
static const uint64_t IDX_CEN_GP4_NOT_USED80 = 26744;
static const uint64_t IDX_CEN_GP4_NOT_USED81 = 26745;
static const uint64_t IDX_CEN_GP4_NOT_USED82 = 26746;
static const uint64_t IDX_CEN_GP4_NOT_USED83 = 26747;
static const uint64_t IDX_CEN_GP4_NOT_USED84 = 26748;
static const uint64_t IDX_CEN_GPIO_PROTECT_MODE_REG_READ_ENABLE = 26749;
static const uint64_t IDX_CEN_GPIO_PROTECT_MODE_REG_WRITE_ENABLE = 26750;
static const uint64_t IDX_CEN_GPIO_ATOMIC_LOCK_REG_ENABLE = 26751;
static const uint64_t IDX_CEN_GPIO_ATOMIC_LOCK_REG_ID = 26752;
static const uint64_t IDX_CEN_GPIO_ATOMIC_LOCK_REG_ID_LEN = 26753;
static const uint64_t IDX_CEN_XFIR_IN0 = 26754;
static const uint64_t IDX_CEN_XFIR_IN1 = 26755;
static const uint64_t IDX_CEN_XFIR_IN2 = 26756;
static const uint64_t IDX_CEN_XFIR_IN3 = 26757;
static const uint64_t IDX_CEN_XFIR_IN4 = 26758;
static const uint64_t IDX_CEN_XFIR_IN4_LEN = 26759;
static const uint64_t IDX_CEN_XFIR_IN26 = 26760;
static const uint64_t IDX_CEN_RFIR_IN0 = 26761;
static const uint64_t IDX_CEN_RFIR_LFIR_RECOV_ERR = 26762;
static const uint64_t IDX_CEN_RFIR_IN = 26763;
static const uint64_t IDX_CEN_RFIR_IN_LEN = 26764;
static const uint64_t IDX_CEN_FIR_MASK_IN0 = 26765;
static const uint64_t IDX_CEN_FIR_MASK_IN1 = 26766;
static const uint64_t IDX_CEN_FIR_MASK_IN2 = 26767;
static const uint64_t IDX_CEN_FIR_MASK_IN3 = 26768;
static const uint64_t IDX_CEN_FIR_MASK_IN4 = 26769;
static const uint64_t IDX_CEN_FIR_MASK_IN4_LEN = 26770;
static const uint64_t IDX_CEN_LOCAL_FIR_IN0 = 26771;
static const uint64_t IDX_CEN_LOCAL_FIR_IN1 = 26772;
static const uint64_t IDX_CEN_LOCAL_FIR_IN2 = 26773;
static const uint64_t IDX_CEN_LOCAL_FIR_IN3 = 26774;
static const uint64_t IDX_CEN_LOCAL_FIR_IN4 = 26775;
static const uint64_t IDX_CEN_LOCAL_FIR_IN5 = 26776;
static const uint64_t IDX_CEN_LOCAL_FIR_IN6 = 26777;
static const uint64_t IDX_CEN_LOCAL_FIR_IN7 = 26778;
static const uint64_t IDX_CEN_LOCAL_FIR_IN8 = 26779;
static const uint64_t IDX_CEN_LOCAL_FIR_IN9 = 26780;
static const uint64_t IDX_CEN_LOCAL_FIR_IN10 = 26781;
static const uint64_t IDX_CEN_LOCAL_FIR_IN11 = 26782;
static const uint64_t IDX_CEN_LOCAL_FIR_IN12 = 26783;
static const uint64_t IDX_CEN_LOCAL_FIR_IN13 = 26784;
static const uint64_t IDX_CEN_LOCAL_FIR_IN13_LEN = 26785;
static const uint64_t IDX_CEN_LOCAL_FIR_IN15 = 26786;
static const uint64_t IDX_CEN_LOCAL_FIR_IN16 = 26787;
static const uint64_t IDX_CEN_LOCAL_FIR_IN16_LEN = 26788;
static const uint64_t IDX_CEN_LOCAL_FIR_IN19 = 26789;
static const uint64_t IDX_CEN_LOCAL_FIR_IN20 = 26790;
static const uint64_t IDX_CEN_LOCAL_FIR_IN21 = 26791;
static const uint64_t IDX_CEN_LOCAL_FIR_IN21_LEN = 26792;
static const uint64_t IDX_CEN_LOCAL_FIR_IN40 = 26793;
static const uint64_t IDX_CEN_DBG_MODE_REG_GLB_BRCST = 26794;
static const uint64_t IDX_CEN_DBG_MODE_REG_GLB_BRCST_LEN = 26795;
static const uint64_t IDX_CEN_DBG_MODE_REG_TRACE_SEL = 26796;
static const uint64_t IDX_CEN_DBG_MODE_REG_TRACE_SEL_LEN = 26797;
static const uint64_t IDX_CEN_DBG_MODE_REG_TRIG_SEL = 26798;
static const uint64_t IDX_CEN_DBG_MODE_REG_TRIG_SEL_LEN = 26799;
static const uint64_t IDX_CEN_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 26800;
static const uint64_t IDX_CEN_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 26801;
static const uint64_t IDX_CEN_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 26802;
static const uint64_t IDX_CEN_DBG_MODE_REG_FREEZE_SEL = 26803;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND1_SEL_A = 26804;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 26805;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND1_SEL_B = 26806;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 26807;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND2_SEL_A = 26808;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 26809;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND2_SEL_B = 26810;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 26811;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 26812;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 26813;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 26814;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 26815;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 = 26816;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN = 26817;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 26818;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 26819;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 26820;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 26821;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 = 26822;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN = 26823;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 26824;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 26825;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 26826;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 26827;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 26828;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 26829;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_C1_COUNT_LT = 26830;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 26831;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_C2_COUNT_LT = 26832;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 26833;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 26834;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 26835;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_1_A = 26836;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_1_A_LEN = 26837;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 26838;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 26839;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_A = 26840;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_A_LEN = 26841;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_B = 26842;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_2_B_LEN = 26843;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_SP_COUNT_LT = 26844;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN = 26845;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE = 26846;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN = 26847;
static const uint64_t IDX_CEN_DBG_INST1_COND_REG_2_FORCE_TEST_MODE = 26848;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND1_SEL_A = 26849;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 26850;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND1_SEL_B = 26851;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 26852;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND2_SEL_A = 26853;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 26854;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND2_SEL_B = 26855;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 26856;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 26857;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 26858;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 26859;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 26860;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 = 26861;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN = 26862;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 26863;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 26864;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 26865;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 26866;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 = 26867;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN = 26868;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 26869;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 26870;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 26871;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 26872;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 26873;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 26874;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_C1_COUNT_LT = 26875;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 26876;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_C2_COUNT_LT = 26877;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 26878;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 26879;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 26880;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_1_A = 26881;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_1_A_LEN = 26882;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 26883;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 26884;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_A = 26885;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_A_LEN = 26886;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_B = 26887;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_2_B_LEN = 26888;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_SP_COUNT_LT = 26889;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN = 26890;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE = 26891;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN = 26892;
static const uint64_t IDX_CEN_DBG_INST2_COND_REG_2_FORCE_TEST_MODE = 26893;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 26894;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 26895;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 26896;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 26897;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 26898;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 26899;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 26900;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 26901;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 26902;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 26903;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 26904;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 26905;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 26906;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 26907;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 26908;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 26909;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 26910;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 26911;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 26912;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 26913;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 26914;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 26915;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 26916;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 26917;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 26918;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 26919;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 26920;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 26921;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_ARM_SEL = 26922;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_ARM_SEL_LEN = 26923;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 26924;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 26925;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 26926;
static const uint64_t IDX_CEN_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 26927;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 26928;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 26929;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 26930;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 26931;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 26932;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 26933;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 26934;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 26935;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 26936;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 26937;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 26938;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 26939;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 26940;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 26941;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26942;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 26943;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 26944;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 26945;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 26946;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 26947;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 26948;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 26949;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 26950;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 26951;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 26952;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 26953;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 26954;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 26955;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 26956;
static const uint64_t IDX_CEN_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 26957;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 26958;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 26959;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 26960;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 26961;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 26962;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_FORCE_TEST = 26963;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 26964;
static const uint64_t IDX_CEN_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON = 26965;
static const uint64_t IDX_CEN_DTS_RESULT0_0_RESULT = 26966;
static const uint64_t IDX_CEN_DTS_RESULT0_0_RESULT_LEN = 26967;
static const uint64_t IDX_CEN_DTS_RESULT0_1_RESULT = 26968;
static const uint64_t IDX_CEN_DTS_RESULT0_1_RESULT_LEN = 26969;
static const uint64_t IDX_CEN_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 26970;
static const uint64_t IDX_CEN_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 26971;
static const uint64_t IDX_CEN_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 26972;
static const uint64_t IDX_CEN_DTS_TRC_RESULT_0_RESULT = 26973;
static const uint64_t IDX_CEN_DTS_TRC_RESULT_0_RESULT_LEN = 26974;
static const uint64_t IDX_CEN_ENC_CPM_RESULT0_DTS_0_RESULT = 26975;
static const uint64_t IDX_CEN_ENC_CPM_RESULT0_DTS_0_RESULT_LEN = 26976;
static const uint64_t IDX_CEN_ENC_CPM_RESULT0_DTS_1_RESULT = 26977;
static const uint64_t IDX_CEN_ENC_CPM_RESULT0_DTS_1_RESULT_LEN = 26978;
static const uint64_t IDX_CEN_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 26979;
static const uint64_t IDX_CEN_THERM_MODE_REG_FORCE_THRES_ACT = 26980;
static const uint64_t IDX_CEN_THERM_MODE_REG_THRES_TRIP_ENA = 26981;
static const uint64_t IDX_CEN_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 26982;
static const uint64_t IDX_CEN_THERM_MODE_REG_DTS_SAMPLE_ENA = 26983;
static const uint64_t IDX_CEN_THERM_MODE_REG_SAMPLE_PULSE_CNT = 26984;
static const uint64_t IDX_CEN_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 26985;
static const uint64_t IDX_CEN_THERM_MODE_REG_THRES_ENA = 26986;
static const uint64_t IDX_CEN_THERM_MODE_REG_THRES_ENA_LEN = 26987;
static const uint64_t IDX_CEN_THERM_MODE_REG_DTS_TRIGGER = 26988;
static const uint64_t IDX_CEN_THERM_MODE_REG_DTS_TRIGGER_SEL = 26989;
static const uint64_t IDX_CEN_THERM_MODE_REG_UNUSED = 26990;
static const uint64_t IDX_CEN_THERM_MODE_REG_UNUSED_LEN = 26991;
static const uint64_t IDX_CEN_THERM_MODE_REG_DTS_READ_SEL = 26992;
static const uint64_t IDX_CEN_THERM_MODE_REG_DTS_READ_SEL_LEN = 26993;
static const uint64_t IDX_CEN_THERM_MODE_REG_DTS_ENABLE = 26994;
static const uint64_t IDX_CEN_THERM_MODE_REG_DTS_ENABLE_LEN = 26995;
static const uint64_t IDX_CEN_THERM_MODE_REG_CPM_ENABLE = 26996;
static const uint64_t IDX_CEN_THERM_MODE_REG_CPM_ENABLE_LEN = 26997;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_HOLD_SAMPLE = 26998;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_DISABLE_STICKINESS = 26999;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_UNUSED1 = 27000;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_UNUSED1_LEN = 27001;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 27002;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 27003;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_RESET_TRIG_SEL = 27004;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 27005;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_SAMPLE_GUTS = 27006;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 27007;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 27008;
static const uint64_t IDX_CEN_SKITTER_MODE_REG_DATA_V_LT = 27009;
static const uint64_t IDX_CEN_SKITTER_CLKSRC_REG_SKITTER0 = 27010;
static const uint64_t IDX_CEN_SKITTER_CLKSRC_REG_SKITTER0_LEN = 27011;
static const uint64_t IDX_CEN_INJECT_REG_THERM_TRIP = 27012;
static const uint64_t IDX_CEN_INJECT_REG_THERM_TRIP_LEN = 27013;
static const uint64_t IDX_CEN_INJECT_REG_THERM_MODE = 27014;
static const uint64_t IDX_CEN_INJECT_REG_THERM_MODE_LEN = 27015;
static const uint64_t IDX_CEN_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 27016;
static const uint64_t IDX_CEN_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 27017;
static const uint64_t IDX_CEN_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 27018;
static const uint64_t IDX_CEN_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 27019;
static const uint64_t IDX_CEN_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_MASK = 27020;
static const uint64_t IDX_CEN_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 27021;
static const uint64_t IDX_CEN_ERR_STATUS_REG_COUNT_STATE_MASK = 27022;
static const uint64_t IDX_CEN_ERR_STATUS_REG_RUN_STATE_MASK = 27023;
static const uint64_t IDX_CEN_ERR_STATUS_REG_THRES_STATE_MASK = 27024;
static const uint64_t IDX_CEN_ERR_STATUS_REG_OVERFLOW_MASK = 27025;
static const uint64_t IDX_CEN_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 27026;
static const uint64_t IDX_CEN_ERR_STATUS_REG_SHIFTER_VALID_MASK = 27027;
static const uint64_t IDX_CEN_ERR_STATUS_REG_TIMEOUT_MASK = 27028;
static const uint64_t IDX_CEN_ERR_STATUS_REG_F_SKITTER_READ_MASK = 27029;
static const uint64_t IDX_CEN_ERR_STATUS_REG_PCB_MASK = 27030;
static const uint64_t IDX_CEN_SKITTER_FORCE_REG_F_READ = 27031;
static const uint64_t IDX_CEN_VOLT_MODE_REG_MEASURE_ENA = 27032;
static const uint64_t IDX_CEN_VOLT_MODE_REG_TRIP_ENA = 27033;
static const uint64_t IDX_CEN_VOLT_MODE_REG_ENABLE = 27034;
static const uint64_t IDX_CEN_VOLT_MODE_REG_ENABLE_LEN = 27035;
static const uint64_t IDX_CEN_TIMESTAMP_COUNTER_READ_VALUE = 27036;
static const uint64_t IDX_CEN_TIMESTAMP_COUNTER_READ_VALUE_LEN = 27037;
static const uint64_t IDX_CEN_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 27038;
static const uint64_t IDX_CEN_SPATTN_IN0 = 27039;
static const uint64_t IDX_CEN_SPATTN_IN1 = 27040;
static const uint64_t IDX_CEN_SPATTN_IN2 = 27041;
static const uint64_t IDX_CEN_SPATTN_IN2_LEN = 27042;
static const uint64_t IDX_CEN_SPA_MASK_IN = 27043;
static const uint64_t IDX_CEN_SPA_MASK_IN_LEN = 27044;
static const uint64_t IDX_CEN_MODE_REG_IN0 = 27045;
static const uint64_t IDX_CEN_MODE_REG_IN1 = 27046;
static const uint64_t IDX_CEN_MODE_REG_IN2 = 27047;
static const uint64_t IDX_CEN_MODE_REG_IN3 = 27048;
static const uint64_t IDX_CEN_MODE_REG_IN4 = 27049;
static const uint64_t IDX_CEN_MODE_REG_IN5 = 27050;
static const uint64_t IDX_CEN_MODE_REG_IN6 = 27051;
static const uint64_t IDX_CEN_MODE_REG_IN7 = 27052;
static const uint64_t IDX_CEN_MODE_REG_IN8 = 27053;
static const uint64_t IDX_CEN_MODE_REG_IN9 = 27054;
static const uint64_t IDX_CEN_MODE_REG_IN10 = 27055;
static const uint64_t IDX_CEN_MODE_REG_IN11 = 27056;
static const uint64_t IDX_CEN_MODE_REG_IN = 27057;
static const uint64_t IDX_CEN_MODE_REG_IN_LEN = 27058;
static const uint64_t IDX_CEN_LOCAL_FIR_ACTION0_IN = 27059;
static const uint64_t IDX_CEN_LOCAL_FIR_ACTION0_IN_LEN = 27060;
static const uint64_t IDX_CEN_LOCAL_FIR_ACTION1_IN = 27061;
static const uint64_t IDX_CEN_LOCAL_FIR_ACTION1_IN_LEN = 27062;
static const uint64_t IDX_CEN_LOCAL_FIR_MASK_LFIR_IN = 27063;
static const uint64_t IDX_CEN_LOCAL_FIR_MASK_LFIR_IN_LEN = 27064;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 27065;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 27066;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR = 27067;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 27068;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_WATCHDOG_ENABLE = 27069;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 27070;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 27071;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_FORCE_ALL_RINGS = 27072;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 27073;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_RESERVED_LT = 27074;
static const uint64_t IDX_CEN_PSCOM_MODE_REG_RESERVED_LT_LEN = 27075;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 27076;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 27077;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 27078;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 27079;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 27080;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 27081;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 27082;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 27083;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 27084;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27085;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 27086;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 27087;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 27088;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 27089;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 27090;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 27091;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 27092;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 27093;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 27094;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 27095;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 27096;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 27097;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 27098;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 27099;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 27100;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 27101;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 27102;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27103;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 27104;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 27105;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 27106;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 27107;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 27108;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 27109;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 27110;
static const uint64_t IDX_CEN_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 27111;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 27112;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 27113;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 27114;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_DL_RETURN_P0 = 27115;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 27116;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_UL_P0 = 27117;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 27118;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 27119;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 27120;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27121;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 27122;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_MASK_PARALLEL_WRITE_NVLD = 27123;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_MASK_PARALLEL_READ_NVLD = 27124;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_MASK_PARALLEL_ADDR_INVALID = 27125;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 27126;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 27127;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 27128;
static const uint64_t IDX_CEN_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 27129;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 27130;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 27131;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 27132;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_RESERVED_LAST_LT = 27133;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 27134;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 27135;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 27136;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 27137;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 27138;
static const uint64_t IDX_CEN_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 27139;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN = 27140;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_TRACE_STATE_LAT = 27141;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN = 27142;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_TRACE_FREEZE = 27143;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_COND3_STATE_LT = 27144;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_COND3_STATE_LT_LEN = 27145;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_COND5_STATE_LT = 27146;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_COND5_STATE_LT_LEN = 27147;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT = 27148;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT = 27149;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT = 27150;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT = 27151;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT = 27152;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT = 27153;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_RESERVED_TCDBG_LT = 27154;
static const uint64_t IDX_CEN_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN = 27155;
static const uint64_t IDX_CEN_PSCOM_WRITE_PROTECT_REG_ENABLE_SERIAL_RING = 27156;
static const uint64_t IDX_CEN_PSCOM_WRITE_PROTECT_REG_RESERVED = 27157;
static const uint64_t IDX_CEN_ATOMIC_LOCK_REG_ENABLE = 27158;
static const uint64_t IDX_CEN_ATOMIC_LOCK_REG_ID = 27159;
static const uint64_t IDX_CEN_ATOMIC_LOCK_REG_ID_LEN = 27160;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 27161;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 27162;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE = 27163;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN = 27164;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_BANK_MODE = 27165;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_ENH_MODE = 27166;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL = 27167;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN = 27168;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 27169;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 27170;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 27171;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 27172;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_2_PATTERNA = 27173;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 27174;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_2_PATTERNB = 27175;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 27176;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_3_PATTERNC = 27177;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 27178;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_3_PATTERND = 27179;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 27180;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_4_MASKA = 27181;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 27182;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_4_MASKB = 27183;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 27184;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_5_MASKC = 27185;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 27186;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_5_MASKD = 27187;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 27188;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 27189;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 27190;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 27191;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 27192;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 27193;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 27194;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 27195;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 27196;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 27197;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 27198;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 27199;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 27200;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 27201;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 27202;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 27203;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 27204;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 27205;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 27206;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 27207;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27208;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 27209;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 27210;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_HI_DATA_REG_DATA = 27211;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_HI_DATA_REG_DATA_LEN = 27212;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_DATA = 27213;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_DATA_LEN = 27214;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_ADDRESS = 27215;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_ADDRESS_LEN = 27216;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_LAST_BANK = 27217;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_LAST_BANK_LEN = 27218;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_LAST_BANK_VALID = 27219;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_WRITE_ON_RUN = 27220;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_RUNNING = 27221;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_HOLD_ADDRESS = 27222;
static const uint64_t IDX_CEN_TRA_PERVTRA_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 27223;
static const uint64_t IDX_CEN_FMU_MODE_REG_TOD_CNTR_REF = 27224;
static const uint64_t IDX_CEN_FMU_MODE_REG_TOD_CNTR_REF_LEN = 27225;
static const uint64_t IDX_CEN_FMU_MODE_REG_POWER_UP_CNTR_REF = 27226;
static const uint64_t IDX_CEN_FMU_MODE_REG_POWER_UP_CNTR_REF_LEN = 27227;
static const uint64_t IDX_CEN_FMU_OSC_CNTR1_REG_RESULT_AVAILABLE = 27228;
static const uint64_t IDX_CEN_FMU_OSC_CNTR1_REG_PULSE1_CNTR = 27229;
static const uint64_t IDX_CEN_FMU_OSC_CNTR1_REG_PULSE1_CNTR_LEN = 27230;
static const uint64_t IDX_CEN_FMU_PULSE_GEN_REG_INT_ENA = 27231;
static const uint64_t IDX_CEN_FMU_PULSE_GEN_REG_INT_CNTR_REF = 27232;
static const uint64_t IDX_CEN_FMU_PULSE_GEN_REG_INT_CNTR_REF_LEN = 27233;
static const uint64_t IDX_CEN_FMU_OSC_CNTR2_REG_RESULT_AVAILABLE = 27234;
static const uint64_t IDX_CEN_FMU_OSC_CNTR2_REG_PULSE2_CNTR = 27235;
static const uint64_t IDX_CEN_FMU_OSC_CNTR2_REG_PULSE2_CNTR_LEN = 27236;
static const uint64_t IDX_CEN_HOST_MASK_REG_IPOLL_X = 27237;
static const uint64_t IDX_CEN_HOST_MASK_REG_IPOLL_R = 27238;
static const uint64_t IDX_CEN_HOST_MASK_REG_IPOLL_A = 27239;
static const uint64_t IDX_CEN_HOST_MASK_REG_IPOLL_H = 27240;
static const uint64_t IDX_CEN_HOST_MASK_REG_ERROR_X = 27241;
static const uint64_t IDX_CEN_HOST_MASK_REG_ERROR_R = 27242;
static const uint64_t IDX_CEN_HOST_MASK_REG_ERROR_A = 27243;
static const uint64_t IDX_CEN_HOST_MASK_REG_ERROR_H = 27244;
static const uint64_t IDX_CEN_OSCERR_HOLD_CP = 27245;
static const uint64_t IDX_CEN_OSCERR_HOLD_CP_LEN = 27246;
static const uint64_t IDX_CEN_OSCERR_HOLD_MEM = 27247;
static const uint64_t IDX_CEN_OSCERR_HOLD_MEM_LEN = 27248;
static const uint64_t IDX_CEN_OSCERR_HOLD_GX = 27249;
static const uint64_t IDX_CEN_OSCERR_HOLD_GX_LEN = 27250;
static const uint64_t IDX_CEN_OSCERR_HOLD_CPLITE = 27251;
static const uint64_t IDX_CEN_OSCERR_HOLD_CPLITE_LEN = 27252;
static const uint64_t IDX_CEN_OSCERR_MASK_CP = 27253;
static const uint64_t IDX_CEN_OSCERR_MASK_CP_LEN = 27254;
static const uint64_t IDX_CEN_OSCERR_MASK_MEM = 27255;
static const uint64_t IDX_CEN_OSCERR_MASK_MEM_LEN = 27256;
static const uint64_t IDX_CEN_OSCERR_MASK_GX = 27257;
static const uint64_t IDX_CEN_OSCERR_MASK_GX_LEN = 27258;
static const uint64_t IDX_CEN_OSCERR_MASK_CPLITE = 27259;
static const uint64_t IDX_CEN_OSCERR_MASK_CPLITE_LEN = 27260;
static const uint64_t IDX_CEN_OSCERR_MCODE_IN = 27261;
static const uint64_t IDX_CEN_OSCERR_MCODE_IN_LEN = 27262;
static const uint64_t IDX_CEN_INTERRUPT1_REG_INTERRUPT1 = 27263;
static const uint64_t IDX_CEN_INTERRUPT1_REG_INTERRUPT1_LEN = 27264;
static const uint64_t IDX_CEN_INTERRUPT2_REG_INTERRUPT2 = 27265;
static const uint64_t IDX_CEN_INTERRUPT2_REG_INTERRUPT2_LEN = 27266;
static const uint64_t IDX_CEN_INTERRUPT3_REG_INTERRUPT3 = 27267;
static const uint64_t IDX_CEN_INTERRUPT3_REG_INTERRUPT3_LEN = 27268;
static const uint64_t IDX_CEN_INTERRUPT4_REG_INTERRUPT4 = 27269;
static const uint64_t IDX_CEN_INTERRUPT4_REG_INTERRUPT4_LEN = 27270;
static const uint64_t IDX_CEN_INTERRUPT_TYPE_MASK_REG_GP = 27271;
static const uint64_t IDX_CEN_INTERRUPT_TYPE_MASK_REG_CC = 27272;
static const uint64_t IDX_CEN_INTERRUPT_TYPE_MASK_REG_UNUSED2 = 27273;
static const uint64_t IDX_CEN_INTERRUPT_TYPE_MASK_REG_UNUSED3 = 27274;
static const uint64_t IDX_CEN_INTERRUPT_CONF_REG_GP = 27275;
static const uint64_t IDX_CEN_INTERRUPT_CONF_REG_CC = 27276;
static const uint64_t IDX_CEN_INTERRUPT_CONF_REG_UNUSED2 = 27277;
static const uint64_t IDX_CEN_INTERRUPT_CONF_REG_UNUSED3 = 27278;
static const uint64_t IDX_CEN_INTERRUPT_HOLD_REG_HOLD = 27279;
static const uint64_t IDX_CEN_INTERRUPT_HOLD_REG_HOLD_LEN = 27280;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_1_MULTICAST1 = 27281;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_1_MULTICAST1_LEN = 27282;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_2_MULTICAST2 = 27283;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_2_MULTICAST2_LEN = 27284;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_3_MULTICAST3 = 27285;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_3_MULTICAST3_LEN = 27286;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_4_MULTICAST4 = 27287;
static const uint64_t IDX_CEN_PCBSLPERV_MULTICAST_GROUP_4_MULTICAST4_LEN = 27288;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CE = 27289;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CHIPLET_ERRORS = 27290;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CHIPLET_ERRORS_LEN = 27291;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_PARITY = 27292;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_DATA_BUFFER = 27293;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_ADDR_BUFFER = 27294;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_PCB_FSM = 27295;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CL_FSM = 27296;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_INT_RX_FSM = 27297;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_INT_TX_FSM = 27298;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_INT_TYPE = 27299;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CL_DATA = 27300;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_INFO = 27301;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_UNUSED_0 = 27302;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CHIPLET_ATOMIC_LOCK = 27303;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_PCB_INTERFACE = 27304;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CHIPLET_OFFLINE = 27305;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CHIPLET_GRID_SKITTER = 27306;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_GP3_PARITY = 27307;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_ADDRESS_PARITY = 27308;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_TIMEOUT_PARITY = 27309;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CONFIG_PARITY = 27310;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_CLK_ADJ_PARITY = 27311;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_DIV_PARITY = 27312;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_PLL_UNLOCK = 27313;
static const uint64_t IDX_CEN_PCBSLPERV_ERROR_REG_PLL_UNLOCK_LEN = 27314;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_CHIPLET_ENABLE = 27315;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_PCB_EP_RESET = 27316;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_TP_CPLT_PRV_CLKOFF_DC = 27317;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_NCLK_NODIV = 27318;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_VITAL_SCAN = 27319;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_VITAL_SCAN_IN = 27320;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_D_MODE = 27321;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_ACT_DIS = 27322;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_MPW2 = 27323;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_MPW1 = 27324;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_DELAY_LCLKR = 27325;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_VITAL_THOLD = 27326;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_FENCE2_EN = 27327;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_FENCE_EN = 27328;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_RESCLK_FLUSH = 27329;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_RESCLK_OVERRIDE_VALUE = 27330;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_DPHY_PLL = 27331;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_TP_FENCE_PCB = 27332;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_FSYNC_ENABLE = 27333;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_L3_EDRAM_ENABLE = 27334;
static const uint64_t IDX_CEN_PCBSLPERV_GP3_REG_PGENABLE = 27335;
static const uint64_t IDX_CEN_PCBSLPERV_CLK_ADJ_SET_REG = 27336;
static const uint64_t IDX_CEN_PCBSLPERV_CLK_ADJ_SET_REG_LEN = 27337;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_0_REG_0 = 27338;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_0_REG_0_LEN = 27339;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_0_REG_SUPPRESS_0 = 27340;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_1_REG_1 = 27341;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_1_REG_1_LEN = 27342;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_1_REG_SUPPRESS_1 = 27343;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_2_REG_2 = 27344;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_2_REG_2_LEN = 27345;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_2_REG_SUPPRESS_2 = 27346;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_3_REG_3 = 27347;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_3_REG_3_LEN = 27348;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_3_REG_SUPPRESS_3 = 27349;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_4_REG_4 = 27350;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_4_REG_4_LEN = 27351;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_4_REG_SUPPRESS_4 = 27352;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_5_REG_5 = 27353;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_5_REG_5_LEN = 27354;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_5_REG_SUPPRESS_5 = 27355;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_6_REG_6 = 27356;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_6_REG_6_LEN = 27357;
static const uint64_t IDX_CEN_PCBSLPERV_HANG_PULSE_6_REG_SUPPRESS_6 = 27358;
static const uint64_t IDX_CEN_PCBSLPERV_PRE_COUNTER_REG_COUNTER = 27359;
static const uint64_t IDX_CEN_PCBSLPERV_PRE_COUNTER_REG_COUNTER_LEN = 27360;
static const uint64_t IDX_CEN_PCBSLPERV_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 27361;
static const uint64_t IDX_CEN_PCBSLPERV_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 27362;
static const uint64_t IDX_CEN_PCBSLPERV_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 27363;
static const uint64_t IDX_CEN_PCBSLPERV_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 27364;
static const uint64_t IDX_CEN_PCBSLPERV_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 27365;
static const uint64_t IDX_CEN_PCBSLPERV_SLAVE_CONFIG_REG_ERROR_MASK = 27366;
static const uint64_t IDX_CEN_PCBSLPERV_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 27367;
static const uint64_t IDX_CEN_PCBSLPERV_HEARTBEAT_REG_DEAD = 27368;
static const uint64_t IDX_CEN_PCBSLPERV_PROTECT_MODE_REG_READ_ENABLE = 27369;
static const uint64_t IDX_CEN_PCBSLPERV_PROTECT_MODE_REG_WRITE_ENABLE = 27370;
static const uint64_t IDX_CEN_PCBSLPERV_ATOMIC_LOCK_REG_ENABLE = 27371;
static const uint64_t IDX_CEN_PCBSLPERV_ATOMIC_LOCK_REG_ID = 27372;
static const uint64_t IDX_CEN_PCBSLPERV_ATOMIC_LOCK_REG_ID_LEN = 27373;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_1_MULTICAST1 = 27374;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_1_MULTICAST1_LEN = 27375;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_2_MULTICAST2 = 27376;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_2_MULTICAST2_LEN = 27377;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_3_MULTICAST3 = 27378;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_3_MULTICAST3_LEN = 27379;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_4_MULTICAST4 = 27380;
static const uint64_t IDX_CEN_PCBSLNEST_MULTICAST_GROUP_4_MULTICAST4_LEN = 27381;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CE = 27382;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CHIPLET_ERRORS = 27383;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CHIPLET_ERRORS_LEN = 27384;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_PARITY = 27385;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_DATA_BUFFER = 27386;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_ADDR_BUFFER = 27387;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_PCB_FSM = 27388;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CL_FSM = 27389;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_INT_RX_FSM = 27390;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_INT_TX_FSM = 27391;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_INT_TYPE = 27392;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CL_DATA = 27393;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_INFO = 27394;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_UNUSED_0 = 27395;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CHIPLET_ATOMIC_LOCK = 27396;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_PCB_INTERFACE = 27397;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CHIPLET_OFFLINE = 27398;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CHIPLET_GRID_SKITTER = 27399;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_GP3_PARITY = 27400;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_ADDRESS_PARITY = 27401;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_TIMEOUT_PARITY = 27402;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CONFIG_PARITY = 27403;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_CLK_ADJ_PARITY = 27404;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_DIV_PARITY = 27405;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_PLL_UNLOCK = 27406;
static const uint64_t IDX_CEN_PCBSLNEST_ERROR_REG_PLL_UNLOCK_LEN = 27407;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_CHIPLET_ENABLE = 27408;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_PCB_EP_RESET = 27409;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_TP_CPLT_PRV_CLKOFF_DC = 27410;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_NCLK_NODIV = 27411;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_VITAL_SCAN = 27412;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_VITAL_SCAN_IN = 27413;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_D_MODE = 27414;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_ACT_DIS = 27415;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_MPW2 = 27416;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_MPW1 = 27417;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_DELAY_LCLKR = 27418;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_VITAL_THOLD = 27419;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_FENCE2_EN = 27420;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_FENCE_EN = 27421;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_RESCLK_FLUSH = 27422;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_RESCLK_OVERRIDE_VALUE = 27423;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_DPHY_PLL = 27424;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_TP_FENCE_PCB = 27425;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_FSYNC_ENABLE = 27426;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_L3_EDRAM_ENABLE = 27427;
static const uint64_t IDX_CEN_PCBSLNEST_GP3_REG_PGENABLE = 27428;
static const uint64_t IDX_CEN_PCBSLNEST_CLK_ADJ_SET_REG = 27429;
static const uint64_t IDX_CEN_PCBSLNEST_CLK_ADJ_SET_REG_LEN = 27430;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_0_REG_0 = 27431;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_0_REG_0_LEN = 27432;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_0_REG_SUPPRESS_0 = 27433;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_1_REG_1 = 27434;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_1_REG_1_LEN = 27435;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_1_REG_SUPPRESS_1 = 27436;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_2_REG_2 = 27437;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_2_REG_2_LEN = 27438;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_2_REG_SUPPRESS_2 = 27439;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_3_REG_3 = 27440;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_3_REG_3_LEN = 27441;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_3_REG_SUPPRESS_3 = 27442;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_4_REG_4 = 27443;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_4_REG_4_LEN = 27444;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_4_REG_SUPPRESS_4 = 27445;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_5_REG_5 = 27446;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_5_REG_5_LEN = 27447;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_5_REG_SUPPRESS_5 = 27448;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_6_REG_6 = 27449;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_6_REG_6_LEN = 27450;
static const uint64_t IDX_CEN_PCBSLNEST_HANG_PULSE_6_REG_SUPPRESS_6 = 27451;
static const uint64_t IDX_CEN_PCBSLNEST_PRE_COUNTER_REG_COUNTER = 27452;
static const uint64_t IDX_CEN_PCBSLNEST_PRE_COUNTER_REG_COUNTER_LEN = 27453;
static const uint64_t IDX_CEN_PCBSLNEST_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 27454;
static const uint64_t IDX_CEN_PCBSLNEST_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 27455;
static const uint64_t IDX_CEN_PCBSLNEST_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 27456;
static const uint64_t IDX_CEN_PCBSLNEST_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 27457;
static const uint64_t IDX_CEN_PCBSLNEST_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 27458;
static const uint64_t IDX_CEN_PCBSLNEST_SLAVE_CONFIG_REG_ERROR_MASK = 27459;
static const uint64_t IDX_CEN_PCBSLNEST_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 27460;
static const uint64_t IDX_CEN_PCBSLNEST_HEARTBEAT_REG_DEAD = 27461;
static const uint64_t IDX_CEN_PCBSLNEST_PROTECT_MODE_REG_READ_ENABLE = 27462;
static const uint64_t IDX_CEN_PCBSLNEST_PROTECT_MODE_REG_WRITE_ENABLE = 27463;
static const uint64_t IDX_CEN_PCBSLNEST_ATOMIC_LOCK_REG_ENABLE = 27464;
static const uint64_t IDX_CEN_PCBSLNEST_ATOMIC_LOCK_REG_ID = 27465;
static const uint64_t IDX_CEN_PCBSLNEST_ATOMIC_LOCK_REG_ID_LEN = 27466;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_1_MULTICAST1 = 27467;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_1_MULTICAST1_LEN = 27468;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_2_MULTICAST2 = 27469;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_2_MULTICAST2_LEN = 27470;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_3_MULTICAST3 = 27471;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_3_MULTICAST3_LEN = 27472;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_4_MULTICAST4 = 27473;
static const uint64_t IDX_CEN_PCBSLMEM_MULTICAST_GROUP_4_MULTICAST4_LEN = 27474;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CE = 27475;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CHIPLET_ERRORS = 27476;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CHIPLET_ERRORS_LEN = 27477;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_PARITY = 27478;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_DATA_BUFFER = 27479;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_ADDR_BUFFER = 27480;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_PCB_FSM = 27481;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CL_FSM = 27482;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_INT_RX_FSM = 27483;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_INT_TX_FSM = 27484;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_INT_TYPE = 27485;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CL_DATA = 27486;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_INFO = 27487;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_UNUSED_0 = 27488;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CHIPLET_ATOMIC_LOCK = 27489;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_PCB_INTERFACE = 27490;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CHIPLET_OFFLINE = 27491;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CHIPLET_GRID_SKITTER = 27492;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_GP3_PARITY = 27493;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_ADDRESS_PARITY = 27494;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_TIMEOUT_PARITY = 27495;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CONFIG_PARITY = 27496;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_CLK_ADJ_PARITY = 27497;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_DIV_PARITY = 27498;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_PLL_UNLOCK = 27499;
static const uint64_t IDX_CEN_PCBSLMEM_ERROR_REG_PLL_UNLOCK_LEN = 27500;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_CHIPLET_ENABLE = 27501;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_PCB_EP_RESET = 27502;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_TP_CPLT_PRV_CLKOFF_DC = 27503;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_NCLK_NODIV = 27504;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_VITAL_SCAN = 27505;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_VITAL_SCAN_IN = 27506;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_D_MODE = 27507;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_ACT_DIS = 27508;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_MPW2 = 27509;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_MPW1 = 27510;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_DELAY_LCLKR = 27511;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_VITAL_THOLD = 27512;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_FENCE2_EN = 27513;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_FENCE_EN = 27514;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_RESCLK_FLUSH = 27515;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_RESCLK_OVERRIDE_VALUE = 27516;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_DPHY_PLL = 27517;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_TP_FENCE_PCB = 27518;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_FSYNC_ENABLE = 27519;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_L3_EDRAM_ENABLE = 27520;
static const uint64_t IDX_CEN_PCBSLMEM_GP3_REG_PGENABLE = 27521;
static const uint64_t IDX_CEN_PCBSLMEM_CLK_ADJ_SET_REG = 27522;
static const uint64_t IDX_CEN_PCBSLMEM_CLK_ADJ_SET_REG_LEN = 27523;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_0_REG_0 = 27524;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_0_REG_0_LEN = 27525;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_0_REG_SUPPRESS_0 = 27526;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_1_REG_1 = 27527;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_1_REG_1_LEN = 27528;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_1_REG_SUPPRESS_1 = 27529;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_2_REG_2 = 27530;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_2_REG_2_LEN = 27531;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_2_REG_SUPPRESS_2 = 27532;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_3_REG_3 = 27533;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_3_REG_3_LEN = 27534;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_3_REG_SUPPRESS_3 = 27535;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_4_REG_4 = 27536;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_4_REG_4_LEN = 27537;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_4_REG_SUPPRESS_4 = 27538;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_5_REG_5 = 27539;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_5_REG_5_LEN = 27540;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_5_REG_SUPPRESS_5 = 27541;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_6_REG_6 = 27542;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_6_REG_6_LEN = 27543;
static const uint64_t IDX_CEN_PCBSLMEM_HANG_PULSE_6_REG_SUPPRESS_6 = 27544;
static const uint64_t IDX_CEN_PCBSLMEM_PRE_COUNTER_REG_COUNTER = 27545;
static const uint64_t IDX_CEN_PCBSLMEM_PRE_COUNTER_REG_COUNTER_LEN = 27546;
static const uint64_t IDX_CEN_PCBSLMEM_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 27547;
static const uint64_t IDX_CEN_PCBSLMEM_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 27548;
static const uint64_t IDX_CEN_PCBSLMEM_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 27549;
static const uint64_t IDX_CEN_PCBSLMEM_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 27550;
static const uint64_t IDX_CEN_PCBSLMEM_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 27551;
static const uint64_t IDX_CEN_PCBSLMEM_SLAVE_CONFIG_REG_ERROR_MASK = 27552;
static const uint64_t IDX_CEN_PCBSLMEM_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 27553;
static const uint64_t IDX_CEN_PCBSLMEM_HEARTBEAT_REG_DEAD = 27554;
static const uint64_t IDX_CEN_PCBSLMEM_PROTECT_MODE_REG_READ_ENABLE = 27555;
static const uint64_t IDX_CEN_PCBSLMEM_PROTECT_MODE_REG_WRITE_ENABLE = 27556;
static const uint64_t IDX_CEN_PCBSLMEM_ATOMIC_LOCK_REG_ENABLE = 27557;
static const uint64_t IDX_CEN_PCBSLMEM_ATOMIC_LOCK_REG_ID = 27558;
static const uint64_t IDX_CEN_PCBSLMEM_ATOMIC_LOCK_REG_ID_LEN = 27559;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART0_REGISTER_PART_0 = 27560;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART0_REGISTER_PART_0_LEN = 27561;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART1_REGISTER_PART_1 = 27562;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART1_REGISTER_PART_1_LEN = 27563;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART2_REGISTER_PART_2 = 27564;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART2_REGISTER_PART_2_LEN = 27565;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART3_REGISTER_PART_3 = 27566;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART3_REGISTER_PART_3_LEN = 27567;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART4_REGISTER_PART_4 = 27568;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART4_REGISTER_PART_4_LEN = 27569;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART5_REGISTER_PART_5 = 27570;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART5_REGISTER_PART_5_LEN = 27571;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART6_REGISTER_PART_6 = 27572;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART6_REGISTER_PART_6_LEN = 27573;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART7_REGISTER_PART_7 = 27574;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART7_REGISTER_PART_7_LEN = 27575;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART8_REGISTER_PART_8 = 27576;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART8_REGISTER_PART_8_LEN = 27577;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART9_REGISTER_PART_9 = 27578;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART9_REGISTER_PART_9_LEN = 27579;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART10_REGISTER_PART_10 = 27580;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART10_REGISTER_PART_10_LEN = 27581;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART11_REGISTER_PART_11 = 27582;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART11_REGISTER_PART_11_LEN = 27583;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART12_REGISTER_PART_12 = 27584;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART12_REGISTER_PART_12_LEN = 27585;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART13_REGISTER_PART_13 = 27586;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART13_REGISTER_PART_13_LEN = 27587;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART14_REGISTER_PART_14 = 27588;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART14_REGISTER_PART_14_LEN = 27589;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART15_REGISTER_PART_15 = 27590;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART15_REGISTER_PART_15_LEN = 27591;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART16_REGISTER_PART_16 = 27592;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART16_REGISTER_PART_16_LEN = 27593;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART17_REGISTER_PART_17 = 27594;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART17_REGISTER_PART_17_LEN = 27595;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART18_REGISTER_PART_18 = 27596;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART18_REGISTER_PART_18_LEN = 27597;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART19_REGISTER_PART_19 = 27598;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART19_REGISTER_PART_19_LEN = 27599;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART20_REGISTER_PART_20 = 27600;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART20_REGISTER_PART_20_LEN = 27601;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART21_REGISTER_PART_21 = 27602;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART21_REGISTER_PART_21_LEN = 27603;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART22_REGISTER_PART_22 = 27604;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART22_REGISTER_PART_22_LEN = 27605;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART23_REGISTER_PART_23 = 27606;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART23_REGISTER_PART_23_LEN = 27607;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART24_REGISTER_PART_24 = 27608;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART24_REGISTER_PART_24_LEN = 27609;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART25_REGISTER_PART_25 = 27610;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART25_REGISTER_PART_25_LEN = 27611;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART26_REGISTER_PART_26 = 27612;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART26_REGISTER_PART_26_LEN = 27613;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART27_REGISTER_PART_27 = 27614;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART27_REGISTER_PART_27_LEN = 27615;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART28_REGISTER_PART_28 = 27616;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART28_REGISTER_PART_28_LEN = 27617;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART29_REGISTER_PART_29 = 27618;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART29_REGISTER_PART_29_LEN = 27619;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART30_REGISTER_PART_30 = 27620;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART30_REGISTER_PART_30_LEN = 27621;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART31_REGISTER_PART_31 = 27622;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART31_REGISTER_PART_31_LEN = 27623;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART32_REGISTER_PART_32 = 27624;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART32_REGISTER_PART_32_LEN = 27625;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART33_REGISTER_PART_33 = 27626;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART33_REGISTER_PART_33_LEN = 27627;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART34_REGISTER_PART_34 = 27628;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART34_REGISTER_PART_34_LEN = 27629;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART35_REGISTER_PART_35 = 27630;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART35_REGISTER_PART_35_LEN = 27631;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART36_REGISTER_PART_36 = 27632;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART36_REGISTER_PART_36_LEN = 27633;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART37_REGISTER_PART_37 = 27634;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART37_REGISTER_PART_37_LEN = 27635;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART38_REGISTER_PART_38 = 27636;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART38_REGISTER_PART_38_LEN = 27637;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART39_REGISTER_PART_39 = 27638;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART39_REGISTER_PART_39_LEN = 27639;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART40_REGISTER_PART_40 = 27640;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART40_REGISTER_PART_40_LEN = 27641;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART41_REGISTER_PART_41 = 27642;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART41_REGISTER_PART_41_LEN = 27643;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART42_REGISTER_PART_42 = 27644;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART42_REGISTER_PART_42_LEN = 27645;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART43_REGISTER_PART_43 = 27646;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART43_REGISTER_PART_43_LEN = 27647;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART44_REGISTER_PART_44 = 27648;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART44_REGISTER_PART_44_LEN = 27649;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART45_REGISTER_PART_45 = 27650;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART45_REGISTER_PART_45_LEN = 27651;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART46_REGISTER_PART_46 = 27652;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART46_REGISTER_PART_46_LEN = 27653;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART47_REGISTER_PART_47 = 27654;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART47_REGISTER_PART_47_LEN = 27655;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART48_REGISTER_PART_48 = 27656;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART48_REGISTER_PART_48_LEN = 27657;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART49_REGISTER_PART_49 = 27658;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART49_REGISTER_PART_49_LEN = 27659;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART50_REGISTER_PART_50 = 27660;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART50_REGISTER_PART_50_LEN = 27661;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART51_REGISTER_PART_51 = 27662;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART51_REGISTER_PART_51_LEN = 27663;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART52_REGISTER_PART_52 = 27664;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART52_REGISTER_PART_52_LEN = 27665;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART53_REGISTER_PART_53 = 27666;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART53_REGISTER_PART_53_LEN = 27667;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART54_REGISTER_PART_54 = 27668;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART54_REGISTER_PART_54_LEN = 27669;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART55_REGISTER_PART_55 = 27670;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART55_REGISTER_PART_55_LEN = 27671;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART56_REGISTER_PART_56 = 27672;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART56_REGISTER_PART_56_LEN = 27673;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART57_REGISTER_PART_57 = 27674;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART57_REGISTER_PART_57_LEN = 27675;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART58_REGISTER_PART_58 = 27676;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART58_REGISTER_PART_58_LEN = 27677;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART59_REGISTER_PART_59 = 27678;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART59_REGISTER_PART_59_LEN = 27679;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART60_REGISTER_PART_60 = 27680;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART60_REGISTER_PART_60_LEN = 27681;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART61_REGISTER_PART_61 = 27682;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART61_REGISTER_PART_61_LEN = 27683;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART62_REGISTER_PART_62 = 27684;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART62_REGISTER_PART_62_LEN = 27685;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART63_REGISTER_PART_63 = 27686;
static const uint64_t IDX_CEN_OTPROM0_ECID_PART63_REGISTER_PART_63_LEN = 27687;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART0_REGISTER_PART_0 = 27688;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART0_REGISTER_PART_0_LEN = 27689;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART1_REGISTER_PART_1 = 27690;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART1_REGISTER_PART_1_LEN = 27691;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART2_REGISTER_PART_2 = 27692;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART2_REGISTER_PART_2_LEN = 27693;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART3_REGISTER_PART_3 = 27694;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART3_REGISTER_PART_3_LEN = 27695;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART4_REGISTER_PART_4 = 27696;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART4_REGISTER_PART_4_LEN = 27697;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART5_REGISTER_PART_5 = 27698;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART5_REGISTER_PART_5_LEN = 27699;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART6_REGISTER_PART_6 = 27700;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART6_REGISTER_PART_6_LEN = 27701;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART7_REGISTER_PART_7 = 27702;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART7_REGISTER_PART_7_LEN = 27703;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART8_REGISTER_PART_8 = 27704;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART8_REGISTER_PART_8_LEN = 27705;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART9_REGISTER_PART_9 = 27706;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN = 27707;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART10_REGISTER_PART_10 = 27708;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART10_REGISTER_PART_10_LEN = 27709;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART11_REGISTER_PART_11 = 27710;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART11_REGISTER_PART_11_LEN = 27711;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART12_REGISTER_PART_12 = 27712;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART12_REGISTER_PART_12_LEN = 27713;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART13_REGISTER_PART_13 = 27714;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART13_REGISTER_PART_13_LEN = 27715;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART14_REGISTER_PART_14 = 27716;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART14_REGISTER_PART_14_LEN = 27717;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART15_REGISTER_PART_15 = 27718;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART15_REGISTER_PART_15_LEN = 27719;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART16_REGISTER_PART_16 = 27720;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART16_REGISTER_PART_16_LEN = 27721;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART17_REGISTER_PART_17 = 27722;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART17_REGISTER_PART_17_LEN = 27723;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART18_REGISTER_PART_18 = 27724;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART18_REGISTER_PART_18_LEN = 27725;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART19_REGISTER_PART_19 = 27726;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART19_REGISTER_PART_19_LEN = 27727;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART20_REGISTER_PART_20 = 27728;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART20_REGISTER_PART_20_LEN = 27729;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART21_REGISTER_PART_21 = 27730;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART21_REGISTER_PART_21_LEN = 27731;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART22_REGISTER_PART_22 = 27732;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART22_REGISTER_PART_22_LEN = 27733;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART23_REGISTER_PART_23 = 27734;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART23_REGISTER_PART_23_LEN = 27735;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART24_REGISTER_PART_24 = 27736;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART24_REGISTER_PART_24_LEN = 27737;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART25_REGISTER_PART_25 = 27738;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART25_REGISTER_PART_25_LEN = 27739;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART26_REGISTER_PART_26 = 27740;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART26_REGISTER_PART_26_LEN = 27741;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART27_REGISTER_PART_27 = 27742;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART27_REGISTER_PART_27_LEN = 27743;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART28_REGISTER_PART_28 = 27744;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART28_REGISTER_PART_28_LEN = 27745;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART29_REGISTER_PART_29 = 27746;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART29_REGISTER_PART_29_LEN = 27747;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART30_REGISTER_PART_30 = 27748;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART30_REGISTER_PART_30_LEN = 27749;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART31_REGISTER_PART_31 = 27750;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART31_REGISTER_PART_31_LEN = 27751;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART32_REGISTER_PART_32 = 27752;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART32_REGISTER_PART_32_LEN = 27753;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART33_REGISTER_PART_33 = 27754;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART33_REGISTER_PART_33_LEN = 27755;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART34_REGISTER_PART_34 = 27756;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART34_REGISTER_PART_34_LEN = 27757;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART35_REGISTER_PART_35 = 27758;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART35_REGISTER_PART_35_LEN = 27759;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART36_REGISTER_PART_36 = 27760;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART36_REGISTER_PART_36_LEN = 27761;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART37_REGISTER_PART_37 = 27762;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART37_REGISTER_PART_37_LEN = 27763;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART38_REGISTER_PART_38 = 27764;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART38_REGISTER_PART_38_LEN = 27765;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART39_REGISTER_PART_39 = 27766;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART39_REGISTER_PART_39_LEN = 27767;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART40_REGISTER_PART_40 = 27768;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART40_REGISTER_PART_40_LEN = 27769;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART41_REGISTER_PART_41 = 27770;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART41_REGISTER_PART_41_LEN = 27771;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART42_REGISTER_PART_42 = 27772;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART42_REGISTER_PART_42_LEN = 27773;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART43_REGISTER_PART_43 = 27774;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART43_REGISTER_PART_43_LEN = 27775;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART44_REGISTER_PART_44 = 27776;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART44_REGISTER_PART_44_LEN = 27777;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART45_REGISTER_PART_45 = 27778;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART45_REGISTER_PART_45_LEN = 27779;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART46_REGISTER_PART_46 = 27780;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART46_REGISTER_PART_46_LEN = 27781;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART47_REGISTER_PART_47 = 27782;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART47_REGISTER_PART_47_LEN = 27783;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART48_REGISTER_PART_48 = 27784;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART48_REGISTER_PART_48_LEN = 27785;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART49_REGISTER_PART_49 = 27786;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART49_REGISTER_PART_49_LEN = 27787;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART50_REGISTER_PART_50 = 27788;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART50_REGISTER_PART_50_LEN = 27789;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART51_REGISTER_PART_51 = 27790;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART51_REGISTER_PART_51_LEN = 27791;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART52_REGISTER_PART_52 = 27792;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART52_REGISTER_PART_52_LEN = 27793;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART53_REGISTER_PART_53 = 27794;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART53_REGISTER_PART_53_LEN = 27795;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART54_REGISTER_PART_54 = 27796;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART54_REGISTER_PART_54_LEN = 27797;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART55_REGISTER_PART_55 = 27798;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART55_REGISTER_PART_55_LEN = 27799;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART56_REGISTER_PART_56 = 27800;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART56_REGISTER_PART_56_LEN = 27801;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART57_REGISTER_PART_57 = 27802;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART57_REGISTER_PART_57_LEN = 27803;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART58_REGISTER_PART_58 = 27804;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART58_REGISTER_PART_58_LEN = 27805;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART59_REGISTER_PART_59 = 27806;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART59_REGISTER_PART_59_LEN = 27807;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART60_REGISTER_PART_60 = 27808;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART60_REGISTER_PART_60_LEN = 27809;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART61_REGISTER_PART_61 = 27810;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART61_REGISTER_PART_61_LEN = 27811;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART62_REGISTER_PART_62 = 27812;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART62_REGISTER_PART_62_LEN = 27813;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART63_REGISTER_PART_63 = 27814;
static const uint64_t IDX_CEN_OTPROM1_ECID_PART63_REGISTER_PART_63_LEN = 27815;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART0_REGISTER_PART_0 = 27816;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART0_REGISTER_PART_0_LEN = 27817;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART1_REGISTER_PART_1 = 27818;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART1_REGISTER_PART_1_LEN = 27819;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART2_REGISTER_PART_2 = 27820;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART2_REGISTER_PART_2_LEN = 27821;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART3_REGISTER_PART_3 = 27822;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART3_REGISTER_PART_3_LEN = 27823;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART4_REGISTER_PART_4 = 27824;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART4_REGISTER_PART_4_LEN = 27825;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART5_REGISTER_PART_5 = 27826;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART5_REGISTER_PART_5_LEN = 27827;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART6_REGISTER_PART_6 = 27828;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART6_REGISTER_PART_6_LEN = 27829;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART7_REGISTER_PART_7 = 27830;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART7_REGISTER_PART_7_LEN = 27831;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART8_REGISTER_PART_8 = 27832;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART8_REGISTER_PART_8_LEN = 27833;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART9_REGISTER_PART_9 = 27834;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART9_REGISTER_PART_9_LEN = 27835;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART10_REGISTER_PART_10 = 27836;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART10_REGISTER_PART_10_LEN = 27837;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART11_REGISTER_PART_11 = 27838;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART11_REGISTER_PART_11_LEN = 27839;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART12_REGISTER_PART_12 = 27840;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART12_REGISTER_PART_12_LEN = 27841;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART13_REGISTER_PART_13 = 27842;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART13_REGISTER_PART_13_LEN = 27843;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART14_REGISTER_PART_14 = 27844;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART14_REGISTER_PART_14_LEN = 27845;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART15_REGISTER_PART_15 = 27846;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART15_REGISTER_PART_15_LEN = 27847;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART16_REGISTER_PART_16 = 27848;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART16_REGISTER_PART_16_LEN = 27849;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART17_REGISTER_PART_17 = 27850;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART17_REGISTER_PART_17_LEN = 27851;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART18_REGISTER_PART_18 = 27852;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART18_REGISTER_PART_18_LEN = 27853;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART19_REGISTER_PART_19 = 27854;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART19_REGISTER_PART_19_LEN = 27855;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART20_REGISTER_PART_20 = 27856;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART20_REGISTER_PART_20_LEN = 27857;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART21_REGISTER_PART_21 = 27858;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART21_REGISTER_PART_21_LEN = 27859;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART22_REGISTER_PART_22 = 27860;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART22_REGISTER_PART_22_LEN = 27861;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART23_REGISTER_PART_23 = 27862;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART23_REGISTER_PART_23_LEN = 27863;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART24_REGISTER_PART_24 = 27864;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART24_REGISTER_PART_24_LEN = 27865;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART25_REGISTER_PART_25 = 27866;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART25_REGISTER_PART_25_LEN = 27867;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART26_REGISTER_PART_26 = 27868;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART26_REGISTER_PART_26_LEN = 27869;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART27_REGISTER_PART_27 = 27870;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART27_REGISTER_PART_27_LEN = 27871;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART28_REGISTER_PART_28 = 27872;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART28_REGISTER_PART_28_LEN = 27873;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART29_REGISTER_PART_29 = 27874;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART29_REGISTER_PART_29_LEN = 27875;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART30_REGISTER_PART_30 = 27876;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART30_REGISTER_PART_30_LEN = 27877;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART31_REGISTER_PART_31 = 27878;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART31_REGISTER_PART_31_LEN = 27879;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART32_REGISTER_PART_32 = 27880;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART32_REGISTER_PART_32_LEN = 27881;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART33_REGISTER_PART_33 = 27882;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART33_REGISTER_PART_33_LEN = 27883;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART34_REGISTER_PART_34 = 27884;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART34_REGISTER_PART_34_LEN = 27885;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART35_REGISTER_PART_35 = 27886;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART35_REGISTER_PART_35_LEN = 27887;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART36_REGISTER_PART_36 = 27888;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART36_REGISTER_PART_36_LEN = 27889;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART37_REGISTER_PART_37 = 27890;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART37_REGISTER_PART_37_LEN = 27891;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART38_REGISTER_PART_38 = 27892;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART38_REGISTER_PART_38_LEN = 27893;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART39_REGISTER_PART_39 = 27894;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART39_REGISTER_PART_39_LEN = 27895;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART40_REGISTER_PART_40 = 27896;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART40_REGISTER_PART_40_LEN = 27897;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART41_REGISTER_PART_41 = 27898;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART41_REGISTER_PART_41_LEN = 27899;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART42_REGISTER_PART_42 = 27900;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART42_REGISTER_PART_42_LEN = 27901;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART43_REGISTER_PART_43 = 27902;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART43_REGISTER_PART_43_LEN = 27903;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART44_REGISTER_PART_44 = 27904;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART44_REGISTER_PART_44_LEN = 27905;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART45_REGISTER_PART_45 = 27906;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART45_REGISTER_PART_45_LEN = 27907;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART46_REGISTER_PART_46 = 27908;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART46_REGISTER_PART_46_LEN = 27909;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART47_REGISTER_PART_47 = 27910;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART47_REGISTER_PART_47_LEN = 27911;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART48_REGISTER_PART_48 = 27912;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART48_REGISTER_PART_48_LEN = 27913;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART49_REGISTER_PART_49 = 27914;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART49_REGISTER_PART_49_LEN = 27915;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART50_REGISTER_PART_50 = 27916;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART50_REGISTER_PART_50_LEN = 27917;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART51_REGISTER_PART_51 = 27918;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART51_REGISTER_PART_51_LEN = 27919;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART52_REGISTER_PART_52 = 27920;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART52_REGISTER_PART_52_LEN = 27921;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART53_REGISTER_PART_53 = 27922;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART53_REGISTER_PART_53_LEN = 27923;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART54_REGISTER_PART_54 = 27924;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART54_REGISTER_PART_54_LEN = 27925;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART55_REGISTER_PART_55 = 27926;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART55_REGISTER_PART_55_LEN = 27927;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART56_REGISTER_PART_56 = 27928;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART56_REGISTER_PART_56_LEN = 27929;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART57_REGISTER_PART_57 = 27930;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART57_REGISTER_PART_57_LEN = 27931;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART58_REGISTER_PART_58 = 27932;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART58_REGISTER_PART_58_LEN = 27933;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART59_REGISTER_PART_59 = 27934;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART59_REGISTER_PART_59_LEN = 27935;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART60_REGISTER_PART_60 = 27936;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART60_REGISTER_PART_60_LEN = 27937;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART61_REGISTER_PART_61 = 27938;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART61_REGISTER_PART_61_LEN = 27939;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART62_REGISTER_PART_62 = 27940;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART62_REGISTER_PART_62_LEN = 27941;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART63_REGISTER_PART_63 = 27942;
static const uint64_t IDX_CEN_OTPROM2_ECID_PART63_REGISTER_PART_63_LEN = 27943;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART0_REGISTER_PART_0 = 27944;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART0_REGISTER_PART_0_LEN = 27945;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART1_REGISTER_PART_1 = 27946;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART1_REGISTER_PART_1_LEN = 27947;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART2_REGISTER_PART_2 = 27948;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART2_REGISTER_PART_2_LEN = 27949;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART3_REGISTER_PART_3 = 27950;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART3_REGISTER_PART_3_LEN = 27951;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART4_REGISTER_PART_4 = 27952;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART4_REGISTER_PART_4_LEN = 27953;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART5_REGISTER_PART_5 = 27954;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART5_REGISTER_PART_5_LEN = 27955;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART6_REGISTER_PART_6 = 27956;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART6_REGISTER_PART_6_LEN = 27957;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART7_REGISTER_PART_7 = 27958;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART7_REGISTER_PART_7_LEN = 27959;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART8_REGISTER_PART_8 = 27960;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART8_REGISTER_PART_8_LEN = 27961;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART9_REGISTER_PART_9 = 27962;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART9_REGISTER_PART_9_LEN = 27963;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART10_REGISTER_PART_10 = 27964;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART10_REGISTER_PART_10_LEN = 27965;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART11_REGISTER_PART_11 = 27966;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART11_REGISTER_PART_11_LEN = 27967;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART12_REGISTER_PART_12 = 27968;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART12_REGISTER_PART_12_LEN = 27969;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART13_REGISTER_PART_13 = 27970;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART13_REGISTER_PART_13_LEN = 27971;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART14_REGISTER_PART_14 = 27972;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART14_REGISTER_PART_14_LEN = 27973;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART15_REGISTER_PART_15 = 27974;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART15_REGISTER_PART_15_LEN = 27975;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART16_REGISTER_PART_16 = 27976;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART16_REGISTER_PART_16_LEN = 27977;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART17_REGISTER_PART_17 = 27978;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART17_REGISTER_PART_17_LEN = 27979;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART18_REGISTER_PART_18 = 27980;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART18_REGISTER_PART_18_LEN = 27981;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART19_REGISTER_PART_19 = 27982;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART19_REGISTER_PART_19_LEN = 27983;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART20_REGISTER_PART_20 = 27984;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART20_REGISTER_PART_20_LEN = 27985;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART21_REGISTER_PART_21 = 27986;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART21_REGISTER_PART_21_LEN = 27987;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART22_REGISTER_PART_22 = 27988;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART22_REGISTER_PART_22_LEN = 27989;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART23_REGISTER_PART_23 = 27990;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART23_REGISTER_PART_23_LEN = 27991;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART24_REGISTER_PART_24 = 27992;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART24_REGISTER_PART_24_LEN = 27993;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART25_REGISTER_PART_25 = 27994;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART25_REGISTER_PART_25_LEN = 27995;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART26_REGISTER_PART_26 = 27996;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART26_REGISTER_PART_26_LEN = 27997;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART27_REGISTER_PART_27 = 27998;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART27_REGISTER_PART_27_LEN = 27999;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART28_REGISTER_PART_28 = 28000;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART28_REGISTER_PART_28_LEN = 28001;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART29_REGISTER_PART_29 = 28002;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART29_REGISTER_PART_29_LEN = 28003;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART30_REGISTER_PART_30 = 28004;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART30_REGISTER_PART_30_LEN = 28005;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART31_REGISTER_PART_31 = 28006;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART31_REGISTER_PART_31_LEN = 28007;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART32_REGISTER_PART_32 = 28008;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART32_REGISTER_PART_32_LEN = 28009;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART33_REGISTER_PART_33 = 28010;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART33_REGISTER_PART_33_LEN = 28011;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART34_REGISTER_PART_34 = 28012;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART34_REGISTER_PART_34_LEN = 28013;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART35_REGISTER_PART_35 = 28014;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART35_REGISTER_PART_35_LEN = 28015;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART36_REGISTER_PART_36 = 28016;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART36_REGISTER_PART_36_LEN = 28017;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART37_REGISTER_PART_37 = 28018;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART37_REGISTER_PART_37_LEN = 28019;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART38_REGISTER_PART_38 = 28020;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART38_REGISTER_PART_38_LEN = 28021;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART39_REGISTER_PART_39 = 28022;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART39_REGISTER_PART_39_LEN = 28023;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART40_REGISTER_PART_40 = 28024;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART40_REGISTER_PART_40_LEN = 28025;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART41_REGISTER_PART_41 = 28026;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART41_REGISTER_PART_41_LEN = 28027;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART42_REGISTER_PART_42 = 28028;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART42_REGISTER_PART_42_LEN = 28029;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART43_REGISTER_PART_43 = 28030;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART43_REGISTER_PART_43_LEN = 28031;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART44_REGISTER_PART_44 = 28032;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART44_REGISTER_PART_44_LEN = 28033;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART45_REGISTER_PART_45 = 28034;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART45_REGISTER_PART_45_LEN = 28035;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART46_REGISTER_PART_46 = 28036;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART46_REGISTER_PART_46_LEN = 28037;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART47_REGISTER_PART_47 = 28038;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART47_REGISTER_PART_47_LEN = 28039;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART48_REGISTER_PART_48 = 28040;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART48_REGISTER_PART_48_LEN = 28041;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART49_REGISTER_PART_49 = 28042;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART49_REGISTER_PART_49_LEN = 28043;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART50_REGISTER_PART_50 = 28044;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART50_REGISTER_PART_50_LEN = 28045;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART51_REGISTER_PART_51 = 28046;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART51_REGISTER_PART_51_LEN = 28047;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART52_REGISTER_PART_52 = 28048;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART52_REGISTER_PART_52_LEN = 28049;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART53_REGISTER_PART_53 = 28050;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART53_REGISTER_PART_53_LEN = 28051;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART54_REGISTER_PART_54 = 28052;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART54_REGISTER_PART_54_LEN = 28053;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART55_REGISTER_PART_55 = 28054;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART55_REGISTER_PART_55_LEN = 28055;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART56_REGISTER_PART_56 = 28056;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART56_REGISTER_PART_56_LEN = 28057;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART57_REGISTER_PART_57 = 28058;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART57_REGISTER_PART_57_LEN = 28059;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART58_REGISTER_PART_58 = 28060;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART58_REGISTER_PART_58_LEN = 28061;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART59_REGISTER_PART_59 = 28062;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART59_REGISTER_PART_59_LEN = 28063;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART60_REGISTER_PART_60 = 28064;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART60_REGISTER_PART_60_LEN = 28065;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART61_REGISTER_PART_61 = 28066;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART61_REGISTER_PART_61_LEN = 28067;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART62_REGISTER_PART_62 = 28068;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART62_REGISTER_PART_62_LEN = 28069;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART63_REGISTER_PART_63 = 28070;
static const uint64_t IDX_CEN_OTPROM3_ECID_PART63_REGISTER_PART_63_LEN = 28071;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART0_REGISTER_PART_0 = 28072;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART0_REGISTER_PART_0_LEN = 28073;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART1_REGISTER_PART_1 = 28074;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART1_REGISTER_PART_1_LEN = 28075;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART2_REGISTER_PART_2 = 28076;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART2_REGISTER_PART_2_LEN = 28077;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART3_REGISTER_PART_3 = 28078;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART3_REGISTER_PART_3_LEN = 28079;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART4_REGISTER_PART_4 = 28080;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART4_REGISTER_PART_4_LEN = 28081;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART5_REGISTER_PART_5 = 28082;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART5_REGISTER_PART_5_LEN = 28083;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART6_REGISTER_PART_6 = 28084;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART6_REGISTER_PART_6_LEN = 28085;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART7_REGISTER_PART_7 = 28086;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART7_REGISTER_PART_7_LEN = 28087;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART8_REGISTER_PART_8 = 28088;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART8_REGISTER_PART_8_LEN = 28089;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART9_REGISTER_PART_9 = 28090;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART9_REGISTER_PART_9_LEN = 28091;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART10_REGISTER_PART_10 = 28092;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART10_REGISTER_PART_10_LEN = 28093;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART11_REGISTER_PART_11 = 28094;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART11_REGISTER_PART_11_LEN = 28095;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART12_REGISTER_PART_12 = 28096;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART12_REGISTER_PART_12_LEN = 28097;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART13_REGISTER_PART_13 = 28098;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART13_REGISTER_PART_13_LEN = 28099;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART14_REGISTER_PART_14 = 28100;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART14_REGISTER_PART_14_LEN = 28101;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART15_REGISTER_PART_15 = 28102;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART15_REGISTER_PART_15_LEN = 28103;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART16_REGISTER_PART_16 = 28104;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART16_REGISTER_PART_16_LEN = 28105;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART17_REGISTER_PART_17 = 28106;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART17_REGISTER_PART_17_LEN = 28107;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART18_REGISTER_PART_18 = 28108;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART18_REGISTER_PART_18_LEN = 28109;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART19_REGISTER_PART_19 = 28110;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART19_REGISTER_PART_19_LEN = 28111;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART20_REGISTER_PART_20 = 28112;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART20_REGISTER_PART_20_LEN = 28113;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART21_REGISTER_PART_21 = 28114;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART21_REGISTER_PART_21_LEN = 28115;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART22_REGISTER_PART_22 = 28116;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART22_REGISTER_PART_22_LEN = 28117;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART23_REGISTER_PART_23 = 28118;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART23_REGISTER_PART_23_LEN = 28119;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART24_REGISTER_PART_24 = 28120;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART24_REGISTER_PART_24_LEN = 28121;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART25_REGISTER_PART_25 = 28122;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART25_REGISTER_PART_25_LEN = 28123;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART26_REGISTER_PART_26 = 28124;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART26_REGISTER_PART_26_LEN = 28125;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART27_REGISTER_PART_27 = 28126;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART27_REGISTER_PART_27_LEN = 28127;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART28_REGISTER_PART_28 = 28128;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART28_REGISTER_PART_28_LEN = 28129;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART29_REGISTER_PART_29 = 28130;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART29_REGISTER_PART_29_LEN = 28131;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART30_REGISTER_PART_30 = 28132;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART30_REGISTER_PART_30_LEN = 28133;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART31_REGISTER_PART_31 = 28134;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART31_REGISTER_PART_31_LEN = 28135;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART32_REGISTER_PART_32 = 28136;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART32_REGISTER_PART_32_LEN = 28137;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART33_REGISTER_PART_33 = 28138;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART33_REGISTER_PART_33_LEN = 28139;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART34_REGISTER_PART_34 = 28140;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART34_REGISTER_PART_34_LEN = 28141;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART35_REGISTER_PART_35 = 28142;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART35_REGISTER_PART_35_LEN = 28143;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART36_REGISTER_PART_36 = 28144;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART36_REGISTER_PART_36_LEN = 28145;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART37_REGISTER_PART_37 = 28146;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART37_REGISTER_PART_37_LEN = 28147;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART38_REGISTER_PART_38 = 28148;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART38_REGISTER_PART_38_LEN = 28149;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART39_REGISTER_PART_39 = 28150;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART39_REGISTER_PART_39_LEN = 28151;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART40_REGISTER_PART_40 = 28152;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART40_REGISTER_PART_40_LEN = 28153;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART41_REGISTER_PART_41 = 28154;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART41_REGISTER_PART_41_LEN = 28155;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART42_REGISTER_PART_42 = 28156;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART42_REGISTER_PART_42_LEN = 28157;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART43_REGISTER_PART_43 = 28158;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART43_REGISTER_PART_43_LEN = 28159;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART44_REGISTER_PART_44 = 28160;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART44_REGISTER_PART_44_LEN = 28161;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART45_REGISTER_PART_45 = 28162;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART45_REGISTER_PART_45_LEN = 28163;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART46_REGISTER_PART_46 = 28164;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART46_REGISTER_PART_46_LEN = 28165;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART47_REGISTER_PART_47 = 28166;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART47_REGISTER_PART_47_LEN = 28167;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART48_REGISTER_PART_48 = 28168;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART48_REGISTER_PART_48_LEN = 28169;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART49_REGISTER_PART_49 = 28170;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART49_REGISTER_PART_49_LEN = 28171;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART50_REGISTER_PART_50 = 28172;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART50_REGISTER_PART_50_LEN = 28173;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART51_REGISTER_PART_51 = 28174;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART51_REGISTER_PART_51_LEN = 28175;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART52_REGISTER_PART_52 = 28176;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART52_REGISTER_PART_52_LEN = 28177;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART53_REGISTER_PART_53 = 28178;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART53_REGISTER_PART_53_LEN = 28179;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART54_REGISTER_PART_54 = 28180;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART54_REGISTER_PART_54_LEN = 28181;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART55_REGISTER_PART_55 = 28182;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART55_REGISTER_PART_55_LEN = 28183;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART56_REGISTER_PART_56 = 28184;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART56_REGISTER_PART_56_LEN = 28185;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART57_REGISTER_PART_57 = 28186;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART57_REGISTER_PART_57_LEN = 28187;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART58_REGISTER_PART_58 = 28188;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART58_REGISTER_PART_58_LEN = 28189;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART59_REGISTER_PART_59 = 28190;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART59_REGISTER_PART_59_LEN = 28191;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART60_REGISTER_PART_60 = 28192;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART60_REGISTER_PART_60_LEN = 28193;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART61_REGISTER_PART_61 = 28194;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART61_REGISTER_PART_61_LEN = 28195;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART62_REGISTER_PART_62 = 28196;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART62_REGISTER_PART_62_LEN = 28197;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART63_REGISTER_PART_63 = 28198;
static const uint64_t IDX_CEN_OTPROM4_ECID_PART63_REGISTER_PART_63_LEN = 28199;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART0_REGISTER_PART_0 = 28200;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART0_REGISTER_PART_0_LEN = 28201;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART1_REGISTER_PART_1 = 28202;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART1_REGISTER_PART_1_LEN = 28203;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART2_REGISTER_PART_2 = 28204;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART2_REGISTER_PART_2_LEN = 28205;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART3_REGISTER_PART_3 = 28206;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART3_REGISTER_PART_3_LEN = 28207;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART4_REGISTER_PART_4 = 28208;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART4_REGISTER_PART_4_LEN = 28209;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART5_REGISTER_PART_5 = 28210;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART5_REGISTER_PART_5_LEN = 28211;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART6_REGISTER_PART_6 = 28212;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART6_REGISTER_PART_6_LEN = 28213;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART7_REGISTER_PART_7 = 28214;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART7_REGISTER_PART_7_LEN = 28215;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART8_REGISTER_PART_8 = 28216;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART8_REGISTER_PART_8_LEN = 28217;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART9_REGISTER_PART_9 = 28218;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART9_REGISTER_PART_9_LEN = 28219;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART10_REGISTER_PART_10 = 28220;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART10_REGISTER_PART_10_LEN = 28221;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART11_REGISTER_PART_11 = 28222;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART11_REGISTER_PART_11_LEN = 28223;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART12_REGISTER_PART_12 = 28224;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART12_REGISTER_PART_12_LEN = 28225;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART13_REGISTER_PART_13 = 28226;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART13_REGISTER_PART_13_LEN = 28227;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART14_REGISTER_PART_14 = 28228;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART14_REGISTER_PART_14_LEN = 28229;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART15_REGISTER_PART_15 = 28230;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART15_REGISTER_PART_15_LEN = 28231;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART16_REGISTER_PART_16 = 28232;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART16_REGISTER_PART_16_LEN = 28233;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART17_REGISTER_PART_17 = 28234;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART17_REGISTER_PART_17_LEN = 28235;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART18_REGISTER_PART_18 = 28236;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART18_REGISTER_PART_18_LEN = 28237;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART19_REGISTER_PART_19 = 28238;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART19_REGISTER_PART_19_LEN = 28239;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART20_REGISTER_PART_20 = 28240;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART20_REGISTER_PART_20_LEN = 28241;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART21_REGISTER_PART_21 = 28242;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART21_REGISTER_PART_21_LEN = 28243;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART22_REGISTER_PART_22 = 28244;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART22_REGISTER_PART_22_LEN = 28245;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART23_REGISTER_PART_23 = 28246;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART23_REGISTER_PART_23_LEN = 28247;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART24_REGISTER_PART_24 = 28248;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART24_REGISTER_PART_24_LEN = 28249;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART25_REGISTER_PART_25 = 28250;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART25_REGISTER_PART_25_LEN = 28251;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART26_REGISTER_PART_26 = 28252;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART26_REGISTER_PART_26_LEN = 28253;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART27_REGISTER_PART_27 = 28254;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART27_REGISTER_PART_27_LEN = 28255;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART28_REGISTER_PART_28 = 28256;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART28_REGISTER_PART_28_LEN = 28257;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART29_REGISTER_PART_29 = 28258;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART29_REGISTER_PART_29_LEN = 28259;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART30_REGISTER_PART_30 = 28260;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART30_REGISTER_PART_30_LEN = 28261;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART31_REGISTER_PART_31 = 28262;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART31_REGISTER_PART_31_LEN = 28263;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART32_REGISTER_PART_32 = 28264;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART32_REGISTER_PART_32_LEN = 28265;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART33_REGISTER_PART_33 = 28266;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART33_REGISTER_PART_33_LEN = 28267;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART34_REGISTER_PART_34 = 28268;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART34_REGISTER_PART_34_LEN = 28269;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART35_REGISTER_PART_35 = 28270;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART35_REGISTER_PART_35_LEN = 28271;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART36_REGISTER_PART_36 = 28272;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART36_REGISTER_PART_36_LEN = 28273;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART37_REGISTER_PART_37 = 28274;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART37_REGISTER_PART_37_LEN = 28275;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART38_REGISTER_PART_38 = 28276;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART38_REGISTER_PART_38_LEN = 28277;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART39_REGISTER_PART_39 = 28278;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART39_REGISTER_PART_39_LEN = 28279;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART40_REGISTER_PART_40 = 28280;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART40_REGISTER_PART_40_LEN = 28281;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART41_REGISTER_PART_41 = 28282;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART41_REGISTER_PART_41_LEN = 28283;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART42_REGISTER_PART_42 = 28284;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART42_REGISTER_PART_42_LEN = 28285;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART43_REGISTER_PART_43 = 28286;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART43_REGISTER_PART_43_LEN = 28287;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART44_REGISTER_PART_44 = 28288;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART44_REGISTER_PART_44_LEN = 28289;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART45_REGISTER_PART_45 = 28290;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART45_REGISTER_PART_45_LEN = 28291;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART46_REGISTER_PART_46 = 28292;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART46_REGISTER_PART_46_LEN = 28293;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART47_REGISTER_PART_47 = 28294;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART47_REGISTER_PART_47_LEN = 28295;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART48_REGISTER_PART_48 = 28296;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART48_REGISTER_PART_48_LEN = 28297;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART49_REGISTER_PART_49 = 28298;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART49_REGISTER_PART_49_LEN = 28299;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART50_REGISTER_PART_50 = 28300;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART50_REGISTER_PART_50_LEN = 28301;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART51_REGISTER_PART_51 = 28302;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART51_REGISTER_PART_51_LEN = 28303;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART52_REGISTER_PART_52 = 28304;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART52_REGISTER_PART_52_LEN = 28305;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART53_REGISTER_PART_53 = 28306;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART53_REGISTER_PART_53_LEN = 28307;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART54_REGISTER_PART_54 = 28308;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART54_REGISTER_PART_54_LEN = 28309;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART55_REGISTER_PART_55 = 28310;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART55_REGISTER_PART_55_LEN = 28311;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART56_REGISTER_PART_56 = 28312;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART56_REGISTER_PART_56_LEN = 28313;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART57_REGISTER_PART_57 = 28314;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART57_REGISTER_PART_57_LEN = 28315;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART58_REGISTER_PART_58 = 28316;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART58_REGISTER_PART_58_LEN = 28317;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART59_REGISTER_PART_59 = 28318;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART59_REGISTER_PART_59_LEN = 28319;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART60_REGISTER_PART_60 = 28320;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART60_REGISTER_PART_60_LEN = 28321;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART61_REGISTER_PART_61 = 28322;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART61_REGISTER_PART_61_LEN = 28323;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART62_REGISTER_PART_62 = 28324;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART62_REGISTER_PART_62_LEN = 28325;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART63_REGISTER_PART_63 = 28326;
static const uint64_t IDX_CEN_OTPROM5_ECID_PART63_REGISTER_PART_63_LEN = 28327;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART0_REGISTER_PART_0 = 28328;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART0_REGISTER_PART_0_LEN = 28329;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART1_REGISTER_PART_1 = 28330;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART1_REGISTER_PART_1_LEN = 28331;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART2_REGISTER_PART_2 = 28332;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART2_REGISTER_PART_2_LEN = 28333;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART3_REGISTER_PART_3 = 28334;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART3_REGISTER_PART_3_LEN = 28335;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART4_REGISTER_PART_4 = 28336;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART4_REGISTER_PART_4_LEN = 28337;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART5_REGISTER_PART_5 = 28338;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART5_REGISTER_PART_5_LEN = 28339;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART6_REGISTER_PART_6 = 28340;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART6_REGISTER_PART_6_LEN = 28341;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART7_REGISTER_PART_7 = 28342;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART7_REGISTER_PART_7_LEN = 28343;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART8_REGISTER_PART_8 = 28344;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART8_REGISTER_PART_8_LEN = 28345;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART9_REGISTER_PART_9 = 28346;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART9_REGISTER_PART_9_LEN = 28347;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART10_REGISTER_PART_10 = 28348;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART10_REGISTER_PART_10_LEN = 28349;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART11_REGISTER_PART_11 = 28350;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART11_REGISTER_PART_11_LEN = 28351;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART12_REGISTER_PART_12 = 28352;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART12_REGISTER_PART_12_LEN = 28353;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART13_REGISTER_PART_13 = 28354;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART13_REGISTER_PART_13_LEN = 28355;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART14_REGISTER_PART_14 = 28356;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART14_REGISTER_PART_14_LEN = 28357;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART15_REGISTER_PART_15 = 28358;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART15_REGISTER_PART_15_LEN = 28359;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART16_REGISTER_PART_16 = 28360;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART16_REGISTER_PART_16_LEN = 28361;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART17_REGISTER_PART_17 = 28362;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART17_REGISTER_PART_17_LEN = 28363;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART18_REGISTER_PART_18 = 28364;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART18_REGISTER_PART_18_LEN = 28365;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART19_REGISTER_PART_19 = 28366;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART19_REGISTER_PART_19_LEN = 28367;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART20_REGISTER_PART_20 = 28368;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART20_REGISTER_PART_20_LEN = 28369;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART21_REGISTER_PART_21 = 28370;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART21_REGISTER_PART_21_LEN = 28371;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART22_REGISTER_PART_22 = 28372;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART22_REGISTER_PART_22_LEN = 28373;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART23_REGISTER_PART_23 = 28374;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART23_REGISTER_PART_23_LEN = 28375;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART24_REGISTER_PART_24 = 28376;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART24_REGISTER_PART_24_LEN = 28377;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART25_REGISTER_PART_25 = 28378;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART25_REGISTER_PART_25_LEN = 28379;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART26_REGISTER_PART_26 = 28380;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART26_REGISTER_PART_26_LEN = 28381;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART27_REGISTER_PART_27 = 28382;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART27_REGISTER_PART_27_LEN = 28383;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART28_REGISTER_PART_28 = 28384;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART28_REGISTER_PART_28_LEN = 28385;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART29_REGISTER_PART_29 = 28386;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART29_REGISTER_PART_29_LEN = 28387;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART30_REGISTER_PART_30 = 28388;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART30_REGISTER_PART_30_LEN = 28389;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART31_REGISTER_PART_31 = 28390;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART31_REGISTER_PART_31_LEN = 28391;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART32_REGISTER_PART_32 = 28392;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART32_REGISTER_PART_32_LEN = 28393;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART33_REGISTER_PART_33 = 28394;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART33_REGISTER_PART_33_LEN = 28395;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART34_REGISTER_PART_34 = 28396;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART34_REGISTER_PART_34_LEN = 28397;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART35_REGISTER_PART_35 = 28398;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART35_REGISTER_PART_35_LEN = 28399;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART36_REGISTER_PART_36 = 28400;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART36_REGISTER_PART_36_LEN = 28401;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART37_REGISTER_PART_37 = 28402;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART37_REGISTER_PART_37_LEN = 28403;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART38_REGISTER_PART_38 = 28404;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART38_REGISTER_PART_38_LEN = 28405;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART39_REGISTER_PART_39 = 28406;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART39_REGISTER_PART_39_LEN = 28407;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART40_REGISTER_PART_40 = 28408;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART40_REGISTER_PART_40_LEN = 28409;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART41_REGISTER_PART_41 = 28410;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART41_REGISTER_PART_41_LEN = 28411;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART42_REGISTER_PART_42 = 28412;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART42_REGISTER_PART_42_LEN = 28413;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART43_REGISTER_PART_43 = 28414;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART43_REGISTER_PART_43_LEN = 28415;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART44_REGISTER_PART_44 = 28416;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART44_REGISTER_PART_44_LEN = 28417;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART45_REGISTER_PART_45 = 28418;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART45_REGISTER_PART_45_LEN = 28419;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART46_REGISTER_PART_46 = 28420;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART46_REGISTER_PART_46_LEN = 28421;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART47_REGISTER_PART_47 = 28422;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART47_REGISTER_PART_47_LEN = 28423;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART48_REGISTER_PART_48 = 28424;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART48_REGISTER_PART_48_LEN = 28425;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART49_REGISTER_PART_49 = 28426;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART49_REGISTER_PART_49_LEN = 28427;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART50_REGISTER_PART_50 = 28428;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART50_REGISTER_PART_50_LEN = 28429;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART51_REGISTER_PART_51 = 28430;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART51_REGISTER_PART_51_LEN = 28431;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART52_REGISTER_PART_52 = 28432;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART52_REGISTER_PART_52_LEN = 28433;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART53_REGISTER_PART_53 = 28434;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART53_REGISTER_PART_53_LEN = 28435;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART54_REGISTER_PART_54 = 28436;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART54_REGISTER_PART_54_LEN = 28437;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART55_REGISTER_PART_55 = 28438;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART55_REGISTER_PART_55_LEN = 28439;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART56_REGISTER_PART_56 = 28440;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART56_REGISTER_PART_56_LEN = 28441;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART57_REGISTER_PART_57 = 28442;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART57_REGISTER_PART_57_LEN = 28443;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART58_REGISTER_PART_58 = 28444;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART58_REGISTER_PART_58_LEN = 28445;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART59_REGISTER_PART_59 = 28446;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART59_REGISTER_PART_59_LEN = 28447;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART60_REGISTER_PART_60 = 28448;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART60_REGISTER_PART_60_LEN = 28449;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART61_REGISTER_PART_61 = 28450;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART61_REGISTER_PART_61_LEN = 28451;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART62_REGISTER_PART_62 = 28452;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART62_REGISTER_PART_62_LEN = 28453;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART63_REGISTER_PART_63 = 28454;
static const uint64_t IDX_CEN_OTPROM6_ECID_PART63_REGISTER_PART_63_LEN = 28455;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART0_REGISTER_PART_0 = 28456;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART0_REGISTER_PART_0_LEN = 28457;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART1_REGISTER_PART_1 = 28458;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART1_REGISTER_PART_1_LEN = 28459;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART2_REGISTER_PART_2 = 28460;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART2_REGISTER_PART_2_LEN = 28461;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART3_REGISTER_PART_3 = 28462;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART3_REGISTER_PART_3_LEN = 28463;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART4_REGISTER_PART_4 = 28464;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART4_REGISTER_PART_4_LEN = 28465;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART5_REGISTER_PART_5 = 28466;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART5_REGISTER_PART_5_LEN = 28467;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART6_REGISTER_PART_6 = 28468;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART6_REGISTER_PART_6_LEN = 28469;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART7_REGISTER_PART_7 = 28470;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART7_REGISTER_PART_7_LEN = 28471;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART8_REGISTER_PART_8 = 28472;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART8_REGISTER_PART_8_LEN = 28473;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART9_REGISTER_PART_9 = 28474;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART9_REGISTER_PART_9_LEN = 28475;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART10_REGISTER_PART_10 = 28476;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART10_REGISTER_PART_10_LEN = 28477;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART11_REGISTER_PART_11 = 28478;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART11_REGISTER_PART_11_LEN = 28479;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART12_REGISTER_PART_12 = 28480;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART12_REGISTER_PART_12_LEN = 28481;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART13_REGISTER_PART_13 = 28482;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART13_REGISTER_PART_13_LEN = 28483;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART14_REGISTER_PART_14 = 28484;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART14_REGISTER_PART_14_LEN = 28485;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART15_REGISTER_PART_15 = 28486;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART15_REGISTER_PART_15_LEN = 28487;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART16_REGISTER_PART_16 = 28488;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART16_REGISTER_PART_16_LEN = 28489;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART17_REGISTER_PART_17 = 28490;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART17_REGISTER_PART_17_LEN = 28491;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART18_REGISTER_PART_18 = 28492;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART18_REGISTER_PART_18_LEN = 28493;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART19_REGISTER_PART_19 = 28494;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART19_REGISTER_PART_19_LEN = 28495;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART20_REGISTER_PART_20 = 28496;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART20_REGISTER_PART_20_LEN = 28497;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART21_REGISTER_PART_21 = 28498;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART21_REGISTER_PART_21_LEN = 28499;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART22_REGISTER_PART_22 = 28500;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART22_REGISTER_PART_22_LEN = 28501;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART23_REGISTER_PART_23 = 28502;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART23_REGISTER_PART_23_LEN = 28503;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART24_REGISTER_PART_24 = 28504;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART24_REGISTER_PART_24_LEN = 28505;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART25_REGISTER_PART_25 = 28506;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART25_REGISTER_PART_25_LEN = 28507;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART26_REGISTER_PART_26 = 28508;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART26_REGISTER_PART_26_LEN = 28509;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART27_REGISTER_PART_27 = 28510;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART27_REGISTER_PART_27_LEN = 28511;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART28_REGISTER_PART_28 = 28512;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART28_REGISTER_PART_28_LEN = 28513;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART29_REGISTER_PART_29 = 28514;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART29_REGISTER_PART_29_LEN = 28515;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART30_REGISTER_PART_30 = 28516;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART30_REGISTER_PART_30_LEN = 28517;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART31_REGISTER_PART_31 = 28518;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART31_REGISTER_PART_31_LEN = 28519;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART32_REGISTER_PART_32 = 28520;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART32_REGISTER_PART_32_LEN = 28521;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART33_REGISTER_PART_33 = 28522;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART33_REGISTER_PART_33_LEN = 28523;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART34_REGISTER_PART_34 = 28524;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART34_REGISTER_PART_34_LEN = 28525;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART35_REGISTER_PART_35 = 28526;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART35_REGISTER_PART_35_LEN = 28527;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART36_REGISTER_PART_36 = 28528;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART36_REGISTER_PART_36_LEN = 28529;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART37_REGISTER_PART_37 = 28530;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART37_REGISTER_PART_37_LEN = 28531;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART38_REGISTER_PART_38 = 28532;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART38_REGISTER_PART_38_LEN = 28533;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART39_REGISTER_PART_39 = 28534;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART39_REGISTER_PART_39_LEN = 28535;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART40_REGISTER_PART_40 = 28536;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART40_REGISTER_PART_40_LEN = 28537;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART41_REGISTER_PART_41 = 28538;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART41_REGISTER_PART_41_LEN = 28539;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART42_REGISTER_PART_42 = 28540;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART42_REGISTER_PART_42_LEN = 28541;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART43_REGISTER_PART_43 = 28542;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART43_REGISTER_PART_43_LEN = 28543;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART44_REGISTER_PART_44 = 28544;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART44_REGISTER_PART_44_LEN = 28545;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART45_REGISTER_PART_45 = 28546;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART45_REGISTER_PART_45_LEN = 28547;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART46_REGISTER_PART_46 = 28548;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART46_REGISTER_PART_46_LEN = 28549;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART47_REGISTER_PART_47 = 28550;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART47_REGISTER_PART_47_LEN = 28551;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART48_REGISTER_PART_48 = 28552;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART48_REGISTER_PART_48_LEN = 28553;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART49_REGISTER_PART_49 = 28554;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART49_REGISTER_PART_49_LEN = 28555;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART50_REGISTER_PART_50 = 28556;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART50_REGISTER_PART_50_LEN = 28557;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART51_REGISTER_PART_51 = 28558;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART51_REGISTER_PART_51_LEN = 28559;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART52_REGISTER_PART_52 = 28560;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART52_REGISTER_PART_52_LEN = 28561;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART53_REGISTER_PART_53 = 28562;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART53_REGISTER_PART_53_LEN = 28563;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART54_REGISTER_PART_54 = 28564;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART54_REGISTER_PART_54_LEN = 28565;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART55_REGISTER_PART_55 = 28566;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART55_REGISTER_PART_55_LEN = 28567;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART56_REGISTER_PART_56 = 28568;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART56_REGISTER_PART_56_LEN = 28569;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART57_REGISTER_PART_57 = 28570;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART57_REGISTER_PART_57_LEN = 28571;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART58_REGISTER_PART_58 = 28572;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART58_REGISTER_PART_58_LEN = 28573;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART59_REGISTER_PART_59 = 28574;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART59_REGISTER_PART_59_LEN = 28575;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART60_REGISTER_PART_60 = 28576;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART60_REGISTER_PART_60_LEN = 28577;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART61_REGISTER_PART_61 = 28578;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART61_REGISTER_PART_61_LEN = 28579;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART62_REGISTER_PART_62 = 28580;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART62_REGISTER_PART_62_LEN = 28581;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART63_REGISTER_PART_63 = 28582;
static const uint64_t IDX_CEN_OTPROM7_ECID_PART63_REGISTER_PART_63_LEN = 28583;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART0_REGISTER_PART_0 = 28584;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART0_REGISTER_PART_0_LEN = 28585;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART1_REGISTER_PART_1 = 28586;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART1_REGISTER_PART_1_LEN = 28587;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART2_REGISTER_PART_2 = 28588;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART2_REGISTER_PART_2_LEN = 28589;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART3_REGISTER_PART_3 = 28590;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART3_REGISTER_PART_3_LEN = 28591;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART4_REGISTER_PART_4 = 28592;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART4_REGISTER_PART_4_LEN = 28593;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART5_REGISTER_PART_5 = 28594;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART5_REGISTER_PART_5_LEN = 28595;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART6_REGISTER_PART_6 = 28596;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART6_REGISTER_PART_6_LEN = 28597;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART7_REGISTER_PART_7 = 28598;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART7_REGISTER_PART_7_LEN = 28599;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART8_REGISTER_PART_8 = 28600;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART8_REGISTER_PART_8_LEN = 28601;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART9_REGISTER_PART_9 = 28602;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART9_REGISTER_PART_9_LEN = 28603;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART10_REGISTER_PART_10 = 28604;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART10_REGISTER_PART_10_LEN = 28605;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART11_REGISTER_PART_11 = 28606;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART11_REGISTER_PART_11_LEN = 28607;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART12_REGISTER_PART_12 = 28608;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART12_REGISTER_PART_12_LEN = 28609;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART13_REGISTER_PART_13 = 28610;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART13_REGISTER_PART_13_LEN = 28611;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART14_REGISTER_PART_14 = 28612;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART14_REGISTER_PART_14_LEN = 28613;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART15_REGISTER_PART_15 = 28614;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART15_REGISTER_PART_15_LEN = 28615;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART16_REGISTER_PART_16 = 28616;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART16_REGISTER_PART_16_LEN = 28617;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART17_REGISTER_PART_17 = 28618;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART17_REGISTER_PART_17_LEN = 28619;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART18_REGISTER_PART_18 = 28620;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART18_REGISTER_PART_18_LEN = 28621;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART19_REGISTER_PART_19 = 28622;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART19_REGISTER_PART_19_LEN = 28623;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART20_REGISTER_PART_20 = 28624;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART20_REGISTER_PART_20_LEN = 28625;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART21_REGISTER_PART_21 = 28626;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART21_REGISTER_PART_21_LEN = 28627;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART22_REGISTER_PART_22 = 28628;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART22_REGISTER_PART_22_LEN = 28629;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART23_REGISTER_PART_23 = 28630;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART23_REGISTER_PART_23_LEN = 28631;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART24_REGISTER_PART_24 = 28632;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART24_REGISTER_PART_24_LEN = 28633;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART25_REGISTER_PART_25 = 28634;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART25_REGISTER_PART_25_LEN = 28635;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART26_REGISTER_PART_26 = 28636;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART26_REGISTER_PART_26_LEN = 28637;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART27_REGISTER_PART_27 = 28638;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART27_REGISTER_PART_27_LEN = 28639;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART28_REGISTER_PART_28 = 28640;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART28_REGISTER_PART_28_LEN = 28641;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART29_REGISTER_PART_29 = 28642;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART29_REGISTER_PART_29_LEN = 28643;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART30_REGISTER_PART_30 = 28644;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART30_REGISTER_PART_30_LEN = 28645;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART31_REGISTER_PART_31 = 28646;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART31_REGISTER_PART_31_LEN = 28647;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART32_REGISTER_PART_32 = 28648;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART32_REGISTER_PART_32_LEN = 28649;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART33_REGISTER_PART_33 = 28650;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART33_REGISTER_PART_33_LEN = 28651;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART34_REGISTER_PART_34 = 28652;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART34_REGISTER_PART_34_LEN = 28653;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART35_REGISTER_PART_35 = 28654;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART35_REGISTER_PART_35_LEN = 28655;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART36_REGISTER_PART_36 = 28656;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART36_REGISTER_PART_36_LEN = 28657;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART37_REGISTER_PART_37 = 28658;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART37_REGISTER_PART_37_LEN = 28659;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART38_REGISTER_PART_38 = 28660;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART38_REGISTER_PART_38_LEN = 28661;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART39_REGISTER_PART_39 = 28662;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART39_REGISTER_PART_39_LEN = 28663;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART40_REGISTER_PART_40 = 28664;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART40_REGISTER_PART_40_LEN = 28665;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART41_REGISTER_PART_41 = 28666;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART41_REGISTER_PART_41_LEN = 28667;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART42_REGISTER_PART_42 = 28668;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART42_REGISTER_PART_42_LEN = 28669;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART43_REGISTER_PART_43 = 28670;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART43_REGISTER_PART_43_LEN = 28671;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART44_REGISTER_PART_44 = 28672;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART44_REGISTER_PART_44_LEN = 28673;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART45_REGISTER_PART_45 = 28674;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART45_REGISTER_PART_45_LEN = 28675;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART46_REGISTER_PART_46 = 28676;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART46_REGISTER_PART_46_LEN = 28677;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART47_REGISTER_PART_47 = 28678;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART47_REGISTER_PART_47_LEN = 28679;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART48_REGISTER_PART_48 = 28680;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART48_REGISTER_PART_48_LEN = 28681;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART49_REGISTER_PART_49 = 28682;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART49_REGISTER_PART_49_LEN = 28683;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART50_REGISTER_PART_50 = 28684;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART50_REGISTER_PART_50_LEN = 28685;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART51_REGISTER_PART_51 = 28686;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART51_REGISTER_PART_51_LEN = 28687;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART52_REGISTER_PART_52 = 28688;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART52_REGISTER_PART_52_LEN = 28689;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART53_REGISTER_PART_53 = 28690;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART53_REGISTER_PART_53_LEN = 28691;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART54_REGISTER_PART_54 = 28692;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART54_REGISTER_PART_54_LEN = 28693;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART55_REGISTER_PART_55 = 28694;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART55_REGISTER_PART_55_LEN = 28695;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART56_REGISTER_PART_56 = 28696;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART56_REGISTER_PART_56_LEN = 28697;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART57_REGISTER_PART_57 = 28698;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART57_REGISTER_PART_57_LEN = 28699;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART58_REGISTER_PART_58 = 28700;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART58_REGISTER_PART_58_LEN = 28701;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART59_REGISTER_PART_59 = 28702;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART59_REGISTER_PART_59_LEN = 28703;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART60_REGISTER_PART_60 = 28704;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART60_REGISTER_PART_60_LEN = 28705;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART61_REGISTER_PART_61 = 28706;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART61_REGISTER_PART_61_LEN = 28707;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART62_REGISTER_PART_62 = 28708;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART62_REGISTER_PART_62_LEN = 28709;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART63_REGISTER_PART_63 = 28710;
static const uint64_t IDX_CEN_OTPROM8_ECID_PART63_REGISTER_PART_63_LEN = 28711;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART0_REGISTER_PART_0 = 28712;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART0_REGISTER_PART_0_LEN = 28713;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART1_REGISTER_PART_1 = 28714;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART1_REGISTER_PART_1_LEN = 28715;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART2_REGISTER_PART_2 = 28716;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART2_REGISTER_PART_2_LEN = 28717;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART3_REGISTER_PART_3 = 28718;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART3_REGISTER_PART_3_LEN = 28719;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART4_REGISTER_PART_4 = 28720;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART4_REGISTER_PART_4_LEN = 28721;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART5_REGISTER_PART_5 = 28722;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART5_REGISTER_PART_5_LEN = 28723;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART6_REGISTER_PART_6 = 28724;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART6_REGISTER_PART_6_LEN = 28725;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART7_REGISTER_PART_7 = 28726;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART7_REGISTER_PART_7_LEN = 28727;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART8_REGISTER_PART_8 = 28728;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART8_REGISTER_PART_8_LEN = 28729;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART9_REGISTER_PART_9 = 28730;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART9_REGISTER_PART_9_LEN = 28731;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART10_REGISTER_PART_10 = 28732;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART10_REGISTER_PART_10_LEN = 28733;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART11_REGISTER_PART_11 = 28734;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART11_REGISTER_PART_11_LEN = 28735;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART12_REGISTER_PART_12 = 28736;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART12_REGISTER_PART_12_LEN = 28737;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART13_REGISTER_PART_13 = 28738;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART13_REGISTER_PART_13_LEN = 28739;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART14_REGISTER_PART_14 = 28740;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART14_REGISTER_PART_14_LEN = 28741;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART15_REGISTER_PART_15 = 28742;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART15_REGISTER_PART_15_LEN = 28743;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART16_REGISTER_PART_16 = 28744;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART16_REGISTER_PART_16_LEN = 28745;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART17_REGISTER_PART_17 = 28746;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART17_REGISTER_PART_17_LEN = 28747;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART18_REGISTER_PART_18 = 28748;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART18_REGISTER_PART_18_LEN = 28749;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART19_REGISTER_PART_19 = 28750;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART19_REGISTER_PART_19_LEN = 28751;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART20_REGISTER_PART_20 = 28752;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART20_REGISTER_PART_20_LEN = 28753;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART21_REGISTER_PART_21 = 28754;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART21_REGISTER_PART_21_LEN = 28755;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART22_REGISTER_PART_22 = 28756;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART22_REGISTER_PART_22_LEN = 28757;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART23_REGISTER_PART_23 = 28758;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART23_REGISTER_PART_23_LEN = 28759;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART24_REGISTER_PART_24 = 28760;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART24_REGISTER_PART_24_LEN = 28761;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART25_REGISTER_PART_25 = 28762;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART25_REGISTER_PART_25_LEN = 28763;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART26_REGISTER_PART_26 = 28764;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART26_REGISTER_PART_26_LEN = 28765;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART27_REGISTER_PART_27 = 28766;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART27_REGISTER_PART_27_LEN = 28767;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART28_REGISTER_PART_28 = 28768;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART28_REGISTER_PART_28_LEN = 28769;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART29_REGISTER_PART_29 = 28770;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART29_REGISTER_PART_29_LEN = 28771;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART30_REGISTER_PART_30 = 28772;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART30_REGISTER_PART_30_LEN = 28773;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART31_REGISTER_PART_31 = 28774;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART31_REGISTER_PART_31_LEN = 28775;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART32_REGISTER_PART_32 = 28776;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART32_REGISTER_PART_32_LEN = 28777;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART33_REGISTER_PART_33 = 28778;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART33_REGISTER_PART_33_LEN = 28779;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART34_REGISTER_PART_34 = 28780;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART34_REGISTER_PART_34_LEN = 28781;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART35_REGISTER_PART_35 = 28782;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART35_REGISTER_PART_35_LEN = 28783;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART36_REGISTER_PART_36 = 28784;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART36_REGISTER_PART_36_LEN = 28785;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART37_REGISTER_PART_37 = 28786;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART37_REGISTER_PART_37_LEN = 28787;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART38_REGISTER_PART_38 = 28788;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART38_REGISTER_PART_38_LEN = 28789;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART39_REGISTER_PART_39 = 28790;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART39_REGISTER_PART_39_LEN = 28791;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART40_REGISTER_PART_40 = 28792;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART40_REGISTER_PART_40_LEN = 28793;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART41_REGISTER_PART_41 = 28794;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART41_REGISTER_PART_41_LEN = 28795;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART42_REGISTER_PART_42 = 28796;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART42_REGISTER_PART_42_LEN = 28797;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART43_REGISTER_PART_43 = 28798;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART43_REGISTER_PART_43_LEN = 28799;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART44_REGISTER_PART_44 = 28800;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART44_REGISTER_PART_44_LEN = 28801;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART45_REGISTER_PART_45 = 28802;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART45_REGISTER_PART_45_LEN = 28803;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART46_REGISTER_PART_46 = 28804;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART46_REGISTER_PART_46_LEN = 28805;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART47_REGISTER_PART_47 = 28806;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART47_REGISTER_PART_47_LEN = 28807;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART48_REGISTER_PART_48 = 28808;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART48_REGISTER_PART_48_LEN = 28809;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART49_REGISTER_PART_49 = 28810;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART49_REGISTER_PART_49_LEN = 28811;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART50_REGISTER_PART_50 = 28812;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART50_REGISTER_PART_50_LEN = 28813;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART51_REGISTER_PART_51 = 28814;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART51_REGISTER_PART_51_LEN = 28815;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART52_REGISTER_PART_52 = 28816;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART52_REGISTER_PART_52_LEN = 28817;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART53_REGISTER_PART_53 = 28818;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART53_REGISTER_PART_53_LEN = 28819;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART54_REGISTER_PART_54 = 28820;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART54_REGISTER_PART_54_LEN = 28821;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART55_REGISTER_PART_55 = 28822;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART55_REGISTER_PART_55_LEN = 28823;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART56_REGISTER_PART_56 = 28824;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART56_REGISTER_PART_56_LEN = 28825;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART57_REGISTER_PART_57 = 28826;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART57_REGISTER_PART_57_LEN = 28827;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART58_REGISTER_PART_58 = 28828;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART58_REGISTER_PART_58_LEN = 28829;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART59_REGISTER_PART_59 = 28830;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART59_REGISTER_PART_59_LEN = 28831;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART60_REGISTER_PART_60 = 28832;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART60_REGISTER_PART_60_LEN = 28833;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART61_REGISTER_PART_61 = 28834;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART61_REGISTER_PART_61_LEN = 28835;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART62_REGISTER_PART_62 = 28836;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART62_REGISTER_PART_62_LEN = 28837;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART63_REGISTER_PART_63 = 28838;
static const uint64_t IDX_CEN_OTPROM9_ECID_PART63_REGISTER_PART_63_LEN = 28839;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_BYPMODE = 28840;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_BYPMODE_LEN = 28841;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_BYPASS = 28842;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_CHARMODE = 28843;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_CHARMODE_LEN = 28844;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_CP_TUNE = 28845;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_CP_TUNE_LEN = 28846;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_DUTY_ADJ = 28847;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_DUTY_ADJ_LEN = 28848;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_FBKMODE = 28849;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_IREF_TUNE = 28850;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_IREF_TUNE_LEN = 28851;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_JIT_CNTL = 28852;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_JIT_CNTL_LEN = 28853;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_LOCK_TUNE = 28854;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_LOCK_TUNE_LEN = 28855;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_MULT = 28856;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_MULT_LEN = 28857;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_OUTSEL = 28858;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_OUTSEL_LEN = 28859;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_PHASEDET_TUNE = 28860;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_PHASEDET_TUNE_LEN = 28861;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_FBKSEL = 28862;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_RANGEA = 28863;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL0_RANGEA_LEN = 28864;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_RANGEB = 28865;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_RANGEB_LEN = 28866;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_REFDIV = 28867;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_A2D_TUNE_0_TO_1 = 28868;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_A2D_TUNE_0_TO_1_LEN = 28869;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_A2D_TUNE_2_TO_6 = 28870;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_A2D_TUNE_2_TO_6_LEN = 28871;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_ANALOGOUT_TUNE = 28872;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_ANALOGOUT_TUNE_LEN = 28873;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_VREG_TUNE = 28874;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_VREG_TUNE_LEN = 28875;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_CTST_TUNE = 28876;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_LOCK_SEL = 28877;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TST_MODE_EN = 28878;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TSTMODE_NCAP_LT = 28879;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TSTMODE_IREF_LT = 28880;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TSTMODE_DT_LT = 28881;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TSTMODE_AOUT_LT = 28882;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TSTMODE_VCOCMP_LT = 28883;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TSTMODE_CTST_LT = 28884;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TSTMODE_VCO_SEL = 28885;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_CPHASE = 28886;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_E_MODE_ENABLE = 28887;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TUNE = 28888;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_TUNE_LEN = 28889;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL1_OUTA_DISABLE = 28890;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL2_OUTB_DISABLE = 28891;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL2_VCODIV = 28892;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL2_VCODIV_LEN = 28893;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL2_DIGTESTOUT = 28894;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL2_RESET = 28895;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL2_SPARE = 28896;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL2_SPARE_LEN = 28897;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_BYPMODE = 28898;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_BYPMODE_LEN = 28899;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_BYPASS = 28900;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_CHARMODE = 28901;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_CHARMODE_LEN = 28902;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_CP_TUNE = 28903;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_CP_TUNE_LEN = 28904;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_DUTY_ADJ = 28905;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_DUTY_ADJ_LEN = 28906;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_FBKMODE = 28907;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_IREF_TUNE = 28908;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_IREF_TUNE_LEN = 28909;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_JIT_CNTL = 28910;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_JIT_CNTL_LEN = 28911;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_LOCK_TUNE = 28912;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_LOCK_TUNE_LEN = 28913;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_MULT = 28914;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_MULT_LEN = 28915;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_OUTSEL = 28916;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_OUTSEL_LEN = 28917;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_PHASEDET_TUNE = 28918;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_PHASEDET_TUNE_LEN = 28919;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_FBKSEL = 28920;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_RANGEA = 28921;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP0_SHADOW_RANGEA_LEN = 28922;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_RANGEB = 28923;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_RANGEB_LEN = 28924;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_REFDIV = 28925;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_A2D_TUNE_0_TO_1 = 28926;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_A2D_TUNE_0_TO_1_LEN = 28927;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_A2D_TUNE_2_TO_6 = 28928;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_A2D_TUNE_2_TO_6_LEN = 28929;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_ANALOGOUT_TUNE = 28930;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_ANALOGOUT_TUNE_LEN = 28931;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_VREG_TUNE = 28932;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_VREG_TUNE_LEN = 28933;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_CTST_TUNE = 28934;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_LOCK_SEL = 28935;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TST_MODE_EN = 28936;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TSTMODE_NCAP_LT = 28937;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TSTMODE_IREF_LT = 28938;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TSTMODE_DT_LT = 28939;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TSTMODE_AOUT_LT = 28940;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TSTMODE_VCOCMP_LT = 28941;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TSTMODE_CTST_LT = 28942;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TSTMODE_VCO_SEL = 28943;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_CPHASE = 28944;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_E_MODE_ENABLE = 28945;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TUNE = 28946;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_TUNE_LEN = 28947;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP1_SHADOW_OUTA_DISABLE = 28948;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP2_SHADOW_OUTB_DISABLE = 28949;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP2_SHADOW_VCODIV = 28950;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP2_SHADOW_VCODIV_LEN = 28951;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP2_SHADOW_DIGTESTOUT = 28952;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP2_SHADOW_RESET = 28953;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP2_SHADOW_SPARE = 28954;
static const uint64_t IDX_CEN_PLLMEM_PLL_CNTRL_SETUP2_SHADOW_SPARE_LEN = 28955;
static const uint64_t IDX_CEN_SCAC_ACTIONMASK_ACTIONMASK = 28956;
static const uint64_t IDX_CEN_SCAC_ACTIONMASK_ACTIONMASK_LEN = 28957;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP0 = 28958;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP0_LEN = 28959;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP1 = 28960;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP1_LEN = 28961;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP2 = 28962;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP2_LEN = 28963;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP3 = 28964;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP3_LEN = 28965;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP4 = 28966;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP4_LEN = 28967;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP5 = 28968;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP5_LEN = 28969;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP6 = 28970;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP6_LEN = 28971;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP7 = 28972;
static const uint64_t IDX_CEN_SCAC_ADDRMAP_SENSORMAP7_LEN = 28973;
static const uint64_t IDX_CEN_SCAC_CONFIG_MASTERENABLE = 28974;
static const uint64_t IDX_CEN_SCAC_CONFIG_SYNCSELECT = 28975;
static const uint64_t IDX_CEN_SCAC_CONFIG_EDGETYPE = 28976;
static const uint64_t IDX_CEN_SCAC_CONFIG_EXPANSION0 = 28977;
static const uint64_t IDX_CEN_SCAC_CONFIG_EXPANSION0_LEN = 28978;
static const uint64_t IDX_CEN_SCAC_CONFIG_EXPANSION1 = 28979;
static const uint64_t IDX_CEN_SCAC_CONFIG_EXPANSION1_LEN = 28980;
static const uint64_t IDX_CEN_SCAC_CONFIG_INTERVALTIMER = 28981;
static const uint64_t IDX_CEN_SCAC_CONFIG_INTERVALTIMER_LEN = 28982;
static const uint64_t IDX_CEN_SCAC_CONFIG_STALLTHRESHOLD = 28983;
static const uint64_t IDX_CEN_SCAC_CONFIG_STALLTHRESHOLD_LEN = 28984;
static const uint64_t IDX_CEN_SCAC_CONFIG_ERRRESET = 28985;
static const uint64_t IDX_CEN_SCAC_CONFIG_REGPARINJ = 28986;
static const uint64_t IDX_CEN_SCAC_CONFIG_SMINJ = 28987;
static const uint64_t IDX_CEN_SCAC_DATA0_3_CRITTRIP0 = 28988;
static const uint64_t IDX_CEN_SCAC_DATA0_3_ABOVETRIP0 = 28989;
static const uint64_t IDX_CEN_SCAC_DATA0_3_BELOWTRIP0 = 28990;
static const uint64_t IDX_CEN_SCAC_DATA0_3_SIGNBIT0 = 28991;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE0 = 28992;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE0_LEN = 28993;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS0 = 28994;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS0_LEN = 28995;
static const uint64_t IDX_CEN_SCAC_DATA0_3_CRITTRIP1 = 28996;
static const uint64_t IDX_CEN_SCAC_DATA0_3_ABOVETRIP1 = 28997;
static const uint64_t IDX_CEN_SCAC_DATA0_3_BELOWTRIP1 = 28998;
static const uint64_t IDX_CEN_SCAC_DATA0_3_SIGNBIT1 = 28999;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE1 = 29000;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE1_LEN = 29001;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS1 = 29002;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS1_LEN = 29003;
static const uint64_t IDX_CEN_SCAC_DATA0_3_CRITTRIP2 = 29004;
static const uint64_t IDX_CEN_SCAC_DATA0_3_ABOVETRIP2 = 29005;
static const uint64_t IDX_CEN_SCAC_DATA0_3_BELOWTRIP2 = 29006;
static const uint64_t IDX_CEN_SCAC_DATA0_3_SIGNBIT2 = 29007;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE2 = 29008;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE2_LEN = 29009;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS2 = 29010;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS2_LEN = 29011;
static const uint64_t IDX_CEN_SCAC_DATA0_3_CRITTRIP3 = 29012;
static const uint64_t IDX_CEN_SCAC_DATA0_3_ABOVETRIP3 = 29013;
static const uint64_t IDX_CEN_SCAC_DATA0_3_BELOWTRIP3 = 29014;
static const uint64_t IDX_CEN_SCAC_DATA0_3_SIGNBIT3 = 29015;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE3 = 29016;
static const uint64_t IDX_CEN_SCAC_DATA0_3_TEMPERATURE3_LEN = 29017;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS3 = 29018;
static const uint64_t IDX_CEN_SCAC_DATA0_3_STATUS3_LEN = 29019;
static const uint64_t IDX_CEN_SCAC_DATA4_7_CRITTRIP4 = 29020;
static const uint64_t IDX_CEN_SCAC_DATA4_7_ALARMTRIP4 = 29021;
static const uint64_t IDX_CEN_SCAC_DATA4_7_BELOWTRIP4 = 29022;
static const uint64_t IDX_CEN_SCAC_DATA4_7_SIGNBIT4 = 29023;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE4 = 29024;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE4_LEN = 29025;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS4 = 29026;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS4_LEN = 29027;
static const uint64_t IDX_CEN_SCAC_DATA4_7_CRITTRIP5 = 29028;
static const uint64_t IDX_CEN_SCAC_DATA4_7_ALARMTRIP5 = 29029;
static const uint64_t IDX_CEN_SCAC_DATA4_7_BELOWTRIP5 = 29030;
static const uint64_t IDX_CEN_SCAC_DATA4_7_SIGNBIT5 = 29031;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE5 = 29032;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE5_LEN = 29033;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS5 = 29034;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS5_LEN = 29035;
static const uint64_t IDX_CEN_SCAC_DATA4_7_CRITTRIP6 = 29036;
static const uint64_t IDX_CEN_SCAC_DATA4_7_ALARMTRIP6 = 29037;
static const uint64_t IDX_CEN_SCAC_DATA4_7_BELOWTRIP6 = 29038;
static const uint64_t IDX_CEN_SCAC_DATA4_7_SIGNBIT6 = 29039;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE6 = 29040;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE6_LEN = 29041;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS6 = 29042;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS6_LEN = 29043;
static const uint64_t IDX_CEN_SCAC_DATA4_7_CRITTRIP7 = 29044;
static const uint64_t IDX_CEN_SCAC_DATA4_7_ALARMTRIP7 = 29045;
static const uint64_t IDX_CEN_SCAC_DATA4_7_BELOWTRIP7 = 29046;
static const uint64_t IDX_CEN_SCAC_DATA4_7_SIGNBIT7 = 29047;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE7 = 29048;
static const uint64_t IDX_CEN_SCAC_DATA4_7_TEMPERATURE7_LEN = 29049;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS7 = 29050;
static const uint64_t IDX_CEN_SCAC_DATA4_7_STATUS7_LEN = 29051;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR0 = 29052;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR1 = 29053;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR2 = 29054;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR3 = 29055;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR4 = 29056;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR5 = 29057;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR6 = 29058;
static const uint64_t IDX_CEN_SCAC_ENABLE_ENABLESENSOR7 = 29059;
static const uint64_t IDX_CEN_SCAC_ERRRPT_ACTIONMASK_PE_HOLD_OUT = 29060;
static const uint64_t IDX_CEN_SCAC_ERRRPT_ADDRMAP_PE_HOLD_OUT = 29061;
static const uint64_t IDX_CEN_SCAC_ERRRPT_CONFIG_PE_HOLD_OUT = 29062;
static const uint64_t IDX_CEN_SCAC_ERRRPT_DATA0_3_PE_HOLD_OUT = 29063;
static const uint64_t IDX_CEN_SCAC_ERRRPT_DATA_7_PE_HOLD_OUT = 29064;
static const uint64_t IDX_CEN_SCAC_ERRRPT_ENABLE_PE_HOLD_OUT = 29065;
static const uint64_t IDX_CEN_SCAC_ERRRPT_I2CMCTRL_PE_HOLD_OUT = 29066;
static const uint64_t IDX_CEN_SCAC_ERRRPT_MSM_HOLD_OUT = 29067;
static const uint64_t IDX_CEN_SCAC_ERRRPT_PGSM_HOLD_OUT = 29068;
static const uint64_t IDX_CEN_SCAC_ERRRPT_PIBTARGET_PE_HOLD_OUT = 29069;
static const uint64_t IDX_CEN_SCAC_FIRACTION0_FIRACTION0 = 29070;
static const uint64_t IDX_CEN_SCAC_FIRACTION0_FIRACTION0_LEN = 29071;
static const uint64_t IDX_CEN_SCAC_FIRACTION1_FIRACTION1 = 29072;
static const uint64_t IDX_CEN_SCAC_FIRACTION1_FIRACTION1_LEN = 29073;
static const uint64_t IDX_CEN_SCAC_FIRMASK_FIRMASK = 29074;
static const uint64_t IDX_CEN_SCAC_FIRMASK_FIRMASK_LEN = 29075;
static const uint64_t IDX_CEN_SCAC_FIRWOF_FIRWOF = 29076;
static const uint64_t IDX_CEN_SCAC_FIRWOF_FIRWOF_LEN = 29077;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CCMD = 29078;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CCMD_LEN = 29079;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CSEGMENT = 29080;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CSEGMENT_LEN = 29081;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_SPARE1 = 29082;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_SPARE1_LEN = 29083;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CRNW = 29084;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CSPEED = 29085;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CSPEED_LEN = 29086;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CPORT = 29087;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CPORT_LEN = 29088;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CADRLEN = 29089;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CADRLEN_LEN = 29090;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CENHANCED = 29091;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_CTRLOFFSET = 29092;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_CTRLOFFSET_LEN = 29093;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_STATOFFSET = 29094;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_STATOFFSET_LEN = 29095;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_RESETOFFSET = 29096;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_RESETOFFSET_LEN = 29097;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CFIFODATA = 29098;
static const uint64_t IDX_CEN_SCAC_I2CMCTRL_SCAC_I2CMCTRL_I2CFIFODATA_LEN = 29099;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMINVADDR = 29100;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMINVWRITE = 29101;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMINVREAD = 29102;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMAPAR = 29103;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMPAR = 29104;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMLBPAR = 29105;
static const uint64_t IDX_CEN_SCAC_LFIR_EXPANSION = 29106;
static const uint64_t IDX_CEN_SCAC_LFIR_EXPANSION_LEN = 29107;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMINVCMD = 29108;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMPERR = 29109;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMOVERRUN = 29110;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMACCESS = 29111;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMARB = 29112;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMNACK = 29113;
static const uint64_t IDX_CEN_SCAC_LFIR_I2CMSTOP = 29114;
static const uint64_t IDX_CEN_SCAC_LFIR_LOCALPIB1 = 29115;
static const uint64_t IDX_CEN_SCAC_LFIR_LOCALPIB2 = 29116;
static const uint64_t IDX_CEN_SCAC_LFIR_LOCALPIB3 = 29117;
static const uint64_t IDX_CEN_SCAC_LFIR_LOCALPIB4 = 29118;
static const uint64_t IDX_CEN_SCAC_LFIR_LOCALPIB5 = 29119;
static const uint64_t IDX_CEN_SCAC_LFIR_LOCALPIB6 = 29120;
static const uint64_t IDX_CEN_SCAC_LFIR_LOCALPIB7 = 29121;
static const uint64_t IDX_CEN_SCAC_LFIR_STALLERROR = 29122;
static const uint64_t IDX_CEN_SCAC_LFIR_REGPARERR = 29123;
static const uint64_t IDX_CEN_SCAC_LFIR_REGPARERRX = 29124;
static const uint64_t IDX_CEN_SCAC_LFIR_RESERVED_27_31 = 29125;
static const uint64_t IDX_CEN_SCAC_LFIR_RESERVED_27_31_LEN = 29126;
static const uint64_t IDX_CEN_SCAC_LFIR_SMERR = 29127;
static const uint64_t IDX_CEN_SCAC_LFIR_REGACCERR = 29128;
static const uint64_t IDX_CEN_SCAC_LFIR_RESETERR = 29129;
static const uint64_t IDX_CEN_SCAC_LFIR_INTERNAL_SCOM_ERROR = 29130;
static const uint64_t IDX_CEN_SCAC_LFIR_INTERNAL_SCOM_ERROR_CLONE = 29131;
static const uint64_t IDX_CEN_SCAC_PIBTARGET_PRIMARYBASE = 29132;
static const uint64_t IDX_CEN_SCAC_PIBTARGET_PRIMARYBASE_LEN = 29133;
static const uint64_t IDX_CEN_SCAC_PIBTARGET_SPAREBASE = 29134;
static const uint64_t IDX_CEN_SCAC_PIBTARGET_SPAREBASE_LEN = 29135;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG = 29136;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE0_REG_LEN = 29137;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG = 29138;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE1_REG_LEN = 29139;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG = 29140;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE2_REG_LEN = 29141;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG = 29142;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE3_REG_LEN = 29143;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG = 29144;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE4_REG_LEN = 29145;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG = 29146;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE5_REG_LEN = 29147;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG = 29148;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE6_REG_LEN = 29149;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG = 29150;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE7_REG_LEN = 29151;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG = 29152;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE8_REG_LEN = 29153;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG = 29154;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE9_REG_LEN = 29155;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG = 29156;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE10_REG_LEN = 29157;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG = 29158;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE11_REG_LEN = 29159;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG = 29160;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE12_REG_LEN = 29161;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG = 29162;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE13_REG_LEN = 29163;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG = 29164;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE14_REG_LEN = 29165;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG = 29166;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_0_PCB_SLAVE15_REG_LEN = 29167;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS = 29168;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_1_PCB_SLAVE_GROUP1_REGS_LEN = 29169;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS = 29170;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_2_PCB_SLAVE_GROUP2_REGS_LEN = 29171;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS = 29172;
static const uint64_t IDX_CEN_PIBMST_PIB_EXTENDED_ERROR_REGISTER_3_PCB_SLAVE_GROUP3_REGS_LEN = 29173;
static const uint64_t IDX_CEN_FBNAMC_CFG_FBN_ADDR_MASK = 29174;
static const uint64_t IDX_CEN_FBNAMC_CFG_FBN_ADDR_MASK_LEN = 29175;
static const uint64_t IDX_CEN_FBNBAC_CFG_FBN_ADDR_BASE = 29176;
static const uint64_t IDX_CEN_FBNBAC_CFG_FBN_ADDR_BASE_LEN = 29177;
static const uint64_t IDX_CEN_FBNCNTL_FBIST_START = 29178;
static const uint64_t IDX_CEN_FBNCNTL_FBIST_STOP = 29179;
static const uint64_t IDX_CEN_FBNCNTL_RESERVED_2_4 = 29180;
static const uint64_t IDX_CEN_FBNCNTL_RESERVED_2_4_LEN = 29181;
static const uint64_t IDX_CEN_FBNCNTL_FBIST_MODE = 29182;
static const uint64_t IDX_CEN_FBNCNTL_FBIST_CONT = 29183;
static const uint64_t IDX_CEN_FBNCNTL_FBIST_STEP = 29184;
static const uint64_t IDX_CEN_FBNCSPCR_CFG_FBN_CMD_SPC = 29185;
static const uint64_t IDX_CEN_FBNCSPCR_CFG_FBN_CMD_SPC_LEN = 29186;
static const uint64_t IDX_CEN_FBNCSPCR_CFG_FBN_CMD_SPC_SEED = 29187;
static const uint64_t IDX_CEN_FBNCSPCR_CFG_FBN_CMD_SPC_SEED_LEN = 29188;
static const uint64_t IDX_CEN_FBNDCM0_CFG_FBN_DATA_CMP_MASK0 = 29189;
static const uint64_t IDX_CEN_FBNDCM0_CFG_FBN_DATA_CMP_MASK0_LEN = 29190;
static const uint64_t IDX_CEN_FBNDCM1_CFG_FBN_DATA_CMP_MASK1 = 29191;
static const uint64_t IDX_CEN_FBNDCM1_CFG_FBN_DATA_CMP_MASK1_LEN = 29192;
static const uint64_t IDX_CEN_FBNDCM10_CFG_FBN_DATA_CMP_MASK10 = 29193;
static const uint64_t IDX_CEN_FBNDCM10_CFG_FBN_DATA_CMP_MASK10_LEN = 29194;
static const uint64_t IDX_CEN_FBNDCM11_CFG_FBN_DATA_CMP_MASK11 = 29195;
static const uint64_t IDX_CEN_FBNDCM11_CFG_FBN_DATA_CMP_MASK11_LEN = 29196;
static const uint64_t IDX_CEN_FBNDCM12_CFG_FBN_DATA_CMP_MASK12 = 29197;
static const uint64_t IDX_CEN_FBNDCM12_CFG_FBN_DATA_CMP_MASK12_LEN = 29198;
static const uint64_t IDX_CEN_FBNDCM13_CFG_FBN_DATA_CMP_MASK13 = 29199;
static const uint64_t IDX_CEN_FBNDCM13_CFG_FBN_DATA_CMP_MASK13_LEN = 29200;
static const uint64_t IDX_CEN_FBNDCM14_CFG_FBN_DATA_CMP_MASK14 = 29201;
static const uint64_t IDX_CEN_FBNDCM14_CFG_FBN_DATA_CMP_MASK14_LEN = 29202;
static const uint64_t IDX_CEN_FBNDCM15_CFG_FBN_DATA_CMP_MASK15 = 29203;
static const uint64_t IDX_CEN_FBNDCM15_CFG_FBN_DATA_CMP_MASK15_LEN = 29204;
static const uint64_t IDX_CEN_FBNDCM2_CFG_FBN_DATA_CMP_MASK2 = 29205;
static const uint64_t IDX_CEN_FBNDCM2_CFG_FBN_DATA_CMP_MASK2_LEN = 29206;
static const uint64_t IDX_CEN_FBNDCM3_CFG_FBN_DATA_CMP_MASK3 = 29207;
static const uint64_t IDX_CEN_FBNDCM3_CFG_FBN_DATA_CMP_MASK3_LEN = 29208;
static const uint64_t IDX_CEN_FBNDCM4_CFG_FBN_DATA_CMP_MASK4 = 29209;
static const uint64_t IDX_CEN_FBNDCM4_CFG_FBN_DATA_CMP_MASK4_LEN = 29210;
static const uint64_t IDX_CEN_FBNDCM5_CFG_FBN_DATA_CMP_MASK5 = 29211;
static const uint64_t IDX_CEN_FBNDCM5_CFG_FBN_DATA_CMP_MASK5_LEN = 29212;
static const uint64_t IDX_CEN_FBNDCM6_CFG_FBN_DATA_CMP_MASK6 = 29213;
static const uint64_t IDX_CEN_FBNDCM6_CFG_FBN_DATA_CMP_MASK6_LEN = 29214;
static const uint64_t IDX_CEN_FBNDCM7_CFG_FBN_DATA_CMP_MASK7 = 29215;
static const uint64_t IDX_CEN_FBNDCM7_CFG_FBN_DATA_CMP_MASK7_LEN = 29216;
static const uint64_t IDX_CEN_FBNDCM8_CFG_FBN_DATA_CMP_MASK8 = 29217;
static const uint64_t IDX_CEN_FBNDCM8_CFG_FBN_DATA_CMP_MASK8_LEN = 29218;
static const uint64_t IDX_CEN_FBNDCM9_CFG_FBN_DATA_CMP_MASK9 = 29219;
static const uint64_t IDX_CEN_FBNDCM9_CFG_FBN_DATA_CMP_MASK9_LEN = 29220;
static const uint64_t IDX_CEN_FBNDCR_CFG_FBN_DATA_INV = 29221;
static const uint64_t IDX_CEN_FBNDCR_CFG_FBN_DATA_INV_LEN = 29222;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR0 = 29223;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR0_LEN = 29224;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR1 = 29225;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR1_LEN = 29226;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR2 = 29227;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR2_LEN = 29228;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR3 = 29229;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR3_LEN = 29230;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR4 = 29231;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR4_LEN = 29232;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR5 = 29233;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR5_LEN = 29234;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR6 = 29235;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR6_LEN = 29236;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR7 = 29237;
static const uint64_t IDX_CEN_FBNDMEC0_FBN_ERR_CNTR7_LEN = 29238;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR8 = 29239;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR8_LEN = 29240;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR9 = 29241;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR9_LEN = 29242;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR10 = 29243;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR10_LEN = 29244;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR11 = 29245;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR11_LEN = 29246;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR12 = 29247;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR12_LEN = 29248;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR13 = 29249;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR13_LEN = 29250;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR14 = 29251;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR14_LEN = 29252;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR15 = 29253;
static const uint64_t IDX_CEN_FBNDMEC1_FBN_ERR_CNTR15_LEN = 29254;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR16 = 29255;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR16_LEN = 29256;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR17 = 29257;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR17_LEN = 29258;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR18 = 29259;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR18_LEN = 29260;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR19 = 29261;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR19_LEN = 29262;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR20 = 29263;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR20_LEN = 29264;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR21 = 29265;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR21_LEN = 29266;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR22 = 29267;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR22_LEN = 29268;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR23 = 29269;
static const uint64_t IDX_CEN_FBNDMEC2_FBN_ERR_CNTR23_LEN = 29270;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR24 = 29271;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR24_LEN = 29272;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR25 = 29273;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR25_LEN = 29274;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR26 = 29275;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR26_LEN = 29276;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR27 = 29277;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR27_LEN = 29278;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR28 = 29279;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR28_LEN = 29280;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR29 = 29281;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR29_LEN = 29282;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR30 = 29283;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR30_LEN = 29284;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR31 = 29285;
static const uint64_t IDX_CEN_FBNDMEC3_FBN_ERR_CNTR31_LEN = 29286;
static const uint64_t IDX_CEN_FBNEA_CFG_FBN_ERR_ADDR = 29287;
static const uint64_t IDX_CEN_FBNEA_CFG_FBN_ERR_ADDR_LEN = 29288;
static const uint64_t IDX_CEN_FBNEAC_CFG_FBN_ADDR_END = 29289;
static const uint64_t IDX_CEN_FBNEAC_CFG_FBN_ADDR_END_LEN = 29290;
static const uint64_t IDX_CEN_FBNED0_FBN_DATA_EXP0 = 29291;
static const uint64_t IDX_CEN_FBNED0_FBN_DATA_EXP0_LEN = 29292;
static const uint64_t IDX_CEN_FBNED1_FBN_DATA_EXP1 = 29293;
static const uint64_t IDX_CEN_FBNED1_FBN_DATA_EXP1_LEN = 29294;
static const uint64_t IDX_CEN_FBNED10_FBN_DATA_EXP10 = 29295;
static const uint64_t IDX_CEN_FBNED10_FBN_DATA_EXP10_LEN = 29296;
static const uint64_t IDX_CEN_FBNED11_FBN_DATA_EXP11 = 29297;
static const uint64_t IDX_CEN_FBNED11_FBN_DATA_EXP11_LEN = 29298;
static const uint64_t IDX_CEN_FBNED12_FBN_DATA_EXP12 = 29299;
static const uint64_t IDX_CEN_FBNED12_FBN_DATA_EXP12_LEN = 29300;
static const uint64_t IDX_CEN_FBNED13_FBN_DATA_EXP13 = 29301;
static const uint64_t IDX_CEN_FBNED13_FBN_DATA_EXP13_LEN = 29302;
static const uint64_t IDX_CEN_FBNED14_FBN_DATA_EXP14 = 29303;
static const uint64_t IDX_CEN_FBNED14_FBN_DATA_EXP14_LEN = 29304;
static const uint64_t IDX_CEN_FBNED15_FBN_DATA_EXP15 = 29305;
static const uint64_t IDX_CEN_FBNED15_FBN_DATA_EXP15_LEN = 29306;
static const uint64_t IDX_CEN_FBNED2_FBN_DATA_EXP2 = 29307;
static const uint64_t IDX_CEN_FBNED2_FBN_DATA_EXP2_LEN = 29308;
static const uint64_t IDX_CEN_FBNED3_FBN_DATA_EXP3 = 29309;
static const uint64_t IDX_CEN_FBNED3_FBN_DATA_EXP3_LEN = 29310;
static const uint64_t IDX_CEN_FBNED4_FBN_DATA_EXP4 = 29311;
static const uint64_t IDX_CEN_FBNED4_FBN_DATA_EXP4_LEN = 29312;
static const uint64_t IDX_CEN_FBNED5_FBN_DATA_EXP5 = 29313;
static const uint64_t IDX_CEN_FBNED5_FBN_DATA_EXP5_LEN = 29314;
static const uint64_t IDX_CEN_FBNED6_FBN_DATA_EXP6 = 29315;
static const uint64_t IDX_CEN_FBNED6_FBN_DATA_EXP6_LEN = 29316;
static const uint64_t IDX_CEN_FBNED7_FBN_DATA_EXP7 = 29317;
static const uint64_t IDX_CEN_FBNED7_FBN_DATA_EXP7_LEN = 29318;
static const uint64_t IDX_CEN_FBNED8_FBN_DATA_EXP8 = 29319;
static const uint64_t IDX_CEN_FBNED8_FBN_DATA_EXP8_LEN = 29320;
static const uint64_t IDX_CEN_FBNED9_FBN_DATA_EXP9 = 29321;
static const uint64_t IDX_CEN_FBNED9_FBN_DATA_EXP9_LEN = 29322;
static const uint64_t IDX_CEN_FBNEIR_FBN_ERR_CMD_TAG = 29323;
static const uint64_t IDX_CEN_FBNEIR_FBN_ERR_CMD_TAG_LEN = 29324;
static const uint64_t IDX_CEN_FBNEIR_FBN_ERR_DATA_PAT = 29325;
static const uint64_t IDX_CEN_FBNEIR_FBN_ERR_DATA_PAT_LEN = 29326;
static const uint64_t IDX_CEN_FBNEMS_RESERVED_0 = 29327;
static const uint64_t IDX_CEN_FBNEMS_RESERVED_1 = 29328;
static const uint64_t IDX_CEN_FBNEMS_FBIST_IP = 29329;
static const uint64_t IDX_CEN_FBNEMS_FBIST_DONE = 29330;
static const uint64_t IDX_CEN_FBNEMS_FBIST_FAIL = 29331;
static const uint64_t IDX_CEN_FBNEMS_RESERVED_5_31 = 29332;
static const uint64_t IDX_CEN_FBNEMS_RESERVED_5_31_LEN = 29333;
static const uint64_t IDX_CEN_FBNHPC_CFG_FBN_ERR_HANG_PULSE = 29334;
static const uint64_t IDX_CEN_FBNHPC_CFG_FBN_ERR_HANG_PULSE_LEN = 29335;
static const uint64_t IDX_CEN_FBNHPC_CFG_FBN_ERR_HANG_DIS = 29336;
static const uint64_t IDX_CEN_FBNM0_FBN_DS_DATA_MISR = 29337;
static const uint64_t IDX_CEN_FBNM0_FBN_DS_DATA_MISR_LEN = 29338;
static const uint64_t IDX_CEN_FBNM0_FBN_DS_CMD_MISR = 29339;
static const uint64_t IDX_CEN_FBNM0_FBN_DS_CMD_MISR_LEN = 29340;
static const uint64_t IDX_CEN_FBNM0_FBN_US_DATA_MISR = 29341;
static const uint64_t IDX_CEN_FBNM0_FBN_US_DATA_MISR_LEN = 29342;
static const uint64_t IDX_CEN_FBNM1_FBN_US_CMD_MISR = 29343;
static const uint64_t IDX_CEN_FBNM1_FBN_US_CMD_MISR_LEN = 29344;
static const uint64_t IDX_CEN_FBNM1_FBN_DS_ADDR_MISR = 29345;
static const uint64_t IDX_CEN_FBNM1_FBN_DS_ADDR_MISR_LEN = 29346;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0 = 29347;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_LEN = 29348;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_CRSP = 29349;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_CRSP_LEN = 29350;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_AMODE = 29351;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_AMODE_LEN = 29352;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_DPAT = 29353;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_DPAT_LEN = 29354;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_EXORD = 29355;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_IB_FLIP = 29356;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_INV = 29357;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD0_VLD = 29358;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1 = 29359;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_LEN = 29360;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_CRSP = 29361;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_CRSP_LEN = 29362;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_AMODE = 29363;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_AMODE_LEN = 29364;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_DPAT = 29365;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_DPAT_LEN = 29366;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_EXORD = 29367;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_RES = 29368;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_INV = 29369;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD1_VLD = 29370;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2 = 29371;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_LEN = 29372;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_CRSP = 29373;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_CRSP_LEN = 29374;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_AMODE = 29375;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_AMODE_LEN = 29376;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_DPAT = 29377;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_DPAT_LEN = 29378;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_EXORD = 29379;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_RES = 29380;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_INV = 29381;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD2_VLD = 29382;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3 = 29383;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_LEN = 29384;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_CRSP = 29385;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_CRSP_LEN = 29386;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_AMODE = 29387;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_AMODE_LEN = 29388;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_DPAT = 29389;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_DPAT_LEN = 29390;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_EXORD = 29391;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_RES = 29392;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_INV = 29393;
static const uint64_t IDX_CEN_FBNMR0_CFG_FBN_CMD3_VLD = 29394;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4 = 29395;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_LEN = 29396;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_CRSP = 29397;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_CRSP_LEN = 29398;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_AMODE = 29399;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_AMODE_LEN = 29400;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_DPAT = 29401;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_DPAT_LEN = 29402;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_EXORD = 29403;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_RES = 29404;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_INV = 29405;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD4_VLD = 29406;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5 = 29407;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_LEN = 29408;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_CRSP = 29409;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_CRSP_LEN = 29410;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_AMODE = 29411;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_AMODE_LEN = 29412;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_DPAT = 29413;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_DPAT_LEN = 29414;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_EXORD = 29415;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_RES = 29416;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_INV = 29417;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD5_VLD = 29418;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6 = 29419;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_LEN = 29420;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_CRSP = 29421;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_CRSP_LEN = 29422;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_AMODE = 29423;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_AMODE_LEN = 29424;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_DPAT = 29425;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_DPAT_LEN = 29426;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_EXORD = 29427;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_RES = 29428;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_INV = 29429;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD6_VLD = 29430;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7 = 29431;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_LEN = 29432;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_CRSP = 29433;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_CRSP_LEN = 29434;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_AMODE = 29435;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_AMODE_LEN = 29436;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_DPAT = 29437;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_DPAT_LEN = 29438;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_EXORD = 29439;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_RES = 29440;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_INV = 29441;
static const uint64_t IDX_CEN_FBNMR1_CFG_FBN_CMD7_VLD = 29442;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8 = 29443;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_LEN = 29444;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_CRSP = 29445;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_CRSP_LEN = 29446;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_AMODE = 29447;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_AMODE_LEN = 29448;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_DPAT = 29449;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_DPAT_LEN = 29450;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_EXORD = 29451;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_RES = 29452;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_INV = 29453;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD8_VLD = 29454;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9 = 29455;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_LEN = 29456;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_CRSP = 29457;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_CRSP_LEN = 29458;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_AMODE = 29459;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_AMODE_LEN = 29460;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_DPAT = 29461;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_DPAT_LEN = 29462;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_EXORD = 29463;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_RES = 29464;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_INV = 29465;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD9_VLD = 29466;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10 = 29467;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_LEN = 29468;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_CRSP = 29469;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_CRSP_LEN = 29470;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_AMODE = 29471;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_AMODE_LEN = 29472;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_DPAT = 29473;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_DPAT_LEN = 29474;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_EXORD = 29475;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_RES = 29476;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_INV = 29477;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD10_VLD = 29478;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11 = 29479;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_LEN = 29480;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_CRSP = 29481;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_CRSP_LEN = 29482;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_AMODE = 29483;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_AMODE_LEN = 29484;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_DPAT = 29485;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_DPAT_LEN = 29486;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_EXORD = 29487;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_RES = 29488;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_INV = 29489;
static const uint64_t IDX_CEN_FBNMR2_CFG_FBN_CMD11_VLD = 29490;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12 = 29491;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_LEN = 29492;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_CRSP = 29493;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_CRSP_LEN = 29494;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_AMODE = 29495;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_AMODE_LEN = 29496;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_DPAT = 29497;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_DPAT_LEN = 29498;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_EXORD = 29499;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_RES = 29500;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_INV = 29501;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD12_VLD = 29502;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13 = 29503;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_LEN = 29504;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_CRSP = 29505;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_CRSP_LEN = 29506;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_AMODE = 29507;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_AMODE_LEN = 29508;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_DPAT = 29509;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_DPAT_LEN = 29510;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_EXORD = 29511;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_RES = 29512;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_INV = 29513;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD13_VLD = 29514;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14 = 29515;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_LEN = 29516;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_CRSP = 29517;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_CRSP_LEN = 29518;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_AMODE = 29519;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_AMODE_LEN = 29520;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_DPAT = 29521;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_DPAT_LEN = 29522;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_EXORD = 29523;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_RES = 29524;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_INV = 29525;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD14_VLD = 29526;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15 = 29527;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_LEN = 29528;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_CRSP = 29529;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_CRSP_LEN = 29530;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_AMODE = 29531;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_AMODE_LEN = 29532;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_DPAT = 29533;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_DPAT_LEN = 29534;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_EXORD = 29535;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_RES = 29536;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_INV = 29537;
static const uint64_t IDX_CEN_FBNMR3_CFG_FBN_CMD15_VLD = 29538;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16 = 29539;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_LEN = 29540;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_CRSP = 29541;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_CRSP_LEN = 29542;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_AMODE = 29543;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_AMODE_LEN = 29544;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_DPAT = 29545;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_DPAT_LEN = 29546;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_EXORD = 29547;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_RES = 29548;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_INV = 29549;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD16_VLD = 29550;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17 = 29551;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_LEN = 29552;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_CRSP = 29553;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_CRSP_LEN = 29554;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_AMODE = 29555;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_AMODE_LEN = 29556;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_DPAT = 29557;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_DPAT_LEN = 29558;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_EXORD = 29559;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_RES = 29560;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_INV = 29561;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD17_VLD = 29562;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18 = 29563;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_LEN = 29564;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_CRSP = 29565;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_CRSP_LEN = 29566;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_AMODE = 29567;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_AMODE_LEN = 29568;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_DPAT = 29569;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_DPAT_LEN = 29570;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_EXORD = 29571;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_RES = 29572;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_INV = 29573;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD18_VLD = 29574;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19 = 29575;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_LEN = 29576;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_CRSP = 29577;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_CRSP_LEN = 29578;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_AMODE = 29579;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_AMODE_LEN = 29580;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_DPAT = 29581;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_DPAT_LEN = 29582;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_EXORD = 29583;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_RES = 29584;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_INV = 29585;
static const uint64_t IDX_CEN_FBNMR4_CFG_FBN_CMD19_VLD = 29586;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20 = 29587;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_LEN = 29588;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_CRSP = 29589;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_CRSP_LEN = 29590;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_AMODE = 29591;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_AMODE_LEN = 29592;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_DPAT = 29593;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_DPAT_LEN = 29594;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_EXORD = 29595;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_RES = 29596;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_INV = 29597;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD20_VLD = 29598;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21 = 29599;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_LEN = 29600;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_CRSP = 29601;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_CRSP_LEN = 29602;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_AMODE = 29603;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_AMODE_LEN = 29604;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_DPAT = 29605;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_DPAT_LEN = 29606;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_EXORD = 29607;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_RES = 29608;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_INV = 29609;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD21_VLD = 29610;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22 = 29611;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_LEN = 29612;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_CRSP = 29613;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_CRSP_LEN = 29614;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_AMODE = 29615;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_AMODE_LEN = 29616;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_DPAT = 29617;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_DPAT_LEN = 29618;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_EXORD = 29619;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_RES = 29620;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_INV = 29621;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD22_VLD = 29622;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23 = 29623;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_LEN = 29624;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_CRSP = 29625;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_CRSP_LEN = 29626;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_AMODE = 29627;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_AMODE_LEN = 29628;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_DPAT = 29629;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_DPAT_LEN = 29630;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_EXORD = 29631;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_RES = 29632;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_INV = 29633;
static const uint64_t IDX_CEN_FBNMR5_CFG_FBN_CMD23_VLD = 29634;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24 = 29635;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_LEN = 29636;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_CRSP = 29637;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_CRSP_LEN = 29638;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_AMODE = 29639;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_AMODE_LEN = 29640;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_DPAT = 29641;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_DPAT_LEN = 29642;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_EXORD = 29643;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_RES = 29644;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_INV = 29645;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD24_VLD = 29646;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25 = 29647;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_LEN = 29648;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_CRSP = 29649;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_CRSP_LEN = 29650;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_AMODE = 29651;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_AMODE_LEN = 29652;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_DPAT = 29653;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_DPAT_LEN = 29654;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_EXORD = 29655;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_RES = 29656;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_INV = 29657;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD25_VLD = 29658;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26 = 29659;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_LEN = 29660;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_CRSP = 29661;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_CRSP_LEN = 29662;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_AMODE = 29663;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_AMODE_LEN = 29664;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_DPAT = 29665;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_DPAT_LEN = 29666;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_EXORD = 29667;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_RES = 29668;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_INV = 29669;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD26_VLD = 29670;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27 = 29671;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_LEN = 29672;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_CRSP = 29673;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_CRSP_LEN = 29674;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_AMODE = 29675;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_AMODE_LEN = 29676;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_DPAT = 29677;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_DPAT_LEN = 29678;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_EXORD = 29679;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_RES = 29680;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_INV = 29681;
static const uint64_t IDX_CEN_FBNMR6_CFG_FBN_CMD27_VLD = 29682;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28 = 29683;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_LEN = 29684;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_CRSP = 29685;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_CRSP_LEN = 29686;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_AMODE = 29687;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_AMODE_LEN = 29688;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_DPAT = 29689;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_DPAT_LEN = 29690;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_EXORD = 29691;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_RES = 29692;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_INV = 29693;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD28_VLD = 29694;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29 = 29695;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_LEN = 29696;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_CRSP = 29697;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_CRSP_LEN = 29698;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_AMODE = 29699;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_AMODE_LEN = 29700;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_DPAT = 29701;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_DPAT_LEN = 29702;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_EXORD = 29703;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_RES = 29704;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_INV = 29705;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD29_VLD = 29706;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30 = 29707;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_LEN = 29708;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_CRSP = 29709;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_CRSP_LEN = 29710;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_AMODE = 29711;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_AMODE_LEN = 29712;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_DPAT = 29713;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_DPAT_LEN = 29714;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_EXORD = 29715;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_RES = 29716;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_INV = 29717;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD30_VLD = 29718;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31 = 29719;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_LEN = 29720;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_CRSP = 29721;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_CRSP_LEN = 29722;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_AMODE = 29723;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_AMODE_LEN = 29724;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_DPAT = 29725;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_DPAT_LEN = 29726;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_EXORD = 29727;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_RES = 29728;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_INV = 29729;
static const uint64_t IDX_CEN_FBNMR7_CFG_FBN_CMD31_VLD = 29730;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MRANK0 = 29731;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MRANK0_LEN = 29732;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MRANK1 = 29733;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MRANK1_LEN = 29734;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MRANK2 = 29735;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MRANK2_LEN = 29736;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_SRANK0 = 29737;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_SRANK0_LEN = 29738;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_SRANK1 = 29739;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_SRANK1_LEN = 29740;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_SRANK2 = 29741;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_SRANK2_LEN = 29742;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BANK0 = 29743;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BANK0_LEN = 29744;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BANK1 = 29745;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BANK1_LEN = 29746;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BANK2 = 29747;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BANK2_LEN = 29748;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BG0 = 29749;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BG0_LEN = 29750;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BG1 = 29751;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_BG1_LEN = 29752;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_ROW14 = 29753;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_ROW14_LEN = 29754;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_ROW15 = 29755;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_ROW15_LEN = 29756;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_ROW16 = 29757;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_ROW16_LEN = 29758;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MBA = 29759;
static const uint64_t IDX_CEN_FBNPAM0_CFG_FBN_AMAP_MBA_LEN = 29760;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL3 = 29761;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL3_LEN = 29762;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL4 = 29763;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL4_LEN = 29764;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL5 = 29765;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL5_LEN = 29766;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL6 = 29767;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL6_LEN = 29768;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL7 = 29769;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL7_LEN = 29770;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL8 = 29771;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL8_LEN = 29772;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL9 = 29773;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL9_LEN = 29774;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL10 = 29775;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL10_LEN = 29776;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL11 = 29777;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL11_LEN = 29778;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL12 = 29779;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL12_LEN = 29780;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL13 = 29781;
static const uint64_t IDX_CEN_FBNPAM1_CFG_FBN_AMAP_COL13_LEN = 29782;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_MODE = 29783;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_SYS_TYPE = 29784;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_MBA_CHK = 29785;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_CMD_SEQ = 29786;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_CONT_RUN = 29787;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_STOP_ON_ERR = 29788;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_STOP_ON_ADDR = 29789;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_TST_LEN_TYPE = 29790;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_ADDR_CHK = 29791;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_CMD_SPC = 29792;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_DP_TAG_LOC = 29793;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_MEM_TYPE = 29794;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_DS_CRC = 29795;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_US_CRC = 29796;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_DS_CMD_LOC = 29797;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_DS_CMD_LOC_LEN = 29798;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_RST_KEEPER = 29799;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_CACHELINE_CHK = 29800;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_2N_ADDR = 29801;
static const uint64_t IDX_CEN_FBNPARM0_CFG_FBN_MBSXCRQ5 = 29802;
static const uint64_t IDX_CEN_FBNRAER_CFG_FBN_ADDR_RND_END = 29803;
static const uint64_t IDX_CEN_FBNRAER_CFG_FBN_ADDR_RND_END_LEN = 29804;
static const uint64_t IDX_CEN_FBNRAG_CFG_FBN_ADDR_RND_LFSRM = 29805;
static const uint64_t IDX_CEN_FBNRAG_CFG_FBN_ADDR_RND_LFSRM_LEN = 29806;
static const uint64_t IDX_CEN_FBNRAG_CFG_FBN_ADDR_RND_FW = 29807;
static const uint64_t IDX_CEN_FBNRAG_CFG_FBN_ADDR_RND_FW_LEN = 29808;
static const uint64_t IDX_CEN_FBNRAG_CFG_FBN_ADDR_RND_RES = 29809;
static const uint64_t IDX_CEN_FBNRAG_CFG_FBN_ADDR_RND_RES_LEN = 29810;
static const uint64_t IDX_CEN_FBNRAMR_CFG_FBN_ADDR_RND_MASK = 29811;
static const uint64_t IDX_CEN_FBNRAMR_CFG_FBN_ADDR_RND_MASK_LEN = 29812;
static const uint64_t IDX_CEN_FBNRASR_CFG_FBN_ADDR_RND_START = 29813;
static const uint64_t IDX_CEN_FBNRASR_CFG_FBN_ADDR_RND_START_LEN = 29814;
static const uint64_t IDX_CEN_FBNRCCR_CFG_FBN_RCCR_RESERVED0 = 29815;
static const uint64_t IDX_CEN_FBNRCCR_CFG_FBN_RCCR_RESERVED0_LEN = 29816;
static const uint64_t IDX_CEN_FBNRCCR_CFG_FBN_CMD_LOC_SEED = 29817;
static const uint64_t IDX_CEN_FBNRCCR_CFG_FBN_CMD_LOC_SEED_LEN = 29818;
static const uint64_t IDX_CEN_FBNRCCR_CFG_FBN_CMD_CHK_SEED = 29819;
static const uint64_t IDX_CEN_FBNRCCR_CFG_FBN_CMD_CHK_SEED_LEN = 29820;
static const uint64_t IDX_CEN_FBNRCSR_CFG_FBN_CMD_GEN_SEED = 29821;
static const uint64_t IDX_CEN_FBNRCSR_CFG_FBN_CMD_GEN_SEED_LEN = 29822;
static const uint64_t IDX_CEN_FBNRCSR_CFG_FBN_CMD_SEL_SEED = 29823;
static const uint64_t IDX_CEN_FBNRCSR_CFG_FBN_CMD_SEL_SEED_LEN = 29824;
static const uint64_t IDX_CEN_FBNRCSR_CFG_FBN_DATA_PAT_SEED = 29825;
static const uint64_t IDX_CEN_FBNRCSR_CFG_FBN_DATA_PAT_SEED_LEN = 29826;
static const uint64_t IDX_CEN_FBNRD0_FBN_DATA_RX0 = 29827;
static const uint64_t IDX_CEN_FBNRD0_FBN_DATA_RX0_LEN = 29828;
static const uint64_t IDX_CEN_FBNRD1_FBN_DATA_RX1 = 29829;
static const uint64_t IDX_CEN_FBNRD1_FBN_DATA_RX1_LEN = 29830;
static const uint64_t IDX_CEN_FBNRD10_FBN_DATA_RX10 = 29831;
static const uint64_t IDX_CEN_FBNRD10_FBN_DATA_RX10_LEN = 29832;
static const uint64_t IDX_CEN_FBNRD11_FBN_DATA_RX11 = 29833;
static const uint64_t IDX_CEN_FBNRD11_FBN_DATA_RX11_LEN = 29834;
static const uint64_t IDX_CEN_FBNRD12_FBN_DATA_RX12 = 29835;
static const uint64_t IDX_CEN_FBNRD12_FBN_DATA_RX12_LEN = 29836;
static const uint64_t IDX_CEN_FBNRD13_FBN_DATA_RX13 = 29837;
static const uint64_t IDX_CEN_FBNRD13_FBN_DATA_RX13_LEN = 29838;
static const uint64_t IDX_CEN_FBNRD14_FBN_DATA_RX14 = 29839;
static const uint64_t IDX_CEN_FBNRD14_FBN_DATA_RX14_LEN = 29840;
static const uint64_t IDX_CEN_FBNRD15_FBN_DATA_RX15 = 29841;
static const uint64_t IDX_CEN_FBNRD15_FBN_DATA_RX15_LEN = 29842;
static const uint64_t IDX_CEN_FBNRD2_FBN_DATA_RX2 = 29843;
static const uint64_t IDX_CEN_FBNRD2_FBN_DATA_RX2_LEN = 29844;
static const uint64_t IDX_CEN_FBNRD3_FBN_DATA_RX3 = 29845;
static const uint64_t IDX_CEN_FBNRD3_FBN_DATA_RX3_LEN = 29846;
static const uint64_t IDX_CEN_FBNRD4_FBN_DATA_RX4 = 29847;
static const uint64_t IDX_CEN_FBNRD4_FBN_DATA_RX4_LEN = 29848;
static const uint64_t IDX_CEN_FBNRD5_FBN_DATA_RX5 = 29849;
static const uint64_t IDX_CEN_FBNRD5_FBN_DATA_RX5_LEN = 29850;
static const uint64_t IDX_CEN_FBNRD6_FBN_DATA_RX6 = 29851;
static const uint64_t IDX_CEN_FBNRD6_FBN_DATA_RX6_LEN = 29852;
static const uint64_t IDX_CEN_FBNRD7_FBN_DATA_RX7 = 29853;
static const uint64_t IDX_CEN_FBNRD7_FBN_DATA_RX7_LEN = 29854;
static const uint64_t IDX_CEN_FBNRD8_FBN_DATA_RX8 = 29855;
static const uint64_t IDX_CEN_FBNRD8_FBN_DATA_RX8_LEN = 29856;
static const uint64_t IDX_CEN_FBNRD9_FBN_DATA_RX9 = 29857;
static const uint64_t IDX_CEN_FBNRD9_FBN_DATA_RX9_LEN = 29858;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED0 = 29859;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED0_LEN = 29860;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED1 = 29861;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED1_LEN = 29862;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED2 = 29863;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED2_LEN = 29864;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED3 = 29865;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED3_LEN = 29866;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED4 = 29867;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED4_LEN = 29868;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED5 = 29869;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED5_LEN = 29870;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED6 = 29871;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED6_LEN = 29872;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED7 = 29873;
static const uint64_t IDX_CEN_FBNRDSR0_CFG_FBN_DATA_RND_SEED7_LEN = 29874;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEED8 = 29875;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEED8_LEN = 29876;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEED9 = 29877;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEED9_LEN = 29878;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDA = 29879;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDA_LEN = 29880;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDB = 29881;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDB_LEN = 29882;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDC = 29883;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDC_LEN = 29884;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDD = 29885;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDD_LEN = 29886;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDE = 29887;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDE_LEN = 29888;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDF = 29889;
static const uint64_t IDX_CEN_FBNRDSR1_CFG_FBN_DATA_RND_SEEDF_LEN = 29890;
static const uint64_t IDX_CEN_FBNRMWC_CFG_FBN_RMW_FUNC = 29891;
static const uint64_t IDX_CEN_FBNRMWC_CFG_FBN_RMW_FUNC_LEN = 29892;
static const uint64_t IDX_CEN_FBNRMWC_RESERVED_4 = 29893;
static const uint64_t IDX_CEN_FBNRMWC_CFG_FBN_RMW_TSZ = 29894;
static const uint64_t IDX_CEN_FBNRMWC_CFG_FBN_RMW_TSZ_LEN = 29895;
static const uint64_t IDX_CEN_FBNRMWC_RESERVED_12 = 29896;
static const uint64_t IDX_CEN_FBNRMWC_CFG_FBN_RMW_ADDR = 29897;
static const uint64_t IDX_CEN_FBNRMWC_CFG_FBN_RMW_ADDR_LEN = 29898;
static const uint64_t IDX_CEN_FBNRTCTR_FBN_RUN_CNT = 29899;
static const uint64_t IDX_CEN_FBNRTCTR_FBN_RUN_CNT_LEN = 29900;
static const uint64_t IDX_CEN_FBNSAC_CFG_FBN_ADDR_START = 29901;
static const uint64_t IDX_CEN_FBNSAC_CFG_FBN_ADDR_START_LEN = 29902;
static const uint64_t IDX_CEN_FBNTT_CFG_FBN_TEST_TIME = 29903;
static const uint64_t IDX_CEN_FBNTT_CFG_FBN_TEST_TIME_LEN = 29904;
static const uint64_t IDX_CEN_FBNUD0_CFG_FBN_DATA_USR_N = 29905;
static const uint64_t IDX_CEN_FBNUD0_CFG_FBN_DATA_USR_N_LEN = 29906;
static const uint64_t IDX_CEN_FBNUD1_CFG_FBN_DATA_USR_N = 29907;
static const uint64_t IDX_CEN_FBNUD1_CFG_FBN_DATA_USR_N_LEN = 29908;
static const uint64_t IDX_CEN_FBNUD10_CFG_FBN_DATA_USR_N = 29909;
static const uint64_t IDX_CEN_FBNUD10_CFG_FBN_DATA_USR_N_LEN = 29910;
static const uint64_t IDX_CEN_FBNUD11_CFG_FBN_DATA_USR_N = 29911;
static const uint64_t IDX_CEN_FBNUD11_CFG_FBN_DATA_USR_N_LEN = 29912;
static const uint64_t IDX_CEN_FBNUD12_CFG_FBN_DATA_USR_N = 29913;
static const uint64_t IDX_CEN_FBNUD12_CFG_FBN_DATA_USR_N_LEN = 29914;
static const uint64_t IDX_CEN_FBNUD13_CFG_FBN_DATA_USR_N = 29915;
static const uint64_t IDX_CEN_FBNUD13_CFG_FBN_DATA_USR_N_LEN = 29916;
static const uint64_t IDX_CEN_FBNUD14_CFG_FBN_DATA_USR_N = 29917;
static const uint64_t IDX_CEN_FBNUD14_CFG_FBN_DATA_USR_N_LEN = 29918;
static const uint64_t IDX_CEN_FBNUD15_CFG_FBN_DATA_USR_N = 29919;
static const uint64_t IDX_CEN_FBNUD15_CFG_FBN_DATA_USR_N_LEN = 29920;
static const uint64_t IDX_CEN_FBNUD2_CFG_FBN_DATA_USR_N = 29921;
static const uint64_t IDX_CEN_FBNUD2_CFG_FBN_DATA_USR_N_LEN = 29922;
static const uint64_t IDX_CEN_FBNUD3_CFG_FBN_DATA_USR_N = 29923;
static const uint64_t IDX_CEN_FBNUD3_CFG_FBN_DATA_USR_N_LEN = 29924;
static const uint64_t IDX_CEN_FBNUD4_CFG_FBN_DATA_USR_N = 29925;
static const uint64_t IDX_CEN_FBNUD4_CFG_FBN_DATA_USR_N_LEN = 29926;
static const uint64_t IDX_CEN_FBNUD5_CFG_FBN_DATA_USR_N = 29927;
static const uint64_t IDX_CEN_FBNUD5_CFG_FBN_DATA_USR_N_LEN = 29928;
static const uint64_t IDX_CEN_FBNUD6_CFG_FBN_DATA_USR_N = 29929;
static const uint64_t IDX_CEN_FBNUD6_CFG_FBN_DATA_USR_N_LEN = 29930;
static const uint64_t IDX_CEN_FBNUD7_CFG_FBN_DATA_USR_N = 29931;
static const uint64_t IDX_CEN_FBNUD7_CFG_FBN_DATA_USR_N_LEN = 29932;
static const uint64_t IDX_CEN_FBNUD8_CFG_FBN_DATA_USR_N = 29933;
static const uint64_t IDX_CEN_FBNUD8_CFG_FBN_DATA_USR_N_LEN = 29934;
static const uint64_t IDX_CEN_FBNUD9_CFG_FBN_DATA_USR_N = 29935;
static const uint64_t IDX_CEN_FBNUD9_CFG_FBN_DATA_USR_N_LEN = 29936;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_SCOM_UE = 29937;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_USCHK_1HOT = 29938;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_USCHK_DATA_DROP = 29939;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_DGEN_1HOT = 29940;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_CMD_1HOT = 29941;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_CMD_EARLY_RESPONSE = 29942;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_FBIST_FAIL = 29943;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_CMD_HANG = 29944;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_US_CRC_ERR = 29945;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_RESERVED_9_14 = 29946;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_RESERVED_9_14_LEN = 29947;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_INTERNAL_SCOM_ERROR = 29948;
static const uint64_t IDX_CEN_FBN_FIR_ACTION0_REG_INTERNAL_SCOM_ERROR_CLONE = 29949;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_SCOM_UE = 29950;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_USCHK_1HOT = 29951;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_USCHK_DATA_DROP = 29952;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_DGEN_1HOT = 29953;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_CMD_1HOT = 29954;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_CMD_EARLY_RESPONSE = 29955;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_FBIST_FAIL = 29956;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_CMD_HANG = 29957;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_US_CRC_ERR = 29958;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_RESERVED_9_14 = 29959;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_RESERVED_9_14_LEN = 29960;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_INTERNAL_SCOM_ERROR = 29961;
static const uint64_t IDX_CEN_FBN_FIR_ACTION1_REG_INTERNAL_SCOM_ERROR_CLONE = 29962;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_SCOM_UE = 29963;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_USCHK_1HOT = 29964;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_USCHK_DATA_DROP = 29965;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_DGEN_1HOT = 29966;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_CMD_1HOT = 29967;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_CMD_EARLY_RESPONSE = 29968;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_FBIST_FAIL = 29969;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_CMD_HANG = 29970;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_US_CRC_ERR = 29971;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_RESERVED_9_14 = 29972;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_RESERVED_9_14_LEN = 29973;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 29974;
static const uint64_t IDX_CEN_FBN_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 29975;
static const uint64_t IDX_CEN_FBN_FIR_REG_SCOM_UE = 29976;
static const uint64_t IDX_CEN_FBN_FIR_REG_USCHK_1HOT = 29977;
static const uint64_t IDX_CEN_FBN_FIR_REG_USCHK_DATA_DROP = 29978;
static const uint64_t IDX_CEN_FBN_FIR_REG_DGEN_1HOT = 29979;
static const uint64_t IDX_CEN_FBN_FIR_REG_CMD_1HOT = 29980;
static const uint64_t IDX_CEN_FBN_FIR_REG_CMD_EARLY_RESPONSE = 29981;
static const uint64_t IDX_CEN_FBN_FIR_REG_FBIST_FAIL = 29982;
static const uint64_t IDX_CEN_FBN_FIR_REG_CMD_HANG = 29983;
static const uint64_t IDX_CEN_FBN_FIR_REG_US_CRC_ERR = 29984;
static const uint64_t IDX_CEN_FBN_FIR_REG_RESERVED_9_14 = 29985;
static const uint64_t IDX_CEN_FBN_FIR_REG_RESERVED_9_14_LEN = 29986;
static const uint64_t IDX_CEN_FBN_FIR_REG_INTERNAL_SCOM_ERROR = 29987;
static const uint64_t IDX_CEN_FBN_FIR_REG_INTERNAL_SCOM_ERROR_CLONE = 29988;
static const uint64_t IDX_CEN_FBMCRCR_CFG_FBM_CMD_CHK_TAG = 29989;
static const uint64_t IDX_CEN_FBMCRCR_CFG_FBM_CMD_CHK_TAG_LEN = 29990;
static const uint64_t IDX_CEN_FBMDCM0_CFG_FBM_DATA_CMP_MASK0 = 29991;
static const uint64_t IDX_CEN_FBMDCM0_CFG_FBM_DATA_CMP_MASK0_LEN = 29992;
static const uint64_t IDX_CEN_FBMDCM1_CFG_FBM_DATA_CMP_MASK1 = 29993;
static const uint64_t IDX_CEN_FBMDCM1_CFG_FBM_DATA_CMP_MASK1_LEN = 29994;
static const uint64_t IDX_CEN_FBMDCM10_CFG_FBM_DATA_CMP_MASK10 = 29995;
static const uint64_t IDX_CEN_FBMDCM10_CFG_FBM_DATA_CMP_MASK10_LEN = 29996;
static const uint64_t IDX_CEN_FBMDCM11_CFG_FBM_DATA_CMP_MASK11 = 29997;
static const uint64_t IDX_CEN_FBMDCM11_CFG_FBM_DATA_CMP_MASK11_LEN = 29998;
static const uint64_t IDX_CEN_FBMDCM12_CFG_FBM_DATA_CMP_MASK12 = 29999;
static const uint64_t IDX_CEN_FBMDCM12_CFG_FBM_DATA_CMP_MASK12_LEN = 30000;
static const uint64_t IDX_CEN_FBMDCM13_CFG_FBM_DATA_CMP_MASK13 = 30001;
static const uint64_t IDX_CEN_FBMDCM13_CFG_FBM_DATA_CMP_MASK13_LEN = 30002;
static const uint64_t IDX_CEN_FBMDCM14_CFG_FBM_DATA_CMP_MASK14 = 30003;
static const uint64_t IDX_CEN_FBMDCM14_CFG_FBM_DATA_CMP_MASK14_LEN = 30004;
static const uint64_t IDX_CEN_FBMDCM15_CFG_FBM_DATA_CMP_MASK15 = 30005;
static const uint64_t IDX_CEN_FBMDCM15_CFG_FBM_DATA_CMP_MASK15_LEN = 30006;
static const uint64_t IDX_CEN_FBMDCM2_CFG_FBM_DATA_CMP_MASK2 = 30007;
static const uint64_t IDX_CEN_FBMDCM2_CFG_FBM_DATA_CMP_MASK2_LEN = 30008;
static const uint64_t IDX_CEN_FBMDCM3_CFG_FBM_DATA_CMP_MASK3 = 30009;
static const uint64_t IDX_CEN_FBMDCM3_CFG_FBM_DATA_CMP_MASK3_LEN = 30010;
static const uint64_t IDX_CEN_FBMDCM4_CFG_FBM_DATA_CMP_MASK4 = 30011;
static const uint64_t IDX_CEN_FBMDCM4_CFG_FBM_DATA_CMP_MASK4_LEN = 30012;
static const uint64_t IDX_CEN_FBMDCM5_CFG_FBM_DATA_CMP_MASK5 = 30013;
static const uint64_t IDX_CEN_FBMDCM5_CFG_FBM_DATA_CMP_MASK5_LEN = 30014;
static const uint64_t IDX_CEN_FBMDCM6_CFG_FBM_DATA_CMP_MASK6 = 30015;
static const uint64_t IDX_CEN_FBMDCM6_CFG_FBM_DATA_CMP_MASK6_LEN = 30016;
static const uint64_t IDX_CEN_FBMDCM7_CFG_FBM_DATA_CMP_MASK7 = 30017;
static const uint64_t IDX_CEN_FBMDCM7_CFG_FBM_DATA_CMP_MASK7_LEN = 30018;
static const uint64_t IDX_CEN_FBMDCM8_CFG_FBM_DATA_CMP_MASK8 = 30019;
static const uint64_t IDX_CEN_FBMDCM8_CFG_FBM_DATA_CMP_MASK8_LEN = 30020;
static const uint64_t IDX_CEN_FBMDCM9_CFG_FBM_DATA_CMP_MASK9 = 30021;
static const uint64_t IDX_CEN_FBMDCM9_CFG_FBM_DATA_CMP_MASK9_LEN = 30022;
static const uint64_t IDX_CEN_FBMDCR_CFG_FBM_DATA_INV = 30023;
static const uint64_t IDX_CEN_FBMDCR_CFG_FBM_DATA_INV_LEN = 30024;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR0 = 30025;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR0_LEN = 30026;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR1 = 30027;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR1_LEN = 30028;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR2 = 30029;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR2_LEN = 30030;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR3 = 30031;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR3_LEN = 30032;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR4 = 30033;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR4_LEN = 30034;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR5 = 30035;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR5_LEN = 30036;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR6 = 30037;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR6_LEN = 30038;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR7 = 30039;
static const uint64_t IDX_CEN_FBMDMEC0_FBM_ERR_CNTR7_LEN = 30040;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR8 = 30041;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR8_LEN = 30042;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR9 = 30043;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR9_LEN = 30044;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR10 = 30045;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR10_LEN = 30046;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR11 = 30047;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR11_LEN = 30048;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR12 = 30049;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR12_LEN = 30050;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR13 = 30051;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR13_LEN = 30052;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR14 = 30053;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR14_LEN = 30054;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR15 = 30055;
static const uint64_t IDX_CEN_FBMDMEC1_FBM_ERR_CNTR15_LEN = 30056;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR16 = 30057;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR16_LEN = 30058;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR17 = 30059;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR17_LEN = 30060;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR18 = 30061;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR18_LEN = 30062;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR19 = 30063;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR19_LEN = 30064;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR20 = 30065;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR20_LEN = 30066;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR21 = 30067;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR21_LEN = 30068;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR22 = 30069;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR22_LEN = 30070;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR23 = 30071;
static const uint64_t IDX_CEN_FBMDMEC2_FBM_ERR_CNTR23_LEN = 30072;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR24 = 30073;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR24_LEN = 30074;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR25 = 30075;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR25_LEN = 30076;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR26 = 30077;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR26_LEN = 30078;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR27 = 30079;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR27_LEN = 30080;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR28 = 30081;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR28_LEN = 30082;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR29 = 30083;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR29_LEN = 30084;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR30 = 30085;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR30_LEN = 30086;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR31 = 30087;
static const uint64_t IDX_CEN_FBMDMEC3_FBM_ERR_CNTR31_LEN = 30088;
static const uint64_t IDX_CEN_FBMEA_CFG_FBM_ERR_ADDR = 30089;
static const uint64_t IDX_CEN_FBMEA_CFG_FBM_ERR_ADDR_LEN = 30090;
static const uint64_t IDX_CEN_FBMED0_FBM_DATA_EXP0 = 30091;
static const uint64_t IDX_CEN_FBMED0_FBM_DATA_EXP0_LEN = 30092;
static const uint64_t IDX_CEN_FBMED1_FBM_DATA_EXP1 = 30093;
static const uint64_t IDX_CEN_FBMED1_FBM_DATA_EXP1_LEN = 30094;
static const uint64_t IDX_CEN_FBMED10_FBM_DATA_EXP10 = 30095;
static const uint64_t IDX_CEN_FBMED10_FBM_DATA_EXP10_LEN = 30096;
static const uint64_t IDX_CEN_FBMED11_FBM_DATA_EXP11 = 30097;
static const uint64_t IDX_CEN_FBMED11_FBM_DATA_EXP11_LEN = 30098;
static const uint64_t IDX_CEN_FBMED12_FBM_DATA_EXP12 = 30099;
static const uint64_t IDX_CEN_FBMED12_FBM_DATA_EXP12_LEN = 30100;
static const uint64_t IDX_CEN_FBMED13_FBM_DATA_EXP13 = 30101;
static const uint64_t IDX_CEN_FBMED13_FBM_DATA_EXP13_LEN = 30102;
static const uint64_t IDX_CEN_FBMED14_FBM_DATA_EXP14 = 30103;
static const uint64_t IDX_CEN_FBMED14_FBM_DATA_EXP14_LEN = 30104;
static const uint64_t IDX_CEN_FBMED15_FBM_DATA_EXP15 = 30105;
static const uint64_t IDX_CEN_FBMED15_FBM_DATA_EXP15_LEN = 30106;
static const uint64_t IDX_CEN_FBMED2_FBM_DATA_EXP2 = 30107;
static const uint64_t IDX_CEN_FBMED2_FBM_DATA_EXP2_LEN = 30108;
static const uint64_t IDX_CEN_FBMED3_FBM_DATA_EXP3 = 30109;
static const uint64_t IDX_CEN_FBMED3_FBM_DATA_EXP3_LEN = 30110;
static const uint64_t IDX_CEN_FBMED4_FBM_DATA_EXP4 = 30111;
static const uint64_t IDX_CEN_FBMED4_FBM_DATA_EXP4_LEN = 30112;
static const uint64_t IDX_CEN_FBMED5_FBM_DATA_EXP5 = 30113;
static const uint64_t IDX_CEN_FBMED5_FBM_DATA_EXP5_LEN = 30114;
static const uint64_t IDX_CEN_FBMED6_FBM_DATA_EXP6 = 30115;
static const uint64_t IDX_CEN_FBMED6_FBM_DATA_EXP6_LEN = 30116;
static const uint64_t IDX_CEN_FBMED7_FBM_DATA_EXP7 = 30117;
static const uint64_t IDX_CEN_FBMED7_FBM_DATA_EXP7_LEN = 30118;
static const uint64_t IDX_CEN_FBMED8_FBM_DATA_EXP8 = 30119;
static const uint64_t IDX_CEN_FBMED8_FBM_DATA_EXP8_LEN = 30120;
static const uint64_t IDX_CEN_FBMED9_FBM_DATA_EXP9 = 30121;
static const uint64_t IDX_CEN_FBMED9_FBM_DATA_EXP9_LEN = 30122;
static const uint64_t IDX_CEN_FBMEIR_FBM_ERR_CMD_TAG = 30123;
static const uint64_t IDX_CEN_FBMEIR_FBM_ERR_CMD_TAG_LEN = 30124;
static const uint64_t IDX_CEN_FBMEIR_FBM_ERR_DATA_PAT = 30125;
static const uint64_t IDX_CEN_FBMEIR_FBM_ERR_DATA_PAT_LEN = 30126;
static const uint64_t IDX_CEN_FBMM0_FBM_DS_DATA_MISR = 30127;
static const uint64_t IDX_CEN_FBMM0_FBM_DS_DATA_MISR_LEN = 30128;
static const uint64_t IDX_CEN_FBMM0_FBM_DS_CMD_MISR = 30129;
static const uint64_t IDX_CEN_FBMM0_FBM_DS_CMD_MISR_LEN = 30130;
static const uint64_t IDX_CEN_FBMM0_FBM_DS_ADDR_MISR = 30131;
static const uint64_t IDX_CEN_FBMM0_FBM_DS_ADDR_MISR_LEN = 30132;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR0 = 30133;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR0_LEN = 30134;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR1 = 30135;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR1_LEN = 30136;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR2 = 30137;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR2_LEN = 30138;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR3 = 30139;
static const uint64_t IDX_CEN_FBMM1_FBM_US_DATA_MISR3_LEN = 30140;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S0 = 30141;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S0_LEN = 30142;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S1 = 30143;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S1_LEN = 30144;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S2 = 30145;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S2_LEN = 30146;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S3 = 30147;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M0S3_LEN = 30148;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S0 = 30149;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S0_LEN = 30150;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S1 = 30151;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S1_LEN = 30152;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S2 = 30153;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S2_LEN = 30154;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S3 = 30155;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M1S3_LEN = 30156;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M2S0 = 30157;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M2S0_LEN = 30158;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M3S0 = 30159;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_M3S0_LEN = 30160;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_MEM_TYPE = 30161;
static const uint64_t IDX_CEN_FBMMC0_CFG_FBM_MEM_TYPE_LEN = 30162;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0 = 30163;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_LEN = 30164;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_CRSP = 30165;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_CRSP_LEN = 30166;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_AMODE = 30167;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_AMODE_LEN = 30168;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_DPAT = 30169;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_DPAT_LEN = 30170;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_EXORD = 30171;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_RES = 30172;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_INV = 30173;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD0_VLD = 30174;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1 = 30175;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_LEN = 30176;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_CRSP = 30177;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_CRSP_LEN = 30178;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_AMODE = 30179;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_AMODE_LEN = 30180;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_DPAT = 30181;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_DPAT_LEN = 30182;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_EXORD = 30183;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_RES = 30184;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_INV = 30185;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD1_VLD = 30186;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2 = 30187;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_LEN = 30188;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_CRSP = 30189;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_CRSP_LEN = 30190;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_AMODE = 30191;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_AMODE_LEN = 30192;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_DPAT = 30193;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_DPAT_LEN = 30194;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_EXORD = 30195;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_RES = 30196;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_INV = 30197;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD2_VLD = 30198;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3 = 30199;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_LEN = 30200;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_CRSP = 30201;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_CRSP_LEN = 30202;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_AMODE = 30203;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_AMODE_LEN = 30204;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_DPAT = 30205;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_DPAT_LEN = 30206;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_EXORD = 30207;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_RES = 30208;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_INV = 30209;
static const uint64_t IDX_CEN_FBMMR0_CFG_FBM_CMD3_VLD = 30210;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4 = 30211;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_LEN = 30212;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_CRSP = 30213;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_CRSP_LEN = 30214;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_AMODE = 30215;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_AMODE_LEN = 30216;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_DPAT = 30217;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_DPAT_LEN = 30218;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_EXORD = 30219;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_RES = 30220;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_INV = 30221;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD4_VLD = 30222;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5 = 30223;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_LEN = 30224;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_CRSP = 30225;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_CRSP_LEN = 30226;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_AMODE = 30227;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_AMODE_LEN = 30228;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_DPAT = 30229;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_DPAT_LEN = 30230;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_EXORD = 30231;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_RES = 30232;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_INV = 30233;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD5_VLD = 30234;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6 = 30235;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_LEN = 30236;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_CRSP = 30237;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_CRSP_LEN = 30238;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_AMODE = 30239;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_AMODE_LEN = 30240;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_DPAT = 30241;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_DPAT_LEN = 30242;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_EXORD = 30243;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_RES = 30244;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_INV = 30245;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD6_VLD = 30246;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7 = 30247;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_LEN = 30248;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_CRSP = 30249;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_CRSP_LEN = 30250;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_AMODE = 30251;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_AMODE_LEN = 30252;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_DPAT = 30253;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_DPAT_LEN = 30254;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_EXORD = 30255;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_RES = 30256;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_INV = 30257;
static const uint64_t IDX_CEN_FBMMR1_CFG_FBM_CMD7_VLD = 30258;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8 = 30259;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_LEN = 30260;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_CRSP = 30261;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_CRSP_LEN = 30262;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_AMODE = 30263;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_AMODE_LEN = 30264;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_DPAT = 30265;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_DPAT_LEN = 30266;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_EXORD = 30267;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_RES = 30268;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_INV = 30269;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD8_VLD = 30270;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9 = 30271;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_LEN = 30272;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_CRSP = 30273;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_CRSP_LEN = 30274;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_AMODE = 30275;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_AMODE_LEN = 30276;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_DPAT = 30277;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_DPAT_LEN = 30278;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_EXORD = 30279;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_RES = 30280;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_INV = 30281;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD9_VLD = 30282;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10 = 30283;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_LEN = 30284;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_CRSP = 30285;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_CRSP_LEN = 30286;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_AMODE = 30287;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_AMODE_LEN = 30288;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_DPAT = 30289;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_DPAT_LEN = 30290;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_EXORD = 30291;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_RES = 30292;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_INV = 30293;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD10_VLD = 30294;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11 = 30295;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_LEN = 30296;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_CRSP = 30297;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_CRSP_LEN = 30298;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_AMODE = 30299;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_AMODE_LEN = 30300;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_DPAT = 30301;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_DPAT_LEN = 30302;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_EXORD = 30303;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_RES = 30304;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_INV = 30305;
static const uint64_t IDX_CEN_FBMMR2_CFG_FBM_CMD11_VLD = 30306;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12 = 30307;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_LEN = 30308;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_CRSP = 30309;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_CRSP_LEN = 30310;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_AMODE = 30311;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_AMODE_LEN = 30312;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_DPAT = 30313;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_DPAT_LEN = 30314;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_EXORD = 30315;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_RES = 30316;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_INV = 30317;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD12_VLD = 30318;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13 = 30319;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_LEN = 30320;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_CRSP = 30321;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_CRSP_LEN = 30322;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_AMODE = 30323;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_AMODE_LEN = 30324;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_DPAT = 30325;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_DPAT_LEN = 30326;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_EXORD = 30327;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_RES = 30328;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_INV = 30329;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD13_VLD = 30330;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14 = 30331;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_LEN = 30332;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_CRSP = 30333;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_CRSP_LEN = 30334;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_AMODE = 30335;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_AMODE_LEN = 30336;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_DPAT = 30337;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_DPAT_LEN = 30338;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_EXORD = 30339;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_RES = 30340;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_INV = 30341;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD14_VLD = 30342;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15 = 30343;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_LEN = 30344;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_CRSP = 30345;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_CRSP_LEN = 30346;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_AMODE = 30347;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_AMODE_LEN = 30348;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_DPAT = 30349;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_DPAT_LEN = 30350;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_EXORD = 30351;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_RES = 30352;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_INV = 30353;
static const uint64_t IDX_CEN_FBMMR3_CFG_FBM_CMD15_VLD = 30354;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16 = 30355;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_LEN = 30356;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_CRSP = 30357;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_CRSP_LEN = 30358;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_AMODE = 30359;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_AMODE_LEN = 30360;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_DPAT = 30361;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_DPAT_LEN = 30362;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_EXORD = 30363;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_RES = 30364;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_INV = 30365;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD16_VLD = 30366;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17 = 30367;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_LEN = 30368;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_CRSP = 30369;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_CRSP_LEN = 30370;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_AMODE = 30371;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_AMODE_LEN = 30372;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_DPAT = 30373;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_DPAT_LEN = 30374;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_EXORD = 30375;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_RES = 30376;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_INV = 30377;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD17_VLD = 30378;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18 = 30379;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_LEN = 30380;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_CRSP = 30381;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_CRSP_LEN = 30382;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_AMODE = 30383;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_AMODE_LEN = 30384;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_DPAT = 30385;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_DPAT_LEN = 30386;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_EXORD = 30387;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_RES = 30388;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_INV = 30389;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD18_VLD = 30390;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19 = 30391;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_LEN = 30392;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_CRSP = 30393;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_CRSP_LEN = 30394;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_AMODE = 30395;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_AMODE_LEN = 30396;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_DPAT = 30397;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_DPAT_LEN = 30398;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_EXORD = 30399;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_RES = 30400;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_INV = 30401;
static const uint64_t IDX_CEN_FBMMR4_CFG_FBM_CMD19_VLD = 30402;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20 = 30403;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_LEN = 30404;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_CRSP = 30405;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_CRSP_LEN = 30406;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_AMODE = 30407;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_AMODE_LEN = 30408;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_DPAT = 30409;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_DPAT_LEN = 30410;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_EXORD = 30411;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_RES = 30412;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_INV = 30413;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD20_VLD = 30414;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21 = 30415;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_LEN = 30416;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_CRSP = 30417;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_CRSP_LEN = 30418;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_AMODE = 30419;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_AMODE_LEN = 30420;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_DPAT = 30421;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_DPAT_LEN = 30422;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_EXORD = 30423;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_RES = 30424;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_INV = 30425;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD21_VLD = 30426;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22 = 30427;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_LEN = 30428;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_CRSP = 30429;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_CRSP_LEN = 30430;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_AMODE = 30431;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_AMODE_LEN = 30432;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_DPAT = 30433;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_DPAT_LEN = 30434;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_EXORD = 30435;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_RES = 30436;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_INV = 30437;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD22_VLD = 30438;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23 = 30439;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_LEN = 30440;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_CRSP = 30441;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_CRSP_LEN = 30442;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_AMODE = 30443;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_AMODE_LEN = 30444;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_DPAT = 30445;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_DPAT_LEN = 30446;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_EXORD = 30447;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_RES = 30448;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_INV = 30449;
static const uint64_t IDX_CEN_FBMMR5_CFG_FBM_CMD23_VLD = 30450;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24 = 30451;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_LEN = 30452;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_CRSP = 30453;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_CRSP_LEN = 30454;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_AMODE = 30455;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_AMODE_LEN = 30456;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_DPAT = 30457;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_DPAT_LEN = 30458;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_EXORD = 30459;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_RES = 30460;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_INV = 30461;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD24_VLD = 30462;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25 = 30463;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_LEN = 30464;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_CRSP = 30465;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_CRSP_LEN = 30466;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_AMODE = 30467;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_AMODE_LEN = 30468;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_DPAT = 30469;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_DPAT_LEN = 30470;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_EXORD = 30471;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_RES = 30472;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_INV = 30473;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD25_VLD = 30474;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26 = 30475;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_LEN = 30476;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_CRSP = 30477;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_CRSP_LEN = 30478;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_AMODE = 30479;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_AMODE_LEN = 30480;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_DPAT = 30481;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_DPAT_LEN = 30482;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_EXORD = 30483;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_RES = 30484;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_INV = 30485;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD26_VLD = 30486;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27 = 30487;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_LEN = 30488;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_CRSP = 30489;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_CRSP_LEN = 30490;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_AMODE = 30491;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_AMODE_LEN = 30492;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_DPAT = 30493;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_DPAT_LEN = 30494;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_EXORD = 30495;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_RES = 30496;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_INV = 30497;
static const uint64_t IDX_CEN_FBMMR6_CFG_FBM_CMD27_VLD = 30498;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28 = 30499;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_LEN = 30500;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_CRSP = 30501;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_CRSP_LEN = 30502;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_AMODE = 30503;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_AMODE_LEN = 30504;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_DPAT = 30505;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_DPAT_LEN = 30506;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_EXORD = 30507;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_RES = 30508;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_INV = 30509;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD28_VLD = 30510;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29 = 30511;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_LEN = 30512;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_CRSP = 30513;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_CRSP_LEN = 30514;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_AMODE = 30515;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_AMODE_LEN = 30516;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_DPAT = 30517;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_DPAT_LEN = 30518;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_EXORD = 30519;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_RES = 30520;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_INV = 30521;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD29_VLD = 30522;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30 = 30523;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_LEN = 30524;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_CRSP = 30525;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_CRSP_LEN = 30526;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_AMODE = 30527;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_AMODE_LEN = 30528;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_DPAT = 30529;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_DPAT_LEN = 30530;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_EXORD = 30531;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_RES = 30532;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_INV = 30533;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD30_VLD = 30534;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31 = 30535;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_LEN = 30536;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_CRSP = 30537;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_CRSP_LEN = 30538;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_AMODE = 30539;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_AMODE_LEN = 30540;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_DPAT = 30541;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_DPAT_LEN = 30542;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_EXORD = 30543;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_RES = 30544;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_INV = 30545;
static const uint64_t IDX_CEN_FBMMR7_CFG_FBM_CMD31_VLD = 30546;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_MODE = 30547;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_SYS_TYPE = 30548;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_MBA_CHK = 30549;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_US_MUX_SEL = 30550;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_DDR_MODE_OVRD = 30551;
static const uint64_t IDX_CEN_FBMPARM0_RESERVED_5_7 = 30552;
static const uint64_t IDX_CEN_FBMPARM0_RESERVED_5_7_LEN = 30553;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_ADDR_CHK = 30554;
static const uint64_t IDX_CEN_FBMPARM0_RESERVED_9 = 30555;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_DP_TAG_LOC = 30556;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_DDR4 = 30557;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_DS_CRC = 30558;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_US_CRC = 30559;
static const uint64_t IDX_CEN_FBMPARM0_RESERVED_14_15 = 30560;
static const uint64_t IDX_CEN_FBMPARM0_RESERVED_14_15_LEN = 30561;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_RST_KEEPER = 30562;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_CACHELINE_CHK = 30563;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBM_2N_ADDR = 30564;
static const uint64_t IDX_CEN_FBMPARM0_CFG_FBN_MBSXCRQ5 = 30565;
static const uint64_t IDX_CEN_FBMRD0_FBM_DATA_RX0 = 30566;
static const uint64_t IDX_CEN_FBMRD0_FBM_DATA_RX0_LEN = 30567;
static const uint64_t IDX_CEN_FBMRD1_FBM_DATA_RX1 = 30568;
static const uint64_t IDX_CEN_FBMRD1_FBM_DATA_RX1_LEN = 30569;
static const uint64_t IDX_CEN_FBMRD10_FBM_DATA_RX10 = 30570;
static const uint64_t IDX_CEN_FBMRD10_FBM_DATA_RX10_LEN = 30571;
static const uint64_t IDX_CEN_FBMRD11_FBM_DATA_RX11 = 30572;
static const uint64_t IDX_CEN_FBMRD11_FBM_DATA_RX11_LEN = 30573;
static const uint64_t IDX_CEN_FBMRD12_FBM_DATA_RX12 = 30574;
static const uint64_t IDX_CEN_FBMRD12_FBM_DATA_RX12_LEN = 30575;
static const uint64_t IDX_CEN_FBMRD13_FBM_DATA_RX13 = 30576;
static const uint64_t IDX_CEN_FBMRD13_FBM_DATA_RX13_LEN = 30577;
static const uint64_t IDX_CEN_FBMRD14_FBM_DATA_RX14 = 30578;
static const uint64_t IDX_CEN_FBMRD14_FBM_DATA_RX14_LEN = 30579;
static const uint64_t IDX_CEN_FBMRD15_FBM_DATA_RX15 = 30580;
static const uint64_t IDX_CEN_FBMRD15_FBM_DATA_RX15_LEN = 30581;
static const uint64_t IDX_CEN_FBMRD2_FBM_DATA_RX2 = 30582;
static const uint64_t IDX_CEN_FBMRD2_FBM_DATA_RX2_LEN = 30583;
static const uint64_t IDX_CEN_FBMRD3_FBM_DATA_RX3 = 30584;
static const uint64_t IDX_CEN_FBMRD3_FBM_DATA_RX3_LEN = 30585;
static const uint64_t IDX_CEN_FBMRD4_FBM_DATA_RX4 = 30586;
static const uint64_t IDX_CEN_FBMRD4_FBM_DATA_RX4_LEN = 30587;
static const uint64_t IDX_CEN_FBMRD5_FBM_DATA_RX5 = 30588;
static const uint64_t IDX_CEN_FBMRD5_FBM_DATA_RX5_LEN = 30589;
static const uint64_t IDX_CEN_FBMRD6_FBM_DATA_RX6 = 30590;
static const uint64_t IDX_CEN_FBMRD6_FBM_DATA_RX6_LEN = 30591;
static const uint64_t IDX_CEN_FBMRD7_FBM_DATA_RX7 = 30592;
static const uint64_t IDX_CEN_FBMRD7_FBM_DATA_RX7_LEN = 30593;
static const uint64_t IDX_CEN_FBMRD8_FBM_DATA_RX8 = 30594;
static const uint64_t IDX_CEN_FBMRD8_FBM_DATA_RX8_LEN = 30595;
static const uint64_t IDX_CEN_FBMRD9_FBM_DATA_RX9 = 30596;
static const uint64_t IDX_CEN_FBMRD9_FBM_DATA_RX9_LEN = 30597;
static const uint64_t IDX_CEN_FBMRDDR_CFG_FBM_DATA_RD_DLY = 30598;
static const uint64_t IDX_CEN_FBMRDDR_CFG_FBM_DATA_RD_DLY_LEN = 30599;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED0 = 30600;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED0_LEN = 30601;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED1 = 30602;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED1_LEN = 30603;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED2 = 30604;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED2_LEN = 30605;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED3 = 30606;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED3_LEN = 30607;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED4 = 30608;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED4_LEN = 30609;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED5 = 30610;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED5_LEN = 30611;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED6 = 30612;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED6_LEN = 30613;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED7 = 30614;
static const uint64_t IDX_CEN_FBMRDSR0_CFG_FBM_DATA_RND_SEED7_LEN = 30615;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEED8 = 30616;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEED8_LEN = 30617;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEED9 = 30618;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEED9_LEN = 30619;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDA = 30620;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDA_LEN = 30621;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDB = 30622;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDB_LEN = 30623;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDC = 30624;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDC_LEN = 30625;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDD = 30626;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDD_LEN = 30627;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDE = 30628;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDE_LEN = 30629;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDF = 30630;
static const uint64_t IDX_CEN_FBMRDSR1_CFG_FBM_DATA_RND_SEEDF_LEN = 30631;
static const uint64_t IDX_CEN_FBMRMWC_CFG_FBM_RMW_FUNC = 30632;
static const uint64_t IDX_CEN_FBMRMWC_CFG_FBM_RMW_FUNC_LEN = 30633;
static const uint64_t IDX_CEN_FBMRMWC_RESERVED_4 = 30634;
static const uint64_t IDX_CEN_FBMRMWC_CFG_FBM_RMW_TSZ = 30635;
static const uint64_t IDX_CEN_FBMRMWC_CFG_FBM_RMW_TSZ_LEN = 30636;
static const uint64_t IDX_CEN_FBMRMWC_RESERVED_12 = 30637;
static const uint64_t IDX_CEN_FBMRMWC_CFG_FBM_RMW_ADDR = 30638;
static const uint64_t IDX_CEN_FBMRMWC_CFG_FBM_RMW_ADDR_LEN = 30639;
static const uint64_t IDX_CEN_FBMUD0_CFG_FBM_DATA_USR_N = 30640;
static const uint64_t IDX_CEN_FBMUD0_CFG_FBM_DATA_USR_N_LEN = 30641;
static const uint64_t IDX_CEN_FBMUD1_CFG_FBM_DATA_USR_N = 30642;
static const uint64_t IDX_CEN_FBMUD1_CFG_FBM_DATA_USR_N_LEN = 30643;
static const uint64_t IDX_CEN_FBMUD10_CFG_FBM_DATA_USR_N = 30644;
static const uint64_t IDX_CEN_FBMUD10_CFG_FBM_DATA_USR_N_LEN = 30645;
static const uint64_t IDX_CEN_FBMUD11_CFG_FBM_DATA_USR_N = 30646;
static const uint64_t IDX_CEN_FBMUD11_CFG_FBM_DATA_USR_N_LEN = 30647;
static const uint64_t IDX_CEN_FBMUD12_CFG_FBM_DATA_USR_N = 30648;
static const uint64_t IDX_CEN_FBMUD12_CFG_FBM_DATA_USR_N_LEN = 30649;
static const uint64_t IDX_CEN_FBMUD13_CFG_FBM_DATA_USR_N = 30650;
static const uint64_t IDX_CEN_FBMUD13_CFG_FBM_DATA_USR_N_LEN = 30651;
static const uint64_t IDX_CEN_FBMUD14_CFG_FBM_DATA_USR_N = 30652;
static const uint64_t IDX_CEN_FBMUD14_CFG_FBM_DATA_USR_N_LEN = 30653;
static const uint64_t IDX_CEN_FBMUD15_CFG_FBM_DATA_USR_N = 30654;
static const uint64_t IDX_CEN_FBMUD15_CFG_FBM_DATA_USR_N_LEN = 30655;
static const uint64_t IDX_CEN_FBMUD2_CFG_FBM_DATA_USR_N = 30656;
static const uint64_t IDX_CEN_FBMUD2_CFG_FBM_DATA_USR_N_LEN = 30657;
static const uint64_t IDX_CEN_FBMUD3_CFG_FBM_DATA_USR_N = 30658;
static const uint64_t IDX_CEN_FBMUD3_CFG_FBM_DATA_USR_N_LEN = 30659;
static const uint64_t IDX_CEN_FBMUD4_CFG_FBM_DATA_USR_N = 30660;
static const uint64_t IDX_CEN_FBMUD4_CFG_FBM_DATA_USR_N_LEN = 30661;
static const uint64_t IDX_CEN_FBMUD5_CFG_FBM_DATA_USR_N = 30662;
static const uint64_t IDX_CEN_FBMUD5_CFG_FBM_DATA_USR_N_LEN = 30663;
static const uint64_t IDX_CEN_FBMUD6_CFG_FBM_DATA_USR_N = 30664;
static const uint64_t IDX_CEN_FBMUD6_CFG_FBM_DATA_USR_N_LEN = 30665;
static const uint64_t IDX_CEN_FBMUD7_CFG_FBM_DATA_USR_N = 30666;
static const uint64_t IDX_CEN_FBMUD7_CFG_FBM_DATA_USR_N_LEN = 30667;
static const uint64_t IDX_CEN_FBMUD8_CFG_FBM_DATA_USR_N = 30668;
static const uint64_t IDX_CEN_FBMUD8_CFG_FBM_DATA_USR_N_LEN = 30669;
static const uint64_t IDX_CEN_FBMUD9_CFG_FBM_DATA_USR_N = 30670;
static const uint64_t IDX_CEN_FBMUD9_CFG_FBM_DATA_USR_N_LEN = 30671;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_SCOM_UE = 30672;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_CMD_CHK_1HOT = 30673;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_DS_DATA_DROP = 30674;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_DGEN_1HOT = 30675;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_DGEN_RD_DATA_DROP = 30676;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_RESERVED_5_14 = 30677;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_RESERVED_5_14_LEN = 30678;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_INTERNAL_SCOM_ERROR = 30679;
static const uint64_t IDX_CEN_FBM_FIR_ACTION0_REG_INTERNAL_SCOM_ERROR_CLONE = 30680;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_SCOM_UE = 30681;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_CMD_CHK_1HOT = 30682;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_DS_DATA_DROP = 30683;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_DGEN_1HOT = 30684;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_DGEN_RD_DATA_DROP = 30685;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_RESERVED_5_14 = 30686;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_RESERVED_5_14_LEN = 30687;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_INTERNAL_SCOM_ERROR = 30688;
static const uint64_t IDX_CEN_FBM_FIR_ACTION1_REG_INTERNAL_SCOM_ERROR_CLONE = 30689;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_SCOM_UE = 30690;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_CMD_CHK_1HOT = 30691;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_DS_DATA_DROP = 30692;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_DGEN_1HOT = 30693;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_DGEN_RD_DATA_DROP = 30694;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_RESERVED_5_14 = 30695;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_RESERVED_5_14_LEN = 30696;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 30697;
static const uint64_t IDX_CEN_FBM_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 30698;
static const uint64_t IDX_CEN_FBM_FIR_REG_SCOM_UE = 30699;
static const uint64_t IDX_CEN_FBM_FIR_REG_CMD_CHK_1HOT = 30700;
static const uint64_t IDX_CEN_FBM_FIR_REG_DS_DATA_DROP = 30701;
static const uint64_t IDX_CEN_FBM_FIR_REG_DGEN_1HOT = 30702;
static const uint64_t IDX_CEN_FBM_FIR_REG_DGEN_RD_DATA_DROP = 30703;
static const uint64_t IDX_CEN_FBM_FIR_REG_RESERVED_5_14 = 30704;
static const uint64_t IDX_CEN_FBM_FIR_REG_RESERVED_5_14_LEN = 30705;
static const uint64_t IDX_CEN_FBM_FIR_REG_INTERNAL_SCOM_ERROR = 30706;
static const uint64_t IDX_CEN_FBM_FIR_REG_INTERNAL_SCOM_ERROR_CLONE = 30707;
#endif
