From d11796515369999cf5bf26da48798c94de59c16d Mon Sep 17 00:00:00 2001 From: Greg Still Date: Tue, 3 Jul 2018 08:56:28 -0500 Subject: SMF: SBE updates for SMF (URMOR set and CPMMR[Runtime Wakeup Mode] clear) - set URMOR if MSR[S] bit is set in p9_sbe_load_bootloader - clear CPMMR[Runtime Wakeup Mode] in all cores in p9_sbe_select_ex to ensure Hostboot starts from known state Change-Id: I572a1d9e0ebf8e194c811e2b8c176d145b7361e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61812 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-by: Prem Shanker Jha Reviewed-by: Jennifer A. Stofer --- import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index 0a485a72..13509e17 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -168,6 +168,8 @@ enum PM_CPPM_CSAR_DEFS enum PM_PPM_FW_FLAGS { CPPM_CPMMR_DISABLE_PERIODIC_CORE_QUIESCE = 2, + CPPM_CPMMR_RUNTIME_WAKEUP_MODE = 3, + CPPM_CPMMR_WAKEUP_ERROR_INJECT_MODE = 8, QPPM_QCCR_IGNORE_QUAD_STOP_EXITS = 10, QPPM_QCCR_IGNORE_QUAD_STOP_ENTRIES = 11 }; -- cgit v1.2.3