From 710c0dedd21f7f46477e8bc328228834945eedf2 Mon Sep 17 00:00:00 2001 From: Rahul Batra Date: Wed, 24 May 2017 20:22:55 -0500 Subject: PSTATE: PGPE updates for new slopes set and Pstates Table fix - Updates PGPE to use new slopes calculation - Fixes Pstates Table generation to use correct slope set Change-Id: I07389e89c58b3c942a6b704ccece1b94ea9101fa HW-Image-Prereq: Ic79ed4d0311c46612d68d6dffdabc459ec88d8e1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40955 Tested-by: Jenkins Server Reviewed-by: Juan R. Medina Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: Gregory S. Still --- .../pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c | 16 ++++++---------- .../ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c | 21 +++++++++------------ .../ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h | 10 +--------- .../ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c | 7 +++---- 4 files changed, 19 insertions(+), 35 deletions(-) diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c index 2d89aa35..faf542c2 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c @@ -105,11 +105,10 @@ void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* g { gpi->raw_pstates[p].pstate = p; gpi->raw_pstates[p].frequency_mhz = (gppb->reference_frequency_khz - freq_khz_offset) / 1000; - gpi->raw_pstates[p].external_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_SYSP, VPD_SLOPES_RAW); - gpi->raw_pstates[p].effective_vdd_mv = gpi->raw_pstates[p].external_vdd_mv; + gpi->raw_pstates[p].external_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_SYSP); + gpi->raw_pstates[p].effective_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_RAW); gpi->raw_pstates[p].effective_regulation_vdd_mv = gpi->raw_pstates[p].external_vdd_mv + gppb->ivrm.deadzone_mv; - - gpi->raw_pstates[p].internal_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_RAW, VPD_SLOPES_RAW); + gpi->raw_pstates[p].internal_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_RAW); gpi->raw_pstates[p].internal_vid = (gpi->raw_pstates[p].internal_vdd_mv - 512) >> 4; gpi->raw_pstates[p].vdm_mv = 0; gpi->raw_pstates[p].vdm_vid = 0; @@ -136,14 +135,11 @@ void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo { gpi->biased_pstates[p].pstate = p; gpi->biased_pstates[p].frequency_mhz = (G_gpi.pstate0_frequency_khz - freq_khz_offset) / 1000; - gpi->biased_pstates[p].external_vdd_mv = (uint16_t)(p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_BIASED_SYSP, - VPD_SLOPES_BIASED)); - gpi->biased_pstates[p].effective_vdd_mv = gpi->biased_pstates[p].external_vdd_mv; + gpi->biased_pstates[p].external_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_BIASED_SYSP); + gpi->biased_pstates[p].effective_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_BIASED); gpi->biased_pstates[p].effective_regulation_vdd_mv = (uint16_t)(gpi->biased_pstates[p].external_vdd_mv + gppb->ivrm.deadzone_mv); - - gpi->biased_pstates[p].internal_vdd_mv = (uint16_t)(p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_BIASED, - VPD_SLOPES_BIASED)); + gpi->biased_pstates[p].internal_vdd_mv = p9_pgpe_gppb_intp_vdd_from_ps(p, VPD_PT_SET_BIASED); gpi->biased_pstates[p].internal_vid = (uint16_t)((gpi->biased_pstates[p].internal_vdd_mv - 512) >> 4); gpi->biased_pstates[p].vdm_mv = 0; gpi->biased_pstates[p].vdm_vid = 0; diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c index 7a8adcf2..b0fb97b8 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c @@ -36,26 +36,20 @@ extern PgpeHeader_t* G_pgpe_header_data; // //Private function prototypes // -void p9_pgpe_gppb_compute_vpd_pts(); -void p9_pgpe_gppb_compute_PsV_slopes(); uint8_t p9_pgpe_gppb_get_ext_vdd_region(uint32_t evid); uint8_t p9_pgpe_gppb_get_ps_region(Pstate ps, uint8_t vpt_pt_set); // //p9_pgpe_gppb_init // -//This sets the pointer to GlobalPstateParmBlock, and calculates slope -//co-efficients +//This sets the pointer to GlobalPstateParmBlock // -//Note: In future, the slope calculation might be done offline void p9_pgpe_gppb_init() { void* gppb_sram_offset = G_pgpe_header_data->g_pgpe_gppb_sram_addr;//GPPB Sram Offset G_gppb = (GlobalPstateParmBlock*)gppb_sram_offset; PK_TRACE_INF("GPP: DPLL0Value=0x%x", G_gppb->dpll_pstate0_value); - PK_TRACE_INF("GPP: PowerSave PS=0x%x", G_gppb->operating_points[POWERSAVE].pstate ); - PK_TRACE_INF("GPP: Nominal PS=0x%x", G_gppb->operating_points[NOMINAL].pstate ); //External VRM increasing rate in us/uv G_ext_vrm_inc_rate_mult_usperus = 1 / G_gppb->ext_vrm_transition_rate_inc_uv_per_us; @@ -69,12 +63,12 @@ void p9_pgpe_gppb_init() // //Interpolate voltage from pstate // -uint32_t p9_pgpe_gppb_intp_vdd_from_ps(Pstate ps, uint8_t vpd_pt_set, uint8_t vpd_slope_set) +uint32_t p9_pgpe_gppb_intp_vdd_from_ps(Pstate ps, uint8_t vpd_pt_set) { uint32_t vdd; uint8_t r = p9_pgpe_gppb_get_ps_region(ps, vpd_pt_set); - vdd = (((G_gppb->PsVSlopes[vpd_slope_set][r]) * - (-ps + G_gppb->operating_points_set[vpd_pt_set][r].pstate)) >> VID_SLOPE_FP_SHIFT) + vdd = (((G_gppb->PStateVSlopes[vpd_pt_set][r]) * + (-ps + G_gppb->operating_points_set[vpd_pt_set][r].pstate)) >> VID_SLOPE_FP_SHIFT_12) + G_gppb->operating_points_set[vpd_pt_set][r].vdd_mv; return vdd; @@ -105,12 +99,15 @@ uint8_t p9_pgpe_gppb_get_ps_region(Pstate ps, uint8_t vpd_pt_set) //p9_pgpe_gppb_intp_ps_from_evid // //Interpolate pstate from evid +//This functions is hardcoded to use BIASED_SYSPARAMETERS pt +//bc currently interpolating pstate from vdd is only needed +//for Biased SysParam VPD during actuation uint8_t p9_pgpe_gppb_intp_ps_from_ext_vdd(uint16_t ext_vdd) { Pstate ps; uint8_t r = p9_pgpe_gppb_get_ext_vdd_region(ext_vdd); - ps = -(((G_gppb->VPsSlopes[VPD_SLOPES_BIASED][r]) * - (ext_vdd - G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][r].vdd_mv)) >> VID_SLOPE_FP_SHIFT) + ps = -(((G_gppb->VPStateSlopes[VPD_PT_SET_BIASED_SYSP][r]) * + (ext_vdd - G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][r].vdd_mv)) >> VID_SLOPE_FP_SHIFT_12) + G_gppb->operating_points_set[VPD_SLOPES_BIASED][r].pstate; return ps; } diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h index 388ba493..7df14af5 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.h @@ -28,17 +28,9 @@ #include "pk.h" #include "p9_pstates_pgpe.h" -//#define EVID_SLOPE_FP_SHIFT 13 #define MAX_DPLL_VALUE 255 -#define NUM_VPD_PTS_SET 4 -#define VPD_PT_SET_RAW 0 -#define VPD_PT_SET_SYSP 1 -#define VPD_PT_SET_BIASED 2 -#define VPD_PT_SET_BIASED_SYSP 3 - - void p9_pgpe_gppb_init(); -uint32_t p9_pgpe_gppb_intp_vdd_from_ps(Pstate ps, uint8_t vpd_pt_set, uint8_t vpd_slope_set); +uint32_t p9_pgpe_gppb_intp_vdd_from_ps(Pstate ps, uint8_t vpd_pt_set); uint8_t p9_pgpe_gppb_intp_ps_from_ext_vdd(uint16_t ext_vdd); #endif //_P9_PGPE_GPPB_H_ diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c index 86c96c88..61c843a5 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c @@ -577,8 +577,7 @@ void p9_pgpe_pstate_do_step() ocb_qcsr_t qcsr; qcsr.value = in32(OCB_QCSR); uint32_t active_conf_cores = 0; - uint32_t targetEVid = p9_pgpe_gppb_intp_vdd_from_ps(G_pgpe_pstate_record.globalPSTarget, VPD_PT_SET_BIASED_SYSP, - VPD_SLOPES_BIASED); + uint32_t targetEVid = p9_pgpe_gppb_intp_vdd_from_ps(G_pgpe_pstate_record.globalPSTarget, VPD_PT_SET_BIASED_SYSP); //Determine active and configured cores for (q = 0; q < MAX_QUADS; q++) @@ -1021,10 +1020,10 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin) PK_TRACE_INF("eVidCurr=%umV", G_pgpe_pstate_record.eVidCurr); #if SIMICS_TUNING == 1 G_pgpe_pstate_record.eVidCurr = p9_pgpe_gppb_intp_vdd_from_ps(G_pgpe_pstate_record.globalPSTarget, - VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED); + VPD_PT_SET_BIASED_SYSP); #endif G_pgpe_pstate_record.eVidNext = p9_pgpe_gppb_intp_vdd_from_ps(G_pgpe_pstate_record.globalPSTarget, - VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED); + VPD_PT_SET_BIASED_SYSP); PK_TRACE_INF("eVidNext=%umV", G_pgpe_pstate_record.eVidNext); pgpe_db0_start_ps_bcast_t db0; -- cgit v1.2.3