From 6cf2512bb3b2a9ba08d21552fe0dd1aeba2fb703 Mon Sep 17 00:00:00 2001
From: Amit Kumar <akumar3@us.ibm.com>
Date: Tue, 24 Jan 2017 18:10:20 -0600
Subject: PM Lib: HWP p9_pm_force_core_access

 - Initial checkin
 - This procedure is based on RTC: 162579
 - Made this HWP level 2( in p3)
 - Added cme id as input

Change-Id: I52abce4b8ece22ebdf4bdcd1b423ccbb251ccb17
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35363
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
---
 import/chips/p9/procedures/hwp/lib/p9_hcd_common.H | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
index e36f3bba..d4bd4224 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
@@ -263,6 +263,11 @@ enum SLAVE_CONFIG_DEFS
     CFG_PM_DISABLE     = 6,
     CFG_PM_MUX_DISABLE = 7
 };
+enum SICR_DEFS
+{
+    PCBMUX_REQ_C0 = 10,
+    PCBMUX_REQ_C1 = 11
+};
 
 } // END OF NAMESPACE p9hcd
 
-- 
cgit v1.2.3