From 6cd78ca6ee3fd719eb467f9cbee9ac7697d0b6b1 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Mon, 26 Jun 2017 09:57:23 -0500 Subject: PCIe updates for Nimbus DD2 GEN4 operation adjust REFISRC, REFISINK, VBGENDOC in PCIE PLL inits for all ECs set EDMOD in RX VGA Control Register 1 for DD2 only Change-Id: Ib10b02fb49dbf7ccf8dcad2ada5ac463a927d4c7 CQ: HW414759 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42423 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Ricardo Mata Reviewed-by: Jenny Huynh Reviewed-by: Jennifer A. Stofer --- import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H b/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H index 1cfafd6c..3a6a9633 100644 --- a/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H +++ b/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H @@ -60,6 +60,10 @@ REG64_FLD(PU_TX_CH_MISC_WEN0, 12, SH_UNT, SH_ACS_SCOM, SH_FLD REG64_FLD(PU_TX_CH_MISC_WEN1, 13, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED); REG64_FLD(PU_TX_CH_MISC_WEN2, 14, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED); +// RX VGA Control Register1 +REG64_FLD(PEC_SCOM0X0B_EDMOD, 52, SH_UNT_PEC, SH_ACS_SCOM, SH_FLD_UNUSED); +REG64_FLD(PEC_SCOM0X0B_EDMOD_LEN, 2, SH_UNT_PEC, SH_ACS_SCOM, SH_FLD_UNUSED); + //Example //Copy the whole line from the *scom_addresses_fld.H file. Then add FIX in front of REG //and add another paramter that is the new value you want. -- cgit v1.2.3