From 421ca1bf24da599f39a2a2af1496f8da103a2c9c Mon Sep 17 00:00:00 2001 From: "Christopher M. Riedl" Date: Wed, 16 Aug 2017 10:14:46 -0500 Subject: PM: CME Fix Resclk CACCR Change-Id: I213c52dad35e13e738bde3b1577cce463bdfa3ae Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44673 Reviewed-by: Michael S. Floyd Tested-by: Jenkins Server Reviewed-by: BRIAN D. VICTOR Reviewed-by: Brian T. Vanderpool Reviewed-by: Gregory S. Still --- .../ppe_closed/cme/pstate_cme/p9_cme_pstate.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c index 117306b1..ceb7e877 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c @@ -284,9 +284,8 @@ void p9_cme_analog_control(uint32_t core_mask, ANALOG_CONTROL enable) // 1) step CACCR to running pstate pstate = G_cme_pstate_record.quadPstate; p9_cme_resclk_update(core_mask, pstate, curr_idx); - // 2) write CACCR[13:15]=0b111 to switch back to common control - // and leave clksync enabled - CME_PUTSCOM(CPPM_CACCR_OR, core_mask, (BITS64(13, 3))); + // 2) write CACCR[13:14]=0b11 to switch back to common control + CME_PUTSCOM(CPPM_CACCR_OR, core_mask, (BITS64(13, 2))); // 3) Clear out the CACCR resclk values CME_PUTSCOM(CPPM_CACCR_CLR, core_mask, BITS64(0, 13)); @@ -295,13 +294,13 @@ void p9_cme_analog_control(uint32_t core_mask, ANALOG_CONTROL enable) else { PK_TRACE_INF("resclk | disabling resclks"); - - // 1) copy QACCR[0:12] into CACCR[0:12], with CACCR[13:15]=0b000, - // to switch away from common control while leaving clksync - // disabled. QACCR will already be set to a value corresponding - // to the current quad Pstate + // 1) copy QACCR[0:12] into CACCR[0:12], with CACCR[13:14]=0b00, + // to switch away from common control. QACCR will already be set + // to a value corresponding to the current quad Pstate ippm_read(QPPM_QACCR, &val); - val &= BITS64(13, 51); + val &= BITS64(0, 13); + // clk_sync enable (bit 15) is ALWAYS 0b0 at this point due to the + // sequence of function calls in Stop Entry CME_PUTSCOM(CPPM_CACCR, core_mask, val); curr_idx = p9_cme_resclk_get_index(G_cme_pstate_record.quadPstate); // 2) step CACCR to a value which disables resonance -- cgit v1.2.1