diff options
| author | Rahul Batra <rbatra@us.ibm.com> | 2018-03-05 10:00:41 -0600 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-04-06 12:39:19 -0500 |
| commit | 6ebb5508cb11657cf867aadb8391d6be2ed60b73 (patch) | |
| tree | 4a34784d5a23acd7fcbc20af1775926ab1327603 /import | |
| parent | 1fb69dc9f9a40980e40ac8f42bb5423f2829a22b (diff) | |
| download | talos-hcode-6ebb5508cb11657cf867aadb8391d6be2ed60b73.tar.gz talos-hcode-6ebb5508cb11657cf867aadb8391d6be2ed60b73.zip | |
PM: Generated Vratio/Vindex tables
Key_Cronus_Test=PM_REGRESS
Change-Id: I3ecb8a4389c7b888c5323f2d8f013c3a17594cc5
Original-Change-Id: I9313dbe90771a549e14c8e90f2c2ca410616293a
CQ: SW421682
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55059
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import')
3 files changed, 135 insertions, 9 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 5c70f5d0..37cc8354 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -631,8 +631,7 @@ typedef struct uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE]; uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)]; - uint8_t pstateTable[sizeof(GeneratedPstateInfo)]; // PPMR + 144KB - uint8_t pstateTableReserve[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE - sizeof(GeneratedPstateInfo)]; + uint8_t pstateTable[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE]; // PPMR + 144KB uint8_t ppmr_reserved1[WOF_TABLE_RESERVE]; uint8_t wofTableSize[OCC_WOF_TABLES_SIZE]; //WOF Tables located ar PPMR base + 768KB } PPMRLayout_t; diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h index b03de373..3056e749 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h +++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,9 +46,11 @@ /// on the fly during Pstate protocol execution based on the Pstate Parameter /// Block content. -#define MAX_PSTATE_TABLE_ENTRIES 128 -#define GEN_PSTATES_TBL_MAGIC 0x50535441424c3030ULL //PSTABL00 (last two ASCII characters indicate version number) -#define GEN_PSTATES_TBL_MAGIC_V1 0x50535441424c3031ULL //PSTABL01 (last two ASCII characters indicate version number) +#define MAX_PSTATE_TABLE_ENTRIES 128 +#define MAX_VRATIO_VINDEX_TABLE_ENTRIES 299 +#define GEN_PSTATES_TBL_MAGIC 0x50535441424c3030ULL //PSTABL00 (last two ASCII characters indicate version number) +#define GEN_PSTATES_TBL_MAGIC_V1 0x50535441424c3031ULL //PSTABL01 (last two ASCII characters indicate version number) +#define GEN_PSTATES_TBL_MAGIC_V2 0x50535441424c3032ULL //PSTABL02 (last two ASCII characters indicate version number) #ifndef __ASSEMBLER__ #ifdef __cplusplus @@ -100,6 +102,11 @@ typedef struct } PstateTable; +typedef struct +{ + uint16_t vratio; + uint16_t vindex; +} VRatioVIndexTable; /// GeneratedPstateInfo - VERSION0 typedef struct @@ -124,6 +131,7 @@ typedef struct /// Note: if all bias attributes are 0, this content will be the same /// as the raw_pstates content. PstateTable biased_pstates[MAX_PSTATE_TABLE_ENTRIES]; + } GeneratedPstateInfo; @@ -167,6 +175,52 @@ typedef struct PstateTable biased_pstates[MAX_PSTATE_TABLE_ENTRIES]; } GeneratedPstateInfo_v1; +/// GeneratedPstateInfo - VERSION2 +typedef struct +{ + uint32_t gppb_offset; + uint32_t gppb_length; + uint32_t ps0_offset; + uint32_t highest_ps_offset; + uint32_t raw_pstate_tbl_offset; + uint32_t raw_pstate_tbl_length; + uint32_t biased_pstate_tbl_offset; + uint32_t biased_pstate_tbl_length; + uint32_t vratio_vindex_tbl_offset; + uint32_t vratio_vindex_tbl_length; +} GeneratedPstateInfoHeader_v2; + +typedef struct +{ + + /// Magic Number + uint64_t magic; // ASCII: "PSTABL02 " + + /// Offset and lengths for fields of this structure + GeneratedPstateInfoHeader_v2 header; + + // PGPE content + GlobalPstateParmBlock globalppb; + + /// The fastest frequency - after biases have been applied + uint32_t pstate0_frequency_khz; + + /// Highest Pstate Number => slowest Pstate generated + uint32_t highest_pstate; + + /// Generated table with system paramters included but without biases + PstateTable raw_pstates[MAX_PSTATE_TABLE_ENTRIES]; + + /// Generated table with system paramters and biases + /// Note: if all bias attributes are 0, this content will be the same + /// as the raw_pstates content. + PstateTable biased_pstates[MAX_PSTATE_TABLE_ENTRIES]; + + ///Generate table with vratio and vindex for all + ///combinations of activeCores and sortCores + VRatioVIndexTable vratio_vindex[MAX_VRATIO_VINDEX_TABLE_ENTRIES]; +} GeneratedPstateInfo_v2; + #ifdef __cplusplus } // end extern C diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c index 48bcc229..04d0306c 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2017 */ +/* COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,6 +28,7 @@ #include "p9_pgpe_gppb.h" #include "p9_pgpe_header.h" #include "pstate_pgpe_occ_api.h" +#include "p9_pgpe.h" //Externs extern PgpeHeader_t* G_pgpe_header_data; @@ -37,14 +38,21 @@ extern GlobalPstateParmBlock* G_gppb; GeneratedPstateInfo* G_gpi; #elif USE_GEN_PSTATE_STRUCT_V == 1 GeneratedPstateInfo_v1* G_gpi; +#elif USE_GEN_PSTATE_STRUCT_V == 2 + GeneratedPstateInfo_v2* G_gpi; #endif +compile_assert(GEN_PSTATE_INFO_CHECK, sizeof(GeneratedPstateInfo) < PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE); +compile_assert(GEN_PSTATE_INFO_V1_CHECK, sizeof(GeneratedPstateInfo_v1) < PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE); +compile_assert(GEN_PSTATE_INFO_V2_CHECK, sizeof(GeneratedPstateInfo_v2) < PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE); + // //Local function prototypes // -void p9_pgpe_gen_raw_pstates(); -void p9_pgpe_gen_biased_pstates(); +void p9_pgpe_gen_raw_pstates(PstateTable* tbl); +void p9_pgpe_gen_biased_pstates(PstateTable* tbl); void p9_pgpe_gen_occ_pstate_tbl(); +void p9_pgpe_gen_vratio_vindex_tbl(VRatioVIndexTable* tbl); // //p9_pgpe_gen_pstate_info @@ -89,6 +97,41 @@ void p9_pgpe_gen_pstate_info() PK_TRACE_DBG("INIT:highest_ps=0x%x, ps0=0x%x", *highest_pstate, *ps0); +#elif USE_GEN_PSTATE_STRUCT_V == 2 + G_gpi = (GeneratedPstateInfo_v2*)G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset; + G_gpi->magic = GEN_PSTATES_TBL_MAGIC_V2; + G_gpi->header.gppb_offset = offsetof(GeneratedPstateInfo_v2, globalppb) >> 2; + G_gpi->header.gppb_length = sizeof(GlobalPstateParmBlock); + G_gpi->header.ps0_offset = offsetof(GeneratedPstateInfo_v2, pstate0_frequency_khz) >> 2; + G_gpi->header.highest_ps_offset = offsetof(GeneratedPstateInfo_v2, highest_pstate) >> 2; + G_gpi->header.raw_pstate_tbl_offset = offsetof(GeneratedPstateInfo_v2, raw_pstates) >> 2; + G_gpi->header.raw_pstate_tbl_length = sizeof(PstateTable) * MAX_PSTATE_TABLE_ENTRIES; + G_gpi->header.biased_pstate_tbl_offset = offsetof(GeneratedPstateInfo_v2, biased_pstates) >> 2; + G_gpi->header.biased_pstate_tbl_length = sizeof(PstateTable) * MAX_PSTATE_TABLE_ENTRIES; + G_gpi->header.vratio_vindex_tbl_offset = offsetof(GeneratedPstateInfo_v2, vratio_vindex) >> 2; + G_gpi->header.vratio_vindex_tbl_length = sizeof(VRatioVIndexTable) * MAX_VRATIO_VINDEX_TABLE_ENTRIES; + + PK_TRACE_DBG("INIT:gppb=0x%x, ps0=0x%x", + G_gpi->header.gppb_offset, + G_gpi->header.ps0_offset); + PK_TRACE_DBG("INIT:highest_ps=0x%x, biased_ps=0x%x", + G_gpi->header.highest_ps_offset, + G_gpi->header.biased_pstate_tbl_offset); + PK_TRACE_DBG("INIT:vratio_vindex ofsset=0x%x,length=0x%x ", + G_gpi->header.vratio_vindex_tbl_offset, + G_gpi->header.vratio_vindex_tbl_length); + gppb = (GlobalPstateParmBlock*)((G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.gppb_offset)); + ps0 = (uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.ps0_offset); + highest_pstate = (uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.highest_ps_offset); + rTbl = (PstateTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.raw_pstate_tbl_offset); + bTbl = (PstateTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.biased_pstate_tbl_offset); + VRatioVIndexTable* vTbl = (VRatioVIndexTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + + G_gpi->header.vratio_vindex_tbl_offset); + PK_TRACE_DBG("INIT:highest_ps=0x%x, ps0=0x%x", + *highest_pstate, + *ps0); + + p9_pgpe_gen_vratio_vindex_tbl(vTbl); #endif PK_TRACE_DBG("INIT:G_gpi=0x%x, rTbl=0x%x,bTbl=0x%x", (uint32_t)G_gpi, (uint32_t)rTbl, (uint32_t)bTbl); @@ -102,6 +145,7 @@ void p9_pgpe_gen_pstate_info() //Generate Pstate table for OCC in SRAM p9_pgpe_gen_occ_pstate_tbl(); + } // @@ -182,3 +226,32 @@ void p9_pgpe_gen_occ_pstate_tbl() PK_TRACE_DBG("INIT: Generated OCC Tbl"); } + + +void p9_pgpe_gen_vratio_vindex_tbl(VRatioVIndexTable* tbl) +{ + uint32_t ac, sc, idx = 0; + + PK_TRACE_DBG("INIT: Generating Vindex Vratio Tbl"); + + for (sc = 1; sc <= 24; sc++) + { + for (ac = 1; ac <= sc; ac++) + { + tbl[idx].vratio = (ac * MAX_VRATIO) / sc; + + if (ac != 0) + { + tbl[idx].vindex = (((24 * tbl[idx].vratio) + VRATIO_ROUNDING_ADJUST) / MAX_VRATIO) - 1; + } + else + { + tbl[idx].vindex = 0; + } + + idx++; + } + + PK_TRACE_DBG("INIT: Generated sc=%d", sc); + } +} |

