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| author | Rahul Batra <rbatra@us.ibm.com> | 2018-04-12 13:00:07 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-04-13 09:17:54 -0500 |
| commit | 1d6d88387b40198f5a90d27526d7e6a7c191d2c5 (patch) | |
| tree | 9d6a1e8c0f492620f3c19860ac74f83194aa3241 /import | |
| parent | 6127d105431fc13ce8a61f8d7262c6add47193dd (diff) | |
| download | talos-hcode-1d6d88387b40198f5a90d27526d7e6a7c191d2c5.tar.gz talos-hcode-1d6d88387b40198f5a90d27526d7e6a7c191d2c5.zip | |
PM: IOTA Fixes
Key_Cronus_Test=PM_REGRESS
Change-Id: Ie8be627853aa7452805408cbb159166e70f96e48
CQ: SW424742
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57124
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Tested-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import')
5 files changed, 26 insertions, 6 deletions
diff --git a/import/chips/p9/procedures/ppe/iota/iota.h b/import/chips/p9/procedures/ppe/iota/iota.h index 1e4c79ad..159d6dcb 100644 --- a/import/chips/p9/procedures/ppe/iota/iota.h +++ b/import/chips/p9/procedures/ppe/iota/iota.h @@ -177,7 +177,7 @@ typedef struct uint32_t GPR3; uint32_t GPR10; uint32_t CTR; - uint32_t padding; // needs to be 8B aligned + uint32_t XER; // needs to be 8B aligned } iotaMachineState; typedef void (*iotaTaskFuncPtr )( ); diff --git a/import/chips/p9/procedures/ppe/iota/iota_ppe42.S b/import/chips/p9/procedures/ppe/iota/iota_ppe42.S index 017ddd5f..cceb64db 100644 --- a/import/chips/p9/procedures/ppe/iota/iota_ppe42.S +++ b/import/chips/p9/procedures/ppe/iota/iota_ppe42.S @@ -92,7 +92,9 @@ __iota_save_interrupt_state_and_schedule: mfcr %r5 stvd %d4, _IOTA_SAVE_LR_OFFSET(%r9) mfctr %r4 - stw %r4, _IOTA_SAVE_CTR_OFFSET(%r9) + mfxer %r5 + stvd %d4, _IOTA_SAVE_CTR_OFFSET(%r9) + # All state is saved, sp(r1) intact pointing to "Execution Stack" # _iota_schedule(uint32_t schedule_reason) @@ -119,8 +121,9 @@ __iota_save_interrupt_state_and_schedule: lvd %d8, _IOTA_SAVE_LR_OFFSET(%r3) mtlr %r8 mtcr0 %r9 - lwz %r9, _IOTA_SAVE_CTR_OFFSET(%r3) - mtctr %r9 + lvd %d8, _IOTA_SAVE_CTR_OFFSET(%r3) + mtctr %r8 + mtxer %r9 lvd %d8, _IOTA_SAVE_SRR0_OFFSET(%r3) mtsrr0 %r8 mtsrr1 %r9 diff --git a/import/chips/p9/procedures/ppe/iota/iota_ppe42.h b/import/chips/p9/procedures/ppe/iota/iota_ppe42.h index 7065d0bb..96399050 100644 --- a/import/chips/p9/procedures/ppe/iota/iota_ppe42.h +++ b/import/chips/p9/procedures/ppe/iota/iota_ppe42.h @@ -55,7 +55,7 @@ #define _IOTA_SAVE_R3_OFFSET 64 #define _IOTA_SAVE_R10_OFFSET 68 #define _IOTA_SAVE_CTR_OFFSET 72 -#define _IOTA_SAVE_PADDING_OFFSET 76 +#define _IOTA_SAVE_XER_OFFSET 76 #define _IOTA_TEMPORARY_R3_STACK_OFFSET -4 diff --git a/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h index c565ec75..2bbc9efb 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/iota_app_cfg.h @@ -46,8 +46,23 @@ #endif + +#define NUM_TIMER_INTERRUPTS \ + (ENABLE_CME_WATCHDOG_TIMER ? 1:0 + \ + ENABLE_CME_DEC_TIMER ? 1:0 + \ + DISABLE_CME_FIT_TIMER ? 0:1) + // Maximum number of expected nested interrupts -#define IOTA_MAX_NESTED_INTERRUPTS 12 +// +// We add 3 here to account for FIT, DEC, and Watchdog Interrupts +// First, we start with the total number of priority levels, and then +// add one for each enabled timer interrupt plus one to leave a +// stack entry unused for checking +// +#define IOTA_MAX_NESTED_INTERRUPTS (IOTA_NUM_EXT_IRQ_PRIORITIES + \ + NUM_TIMER_INTERRUPTS + 1) + + //An "idle" task is one that only runs when the ppe42 engine would otherwise //be idle and thus has the lowest priority and can be interrupted by anything. diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h index 74dcb72d..6d76f329 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h @@ -57,6 +57,7 @@ // being enabled on all other dd levels unless this override #define DISABLE_CME_DUAL_CAST 0 + #if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1 // NDD2: no catchup due to dual cast bug #undef SKIP_ENTRY_CATCHUP @@ -75,6 +76,7 @@ #define DISABLE_CME_FIT_TIMER 0 #endif +#define ENABLE_CME_WATCHDOG_TIMER 0 // -------------------- #define ENABLE_CME_DEC_TIMER 0 // -------------------- |
