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| author | Jin Song Jiang <jjsjiang@cn.ibm.com> | 2017-04-21 11:47:20 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:40:35 -0500 |
| commit | fd5ec305dd6d63b03face4268f476b4e7215ef8e (patch) | |
| tree | 5c7bcec070ec5562bfb5813cb872146371895af9 /import/chips/p9/common | |
| parent | 916fd4f80869a30fd904e957b3d946e02938d105 (diff) | |
| download | talos-hcode-fd5ec305dd6d63b03face4268f476b4e7215ef8e.tar.gz talos-hcode-fd5ec305dd6d63b03face4268f476b4e7215ef8e.zip | |
p9_cen_framelock -- 2nd version
1) Replace MCSMODE4 register with MCMODE2 and MCBCFGQ register
shift host attention enablement to p9c_set_inband_addr HWP
2) Update FIR registers'(ACT0,ACT1 and MASK) set from p8 to p9c
Change-Id: Ifdce2d948c12ad2b82a74cfc6a8731617a3086df
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39558
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/common')
| -rw-r--r-- | import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H | 26 | ||||
| -rw-r--r-- | import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H | 1 |
2 files changed, 26 insertions, 1 deletions
diff --git a/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H b/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H index cc611c0e..ac4df64f 100644 --- a/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H +++ b/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H @@ -43,6 +43,32 @@ REG64( MCA_MBA_MCP0XLT0 , RULL(0x05010820), REG64( MCA_MBA_MCP0XLT1 , RULL(0x05010821), SH_UNT_MCA , SH_ACS_SCOM_RW ); REG64( MCA_MBA_MCP0XLT2 , RULL(0x05010822), SH_UNT_MCA , SH_ACS_SCOM_RW ); +// Register define for Framelock +REG64( DMI_DATAPATHFIR_0x07010900 , RULL(0x07010900), SH_UNT_MCA , + SH_ACS_SCOM_RW ); +REG64( DMI_DATAPATHFIR_AND_0x07010901 , RULL(0x07010901), SH_UNT_MCA , + SH_ACS_SCOM1_AND ); +REG64( DMI_DATAPATHFIR_OR_0x07010902 , RULL(0x07010902), SH_UNT_MCA , + SH_ACS_SCOM2_OR ); +REG64( DMI_DATAPATHFIRMASK_0x07010903 , RULL(0x07010903), SH_UNT_MCA , + SH_ACS_SCOM_RW ); +REG64( DMI_DATAPATHFIRMASK_AND_0x07010904 , RULL(0x07010904), SH_UNT_MCA , + SH_ACS_SCOM1_AND ); +REG64( DMI_DATAPATHFIRMASK_OR_0x07010905 , RULL(0x07010905), SH_UNT_MCA , + SH_ACS_SCOM2_OR ); +REG64( DMI_DATAPATHFIRACT0_0x07010906 , RULL(0x07010906), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_DATAPATHFIRACT1_0x07010907 , RULL(0x07010907), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_MCICFG_0x0701090A , RULL(0x0701090A), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_MCISTAT_0x0701090B , RULL(0x0701090B), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( MI_MCMODE2_0x05010813 , RULL(0x05010813), SH_UNT_MCA , + SH_ACS_SCOM ); +REG64( DMI_MCBCFG_0x070123E0 , RULL(0x070123E0), SH_UNT_MCA , + SH_ACS_SCOM ); + // DDRPHY registers renamed in DD2.0 REG64( MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0 , RULL(0x800000160701103F), SH_UNT_MCA , SH_ACS_SCOM_RW ); diff --git a/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H b/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H index 8141bec8..495308f4 100644 --- a/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H +++ b/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H @@ -549,5 +549,4 @@ REG64( PEC_1_PCS_PCLCK_CNTL_PLLB_REG , RULL(0x8000054F REG64( PEC_2_PCS_PCLCK_CNTL_PLLB_REG , RULL(0x8000054F0F010C3F), SH_UNT_PEC_2 , SH_ACS_SCOM ); - #endif |
