diff options
| author | Joe McGill <jmcgill@us.ibm.com> | 2017-05-01 22:43:03 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:30:20 -0500 |
| commit | e786e55f107792908590c1642ef3f6fff2728587 (patch) | |
| tree | 130199f77e5cbfbff1692cdb4fd06032b32afc93 /import/chips/p9/common/include | |
| parent | 0a16f9e369cf50fe2c355058c74f1c9274c7a8db (diff) | |
| download | talos-hcode-e786e55f107792908590c1642ef3f6fff2728587.tar.gz talos-hcode-e786e55f107792908590c1642ef3f6fff2728587.zip | |
p9_mss_setup_bars -- customize interleave granularity
create new attribute to encapsulate system-wide interleave
granularity, ship default should be 128B (so that the stride
between channels in a group is a single cacheline)
other enums are supported for logic and performance verification
update p9_mss_setup_bars HWP to apply granularity customization
only for supported group sizes of 2, 4, and 8
Change-Id: Iadecb9164efbf6c9ce0658f75a0def03cc600f01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39923
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/common/include')
| -rw-r--r-- | import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H index f18fa08b..24c9914e 100644 --- a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H +++ b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H @@ -64,5 +64,11 @@ REG64_FLD( MCBIST_MCBCFGQ_CFG_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK , 34 , SH_UN REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MCE , 33 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_PAUSE_ON_MCE ); +REG64_FLD( MCS_MCMODE0_GROUP_INTERLEAVE_GRANULARITY , 52 , SH_UNT_MCS , SH_ACS_SCOM_RW , + 0 ); +REG64_FLD( MCS_MCMODE0_GROUP_INTERLEAVE_GRANULARITY_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + 0 ); + + #endif |
