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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2018-12-20 00:41:47 -0600 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2019-01-26 10:41:52 -0600 |
| commit | 41a92e1e1fc1e89a0a47582d7e6974a8fe47d7f6 (patch) | |
| tree | d64fc0bc7a296d0eea50ffb305981b83b8469355 | |
| parent | 68d1acfd7de3588094745ccc1f49256a760fa95c (diff) | |
| download | talos-hcode-41a92e1e1fc1e89a0a47582d7e6974a8fe47d7f6.tar.gz talos-hcode-41a92e1e1fc1e89a0a47582d7e6974a8fe47d7f6.zip | |
VDM(Part 1): Introduced new members in CME and CPMR image headers
commit introduces new members in CPMR and CME image headers. These
fields will be utilised in subsequent commits to facilitate and
execute downloading of LPSPB customized for a quad.
Key_Cronus_Test=PM_REGRESS
Change-Id: I9af8f2e6c2570a4bb0ea6a95a458b30b7e25273e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69964
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 92419f7b..eeae5161 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -155,6 +155,12 @@ HCD_HDR_UINT32( coreScomLength, 0); HCD_HDR_UINT32( coreSelfRestoreOffset, 0); HCD_HDR_UINT32( coreSelfRestoreLength, 0); HCD_HDR_UINT32( coreMaxScomEntry, 0); +HCD_HDR_UINT32( quad0PstateOffset, 0); +HCD_HDR_UINT32( quad1PstateOffset, 0); +HCD_HDR_UINT32( quad2PstateOffset, 0); +HCD_HDR_UINT32( quad3PstateOffset, 0); +HCD_HDR_UINT32( quad4PstateOffset, 0); +HCD_HDR_UINT32( quad5PstateOffset, 0); HCD_HDR_PAD(CPMR_HEADER_SIZE); #ifdef __ASSEMBLER__ .endm @@ -305,6 +311,8 @@ HCD_HDR_UINT16(g_cme_qm_mode_flags, 0); HCD_HDR_UINT32(g_cme_timebase_hz, 0); //Retain next field at 8B boundary HCD_HDR_UINT64(g_cme_cpmr_PhyAddr, 0); HCD_HDR_UINT64(g_cme_unsec_cpmr_PhyAddr, 0); +HCD_HDR_UINT32(g_cme_pstate_offset, 0); +HCD_HDR_UINT32(g_cme_custom_length, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm |
