STOP: Fix PLS deepest when stop4+ due to self restore wakeup

Key_Cronus_Test=PM_REGRESS

Change-Id: I5885bea7bc31fcc4ce5575a543997879d60423d1
Original-Change-Id: I4cc1e50a848d627f0ec3917bb8ebd39f20dc9466
CQ: HW420338
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51719
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Dev-Ready: YUE DU <daviddu@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

3 files changed, 21 insertions, 24 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h
index 805ef0e4..8bdee2ba 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2017                                                         */
+/* COPYRIGHT 2017,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -28,7 +28,7 @@
 #include "pk.h"
 #include "p9_pm_hcd_flags.h"
 
-#ifdef PCQW_ENABLE
+#if !DISABLE_PERIODIC_CORE_QUIESCE && (NIMBUS_DD_LEVEL == 20 || NIMBUS_DD_LEVEL == 21 || CUMULUS_DD_LEVEL == 10)
 
 typedef struct
 {
@@ -50,7 +50,7 @@ typedef struct
     uint32_t     core_enabled;
     uint32_t     spurr_freq_ref_upper;
 
-#ifdef PCQW_ENABLE
+#if !DISABLE_PERIODIC_CORE_QUIESCE && (NIMBUS_DD_LEVEL == 20 || NIMBUS_DD_LEVEL == 21 || CUMULUS_DD_LEVEL == 10)
 
     CmeFitRecord fit_record;
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c
index e78c16a2..9906ba48 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2016,2017                                                    */
+/* COPYRIGHT 2016,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -60,7 +60,7 @@ p9_cme_stop_init()
 
     if (!G_cme_record.core_enabled)
     {
-        PK_TRACE_ERR("ERROR: No Partial Good Core Configured to this CME. HALT CME!");
+        PK_TRACE_DBG("ERROR: No Partial Good Core Configured to this CME. HALT CME!");
         PK_PANIC(CME_STOP_NO_PARTIAL_GOOD_CORE);
     }
 
@@ -82,7 +82,7 @@ p9_cme_stop_init()
     // use SISR[16:17] SPECIAL_WKUP_DONE to init special wakeup status
     G_cme_stop_record.core_in_spwu = ((in32(CME_LCL_SISR) & BITS32(16, 2)) >> SHIFT32(17));
 
-    PK_TRACE_INF("Setup: cme_flags[%x] entry_first[%x] exit_first[%x]",
+    PK_TRACE_DBG("Setup: cme_flags[%x] entry_first[%x] exit_first[%x]",
                  cme_flags, entry_first, exit_first);
 
     for (core_mask = 2; core_mask; core_mask--)
@@ -116,7 +116,7 @@ p9_cme_stop_init()
 
     if( BLOCK_COPY_SUCCESS != check_cme_block_copy() )
     {
-        PK_TRACE_ERR("ERROR: BCE Copy of Core Specific Scan Ring Failed. HALT CME!");
+        PK_TRACE_DBG("ERROR: BCE Copy of Core Specific Scan Ring Failed. HALT CME!");
         PK_PANIC(CME_STOP_BCE_CORE_RING_FAILED);
     }
 
@@ -136,9 +136,6 @@ p9_cme_stop_init()
     // Common Hardware Settings
     //--------------------------------------------------------------------------
 
-    PK_TRACE("Drop reset_state_indicator on good core via GPMMR[15]");
-    CME_PUTSCOM(PPM_GPMMR_CLR, G_cme_record.core_enabled, BIT64(15));
-
 #if HW386841_NDD1_DSL_STOP1_FIX
 
     PK_TRACE("Disable the Auto-STOP1 function for Nimbus DD1 via LMCR[18,19]");
@@ -149,23 +146,23 @@ p9_cme_stop_init()
     PK_TRACE("Drop STOP override mode and active mask via LMCR[16,17]");
     out32(CME_LCL_LMCR_CLR, BITS32(16, 2));
 
-    PK_TRACE_INF("Setup: SPWU Interrupt Polority[%d]", G_cme_stop_record.core_in_spwu);
+    PK_TRACE_DBG("Setup: SPWU Interrupt Polority[%d]", G_cme_stop_record.core_in_spwu);
     out32(CME_LCL_EIPR_CLR, (G_cme_stop_record.core_in_spwu << SHIFT32(15)));
     out32(CME_LCL_EIPR_OR,  (((~G_cme_stop_record.core_in_spwu) & CME_MASK_BC) << SHIFT32(15)));
 
-    PK_TRACE_INF("Setup: Umask STOP Interrupts Now Based on Entry_First Flag");
-    out32(CME_LCL_EIMR_CLR, (entry_first << SHIFT32(21)) |
-          (exit_first  << SHIFT32(13)) |
+    PK_TRACE_DBG("Setup: Umask STOP Interrupts Now Based on Entry_First Flag");
+    // unmask db1 for block stop protocol
+    out32_sh(CME_LCL_EIMR_CLR, (CME_MASK_BC << SHIFT64SH(41)));
+    out32(CME_LCL_EIMR_CLR,
+          ((CME_MASK_BC << SHIFT32(19)) |  // DB2
+           (entry_first << SHIFT32(21)) |  // PM_ACTIVE
+           (exit_first  << SHIFT32(13)) |  // PC_INTR_PENDING
 #if SPWU_AUTO
-          (exit_first  << SHIFT32(15)) |
+           (exit_first  << SHIFT32(15)) |
 #else
-          (CME_MASK_BC << SHIFT32(15)) | // always unmask spwu
+           (CME_MASK_BC << SHIFT32(15)) |  // SPWU always unmask
 #endif
-          (exit_first  << SHIFT32(17)));
-
-    // unmask db2 for block stop protocol
-    out32_sh(CME_LCL_EIMR_CLR, (CME_MASK_BC << SHIFT64SH(41)));
-    out32(CME_LCL_EIMR_CLR, (CME_MASK_BC << SHIFT32(19)));
+           (exit_first  << SHIFT32(17)))); // RGWU
 
     //--------------------------------------------------------------------------
     // CME Init Completed
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
index 98855ee6..3654776d 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2016,2017                                                    */
+/* COPYRIGHT 2016,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -294,7 +294,7 @@ int rs4DecompressionSvc(
         }
         else if( CMSK == i_rs4Type )
         {
-            PKTRACE("CMSK start");
+            PK_TRACE_DBG("CMSK start");
             l_rs4Header = (CompressedScanData*)(i_rs4 + sizeof( CompressedScanData ));
             l_rs4Str = i_rs4 + ( sizeof( CompressedScanData) << 1);
         }
@@ -530,7 +530,7 @@ int rs4DecompressionSvc(
 
         if( CMSK == i_rs4Type )
         {
-            PKTRACE("CMSK END");
+            PK_TRACE_DBG("CMSK END");
         }
 
         // Verify header