STOP/PState: SGPE/PGPE Error Handling Support

Upon PGPE Halt
1) SGPE performs STOP Recovery Trigger to set
a malfunction alert and removes PGPE IPCs
from wake-up decisions.
2) CME is interrupted by QPPM OCC Heartbeat
Lost that PGPE stopped updating

Upon SGPE Halt
1) PGPE moves to Psafe
2) PGPE performs STOP Recovery Trigger to set
a malfunction alert.

This commit also includes SGPE Panic Code
Cleanup such as debug halt support.
However PGPE Panic Code Cleanup is dealt in
a different commit

Key_Cronus_Test=PM_REGRESS

Change-Id: I69738c0bacf18e040cd3bee17601c70b14b80896
Original-Change-Id: I893aa1ef21d2f684722b8c10dbbeb92b9505c1c4
CQ: SW410252
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49275
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

2 files changed, 10 insertions, 9 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h
index 39133da0..3d9aafaa 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.h
@@ -187,6 +187,7 @@ void p9_cme_pstate_pmcr_handler(void*, PkIrqId);
 void p9_cme_pstate_db_handler(void*, PkIrqId);
 void p9_cme_pstate_intercme_in0_irq_handler(void*, PkIrqId);
 void p9_cme_pstate_intercme_msg_handler(void* arg, PkIrqId irq);
+void p9_cme_pstate_db0_safe_mode();
 int send_pig_packet(uint64_t data, uint32_t coreMask);
 void poll_dpll_update_complete();
 void ippm_read(uint32_t addr, uint64_t* data);
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index 2ea642cc..0de737ef 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -343,15 +343,15 @@ p9_cme_stop_exit_lv2(uint32_t core)
     PK_TRACE_PERF("+++++ +++++ STOP LEVEL 2 EXIT +++++ +++++");
     //--------------------------------------------------------------------------
 
-    //============================
-    MARK_TAG(SX_STARTCLOCKS, core)
-    //============================
-
     // do this again here for stop2 in addition to chiplet_reset
     // Note IPL doesnt need to do this twice
     PK_TRACE("Assert core glitchless mux to DPLL via CGCR[3]");
     CME_PUTSCOM(C_PPM_CGCR, core, BIT64(3));
 
+    //=========================
+    MARK_TRAP(SX_ENABLE_ANALOG)
+    //=========================
+
     p9_cme_core_stop_analog_control(core, ANALOG_ENABLE);
 
     // do this after assert glsmux so glitch can have time to resolve
@@ -377,6 +377,10 @@ p9_cme_stop_exit_lv2(uint32_t core)
 
 #endif
 
+    //============================
+    MARK_TAG(SX_STARTCLOCKS, core)
+    //============================
+
     PK_TRACE_PERF("SX.2A: Core Start Clock");
     p9_hcd_core_startclocks(core);
 
@@ -554,7 +558,7 @@ p9_cme_stop_exit()
 
         if (!core)
         {
-            PK_TRACE_INF("WARNING: Only Freebie Special Wakeup Processed. Return");
+            PK_TRACE_INF("Only processed Special Wakeup on running cores. Return");
             return;
         }
     }
@@ -1145,10 +1149,6 @@ p9_cme_stop_exit()
             }
         }
 
-        //=========================
-        MARK_TRAP(SX_ENABLE_ANALOG)
-        //=========================
-
         p9_cme_stop_exit_end(core, spwu_stop);
 
 #if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1