diff options
| author | Yue Du <daviddu@us.ibm.com> | 2018-02-14 09:15:49 -0600 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-03-22 14:04:08 -0500 |
| commit | 97d0766efd35bfcd36419601385249b293718f25 (patch) | |
| tree | 677749004f0200080044d35bc8bbd616e9afa66c | |
| parent | 47cbe0a34c97136c98227f353c71d678e11a8dc7 (diff) | |
| download | talos-hcode-97d0766efd35bfcd36419601385249b293718f25.tar.gz talos-hcode-97d0766efd35bfcd36419601385249b293718f25.zip | |
STOP: Fix Block Wakeup Mode with Catchup and Abort cases
Key_Cronus_Test=PM_REGRESS
Change-Id: I9020bc4667f3f3887bf1f6560676bc3583c547c5
CQ: SW417400
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54040
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
| -rwxr-xr-x | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index d17097f7..fd0571fa 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -233,6 +233,9 @@ p9_cme_stop_entry() uint32_t origin_core = 0; uint32_t core_catchup = 0; #endif +#if !SKIP_ABORT + uint32_t core_wakeup = 0; +#endif uint32_t core_aborted = 0; uint32_t core_stop1 = 0; uint32_t core_index = 0; @@ -1214,9 +1217,10 @@ p9_cme_stop_entry() //=========================== #if !SKIP_ABORT - out32(CME_LCL_EIMR_CLR, (core << SHIFT32(13)) | - (core << SHIFT32(15)) | - (core << SHIFT32(17))); + core_wakeup = core & (~G_cme_stop_record.core_blockwu); + out32(CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) | + (core_wakeup << SHIFT32(15)) | + (core_wakeup << SHIFT32(17))); sync(); wrteei(0); out32(CME_LCL_EIMR_OR, (BITS32(12, 6) | BITS32(20, 2))); @@ -1444,9 +1448,10 @@ p9_cme_stop_entry() //=========================== #if !SKIP_ABORT - out32(CME_LCL_EIMR_CLR, (core << SHIFT32(13)) | - (core << SHIFT32(15)) | - (core << SHIFT32(17))); + core_wakeup = core & (~G_cme_stop_record.core_blockwu); + out32(CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) | + (core_wakeup << SHIFT32(15)) | + (core_wakeup << SHIFT32(17))); sync(); wrteei(0); out32(CME_LCL_EIMR_OR, (BITS32(12, 6) | BITS32(20, 2))); @@ -1488,7 +1493,7 @@ p9_cme_stop_entry() //---------------------------------------------------------------------- // NDD1 workaround to save cme image size -#if NIMBUS_DD_LEVEL != 10 +#if NIMBUS_DD_LEVEL != 10 && DISABLE_STOP8 != 1 if ((G_cme_stop_record.req_level[0] >= STOP_LEVEL_8) && (G_cme_stop_record.req_level[1] >= STOP_LEVEL_8)) |
