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authorRahul Batra <rbatra@us.ibm.com>2017-12-20 13:31:00 -0600
committerJoshua Hunsberger <jahunsbe@us.ibm.com>2018-02-01 17:16:20 -0600
commit92a6b35a7bac84c4afeb7ee48974fa650876fe95 (patch)
treed67a5db77e9a2ad89f5a825785654a8c33ff6714
parentc91fbdc36d394d9b97231e70504796cbc7584433 (diff)
downloadtalos-hcode-92a6b35a7bac84c4afeb7ee48974fa650876fe95.tar.gz
talos-hcode-92a6b35a7bac84c4afeb7ee48974fa650876fe95.zip
PM: VDM Prolonged Droop Fix
Key_Cronus_Test=PM_REGRESS Change-Id: I5125ac17b96e4a4bbe08a629d3bf9a7dd7f8b098 Original-Change-Id: I73d38d6029a5b84590d1081855e12c145a535869 CQ: SW413192 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51338 Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
-rw-r--r--import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h15
-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/iota_lnk_cfg.h4
-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h63
-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c34
4 files changed, 74 insertions, 42 deletions
diff --git a/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h b/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h
index 0b62feaa..f51db666 100644
--- a/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h
+++ b/import/chips/p9/common/pmlib/include/wof_sgpe_pgpe_api.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HCODE Project */
/* */
-/* COPYRIGHT 2016,2017 */
+/* COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -69,6 +69,16 @@ enum UPDATE_ACTIVE_TYPES
UPDATE_ACTIVE_QUADS_ENTRY_TYPE_NOTIFY = 0x1
};
+enum SUSPEND_STOP_COMMANDS
+{
+ SUSPEND_STOP_UNSUSPEND_ENTRY = 0x1,
+ SUSPEND_STOP_UNSUSPEND_EXIT = 0x2,
+ SUSPEND_STOP_UNSUSPEND_ENTRY_EXIT = 0x3,
+ SUSPEND_STOP_SUSPEND_ENTRY = 0x5,
+ SUSPEND_STOP_SUSPEND_EXIT = 0x6,
+ SUSPEND_STOP_SUSPEND_ENTRY_EXIT = 0x7
+};
+
//
// Return Codes
//
@@ -140,7 +150,8 @@ typedef union
{
uint32_t msg_num : 8;
uint32_t return_code : 8;
- uint32_t reserved0 : 16;
+ uint32_t command : 8;
+ uint32_t reserved0 : 8;
uint32_t reserved1 : 32;
} fields;
} ipcmsg_p2s_suspend_stop_t;
diff --git a/import/chips/p9/procedures/ppe_closed/cme/iota_lnk_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/iota_lnk_cfg.h
index 35afb672..824bdca1 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/iota_lnk_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/iota_lnk_cfg.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HCODE Project */
/* */
-/* COPYRIGHT 2017 */
+/* COPYRIGHT 2017,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -37,7 +37,7 @@
#define PPE_DEBUG_PTRS_OFFSET CME_DEBUG_PTRS_OFFSET
#define PPE_DEBUG_PTRS_SIZE CME_DEBUG_PTRS_SIZE
-#define PPE_DUMP_PTR_PSTATE_SIZE 0x44
+#define PPE_DUMP_PTR_PSTATE_SIZE 0x48
#define PPE_DUMP_PTR_STOP_SIZE 0x28
#define PPE_DUMP_PTR_COMMON_SIZE 0x4
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h
index 74fdbbe2..67e95b2f 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HCODE Project */
/* */
-/* COPYRIGHT 2015,2017 */
+/* COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -77,14 +77,19 @@
#define IRQ_VEC_PRTY2_CME (uint64_t)(0x0000300000000000)
// Group3: SPWU
#define IRQ_VEC_PRTY3_CME (uint64_t)(0x0003000000000000)
+#define IRQ_SPWU IRQ_VEC_PRTY3_CME
// Group4: RGWU
#define IRQ_VEC_PRTY4_CME (uint64_t)(0x0000C00000000000)
+#define IRQ_RGWU IRQ_VEC_PRTY4_CME
// Group5: PCWU
#define IRQ_VEC_PRTY5_CME (uint64_t)(0x000C000000000000)
+#define IRQ_PCWU IRQ_VEC_PRTY5_CME
// Group6: PM_ACTIVE
#define IRQ_VEC_PRTY6_CME (uint64_t)(0x00000C0000000000)
+#define IRQ_PMACT IRQ_VEC_PRTY6_CME
// Group7: DB1
#define IRQ_VEC_PRTY7_CME (uint64_t)(0x0000000000C00000)
+#define IRQ_DB1 IRQ_VEC_PRTY7_CME
// Group8: DB0
#define IRQ_VEC_PRTY8_CME (uint64_t)(0x000000000C000000)
// Group9: INTERCME_IN0
@@ -96,20 +101,50 @@
// Group12: We should never detect these
#define IRQ_VEC_PRTY12_CME (uint64_t)(0x00C003FBC33FFFFF)
+// Combined vector for all Stop IRQs that need to be manually
+// masked during STOP state processing Do not include DB2 (always unmasked)
+#define IRQ_VEC_STOP_CME (\
+ IRQ_SPWU | \
+ IRQ_RGWU | \
+ IRQ_PCWU | \
+ IRQ_PMACT | \
+ IRQ_DB1 \
+ )
+
// This should be 0xFFFFFFFFFFFFFFFF
-#define IRQ_VEC_PRTY_CHECK ( IRQ_VEC_PRTY0_CME | \
- IRQ_VEC_PRTY1_CME | \
- IRQ_VEC_PRTY2_CME | \
- IRQ_VEC_PRTY3_CME | \
- IRQ_VEC_PRTY4_CME | \
- IRQ_VEC_PRTY5_CME | \
- IRQ_VEC_PRTY6_CME | \
- IRQ_VEC_PRTY7_CME | \
- IRQ_VEC_PRTY8_CME | \
- IRQ_VEC_PRTY9_CME | \
- IRQ_VEC_PRTY10_CME | \
- IRQ_VEC_PRTY11_CME | \
- IRQ_VEC_PRTY12_CME )
+#define IRQ_VEC_PRTY_ALL_CHECK (IRQ_VEC_PRTY0_CME | \
+ IRQ_VEC_PRTY1_CME | \
+ IRQ_VEC_PRTY2_CME | \
+ IRQ_VEC_PRTY3_CME | \
+ IRQ_VEC_PRTY4_CME | \
+ IRQ_VEC_PRTY5_CME | \
+ IRQ_VEC_PRTY6_CME | \
+ IRQ_VEC_PRTY7_CME | \
+ IRQ_VEC_PRTY8_CME | \
+ IRQ_VEC_PRTY9_CME | \
+ IRQ_VEC_PRTY10_CME | \
+ IRQ_VEC_PRTY11_CME | \
+ IRQ_VEC_PRTY12_CME )
+
+#define IRQ_VEC_PRTY_XOR_CHECK (IRQ_VEC_PRTY0_CME ^ \
+ IRQ_VEC_PRTY1_CME ^ \
+ IRQ_VEC_PRTY2_CME ^ \
+ IRQ_VEC_PRTY3_CME ^ \
+ IRQ_VEC_PRTY4_CME ^ \
+ IRQ_VEC_PRTY5_CME ^ \
+ IRQ_VEC_PRTY6_CME ^ \
+ IRQ_VEC_PRTY7_CME ^ \
+ IRQ_VEC_PRTY8_CME ^ \
+ IRQ_VEC_PRTY9_CME ^ \
+ IRQ_VEC_PRTY10_CME ^ \
+ IRQ_VEC_PRTY11_CME ^ \
+ IRQ_VEC_PRTY12_CME )
+
+
+#define compile_assert(name,e) \
+ enum { compile_assert__##name = 1/(e) };
+
+
#if !defined(__IOTA__)
extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2];
extern uint32_t g_current_prty_level;
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c
index f1824bd6..7388698b 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq_priority_table.c
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HCODE Project */
/* */
-/* COPYRIGHT 2017 */
+/* COPYRIGHT 2017,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -81,11 +81,7 @@
IRQ_VEC_PRTY9_CME |
IRQ_VEC_PRTY10_CME |
IRQ_VEC_PRTY11_CME |
- IRQ_VEC_PRTY12_CME |
- // For Stop Entry/Exit related priority groups, mask every other SE/SX
- // related priority group, even higher ones, since the actual procedures
- // will open up EIMR at specific points in the SE/SX sequence.
- IRQ_VEC_PRTY1_CME
+ IRQ_VEC_PRTY12_CME
},
{
IRQ_VEC_PRTY3_CME, /* 3: IDX_PRTY_LVL_SPWU */
@@ -98,12 +94,7 @@
IRQ_VEC_PRTY9_CME |
IRQ_VEC_PRTY10_CME |
IRQ_VEC_PRTY11_CME |
- IRQ_VEC_PRTY12_CME |
- // For Stop Entry/Exit related priority groups, mask every other SE/SX
- // related priority group, even higher ones, since the actual procedures
- // will open up EIMR at specific points in the SE/SX sequence.
- IRQ_VEC_PRTY2_CME |
- IRQ_VEC_PRTY1_CME
+ IRQ_VEC_PRTY12_CME
},
{
IRQ_VEC_PRTY4_CME, /* 4: IDX_PRTY_LVL_RGWU */
@@ -119,9 +110,7 @@
// For Stop Entry/Exit related priority groups, mask every other SE/SX
// related priority group, even higher ones, since the actual procedures
// will open up EIMR at specific points in the SE/SX sequence.
- IRQ_VEC_PRTY3_CME |
- IRQ_VEC_PRTY2_CME |
- IRQ_VEC_PRTY1_CME
+ IRQ_VEC_STOP_CME
},
{
IRQ_VEC_PRTY5_CME, /* 5: IDX_PRTY_LVL_PCWU */
@@ -136,10 +125,7 @@
// For Stop Entry/Exit related priority groups, mask every other SE/SX
// related priority group, even higher ones, since the actual procedures
// will open up EIMR at specific points in the SE/SX sequence.
- IRQ_VEC_PRTY4_CME |
- IRQ_VEC_PRTY3_CME |
- IRQ_VEC_PRTY2_CME |
- IRQ_VEC_PRTY1_CME
+ IRQ_VEC_STOP_CME
},
{
IRQ_VEC_PRTY6_CME, /* 6: IDX_PRTY_LVL_PM_ACTIVE */
@@ -153,11 +139,7 @@
// For Stop Entry/Exit related priority groups, mask every other SE/SX
// related priority group, even higher ones, since the actual procedures
// will open up EIMR at specific points in the SE/SX sequence.
- IRQ_VEC_PRTY5_CME |
- IRQ_VEC_PRTY4_CME |
- IRQ_VEC_PRTY3_CME |
- IRQ_VEC_PRTY2_CME |
- IRQ_VEC_PRTY1_CME
+ IRQ_VEC_STOP_CME
},
{
IRQ_VEC_PRTY7_CME, /* 7: IDX_PRTY_LVL_DB1 */
@@ -224,3 +206,7 @@
IRQ_VEC_PRTY12_CME
}
};
+
+
+compile_assert(ALL_CHECK, IRQ_VEC_PRTY_ALL_CHECK == 0xFFFFFFFFFFFFFFFF);
+compile_assert(XOR_CHECK, IRQ_VEC_PRTY_XOR_CHECK == 0xFFFFFFFFFFFFFFFF);
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