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| author | Yue Du <daviddu@us.ibm.com> | 2018-01-09 21:59:00 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2018-02-01 16:32:55 -0600 |
| commit | 66a96c42a1b0efba75d719bccc9cb77e0d56f4fc (patch) | |
| tree | 699c44537a68a0593d6d3fdedc4c2d4f5c69f58c | |
| parent | 9e01ff6c4b46d32792399bc68c56c253d2de5e92 (diff) | |
| download | talos-hcode-66a96c42a1b0efba75d719bccc9cb77e0d56f4fc.tar.gz talos-hcode-66a96c42a1b0efba75d719bccc9cb77e0d56f4fc.zip | |
STOP: Fix PLS deepest when stop4+ due to self restore wakeup
Key_Cronus_Test=PM_REGRESS
Change-Id: I7e375d8762e3464309e3dc196579df110ceb5862
Original-Change-Id: I4cc1e50a848d627f0ec3917bb8ebd39f20dc9466
CQ: HW420338
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51719
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Dev-Ready: YUE DU <daviddu@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index b80eb67f..36b615ed 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -56,7 +56,6 @@ // 31 | GPR0(0) | SPRD(10101 01000) | MFSPR(339) // constant [40:63] 0000 0000 0000 0000 0000 0000 #define RAM_MFSPR_SPRD_GPR0 0x007C1542A6000000 - #define RAM_MTSPR_SPRD_GPR0 0x007C1543A6000000 // ram_vtid [0:1] 00 @@ -67,17 +66,17 @@ // constant [40:63] 0000 0000 0000 0000 0000 0000 #define RAM_MTSPR_HRMOR_GPR0 0x007C194BA6000000 -#define RAM_MTSPR_LPIDR_GPR0 0x107C1F4BA6000000 - -#define RAM_MFSPR_LPIDR_GPR0 0x007C1F4AA6000000 - // ram_vtid [0:1] 00 // pre_decode [2:5] 0000 // spare [6:7] 00 // instruction [8:39] 0111 11,00 000,1 0111 1101 0,011 1010 011,0 // 31 | GPR0(0) | PSSCR(10111 11010) | MTSPR(467) // constant [40:63] 0000 0000 0000 0000 0000 0000 -#define RAM_MTSPR_PSSCR_GPR0 0x7C17D3A6000000 +#define RAM_MTSPR_PSSCR_GPR0 0x007C17D3A6000000 +#define RAM_MFSPR_PSSCR_GPR0 0x007C17D2A6000000 + +#define RAM_MTSPR_LPIDR_GPR0 0x107C1F4BA6000000 +#define RAM_MFSPR_LPIDR_GPR0 0x007C1F4AA6000000 #if HW402407_NDD1_TLBIE_STOP_WORKAROUND #define POWMAN_RESERVED_LPID 0xFFF @@ -107,6 +106,7 @@ #define SPURR_FREQ_SCALE 0x20010AA0 #define SPURR_FREQ_REF 0x20010AA1 #define IMA_EVENT_MASK 0x20010AA8 +#define CORE_THREAD_STATE 0x20010AB3 #define HRMOR 0x20010AB9 #define C_SYNC_CONFIG 0x20030000 |
