STOP: Serialize Scan0 of even and odd cores to reduce droop on wakeup.

  -- Also change to poweron the cores in parallel
Key_Cronus_Test=PM_REGRESS

Change-Id: Id58abe6aa61e333b99d416ea4b3746789fab819d
CQ: SW411197
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50891
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

2 files changed, 17 insertions, 34 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
index 31007cc4..8ddd904c 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2015,2017                                                    */
+/* COPYRIGHT 2015,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -109,16 +109,18 @@ p9_hcd_core_chiplet_reset(uint32_t core)
             scom_data.words.lower |= BIT32(19);
 #endif
             CME_PUTSCOM(C_OPCG_ALIGN, core_mask, scom_data.value);
-        }
-    }
 
-    // Marker for scan0
-    MARK_TRAP(SX_CHIPLET_RESET_SCAN0)
+            // Marker for scan0
+            MARK_TRAP(SX_CHIPLET_RESET_SCAN0)
 #if !SKIP_SCAN0
-    p9_hcd_core_scan0(core, SCAN0_REGION_ALL, SCAN0_TYPE_GPTR_REPR_TIME);
-    p9_hcd_core_scan0(core, SCAN0_REGION_ALL, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME);
+            p9_hcd_core_scan0(core_mask, SCAN0_REGION_ALL, SCAN0_TYPE_GPTR_REPR_TIME);
+            p9_hcd_core_scan0(core_mask, SCAN0_REGION_ALL, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME);
 #endif
 
+        }
+    }
+
+
     /// content of p9_hcd_core_dcc_skewadjust below:
     PK_TRACE("Drop core DCC bypass via NET_CTRL[1]");
     CME_PUTSCOM(CPPM_NC1INDIR_CLR, core, BIT64(1));
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
index c17ed612..1d6beb6a 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2015,2017                                                    */
+/* COPYRIGHT 2015,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -52,36 +52,17 @@ p9_hcd_core_poweron(uint32_t core)
     PK_TRACE("Prepare PFET Controls");
     CME_PUTSCOM(PPM_PFCS_CLR, core, BIT64(4) | BIT64(5) | BIT64(8));
 
-    // Serialize only the PFET power-on for the Core Pair
-    if (core & CME_MASK_C0)
-    {
-        // vdd_pfet_force_state = 11 (Force Von)
-        PK_TRACE("Power On Core VDD");
-        CME_PUTSCOM(PPM_PFCS_OR, CME_MASK_C0, BITS64(0, 2));
-
-        PK_TRACE("Poll for vdd_pfets_enabled_sense");
+    // vdd_pfet_force_state = 11 (Force Von)
+    PK_TRACE("Power On Core VDD");
+    CME_PUTSCOM(PPM_PFCS_OR, core, BITS64(0, 2));
 
-        do
-        {
-            CME_GETSCOM(PPM_PFSNS, CME_MASK_C0, scom_data);
-        }
-        while(!(scom_data & BIT64(0)));
-    }
+    PK_TRACE("Poll for vdd_pfets_enabled_sense");
 
-    if (core & CME_MASK_C1)
+    do
     {
-        // vdd_pfet_force_state = 11 (Force Von)
-        PK_TRACE("Power On Core VDD");
-        CME_PUTSCOM(PPM_PFCS_OR, CME_MASK_C1, BITS64(0, 2));
-
-        PK_TRACE("Poll for vdd_pfets_enabled_sense");
-
-        do
-        {
-            CME_GETSCOM(PPM_PFSNS, CME_MASK_C1, scom_data);
-        }
-        while(!(scom_data & BIT64(0)));
+        CME_GETSCOM_AND(PPM_PFSNS, core, scom_data);
     }
+    while(!(scom_data & BIT64(0)));
 
     // vdd_pfet_force_state = 00 (Nop)
     PK_TRACE("Turn Off Force Von");