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| author | Yue Du <daviddu@us.ibm.com> | 2018-04-05 10:47:22 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-04-13 09:17:40 -0500 |
| commit | 46385e17566c4e12c914414dd0608889d15a798e (patch) | |
| tree | 384126d1aec3e8a9acd5d9c64641464c8a24653d | |
| parent | 48545f1d475a93ff38be0f7f139d610681eed695 (diff) | |
| download | talos-hcode-46385e17566c4e12c914414dd0608889d15a798e.tar.gz talos-hcode-46385e17566c4e12c914414dd0608889d15a798e.zip | |
STOP: Clear ALL OPITs in SGPE Init to fix PM_Reset
Key_Cronus_Test=PM_REGRESS
Change-Id: I55c9295ddbdd46d1bd6d3eaa550676445c6cd41b
CQ: SW423226
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56800
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c index a90e0eb3..f1d4f325 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c @@ -473,6 +473,17 @@ p9_sgpe_stop_init() // Hostboot Mode Booting CME //-------------------------------------------------------------------------- + PK_TRACE_INF("Setup: Clear Type 0,2,3,6 and ipi_lo_3 interrupts"); + out32(OCB_OISR1_CLR, (BIT32(13) | BITS32(15, 2) | BIT32(19) | BIT32(29))); + out32(OCB_OPITNPRA_CLR(0), BITS32(0, 24)); + out32(OCB_OPITNPRA_CLR(1), BITS32(0, 24)); + out32(OCB_OPITNPRA_CLR(2), BITS32(0, 24)); + out32(OCB_OPITNPRA_CLR(3), BITS32(0, 24)); + out32(OCB_OPITNPRA_CLR(4), BITS32(0, 24)); + out32(OCB_OPITNPRA_CLR(5), BITS32(0, 24)); + out32(OCB_OPIT6PRB_CLR, BITS32(0, 6)); + out32(OCB_OPIT7PRB_CLR, BITS32(0, 6)); + #if !SKIP_CME_BOOT_IPL_HB uint32_t cme_flags = 0; @@ -635,12 +646,7 @@ p9_sgpe_stop_init() out32(OCB_OISR0_CLR, (BIT32(8) | BIT32(16))); out32(OCB_OIMR0_CLR, (BIT32(8) | BIT32(16))); - PK_TRACE_INF("Setup: Clear and Unmask Type 0, 2,3,6 and ipi_lo_3 interrupts"); - out32(OCB_OISR1_CLR, (BIT32(13) | BITS32(15, 2) | BIT32(19) | BIT32(29))); - out32(OCB_OPITNPRA_CLR(0), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(2), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(3), BITS32(0, 24)); - out32(OCB_OPIT6PRB_CLR, BITS32(0, 6)); + PK_TRACE_INF("Setup: Unmask Type 0, 2,3,6 and ipi_lo_3 interrupts"); out32(OCB_OIMR1_CLR, BIT32(13) | (BITS32(15, 2) | BIT32(19) | BIT32(29))); //-------------------------------------------------------------------------- |
