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| author | Luke C. Murray <murrayl@us.ibm.com> | 2017-12-06 10:48:04 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2018-02-01 15:48:04 -0600 |
| commit | 22c96c9f098c757228a9dd3e5ce9065f4a6a2945 (patch) | |
| tree | a4d62c962498a67991929f77a1524b24736a5851 | |
| parent | d53628f9258903f1d3acd281ebe6464255cd9fcc (diff) | |
| download | talos-hcode-22c96c9f098c757228a9dd3e5ce9065f4a6a2945.tar.gz talos-hcode-22c96c9f098c757228a9dd3e5ce9065f4a6a2945.zip | |
Increase cache data timeout values
The PCIe timeout have increased to 66-100ms, so we need to double
the NCU master timeouts to be above these timeouts. This has a
chain effect causing the L2/L3 master timeouts to increase which
causes the tlbie snooper to increase which causes the tlbie master
to increase.
This would also ususally cause the core timeout to increas, but
the core is already at around 13 seconds, so there is headroom
there.
Change-Id: I5930076151267a9bfa66e24edef0985c165db0b7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50582
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c index 9223019f..a718bcb5 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c @@ -125,7 +125,7 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8) GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG0, quad, ex_index), scom_data.value); scom_data.words.upper &= ~(BIT32(1) | BITS32(14, 8) | BIT32(22)); - scom_data.words.upper |= (BIT32(2) | BIT32(11) | BIT32(17) | BIT32(19)); + scom_data.words.upper |= (BIT32(2) | BIT32(11) | BITS32(17, 2)); #if NIMBUS_DD_LEVEL != 10 @@ -213,8 +213,11 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8) // EXP.NC.NCMISC.NCSCOMS.TLB_STG2_HANG_POLL_PULSE_DIV // EXP.NC.NCMISC.NCSCOMS.MASTER_TLB_DATA_POLL_PULSE_DIV + scom_data.words.lower = 0; + scom_data.words.upper = (BITS32(3, 2) | BIT32(13) | BIT32(18) | BIT32(22) | BIT32(29)); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_NCU_MODE_REG2, quad, ex_index), - 0x1402220200000000); + scom_data.value); // p9_ncu_scom: EX_NCU_MODE_REG3 // EXP.NC.NCMISC.NCSCOMS.TLBIE_STALL_EN @@ -282,7 +285,7 @@ p9_hcd_cache_scominit(uint32_t quad, uint32_t m_ex, int is_stop8) GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L2_MODE_REG1, quad, ex_index), scom_data.value); scom_data.words.upper &= BITS32(4, 8); - scom_data.words.upper |= (BIT32(7) | BIT32(9)); + scom_data.words.upper |= BITS32(7, 2); if (addr_extension != 0) { |
