talos-hcode/import/chips/p9/common/include, branch dd2.1

update OBUS PLL buckets for p9n dd22, p9c dd11

2018-02-01T23:19:20+00:00

p9n dd22 -> swap bucket1, bucket3 content bucket1 will now produce 25.78125 bucket3 will now produce 25.00000 p9c dd11 -> replace bucket3 content bucket3 will now produce 25.625 initfile changes are comment only -- no change in EMTS Change-Id: Ie49b9b4af81358ee8fa831ffe8fd2c33650dcc50 CQ: HW433692 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51851 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Thi N. Tran Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer

Adding p9c_11 support.

2017-11-17T21:08:19+00:00

Change-Id: If9ffe53acd009c1520cdd7f162e88fd235799225 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46361 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Soma Bhanutej Tested-by: FSP CI Jenkins Reviewed-by: Thi N. Tran Reviewed-by: Jennifer A. Stofer

PLL updates for filter BG, BW including OBUS tank coreqs

2017-10-24T00:33:47+00:00

p9.filter.pll.scan.initfile adjust BG offset to -1 for P9n DD2.[12], P9c DD1.1 apply BW updates to P9n DD2.2, P9c DD1.[01] p9.obus.pll.scan.initfile apply BW updates to P9n DD2.2, P9c DD1.[01] with tests 108, 109, 110 p9_frequency_buckets: default Cumulus OBUS bucket 0 to 25.625gbs chip_ec_attributes.xml add feature attributes for BG, BW controls Change-Id: I5e06da5267db70bb1d6e6eae066611577d32ac7b CQ: HW423532 CQ: HW423535 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48267 Reviewed-by: Ann C. Wu Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Thi N. Tran Reviewed-by: Matt K. Light Reviewed-by: Jennifer A. Stofer

update HWP level metadata for nest, common files

2017-10-24T00:27:12+00:00

Change-Id: I451695b8ae1d8f7d5ed6d512631992dea98b5ee8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46967 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Benjamin Gass Reviewed-by: Thi N. Tran Reviewed-by: Jennifer A. Stofer

Add OBUS pll freq list for Axone and p9n dd2.2

2017-10-24T00:06:56+00:00

Change-Id: I3fece1e530fa9119ef8174529379019fa4a43ed8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45014 Tested-by: FSP CI Jenkins Dev-Ready: Brent Wieman Tested-by: Jenkins Server Reviewed-by: Matt K. Light Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej Reviewed-by: Jennifer A. Stofer

Synchronous stopclk procedure for Quad

2017-10-23T23:53:48+00:00

Change-Id: Id31daf8c02b74d979927540346a3cef5f88768be RTC: 175615 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34935 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: YUE DU Reviewed-by: SRINIVAS V. POLISETTY Reviewed-by: Joachim Fenkes Reviewed-by: RAJA DAS Dev-Ready: Soma Bhanutej Reviewed-by: Jennifer A. Stofer

p9.obus.pll.scan.initfile -- adjust Nimbus DD2 POR to 25gbs

2017-10-23T23:36:08+00:00

Change-Id: I551322dcaaf57cdcb76371eef4da4f5976501725 CQ: HW416892 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43424 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Camille R. Mann Reviewed-by: Thi N. Tran Reviewed-by: Joseph J. McGill

PCIe updates for Nimbus DD2 GEN4 operation

2017-10-23T23:04:03+00:00

adjust REFISRC, REFISINK, VBGENDOC in PCIE PLL inits for all ECs set EDMOD in RX VGA Control Register 1 for DD2 only Change-Id: Ib10b02fb49dbf7ccf8dcad2ada5ac463a927d4c7 CQ: HW414759 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42423 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Ricardo Mata Reviewed-by: Jenny Huynh Reviewed-by: Jennifer A. Stofer

add support for OBUS PLL buckets

2017-10-23T22:54:54+00:00

p9_frequency_buckets.H p9.obus.pll.scan.initfile document and support base frequencies 1611 MHz - 25.78G, 156.25 MHz ref 1250 MHz - 25G, 156.25 MHz ref 1200 MHz - 19.2G, 133.33 MHz ref pervasive_attributes.xml define ATTR_OB[0123]_PLL_BUCKET to hold encoded ring bucket select value nest_attributes.xml define ATTR_FREQ_O_MHZ array to hold per chiplet OBUS frequency retain ATTR_FREQ_A_MHZ to serve as FBC A link frequency indicator p9_setup_sbe_config.C p9_sbe_attr_setup.C transmit bucket selection through FSP/BMC->SBE mailbox encode OBUS bucket selects in Scratch Reg2 bits 24:31 p9_sbe_chiplet_pll_initf.C p9_sbe_chiplet_pll_initf_errors.xml scan correct ring image based on bucket selector attributes p9_ringId.C p9_ringId.H p9_ring_id.h accomodate three copies of obX_pll_bndy (use ID previously reserved for obX_pll_func, which should not be necessary to scan init) scan_procedures.mk generateWrapper.pl initCompiler infrastructure changes to support build of bucket data p9.fbc.ab_hp.scom.initfile p9.fbc.ioo_tl.scom.initfile p9_tod_setup.C updates to handle A,O frequency attribute changes Change-Id: I42f9bb4037a587f7e3ec8dd9848bdb853ac3d7a0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40159 Tested-by: Jenkins Server Reviewed-by: Matt K. Light Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Dean Sanner Reviewed-by: Jennifer A. Stofer

Move p9n2 SCOM headers into base chip include dir, mirror to PPE/HB

2017-10-23T22:53:33+00:00

Change-Id: I5a4b929fad4aa954ad413eb73861ab1e53135360 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42026 Tested-by: PPE CI Tested-by: Hostboot CI Dev-Ready: Matt K. Light Reviewed-by: Benjamin Gass Tested-by: Jenkins Server Reviewed-by: Joseph J. McGill Reviewed-by: Jennifer A. Stofer