talos-hcode/import/chips/common, branch master

Risk level 3/4/5 support: Step 1 - backward compatibility and v6 image

2018-04-26T17:17:20+00:00

- Introducing RV_RL3/4/5 ring variant (RV) support for EC/EQ chiplets. - Dropping RV support for all chiplet's instance rings which saves 456 Quad bytes and 58 Nest bytes in Seeprom's TOR slots (compared to master). - Each additional risk level adds 144 bytes in Seeprom TOR slots. - Various changes to data names associated with ring variants to clarify that the notion of ring variants is now specific only to Common rings while Instance rings only have the BASE variant. - Also, removed backwards compatibility to TOR v5, i.e. from before we introduced RL2 in february. Assumption is that all images/drivers used in fips910/920 and OP920 are TOR v6. - This commit produces a TOR v6 image to ensure EKB FSP CI success. Key_Cronus_Test=XIP_REGRESS Change-Id: Icfcb1e68fd74a10ffc48ee7a5da528a8042ef3b1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56973 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Cronus HW CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Kahn C. Evans Reviewed-by: James N. Klazynski Reviewed-by: Joseph J. McGill

Code restruct: ring_apply

2018-04-06T17:38:08+00:00

- Consolidating the three _image_ring_generation functions into a single shared, and renamed, ring_section_generation function, - Moving several data centric functions into common_ringId API, - Use of sizeof() instead of hardcoded assumptions about structure or data type sizes, - Renaming of variables which makes sense in the context of the scope of this commit, such as: - ringBuffer renamed to ringSection - ringBufSize renamed to ringSectionSize and type changed to uint32_t - Removes the backward compatibility to TORV3/V4 and now only works with latest TOR version, i.e. 6 at this point. About the Hw_ImageBuild_Prereq: - 51511 must have fully propagated into all repos and drivers used in FSP CI tests before this commit (43175) can be merged. 43175 removes the TORV3/V4 backwards compatibility to support TOR ring sections that have TOR level DD coordination. Key_Cronus_Test=XIP_REGRESS Change-Id: I0af25fa623c1c523eb0297e475066497787f3d15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43175 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: Cronus HW CI Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta

Additional risk level support - (step 1) Backward compatibility

2018-03-22T19:07:51+00:00

The purpose of this commit is to avoid a coreq situation by ensuring this commit is fully propagated through our repos and test drivers before introducing the change to the new HW image with two RLs. The commit enables simultaneous support for producing a HW image and retrieving rings from an image that has either one or two risk level (RL) rings in the .rings section. The commit however does NOT actually, yet, make any changes to the image which is the aim of the (step 2) commit 53292. Nor does this commit generate any raw ring files or process any RL2 level rings yet. Again this will happen in 53292. The commit also includes, - various related cleanups in data naming and ring file processing, - some data and invironment specific parts in ring_apply.C have been moved to common_ringId.C. Key_Cronus_Test=XIP_REGRESS HW-Image-Prereq=53292 - This commit (52659) must be fully merged before merging 53292. Change-Id: I6f0b9614f7f7fa8f79f6d180f10d260f99d52562 Original-Change-Id: I402d53c4a3ca6a084c958321069cc6f60e04ad24 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52659 Tested-by: FSP CI Jenkins Tested-by: Cronus HW CI Dev-Ready: Joseph J. McGill Reviewed-by: Joseph J. McGill Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer

Additional risk level support - (step 2) Updating the image w/RL2

2018-03-22T19:06:34+00:00

This commit changes the images' .rings section by adding the TOR RL2 variant slot to the runtime Quad chiplets, EQ and EC. Specifically, we have changed the definition of the ATTR_RISK_LEVEL attribute to now have three risk levels, RL0 (prev FALSE), RL1 (prev TRUE) and RL2 (new). To accomodate RL2, a new "override" txt file has been created, ./attribute_ovd/runtime_risk2.txt and changes to many other files using the ATTR_RISK_LEVEL attrib have been updated as well. Lastly, and to allow for the inclusion of RL2 rings in the HW image, the TOR_VERSION has been updated to version 6 which will allow for RL2 support in the ring ID metadata files. p9_setup_sbe_config is updated to write the RISK_LEVEL value into scratch 3 bits 28:31, and deprecate the existing mailbox. RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's only function is to seed mailboxes which are empty via the attribute state present in the SEEPROM. Since RISK_LEVEL is zero at image build time, and explicitly cleared as a result of every customization, there's logically no need to process the RISK_LEVEL here. PPE changes to accomodate the new RISK_LEVEL mailbox location need to be implemented in the PLAT code: src/hwpf/target.C Key_Cronus_Test=XIP_REGRESS HW-ImageBuild-Preqeq=52659 - 52659 must be fully merged in Cronus and HB before this commit (53292) can be merged. This is to avoid a Coreq situation. CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Cronus HW CI Tested-by: FSP CI Jenkins Tested-by: Hostboot CI Reviewed-by: Richard J. Knight Reviewed-by: Sachin Gupta Reviewed-by: Jennifer A. Stofer

Additional risk level support - (step 1) Backward compatibility

2018-03-22T19:06:33+00:00

The purpose of this commit is to avoid a coreq situation by ensuring this commit is fully propagated through our repos and test drivers before introducing the change to the new HW image with two RLs. The commit enables simultaneous support for producing a HW image and retrieving rings from an image that has either one or two risk level (RL) rings in the .rings section. The commit however does NOT actually, yet, make any changes to the image which is the aim of the (step 2) commit 53292. Nor does this commit generate any raw ring files or process any RL2 level rings yet. Again this will happen in 53292. The commit also includes, - various related cleanups in data naming and ring file processing, - some data and invironment specific parts in ring_apply.C have been moved to common_ringId.C. Key_Cronus_Test=XIP_REGRESS HW-Image-Prereq=53292 - This commit (52659) must be fully merged before merging 53292. Change-Id: I0c50de351045c9f54db9494ae4b0e14f4beafbbd Original-Change-Id: I402d53c4a3ca6a084c958321069cc6f60e04ad24 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52659 Tested-by: FSP CI Jenkins Tested-by: Cronus HW CI Dev-Ready: Joseph J. McGill Reviewed-by: Joseph J. McGill Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer

Moving DD specific ring coord from TOR to XIP (step 2)

2018-03-22T19:06:32+00:00

Step 2 - Producing XIP coordinated DD packaging of the TOR ring sections. - Updated ring_apply to produce N number of DD specific .rings ring sections and which is then assembled using the DD container API. Key_Cronus_Test=XIP_REGRESS HW-ImageBuild-Prereq=42751 - 42751 must be fully merged in Cronus and HB before this commit (51511) can be merged. This is to avoid a Coreq situation. Change-Id: I45a73848f3e8683aae9dcc26fcdf282259c38fcc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51511 Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Cronus HW CI Tested-by: FSP CI Jenkins Reviewed-by: Thi N. Tran Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer

TOR API code restruct: Fixing missing symbols in common_ringId API.

2018-02-02T20:39:49+00:00

Change-Id: Iaf622a739c1d9d9bd4102647170000ff6f3eb686 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50496 Reviewed-by: Thi N. Tran Reviewed-by: Kahn C. Evans Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Dev-Ready: Kahn C. Evans Reviewed-by: Jennifer A. Stofer

Code restruct: TOR API

2018-02-02T20:39:48+00:00

Key_Cronus_Test=XIP_REGRESS Code restructuring aiming at: - utilizing TOR magic header info - enforce a common approach for - extracting metadata for all image,chipType combinations - traversing images for all image,chipType combinations - shrinking code size by reusing common code segments - improve readability by - separating more clearly metadata extraction and image traversal - slight rearrange of certain code segments - remove leftover hardcoded assumptions about ring/TOR data and structs - variables appropriately renamed and now all using camel style Change-Id: Ie292d11201bba9a127c44af83cce3c3fc8da5c66 Original-Change-Id: I50ace8b2fdb340a97ce6d74ce545c5e1acd21c40 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38863 Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Cronus HW CI Tested-by: FSP CI Jenkins Tested-by: Hostboot CI Reviewed-by: GIRISANKAR PAULRAJ Reviewed-by: Thi N. Tran Reviewed-by: Jennifer A. Stofer

Code restruct: TOR API

2018-02-02T20:39:24+00:00

Key_Cronus_Test=XIP_REGRESS Code restructuring aiming at: - utilizing TOR magic header info - enforce a common approach for - extracting metadata for all image,chipType combinations - traversing images for all image,chipType combinations - shrinking code size by reusing common code segments - improve readability by - separating more clearly metadata extraction and image traversal - slight rearrange of certain code segments - remove leftover hardcoded assumptions about ring/TOR data and structs - variables appropriately renamed and now all using camel style Change-Id: I81ab15aae820ac9cca78ae9c519a5c2599b95584 Original-Change-Id: I50ace8b2fdb340a97ce6d74ce545c5e1acd21c40 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38863 Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Cronus HW CI Tested-by: FSP CI Jenkins Tested-by: Hostboot CI Reviewed-by: GIRISANKAR PAULRAJ Reviewed-by: Thi N. Tran Reviewed-by: Jennifer A. Stofer

Moving DD specific ring coord from TOR to XIP (step 1)

2018-02-01T22:15:40+00:00

Step 1 - Ensuring backwards compatibility in TOR and XIP APIs to avoid co-req issue. - Updated TOR and XIP APIs, xip_tool and ipl_build to handle both types of DD coordination. Key_Cronus_Test=XIP_REGRESS HW-Image-Prereq=51511 - 51511 changes the .rings section DD level packaging. This commit (42751) prepares the TOR API and associated codes to handle the new .rings layout while also making the TOR API backwards compatible to the existing .rings section. Change-Id: I7d254340808ca9270fc1c96414102794fcffeabe Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42751 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Cronus HW CI Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Sumit Kumar Reviewed-by: Jennifer A. Stofer