From 7f29521414fe03f8734b02daa229890d0bf3f07d Mon Sep 17 00:00:00 2001 From: rguenth Date: Tue, 24 Jan 2012 09:17:01 +0000 Subject: 2012-01-24 Richard Guenther Forward-port to trunk 2010-09-21 Jakub Jelinek PR middle-end/45678 * expr.c (expand_expr_real_1) : If op0 isn't sufficiently aligned and there is movmisalignM insn for mode, use it to load op0 into a temporary register. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@183470 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/expr.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'gcc/expr.c') diff --git a/gcc/expr.c b/gcc/expr.c index fb93346eb99..e181ee3ef0d 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -10044,10 +10044,32 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, results. */ if (MEM_P (op0)) { + enum insn_code icode; + op0 = copy_rtx (op0); if (TYPE_ALIGN_OK (type)) set_mem_align (op0, MAX (MEM_ALIGN (op0), TYPE_ALIGN (type))); + else if (mode != BLKmode + && MEM_ALIGN (op0) < GET_MODE_ALIGNMENT (mode) + /* If the target does have special handling for unaligned + loads of mode then use them. */ + && ((icode = optab_handler (movmisalign_optab, mode)) + != CODE_FOR_nothing)) + { + rtx reg, insn; + + op0 = adjust_address (op0, mode, 0); + /* We've already validated the memory, and we're creating a + new pseudo destination. The predicates really can't + fail. */ + reg = gen_reg_rtx (mode); + + /* Nor can the insn generator. */ + insn = GEN_FCN (icode) (reg, op0); + emit_insn (insn); + return reg; + } else if (STRICT_ALIGNMENT && mode != BLKmode && MEM_ALIGN (op0) < GET_MODE_ALIGNMENT (mode)) -- cgit v1.2.3