From b8bc42e99d868c3a5913d34a1ebeaf1b58d17dc8 Mon Sep 17 00:00:00 2001
From: zack <zack@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Sat, 25 Oct 2003 02:03:40 +0000
Subject: 	* genmodes.c (struct mode_data): Add contained and next_cont 
 fields. 	(complete_mode): Maintain linked list of modes that have a 
 given component. 	(emit_mode_unit_size): Delete. 	(emit_mode_nunits):
 New. 	(emit_insn_modes_c): Update to match. 	(emit_mode_adjustments):
 Propagate size and alignment 	adjustments from component modes to their
 containers. 	* machmode.h (mode_unit_size): Delete. 	(mode_nunits): New. 
 (GET_MODE_NUNITS): Just return the value in the table. 
 (GET_MODE_UNIT_SIZE): Compute using GET_MODE_INNER and 	GET_MODE_SIZE.
 	* expmed.c (store_bit_field, extract_bit_field): Can use a 	plain
 move instruction if bitsize >= GET_MODE_BITSIZE of 	destination/source
 mode, respectively. 	* varasm.c (assemble_real): Write out the full size of
 the 	constant, not just its bitsize. 	(output_constant): Honor
 TYPE_MODE of TREE_REAL_CSTs.

	* config/ia64/ia64-modes.def: Define XFmode as well as TFmode.
	Use ADJUST_BYTESIZE and ADJUST_ALIGNMENT to set size and
	alignment of XF and TF modes in compliance with ia64 ABIs.
	Can now hardwire the format of both modes.
	* config/ia64/ia64.c: Change TFmode to XFmode wherever appropriate.
	(general_tfmode_operand, destination_tfmode_operand)
	(tfreg_or_fp01_operand, spill_tfmode_operand): Rename to
	general_xfmode_operand, destination_xfmode_operand,
	xfreg_or_fp01_operand, spill_xfmode_operand respectively.
	(ia64_init_builtins): Make TYPE_PRECISION of fpreg_type
	and float80_type be 96 so they get XFmode.  Use !TARGET_HPUX,
	not INTEL_EXTENDED_IEEE_FORMAT, to decide how to define
	__float128.
	* config/ia64/ia64.h: Default TARGET_HPUX to 0.
	Change TFmode to XFmode wherever appropriate.  Remove all
	references to INTEL_EXTENDED_IEEE_FORMAT.
	(LONG_DOUBLE_TYPE_SIZE): Varies with TARGET_HPUX.
	(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Define (always 96).
	(PREDICATE_CODES): Update to match function renames.
	* config/ia64/ia64.md: Change TF to XF throughout; rename all
	patterns to match.  Remove all references to
	INTEL_EXTENDED_IEEE_FORMAT.  Update predicate calls to match
	function renames.
	* config/ia64/ia64-protos.c: Update all prototypes to match
	renamed functions.
	* config/ia64/hpux.h: Redefine TARGET_HPUX to 1.
	Remove all references to INTEL_EXTENDED_IEEE_FORMAT.
	* config/ia64/lib1funcs.asm: Add __divxf3 as new name for
	__divtf3; keep old name for backward compatibility.
	(L__compat): New section providing forwarding stubs for
	__fixtfti, __fixunstfti, __floattitf.
	* config/ia64/t-ia64: Add __compat to LIB1ASMFUNCS.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@72916 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/expmed.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'gcc/expmed.c')

diff --git a/gcc/expmed.c b/gcc/expmed.c
index d93be934be3..da631c940d8 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -326,13 +326,16 @@ store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
 
      If the target is memory, storing any naturally aligned field can be
      done with a simple store.  For targets that support fast unaligned
-     memory, any naturally sized, unit aligned field can be done directly.  */
+     memory, any naturally sized, unit aligned field can be done directly.
+
+     It's okay if the requested bitsize is greater than fieldmode's
+     bitsize; that just means the mode has padding bits.  */
 
   byte_offset = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
                 + (offset * UNITS_PER_WORD);
 
   if (bitpos == 0
-      && bitsize == GET_MODE_BITSIZE (fieldmode)
+      && bitsize >= GET_MODE_BITSIZE (fieldmode)
       && (GET_CODE (op0) != MEM
 	  ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
 	     || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
@@ -1029,9 +1032,11 @@ extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
   if (GET_CODE (op0) == REG
       && mode == GET_MODE (op0)
       && bitnum == 0
-      && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
+      && bitsize >= GET_MODE_BITSIZE (GET_MODE (op0)))
     {
-      /* We're trying to extract a full register from itself.  */
+      /* We're trying to extract a full register from itself.
+         (If the requested bitsize is greater than the bitsize of op0,
+         that just means op0's mode has padding bits.)  */
       return op0;
     }
 
-- 
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