| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
|
|
|
| |
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208602 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
(eligible_for_call_delay): New prototype.
* config/sparc/sparc.c (tls_call_delay): Rename into...
(eligible_for_call_delay): ...this. Return false if the instruction
cannot be put in the delay slot of a branch.
(eligible_for_restore_insn): Simplify.
(eligible_for_return_delay): Return false if the instruction cannot be
put in the delay slot of a branch and simplify.
(eligible_for_sibcall_delay): Return false if the instruction cannot be
put in the delay slot of a branch.
* config/sparc/sparc.md (fix_ut699): New attribute.
(tls_call_delay): Delete.
(in_call_delay): Reimplement.
(eligible_for_sibcall_delay): Rename into...
(in_sibcall_delay): ...this.
(eligible_for_return_delay): Rename into...
(in_return_delay): ...this.
(in_branch_delay): Reimplement.
(in_uncond_branch_delay): Delete.
(in_annul_branch_delay): Delete.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208597 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
PR libfortran/58324
* gfortran.dg/list_read_12.f90: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208592 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
PR fortran/55207
* decl.c (match_attr_spec): Variables in the main program implicitly
get the SAVE attribute in Fortran 2008.
2014-03-15 Janus Weil <janus@gcc.gnu.org>
PR fortran/55207
* gfortran.dg/assumed_rank_7.f90: Explicitly deallocate variables.
* gfortran.dg/c_ptr_tests_16.f90: Put into subroutine.
* gfortran.dg/inline_sum_bounds_check_1.f90: Add
-Wno-aggressive-loop-optimizations and remove an unused variable.
* gfortran.dg/intent_optimize_1.f90: Put into subroutine.
* gfortran.dg/pointer_init_9.f90: New.
* gfortran.dg/volatile4.f90: Put into subroutine.
* gfortran.dg/volatile6.f90: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208590 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* config/i386/i386.md (floathi<X87MODEF>2): Delete expander; rename
define_insn from *floathi<X87MODEF>2_i387; allow nonimmediate_operand.
(*floathi<X87MODEF>2_i387_with_temp): Remove.
(floathi splitters): Remove.
(float<SWI48x>xf2): New pattern.
(float<SWI48><MODEF>2): Rename from float<SWI48x><X87MODEF>2. Drop
code that tried to handle DImode for 32-bit, but which was excluded
by the pattern's condition. Drop allocation of stack temporary.
(*floatsi<MODEF>2_vector_mixed_with_temp): Remove.
(*float<SWI48><MODEF>2_mixed_with_temp): Remove.
(*float<SWI48><MODEF>2_mixed_interunit): Remove.
(*float<SWI48><MODEF>2_mixed_nointerunit): Remove.
(*floatsi<MODEF>2_vector_sse_with_temp): Remove.
(*float<SWI48><MODEF>2_sse_with_temp): Remove.
(*float<SWI48><MODEF>2_sse_interunit): Remove.
(*float<SWI48><MODEF>2_sse_nointerunit): Remove.
(*float<SWI48x><X87MODEF>2_i387_with_temp): Remove.
(*float<SWI48x><X87MODEF>2_i387): Remove.
(all float _with_temp splitters): Remove.
(*float<SWI48x><MODEF>2_i387): New pattern.
(*float<SWI48><MODEF>2_sse): New pattern.
(float TARGET_USE_VECTOR_CONVERTS splitters): Merge them.
(float TARGET_SSE_PARTIAL_REG_DEPENDENCY splitters): Merge them.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208587 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
PR c++/58678
* search.c (get_pure_virtuals): Handle abstract dtor here.
(dfs_get_pure_virtuals): Not here.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208586 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
| |
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208585 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
PR fortran/60392
* trans-array.c (gfc_conv_array_parameter): Don't reuse the descriptor
if it has transposed dimensions.
testsuite/
PR fortran/60392
* gfortran.dg/transpose_4.f90: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208581 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
| |
* search.c (dfs_get_pure_virtuals): Treat the destructor of an
abstract class as pure.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208573 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
| |
* common.opt (dump_base_name_prefixed): New Variable.
* opts.c (finish_options): Don't prepend directory to x_dump_base_name
if x_dump_base_name_prefixed is already set, set it at the end.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208571 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
PR rtl-optimization/60508
* lra-constraints.c (get_reload_reg): Add new parameter
in_subreg_p.
(process_addr_reg, simplify_operand_subreg, curr_insn_transform):
Pass the new parameter values.
2014-03-14 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/60508
* gcc.target/i386/pr60508.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208570 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
| |
* d++.dg/warn/anonymous-namespace-6.C: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208569 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
* common.opt: Revert unintented changes from r205065.
* opts.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208568 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
| |
PR middle-end/60518
* cfghooks.c (split_block): Properly adjust all loops the
block was a latch of.
* g++.dg/pr60518.C: New testcase.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208567 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
PR lto/60461
* ipa-prop.c (ipa_modify_call_arguments): Fix iteration condition
and simplify it.
testsuite/
* gcc.dg/lto/pr60461_0.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208566 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
| |
gcc/testsuite/
* gcc.dg/lto/save-temps_0.c: New file.
* lib/gcc-dg.exp (cleanup-saved-temps): Handle LTO temporaries.
* lib/lto.exp (lto-execute): Cleanup LTO temporaries.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208563 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
| |
* config/avr/avr.c (avr_set_current_function): Pass function name
through default_strip_name_encoding before sanity checking instead
of skipping the first char of the assembler name.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208562 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
| |
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208561 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* c-pragma.c (apply_pragma_weak): Only look at
TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) if
DECL_ASSEMBLER_NAME_SET_P (decl).
(maybe_apply_pending_pragma_weaks): Exit early if
vec_safe_is_empty (pending_weaks) rather than only when
!pending_weaks.
(maybe_apply_pragma_weak): Likewise. If !DECL_ASSEMBLER_NAME_SET_P,
set assembler name back to NULL afterwards.
* c-c++-common/pr36282-1.c: New test.
* c-c++-common/pr36282-2.c: New test.
* c-c++-common/pr36282-3.c: New test.
* c-c++-common/pr36282-4.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208557 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* config/i386/i386.c (ix86_split_fp_branch): Remove pushed argument.
(ix86_force_to_memory, ix86_free_from_memory): Remove.
* config/i386/i386-protos.h: Likewise.
* config/i386/i386.md (floathi<X87MODEF>2): Use assign_386_stack_local
in the expander instead of a splitter.
(float<SWI48x><X87MODEF>2): Use assign_386_stack_local if there is
any possibility of requiring a memory.
(*floatsi<MODEF>2_vector_mixed): Remove, and the splitters.
(*floatsi<MODEF>2_vector_sse): Remove, and the splitters.
(fp branch splitters): Update for ix86_split_fp_branch.
(*jcc<X87MODEF>_<SWI24>_i387): Remove r/f alternative.
(*jcc<X87MODEF>_<SWI24>_r_i387): Likewise.
(splitter for jcc<X87MODEF>_<SWI24>_i387 r/f): Remove.
(*fop_<MODEF>_2_i387): Remove f/r alternative.
(*fop_<MODEF>_3_i387): Likewise.
(*fop_xf_2_i387, *fop_xf_3_i387): Likewise.
(splitters for the fop_* register patterns): Remove.
(fscalexf4_i387): Rename from *fscalexf4_i387.
(ldexpxf3): Use gen_floatsixf2 and gen_fscalexf4_i387.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208556 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
* tree-dfa.c (get_ref_base_and_extent): Use double_int
type for bitsize and maxsize instead of HOST_WIDE_INT.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208554 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
* function.c (rest_of_handle_thread_prologue_and_epilogue): Cleanup
the CFG after thread_prologue_and_epilogue_insns.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208551 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
2014-03-13 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60383
* pt.c (maybe_process_partial_specialization): Check return value
of check_specialization_namespace.
/testsuite
2014-03-13 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60383
* g++.dg/template/crash118.C: New.
* g++.dg/template/crash95.C: Adjust.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208550 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
PR rtl-optimization/57189
* lra-constraints.c (process_alt_operands): Disfavor spilling
vector pseudos.
2014-03-13 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/57189
* gcc.target/i386/pr57189.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208549 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* cstand.adb (Register_Float_Type): Add 'precision' parameter and use
it to set the RM size. Use directly 'size' for the Esize.
(Create_Back_End_Float_Types): Adjust call to above.
* get_targ.ads (Register_Type_Proc): Add 'precision' parameter.
* set_targ.ads (FPT_Mode_Entry): Add 'precision' component.
(Write_Target_Dependent_Values): Adjust comment.
* set_targ.adb (Register_Float_Type): Add 'precision' parameter and
deal with it.
(Write_Target_Dependent_Values): Write the precision in lieu of size.
(Initialization): Read the precision in lieu of size and compute the
size from the precision and the alignment.
* gcc-interface/gigi.h (enumerate_modes): Add integer parameter.
* gcc-interface/misc.c (enumerate_modes): Likewise. Do not register
types for vector modes, pass the size in addition to the precision.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208546 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
2014-03-13 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60254
* semantics.c (finish_static_assert): Call cxx_constant_value only
if require_potential_rvalue_constant_expression returns true.
/testsuite
2014-03-13 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60254
* g++.dg/cpp0x/static_assert10.C: New.
* g++.dg/cpp0x/static_assert11.C: Likewise.
* g++.dg/cpp0x/static_assert3.C: Adjust.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208538 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
* lto-wrapper.c (maybe_unlink_file): Suppress diagnostic
messages.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208537 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
| |
* lib/lto.exp (lto-execute): Fix error catching for dg-final.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208536 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
| |
PR middle-end/60418
* tree-ssa-reassoc.c (sort_by_operand_rank): For SSA_NAMEs with the
same rank, sort by bb_rank and gimple_uid of SSA_NAME_DEF_STMT first.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208535 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
| |
* config/avr/avr.c (avr_out_plus): Swap cc_plus and cc_minus in
calls of avr_out_plus_1.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208532 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
| |
* testsuite/ChangeLog: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208530 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
BB's single pred and update the father loop's latch info later.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208527 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
| |
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208525 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types.
(VEC_M): Likewise.
(VEC_N): Likewise.
(VEC_R): Likewise.
(VEC_base): Likewise.
(mov<MODE>, VEC_M modes): If we are loading TImode into VSX
registers, we need to swap double words in little endian mode.
* config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode
to be a container mode for 128-bit integer operations added in ISA
2.07. Unlike TImode and PTImode, the preferred register set is
the Altivec/VMX registers for the 128-bit operations.
* config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add
declarations.
(rs6000_split_128bit_ok_p): Likewise.
* config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support
macros for creating ISA 2.07 normal and overloaded builtin
functions with 3 arguments.
(BU_P8V_OVERLOAD_3): Likewise.
(VPERM_1T): Add support for V1TImode in 128-bit vector operations
for use as overloaded functions.
(VPERM_1TI_UNS): Likewise.
(VSEL_1TI): Likewise.
(VSEL_1TI_UNS): Likewise.
(ST_INTERNAL_1ti): Likewise.
(LD_INTERNAL_1ti): Likewise.
(XXSEL_1TI): Likewise.
(XXSEL_1TI_UNS): Likewise.
(VPERM_1TI): Likewise.
(VPERM_1TI_UNS): Likewise.
(XXPERMDI_1TI): Likewise.
(SET_1TI): Likewise.
(LXVD2X_V1TI): Likewise.
(STXVD2X_V1TI): Likewise.
(VEC_INIT_V1TI): Likewise.
(VEC_SET_V1TI): Likewise.
(VEC_EXT_V1TI): Likewise.
(EQV_V1TI): Likewise.
(NAND_V1TI): Likewise.
(ORC_V1TI): Likewise.
(VADDCUQ): Add support for 128-bit integer arithmetic instructions
added in ISA 2.07. Add both normal 'altivec' builtins, and the
overloaded builtin.
(VADDUQM): Likewise.
(VSUBCUQ): Likewise.
(VADDEUQM): Likewise.
(VADDECUQ): Likewise.
(VSUBEUQM): Likewise.
(VSUBECUQ): Likewise.
* config/rs6000/rs6000-c.c (__int128_type): New static to hold
__int128_t and __uint128_t types.
(__uint128_type): Likewise.
(altivec_categorize_keyword): Add support for vector __int128_t,
vector __uint128_t, vector __int128, and vector unsigned __int128
as a container type for TImode operations that need to be done in
VSX/Altivec registers.
(rs6000_macro_to_expand): Likewise.
(altivec_overloaded_builtins): Add ISA 2.07 overloaded functions
to support 128-bit integer instructions vaddcuq, vadduqm,
vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm.
(altivec_resolve_overloaded_builtin): Add support for V1TImode.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support
for V1TImode, and set up preferences to use VSX/Altivec
registers. Setup VSX reload handlers.
(rs6000_debug_reg_global): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_preferred_simd_mode): Likewise.
(vspltis_constant): Do not allow V1TImode as easy altivec
constants.
(easy_altivec_constant): Likewise.
(output_vec_const_move): Likewise.
(rs6000_expand_vector_set): Convert V1TImode set and extract to
simple move.
(rs6000_expand_vector_extract): Likewise.
(reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg
addressing.
(rs6000_const_vec): Add support for V1TImode.
(rs6000_emit_le_vsx_load): Swap double words when loading or
storing TImode/V1TImode.
(rs6000_emit_le_vsx_store): Likewise.
(rs6000_emit_le_vsx_move): Likewise.
(rs6000_emit_move): Add support for V1TImode.
(altivec_expand_ld_builtin): Likewise.
(altivec_expand_st_builtin): Likewise.
(altivec_expand_vec_init_builtin): Likewise.
(altivec_expand_builtin): Likewise.
(rs6000_init_builtins): Add support for V1TImode type. Add
support for ISA 2.07 128-bit integer builtins. Define type names
for the VSX/Altivec vector types.
(altivec_init_builtins): Add support for overloaded vector
functions with V1TImode type.
(rs6000_preferred_reload_class): Prefer Altivec registers for
V1TImode.
(rs6000_move_128bit_ok_p): Move 128-bit move/split validation to
external function.
(rs6000_split_128bit_ok_p): Likewise.
(rs6000_handle_altivec_attribute): Create V1TImode from vector
__int128_t and vector __uint128_t.
* config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators
and mode attributes.
(VSX_M): Likewise.
(VSX_M2): Likewise.
(VSm): Likewise.
(VSs): Likewise.
(VSr): Likewise.
(VSv): Likewise.
(VS_scalar): Likewise.
(VS_double): Likewise.
(vsx_set_v1ti): New builtin function to create V1TImode from
TImode.
* config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say
whether we support the ISA 2.07 128-bit integer arithmetic
instructions.
(ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode.
(enum rs6000_builtin_type_index): Add fields to hold V1TImode
and TImode types for use with the builtin functions.
(V1TI_type_node): Likewise.
(unsigned_V1TI_type_node): Likewise.
(intTI_type_internal_node): Likewise.
(uintTI_type_internal_node): Likewise.
* config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA
2.07 128-bit builtin functions.
(UNSPEC_VADDEUQM): Likewise.
(UNSPEC_VADDECUQ): Likewise.
(UNSPEC_VSUBCUQ): Likewise.
(UNSPEC_VSUBEUQM): Likewise.
(UNSPEC_VSUBECUQ): Likewise.
(VM): Add V1TImode to vector mode iterators.
(VM2): Likewise.
(VI_unit): Likewise.
(altivec_vadduqm): Add ISA 2.07 128-bit binary builtins.
(altivec_vaddcuq): Likewise.
(altivec_vsubuqm): Likewise.
(altivec_vsubcuq): Likewise.
(altivec_vaddeuqm): Likewise.
(altivec_vaddecuq): Likewise.
(altivec_vsubeuqm): Likewise.
(altivec_vsubecuq): Likewise.
* config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector
mode iterators.
(BOOL_128): Likewise.
(BOOL_REGS_OUTPUT): Likewise.
(BOOL_REGS_OP1): Likewise.
(BOOL_REGS_OP2): Likewise.
(BOOL_REGS_UNARY): Likewise.
(BOOL_REGS_AND_CR0): Likewise.
* config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07
128-bit integer builtin support.
(vec_vadduqm): Likewise.
(vec_vaddecuq): Likewise.
(vec_vaddeuqm): Likewise.
(vec_vsubecuq): Likewise.
(vec_vsubeuqm): Likewise.
(vec_vsubcuq): Likewise.
(vec_vsubuqm): Likewise.
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm,
vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding
128-bit integer add/subtract to ISA 2.07.
[gcc/testsuite]
2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA
2.07 128-bit arithmetic.
* gcc.target/powerpc/p8vector-int128-2.c: Likewise.
* gcc.target/powerpc/timode_off.c: Restrict cpu type to power5,
due to when TImode is allowed in VSX registers, the allowable
address modes for TImode is just a single indirect address in
order for the value to be loaded and store in either GPR or VSX
registers. This affects the generated code, and it would cause
this test to fail, when such an option is used.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208522 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
| |
Fix third argument passed to conditionalize_nonjump.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208521 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
| |
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Add BUILT_IN_LFLOORF,
BUILT_IN_LLFLOOR, BUILT_IN_LCEILF and BUILT_IN_LLCEIL.
* config/aarch64/arm_neon.h (vcvtaq_u64_f64): Call __builtin_llfloor
instead of __builtin_lfloor.
(vcvtnq_u64_f64): Call __builtin_llceil instead of __builtin_lceil.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208517 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
| |
The test infrastructure for gcc.dg/tree-prof reports relative paths
for all test outcomes except UNSUPPORTED, for which it reports the
absolute path of the test case. This patch ensure a relative path is
reported consistently reducing noise in regression test comparisons.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208514 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
(tree_ssa_ifcombine_bb_1): New function.
(tree_ssa_ifcombine_bb): Use it. Handle also cases where else_bb
is an empty forwarder block to then_bb or vice versa and then_bb
and else_bb are effectively swapped.
* gcc.dg/tree-ssa/ssa-ifcombine-12.c: New test.
* gcc.dg/tree-ssa/ssa-ifcombine-13.c: New test.
* gcc.dg/tree-ssa/phi-opt-2.c: Pass -mbranch-cost=1 if
possible, only test for exactly one if if -mbranch-cost=1
has been passed.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208512 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
| |
PR target/60264
* config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Emit a REG_CFA_DEF_CFA
note.
(arm_expand_epilogue_apcs_frame): call arm_add_cfa_adjust_cfa_note.
(arm_unwind_emit): Allow REG_CFA_DEF_CFA.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208511 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
| |
* tree-ssa-math-opts.c (find_bswap_1): Fix bswap detection.
* gcc.c-torture/execute/pr60454.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208509 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
| |
* config.gcc (aarch64*-*-*): Use ISA flags from aarch64-arches.def.
Do not define target_cpu_default2 to generic.
* config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Use generic cpu.
* config/aarch64/aarch64.c (aarch64_override_options): Update comment.
* config/aarch64/aarch64-arches.def (armv8-a): Use generic cpu.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208508 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
| |
* tree-ssa-reassoc.c (eliminate_not_pairs): Use build_all_ones_cst
instead of build_low_bits_mask.
* gcc.c-torture/compile/pr60502.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208507 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
| |
* tree-vrp.c (register_edge_assert_for_1): Don't add assert
if there are multiple uses, but op doesn't live on E edge.
* tree-cfg.c (assert_unreachable_fallthru_edge_p): Also ignore
clobber stmts before __builtin_unreachable.
* gcc.dg/vect/pr60482.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208506 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
| |
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208504 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
| |
* builtins.c (expand_builtin_setjmp_receiver): Use and clobber
hard_frame_pointer_rtx.
* cse.c (cse_insn): Remove volatile check.
* cselib.c (cselib_process_insn): Likewise.
* dse.c (scan_insn): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208498 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
2014-03-11 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60389
* method.c (get_inherited_ctor): New.
* cp-tree.h (get_inherited_ctor): Declare it.
* semantics.c (is_valid_constexpr_fn): Use it.
/testsuite
2014-03-11 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60389
* g++.dg/cpp0x/inh-ctor19.C: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208491 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
| |
* config/arc/arc.c (conditionalize_nonjump): New function, broken
out of:
(arc_ifcvt) .
(arc_predicate_delay_insns): Use it.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208488 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* config/arc/predicates.md (extend_operand): During/after reload,
allow const_int_operand.
* config/arc/arc.md (mulsidi3_700): Use extend_operand predicate.
(umulsidi3_700): Likewise. Change operand 2 constraint back to "cL".
(mulsi3_highpart): Change operand 2 constraint alternatives 2 and 3
to "i".
(umulsi3_highpart_i): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208487 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
| |
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208486 138bc75d-0d04-0410-961f-82ee72b054a4
|
|
|
|
|
|
|
|
| |
* tree-ssa-structalias.c (get_constraint_for_ptr_offset):
Add asserts to guard possible wrong-code bugs.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208485 138bc75d-0d04-0410-961f-82ee72b054a4
|