diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 19 | ||||
| -rw-r--r-- | gcc/common/config/i386/i386-common.c | 19 | ||||
| -rw-r--r-- | gcc/config/i386/cpuid.h | 1 | ||||
| -rw-r--r-- | gcc/config/i386/driver-i386.c | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386-c.c | 2 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 11 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 1 | ||||
| -rw-r--r-- | gcc/config/i386/i386.opt | 4 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 6 |
9 files changed, 64 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e0d22a84307..5ade55a1564 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2011-08-18 Kirill Yukhin <kirill.yukhin@intel.com> + + * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX2_SET): New. + (OPTION_MASK_ISA_AVX_UNSET): Update. + (OPTION_MASK_ISA_AVX2_UNSET): New. + (ix86_handle_option): Handle OPT_mavx2 case. + * config/i386/cpuid.h (bit_AVX2): New. + * config/i386/driver-i386.c (host_detect_local_cpu): Detect + AVX2 feature. + * config/i386/i386-c.c (ix86_target_macros_internal): + Conditionally define __AVX2__. + * config/i386/i386.c (ix86_option_override_internal): Define + PTA_AVX2. Define "core-avx2" processor alias. Handle avx2 + option. + (ix86_valid_target_attribute_inner_p): Handle avx2 option. + * config/i386/i386.h (TARGET_AVX2): New. + * config/i386/i386.opt (mavx2): New. + * doc/invoke.texi: Document -mavx2. + 2011-08-18 Vladimir Makarov <vmakarov@redhat.com> PR rtl-optimization/49890 diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 1fd33bd39f8..b2018357dfd 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -52,6 +52,8 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET) #define OPTION_MASK_ISA_FMA_SET \ (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA_AVX2_SET \ + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -114,8 +116,10 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) #define OPTION_MASK_ISA_AVX_UNSET \ (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ - | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET) + | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ + | OPTION_MASK_ISA_AVX2_UNSET) #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA +#define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -277,6 +281,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavx2: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 8826c2829ff..d53743fa158 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -66,6 +66,7 @@ /* Extended Features (%eax == 7) */ #define bit_FSGSBASE (1 << 0) #define bit_BMI (1 << 3) +#define bit_AVX2 (1 << 5) #if defined(__i386__) && defined(__PIC__) /* %ebx may be the PIC register. */ diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 1f6fadfe90a..b7a1f523c13 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -393,7 +393,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_lahf_lm = 0, has_sse4a = 0; unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0; - unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0; + unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0; unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0; unsigned int has_bmi = 0, has_tbm = 0, has_lzcnt = 0; @@ -474,6 +474,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) __cpuid (0x7, eax, ebx, ecx, edx); has_bmi = ebx & bit_BMI; + has_avx2 = ebx & bit_AVX2; } if (!arch) @@ -716,13 +717,14 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi"; const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm"; const char *avx = has_avx ? " -mavx" : " -mno-avx"; + const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2"; const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2"; const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1"; const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt"; options = concat (options, cx16, sahf, movbe, ase, pclmul, popcnt, abm, lwp, fma, fma4, xop, bmi, tbm, - avx, sse4_2, sse4_1, lzcnt, NULL); + avx2, avx, sse4_2, sse4_1, lzcnt, NULL); } done: diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index c5a770fcae7..5c1dfe61038 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -257,6 +257,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__PCLMUL__"); if (isa_flag & OPTION_MASK_ISA_AVX) def_or_undef (parse_in, "__AVX__"); + if (isa_flag & OPTION_MASK_ISA_AVX2) + def_or_undef (parse_in, "__AVX2__"); if (isa_flag & OPTION_MASK_ISA_FMA) def_or_undef (parse_in, "__FMA__"); if (isa_flag & OPTION_MASK_ISA_SSE4A) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 58f16e79563..53c59445ce1 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2920,6 +2920,7 @@ ix86_option_override_internal (bool main_args_p) #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27) #define PTA_TBM (HOST_WIDE_INT_1 << 28) #define PTA_XOP (HOST_WIDE_INT_1 << 29) +#define PTA_AVX2 (HOST_WIDE_INT_1 << 30) /* if this reaches 64, need to widen struct pta flags below */ static struct pta @@ -2973,6 +2974,12 @@ ix86_option_override_internal (bool main_args_p) | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE | PTA_RDRND | PTA_F16C}, + {"core-avx2", PROCESSOR_COREI7_64, CPU_COREI7, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2 + | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE + | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_LZCNT | PTA_FMA + | PTA_MOVBE}, {"atom", PROCESSOR_ATOM, CPU_ATOM, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE}, @@ -3263,6 +3270,9 @@ ix86_option_override_internal (bool main_args_p) if (processor_alias_table[i].flags & PTA_AVX && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX)) ix86_isa_flags |= OPTION_MASK_ISA_AVX; + if (processor_alias_table[i].flags & PTA_AVX2 + && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2)) + ix86_isa_flags |= OPTION_MASK_ISA_AVX2; if (processor_alias_table[i].flags & PTA_FMA && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA)) ix86_isa_flags |= OPTION_MASK_ISA_FMA; @@ -4047,6 +4057,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("tbm", OPT_mtbm), IX86_ATTR_ISA ("aes", OPT_maes), IX86_ATTR_ISA ("avx", OPT_mavx), + IX86_ATTR_ISA ("avx2", OPT_mavx2), IX86_ATTR_ISA ("mmx", OPT_mmmx), IX86_ATTR_ISA ("pclmul", OPT_mpclmul), IX86_ATTR_ISA ("popcnt", OPT_mpopcnt), diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f43586d012b..f8a35ba99ae 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -53,6 +53,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 #define TARGET_AVX OPTION_ISA_AVX +#define TARGET_AVX2 OPTION_ISA_AVX2 #define TARGET_FMA OPTION_ISA_FMA #define TARGET_SSE4A OPTION_ISA_SSE4A #define TARGET_FMA4 OPTION_ISA_FMA4 diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 654f4ebbcbd..54d7af1d250 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -457,6 +457,10 @@ mavx Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation +mavx2 +Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation + mfma Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f5d53d1828b..fdc32979a57 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -605,7 +605,7 @@ Objective-C and Objective-C++ Dialects}. -mincoming-stack-boundary=@var{num} @gol -mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip -mvzeroupper @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol --maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol +-mavx2 -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol -msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol -mlwp -mthreads -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol @@ -12666,6 +12666,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @itemx -mno-sse4 @itemx -mavx @itemx -mno-avx +@itemx -mavx2 +@itemx -mno-avx2 @itemx -maes @itemx -mno-aes @itemx -mpclmul @@ -12707,7 +12709,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex m3dnow @opindex mno-3dnow These switches enable or disable the use of instructions in the MMX, SSE, -SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, +SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, LZCNT or 3DNow!@: extended instruction sets. These extensions are also available as built-in functions: see @ref{X86 Built-in Functions}, for details of the functions enabled and |
