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| author | Doug Gilbert <dgilbert@us.ibm.com> | 2015-05-05 13:13:15 -0500 |
|---|---|---|
| committer | Patrick Williams <patrick@stwcx.xyz> | 2016-08-15 11:45:09 -0500 |
| commit | 95e2aa700e6342ef1a18d755cca2796cb2561552 (patch) | |
| tree | 65a8aeb5e8f879e465d46f5954611e0d9c0879ca | |
| parent | f7ef6a9b864039927dc90002a5306cf7d6c7d7d4 (diff) | |
| download | ppe42-gcc-95e2aa700e6342ef1a18d755cca2796cb2561552.tar.gz ppe42-gcc-95e2aa700e6342ef1a18d755cca2796cb2561552.zip | |
provide clrbwibc
| -rw-r--r-- | gcc/config/rs6000/predicates.md | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 70 |
2 files changed, 45 insertions, 30 deletions
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 42d931a8ae2..eac07c71f59 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -166,6 +166,11 @@ (and (match_code "const_int") (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) +;; Return 1 if op is a positive constant integer whos inverted value is an exact power of 2. +(define_predicate "exact_log2_inverted_cint_operand" + (and (match_code "const_int") + (match_test "(~(INTVAL (op))) > 0 && exact_log2 (~(INTVAL (op))) >= 0"))) + ;; Match op = 0 or op = 1. (define_predicate "const_0_to_1_operand" (and (match_code "const_int") diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 243811c1c58..9a0878782d7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -14752,18 +14752,17 @@ (define_insn "*clrbwib" [(set (pc) (if_then_else (match_operator 1 "rs6000_eq_or_ne_operator" - [(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") - (const_int 31) - (match_operand:SI 3 "const_int_operand" "")) - (const_int 0)]) - (label_ref (match_operand 0 "" "")) - (pc)))] + [(and:SI (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "exact_log2_inverted_cint_operand" "")) + (const_int 0)]) + (label_ref (match_operand 0 "" "")) + (pc)))] "(rs6000_cpu == PROCESSOR_PPE42) && optimize_size" "* { return output_fused_clrbwib(REGNO(operands[2]), GET_CODE(operands[1]), - INTVAL(operands[3]), + 31 - exact_log2(~INTVAL(operands[3])), \"%l0\", get_attr_length(insn) == 8); }" @@ -15864,29 +15863,40 @@ -;;(define_peephole2 -;; [(parallel [(set (match_operand:SI 0 "gpc_reg_operand") -;; (and:SI (match_operand:SI 1 "gpc_reg_operand") -;; (match_operand:SI 2 "exact_log2_cint_operand"))) -;; (clobber (match_scratch:CC 3 "=X,X,x,x"))]) -;; (set (pc) -;; (if_then_else (match_operator 5 "rs6000_eq_or_ne_operator" -;; [(match_operand:GPR 6 "gpc_reg_operand") -;; (const_int 0)]) -;; (label_ref (match_operand 4 "" )) -;; (pc)))] -;;"(rs6000_cpu == PROCESSOR_PPE42) && optimize_size && -;; rtx_equal_p(operands[0],operands[1]) && -;; rtx_equal_p(operands[0],operands[6])" -;; [(const_int 0)] -;;{ -;; return output_fused_clrbwib(REGNO(operands[0]), -;; GET_CODE(operands[5]), -;; 31 - exact_log2(INTVAL(operands[2])), -;; \"%l4\", -;; get_attr_length(insn) == 8); -;; DONE; -;;}) +(define_peephole2 + [(parallel [(set (match_operand:SI 0 "gpc_reg_operand") + (and:SI (match_operand:SI 1 "gpc_reg_operand") + (match_operand:SI 2 "exact_log2_inverted_cint_operand"))) + (clobber (match_scratch:CC 3 ))]) + (set (pc) + (if_then_else (match_operator 5 "rs6000_eq_or_ne_operator" + [(match_operand:GPR 6 "gpc_reg_operand") + (const_int 0)]) + (label_ref (match_operand 4 "" )) + (pc)))] +"(rs6000_cpu == PROCESSOR_PPE42) && optimize_size && + rtx_equal_p(operands[0],operands[1]) && + rtx_equal_p(operands[0],operands[6])" + [(const_int 0)] +{ + emit_jump_insn( + gen_rtx_SET( + VOIDmode, + pc_rtx, + gen_rtx_IF_THEN_ELSE( + VOIDmode, + gen_rtx_fmt_ee ( + GET_CODE (operands[5]), + VOIDmode, + gen_rtx_AND ( + SImode, + operands[0], + gen_int_mode(INTVAL(operands[2]),SImode)), + const0_rtx), + gen_rtx_LABEL_REF (VOIDmode, operands[4]), + pc_rtx))); + DONE; +}) ;; Power8 fusion support for fusing an addis instruction with a D-form load of ;; a GPR. The addis instruction must be adjacent to the load, and use the same |
