summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDoug Gilbert <dgilbert@us.ibm.com>2015-03-24 14:37:43 -0500
committerPatrick Williams <patrick@stwcx.xyz>2016-08-15 11:45:09 -0500
commit0081fa342a15c20ccdb20081e0fd79179a435387 (patch)
tree11f4cd6629b98ca55fb5990ad36bccc6b96474c3
parentc1283af40b65f1ad862cf5b27e2d9ed10b2076b6 (diff)
downloadppe42-gcc-0081fa342a15c20ccdb20081e0fd79179a435387.tar.gz
ppe42-gcc-0081fa342a15c20ccdb20081e0fd79179a435387.zip
hack1
-rw-r--r--gcc/config/rs6000/rs6000-cpus.def2
-rw-r--r--gcc/config/rs6000/rs6000.c142
-rw-r--r--gcc/config/rs6000/rs6000.h24
-rw-r--r--gcc/config/rs6000/rs6000.md1622
4 files changed, 900 insertions, 890 deletions
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index b17fd0d7207..98b738ff104 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -115,7 +115,7 @@
RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
-RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
+RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index e1a226c5ecd..c4864144abd 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3296,22 +3296,22 @@ rs6000_option_override_internal (bool global_init_p)
trap. The 750 does not cause an alignment trap (except when the
target is unaligned). */
- if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
- {
+ //if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
+ // {
if (TARGET_MULTIPLE)
{
rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
- warning (0, "-mmultiple is not supported on little endian systems");
+ warning (0, "-mmultiple is not supported on PPE");
}
if (TARGET_STRING)
{
rs6000_isa_flags &= ~OPTION_MASK_STRING;
if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
- warning (0, "-mstring is not supported on little endian systems");
+ warning (0, "-mstring is not supported on PPE");
}
- }
+ // }
/* If little-endian, default to -mstrict-align on older processors.
Testing for htm matches power8 and later. */
@@ -15743,6 +15743,7 @@ expand_block_move (rtx operands[])
mode = V2SImode;
gen_func.mov = gen_movv2si;
}
+#ifdef __STRING_SUPPORT__
else if (TARGET_STRING
&& bytes > 24 /* move up to 32 bytes at a time */
&& ! fixed_regs[5]
@@ -15793,6 +15794,7 @@ expand_block_move (rtx operands[])
move_bytes = (bytes > 8) ? 8 : bytes;
gen_func.movmemsi = gen_movmemsi_2reg;
}
+#endif
else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
{ /* move 4 bytes */
move_bytes = 4;
@@ -15805,11 +15807,13 @@ expand_block_move (rtx operands[])
mode = HImode;
gen_func.mov = gen_movhi;
}
+#ifdef __STRING_SUPPORT__
else if (TARGET_STRING && bytes > 1)
{ /* move up to 4 bytes at a time */
move_bytes = (bytes > 4) ? 4 : bytes;
gen_func.movmemsi = gen_movmemsi_1reg;
}
+#endif
else /* move 1 byte at a time */
{
move_bytes = 1;
@@ -20820,12 +20824,16 @@ rs6000_savres_strategy (rs6000_stack_t *info,
int strategy = 0;
bool lr_save_p;
- if (TARGET_MULTIPLE
+ /* ppe - stmw instruction not supported) */
+ /*if (TARGET_MULTIPLE
&& !TARGET_POWERPC64
&& !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
&& info->first_gp_reg_save < 31
&& !global_regs_p (info->first_gp_reg_save, 32))
- strategy |= SAVRES_MULTIPLE;
+ strategy |= SAVRES_MULTIPLE; */
+
+ /* ppe - always inline gpr saves/restores */
+ strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
if (crtl->calls_eh_return
|| cfun->machine->ra_need_lr)
@@ -22729,8 +22737,8 @@ static inline unsigned
ptr_regno_for_savres (int sel)
{
if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
- return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
- return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
+ return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 10;
+ return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 9;
}
/* Construct a parallel rtx describing the effect of a call to an
@@ -22994,7 +23002,7 @@ rs6000_emit_prologue (void)
&& info->vrsave_save_offset == -224
&& info->altivec_save_offset == -416);
- treg = gen_rtx_REG (SImode, 11);
+ treg = gen_rtx_REG (SImode, 10);
emit_move_insn (treg, GEN_INT (-info->total_size));
/* SAVE_WORLD takes the caller's LR in R0 and the frame size
@@ -23076,7 +23084,7 @@ rs6000_emit_prologue (void)
if (info->total_size < 32767)
frame_off = info->total_size;
else if (need_r11)
- ptr_regno = 11;
+ ptr_regno = 9;
else if (info->cr_save_p
|| info->lr_save_p
|| info->first_fp_reg_save < 64
@@ -23084,7 +23092,7 @@ rs6000_emit_prologue (void)
|| info->altivec_size != 0
|| info->vrsave_mask != 0
|| crtl->calls_eh_return)
- ptr_regno = 12;
+ ptr_regno = 10;
else
{
/* The prologue won't be saving any regs so there is no need
@@ -23146,11 +23154,11 @@ rs6000_emit_prologue (void)
cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
&& !(strategy & (SAVE_INLINE_GPRS
| SAVE_NOINLINE_GPRS_SAVES_LR))
- ? 11 : 12);
+ ? 9 : 10);
if (!WORLD_SAVE_P (info)
&& info->cr_save_p
&& REGNO (frame_reg_rtx) != cr_save_regno
- && !(using_static_chain_p && cr_save_regno == 11))
+ && !(using_static_chain_p && cr_save_regno == 9))
{
cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
START_USE (cr_save_regno);
@@ -23232,7 +23240,7 @@ rs6000_emit_prologue (void)
if (!(strategy & SAVE_INLINE_GPRS))
ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO);
offset = info->spe_gp_save_offset + frame_off - ool_adjust;
- spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
+ spe_save_area_ptr = gen_rtx_REG (Pmode, 9);
save_off = frame_off - offset;
if (using_static_chain_p)
@@ -23244,12 +23252,12 @@ rs6000_emit_prologue (void)
emit_move_insn (r0, spe_save_area_ptr);
}
- else if (REGNO (frame_reg_rtx) != 11)
- START_USE (11);
+ else if (REGNO (frame_reg_rtx) != 9)
+ START_USE (9);
emit_insn (gen_addsi3 (spe_save_area_ptr,
frame_reg_rtx, GEN_INT (offset)));
- if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11)
+ if (!using_static_chain_p && REGNO (frame_reg_rtx) == 9)
frame_off = -info->spe_gp_save_offset + ool_adjust;
}
@@ -23282,8 +23290,8 @@ rs6000_emit_prologue (void)
emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
END_USE (0);
}
- else if (REGNO (frame_reg_rtx) != 11)
- END_USE (11);
+ else if (REGNO (frame_reg_rtx) != 9)
+ END_USE (9);
}
}
else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
@@ -23390,15 +23398,15 @@ rs6000_emit_prologue (void)
rtx save_insn, join_insn, note;
long toc_restore_insn;
- tmp_reg = gen_rtx_REG (Pmode, 11);
- tmp_reg_si = gen_rtx_REG (SImode, 11);
+ tmp_reg = gen_rtx_REG (Pmode, 9);
+ tmp_reg_si = gen_rtx_REG (SImode, 9);
if (using_static_chain_p)
{
START_USE (0);
emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
}
else
- START_USE (11);
+ START_USE (9);
emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
/* Peek at instruction to which this function returns. If it's
restoring r2, then we know we've already saved r2. We can't
@@ -23457,7 +23465,7 @@ rs6000_emit_prologue (void)
END_USE (0);
}
else
- END_USE (11);
+ END_USE (9);
}
/* Save CR if we use any that must be preserved. */
@@ -23644,7 +23652,7 @@ rs6000_emit_prologue (void)
int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
- gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
+ gcc_checking_assert (scratch_regno == 9 || scratch_regno == 10);
NOT_INUSE (0);
if (end_save + frame_off != 0)
{
@@ -23728,13 +23736,13 @@ rs6000_emit_prologue (void)
/* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
be using r12 as frame_reg_rtx and r11 as the static chain
pointer for nested functions. */
- save_regno = 12;
+ save_regno = 10;
if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
&& !using_static_chain_p)
- save_regno = 11;
- else if (REGNO (frame_reg_rtx) == 12)
+ save_regno = 9;
+ else if (REGNO (frame_reg_rtx) == 10)
{
- save_regno = 11;
+ save_regno = 9;
if (using_static_chain_p)
save_regno = 0;
}
@@ -24200,7 +24208,7 @@ rs6000_emit_epilogue (int sibcall)
/* The instruction pattern requires a clobber here;
it is shared with the restVEC helper. */
RTVEC_ELT (p, j++)
- = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
+ = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 9));
{
/* CR register traditionally saved as CR2. */
@@ -24280,16 +24288,16 @@ rs6000_emit_epilogue (int sibcall)
int i;
int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
- gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
+ gcc_checking_assert (scratch_regno == 9 || scratch_regno == 10);
if (use_backchain_to_restore_sp)
{
- int frame_regno = 11;
+ int frame_regno = 9;
if ((strategy & REST_INLINE_VRS) == 0)
{
/* Of r11 and r12, select the one not clobbered by an
out-of-line restore function for the frame register. */
- frame_regno = 11 + 12 - scratch_regno;
+ frame_regno = 9 + 10 - scratch_regno;
}
frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
emit_move_insn (frame_reg_rtx,
@@ -24369,7 +24377,7 @@ rs6000_emit_epilogue (int sibcall)
{
if (use_backchain_to_restore_sp)
{
- frame_reg_rtx = gen_rtx_REG (Pmode, 11);
+ frame_reg_rtx = gen_rtx_REG (Pmode, 9);
emit_move_insn (frame_reg_rtx,
gen_rtx_MEM (Pmode, sp_reg_rtx));
frame_off = 0;
@@ -24378,7 +24386,7 @@ rs6000_emit_epilogue (int sibcall)
frame_reg_rtx = hard_frame_pointer_rtx;
}
- reg = gen_rtx_REG (SImode, 12);
+ reg = gen_rtx_REG (SImode, 10);
emit_insn (gen_frame_load (reg, frame_reg_rtx,
info->vrsave_save_offset + frame_off));
@@ -24395,7 +24403,7 @@ rs6000_emit_epilogue (int sibcall)
/* Under V.4, don't reset the stack pointer until after we're done
loading the saved registers. */
if (DEFAULT_ABI == ABI_V4)
- frame_reg_rtx = gen_rtx_REG (Pmode, 11);
+ frame_reg_rtx = gen_rtx_REG (Pmode, 9);
insn = emit_move_insn (frame_reg_rtx,
gen_rtx_MEM (Pmode, sp_reg_rtx));
@@ -24417,7 +24425,7 @@ rs6000_emit_epilogue (int sibcall)
{
frame_reg_rtx = sp_reg_rtx;
if (DEFAULT_ABI == ABI_V4)
- frame_reg_rtx = gen_rtx_REG (Pmode, 11);
+ frame_reg_rtx = gen_rtx_REG (Pmode, 9);
/* Prevent reordering memory accesses against stack pointer restore. */
else if (cfun->calls_alloca
|| offset_below_red_zone_p (-info->total_size))
@@ -24612,7 +24620,7 @@ rs6000_emit_epilogue (int sibcall)
/* Get the old cr if we saved it. */
if (info->cr_save_p)
{
- unsigned cr_save_regno = 12;
+ unsigned cr_save_regno = 10;
if (!restoring_GPRs_inline)
{
@@ -24622,12 +24630,12 @@ rs6000_emit_epilogue (int sibcall)
int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
int gpr_ptr_regno = ptr_regno_for_savres (sel);
- if (gpr_ptr_regno == 12)
- cr_save_regno = 11;
+ if (gpr_ptr_regno == 10)
+ cr_save_regno = 9;
gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
}
- else if (REGNO (frame_reg_rtx) == 12)
- cr_save_regno = 11;
+ else if (REGNO (frame_reg_rtx) == 10)
+ cr_save_regno = 9;
cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
info->cr_save_offset + frame_off,
@@ -24692,7 +24700,7 @@ rs6000_emit_epilogue (int sibcall)
if (!restoring_GPRs_inline)
ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO);
- frame_reg_rtx = gen_rtx_REG (Pmode, 11);
+ frame_reg_rtx = gen_rtx_REG (Pmode, 9);
emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
GEN_INT (info->spe_gp_save_offset
+ frame_off
@@ -24942,7 +24950,7 @@ rs6000_emit_epilogue (int sibcall)
sym = rs6000_savres_routine_sym (info,
SAVRES_FPR | (lr ? SAVRES_LR : 0));
RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
- reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
+ reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 10;
RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
for (i = 0; i < 64 - info->first_fp_reg_save; i++)
@@ -26142,32 +26150,32 @@ output_function_profiler (FILE *file, int labelno)
asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
assemble_name (file, buf);
fputs ("-.\n1:", file);
- asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
+ asm_fprintf (file, "\tmflr %s\n", reg_names[9]);
asm_fprintf (file, "\taddi %s,%s,4\n",
- reg_names[11], reg_names[11]);
+ reg_names[9], reg_names[9]);
}
else
{
fputs ("\tbcl 20,31,1f\n\t.long ", file);
assemble_name (file, buf);
fputs ("-.\n1:", file);
- asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
+ asm_fprintf (file, "\tmflr %s\n", reg_names[9]);
}
asm_fprintf (file, "\tlwz %s,0(%s)\n",
- reg_names[0], reg_names[11]);
+ reg_names[0], reg_names[9]);
asm_fprintf (file, "\tadd %s,%s,%s\n",
- reg_names[0], reg_names[0], reg_names[11]);
+ reg_names[0], reg_names[0], reg_names[9]);
}
else
{
- asm_fprintf (file, "\tlis %s,", reg_names[12]);
+ asm_fprintf (file, "\tlis %s,", reg_names[10]);
assemble_name (file, buf);
fputs ("@ha\n", file);
asm_fprintf (file, "\tstw %s,4(%s)\n",
reg_names[0], reg_names[1]);
asm_fprintf (file, "\tla %s,", reg_names[0]);
assemble_name (file, buf);
- asm_fprintf (file, "@l(%s)\n", reg_names[12]);
+ asm_fprintf (file, "@l(%s)\n", reg_names[10]);
}
/* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
@@ -28729,7 +28737,7 @@ macho_branch_islands (void)
strcat (tmp_buf, name);
strcat (tmp_buf, "\n");
strcat (tmp_buf, label);
- strcat (tmp_buf, "_pic:\n\tmflr r11\n");
+ strcat (tmp_buf, "_pic:\n\tmflr r9\n");
}
else
{
@@ -28737,10 +28745,10 @@ macho_branch_islands (void)
strcat (tmp_buf, label);
strcat (tmp_buf, "_pic\n");
strcat (tmp_buf, label);
- strcat (tmp_buf, "_pic:\n\tmflr r11\n");
+ strcat (tmp_buf, "_pic:\n\tmflr r9\n");
}
- strcat (tmp_buf, "\taddis r11,r11,ha16(");
+ strcat (tmp_buf, "\taddis r9,r9,ha16(");
strcat (tmp_buf, name_buf);
strcat (tmp_buf, " - ");
strcat (tmp_buf, label);
@@ -28748,21 +28756,21 @@ macho_branch_islands (void)
strcat (tmp_buf, "\tmtlr r0\n");
- strcat (tmp_buf, "\taddi r12,r11,lo16(");
+ strcat (tmp_buf, "\taddi r10,r9,lo16(");
strcat (tmp_buf, name_buf);
strcat (tmp_buf, " - ");
strcat (tmp_buf, label);
strcat (tmp_buf, "_pic)\n");
- strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
+ strcat (tmp_buf, "\tmtctr r10\n\tbctr\n");
}
else
{
- strcat (tmp_buf, ":\nlis r12,hi16(");
+ strcat (tmp_buf, ":\nlis r10,hi16(");
strcat (tmp_buf, name_buf);
- strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
+ strcat (tmp_buf, ")\n\tori r10,r10,lo16(");
strcat (tmp_buf, name_buf);
- strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
+ strcat (tmp_buf, ")\n\tmtctr r10\n\tbctr");
}
output_asm_insn (tmp_buf, 0);
#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
@@ -28889,20 +28897,20 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub)
char name[32];
get_ppc476_thunk_name (name);
fprintf (file, "\tbl %s\n", name);
- fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
+ fprintf (file, "%s:\n\tmflr r9\n", local_label_0);
}
else
{
fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
- fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
+ fprintf (file, "%s:\n\tmflr r9\n", local_label_0);
}
- fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
+ fprintf (file, "\taddis r9,r9,ha16(%s-%s)\n",
lazy_ptr_name, local_label_0);
fprintf (file, "\tmtlr r0\n");
- fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
+ fprintf (file, "\t%s r10,lo16(%s-%s)(r9)\n",
(TARGET_64BIT ? "ldu" : "lwzu"),
lazy_ptr_name, local_label_0);
- fprintf (file, "\tmtctr r12\n");
+ fprintf (file, "\tmtctr r10\n");
fprintf (file, "\tbctr\n");
}
else
@@ -28912,11 +28920,11 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub)
fprintf (file, "%s:\n", stub);
fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
- fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
- fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
+ fprintf (file, "\tlis r9,ha16(%s)\n", lazy_ptr_name);
+ fprintf (file, "\t%s r10,lo16(%s)(r9)\n",
(TARGET_64BIT ? "ldu" : "lwzu"),
lazy_ptr_name);
- fprintf (file, "\tmtctr r12\n");
+ fprintf (file, "\tmtctr r10\n");
fprintf (file, "\tbctr\n");
}
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f36386770d7..203f669376f 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -982,10 +982,10 @@ enum data_align { align_abi, align_opt, align_both };
cr5 is not supposed to be used.
On System V implementations, r13 is fixed and not available for use. */
-
+/* TODO Maybe make R2 available on PPE */
#define FIXED_REGISTERS \
- {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, FIXED_R13, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
@@ -1007,8 +1007,8 @@ enum data_align { align_abi, align_opt, align_both };
Aside from that, you can include as many other registers as you like. */
#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
@@ -1029,8 +1029,8 @@ enum data_align { align_abi, align_opt, align_both };
of `CALL_USED_REGISTERS'. */
#define CALL_REALLY_USED_REGISTERS \
- {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
@@ -1109,12 +1109,12 @@ enum data_align { align_abi, align_opt, align_both };
33, \
63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
50, 49, 48, 47, 46, \
- 75, 74, 69, 68, 72, 71, 70, \
+ 68, \
MAYBE_R2_AVAILABLE \
9, 10, 8, 7, 6, 5, 4, \
- 3, EARLY_R12 11, 0, \
- 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
- 18, 17, 16, 15, 14, 13, LATE_R12 \
+ 3, EARLY_R12 0, \
+ 31, 30, 29, 28, \
+ 13, LATE_R12 \
66, 65, \
73, 1, MAYBE_R2_FIXED 67, 76, \
/* AltiVec registers. */ \
@@ -1305,7 +1305,7 @@ enum data_align { align_abi, align_opt, align_both };
#define ARG_POINTER_REGNUM 67
/* Place to put static chain when calling a function that requires it. */
-#define STATIC_CHAIN_REGNUM 11
+#define STATIC_CHAIN_REGNUM 10
/* Define the classes of registers for register constraints in the
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 46837e15389..47aa2398fe2 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -28,7 +28,7 @@
[(FIRST_GPR_REGNO 0)
(STACK_POINTER_REGNUM 1)
(TOC_REGNUM 2)
- (STATIC_CHAIN_REGNUM 11)
+ (STATIC_CHAIN_REGNUM 10)
(HARD_FRAME_POINTER_REGNUM 31)
(LAST_GPR_REGNO 31)
(FIRST_FPR_REGNO 32)
@@ -1211,7 +1211,7 @@
(sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
"rs6000_gen_cell_microcode"
"@
- lha%U1%X1 %0,%1
+ lhz%U1%X1 %0,%1\;extsh %0,%0
extsh %0,%1"
[(set_attr_alternative "type"
[(if_then_else
@@ -1284,415 +1284,415 @@
;; IBM 405, 440, 464 and 476 half-word multiplication operations.
-(define_insn "*macchwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_dup 2)
- (const_int 16))
- (sign_extend:SI
- (match_dup 1)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "macchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*macchw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "macchw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*macchwuc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_dup 2)
- (const_int 16))
- (zero_extend:SI
- (match_dup 1)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "macchwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*macchwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "macchwu %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*machhwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_dup 1)
- (const_int 16))
- (ashiftrt:SI
- (match_dup 2)
- (const_int 16)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "machhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*machhw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "machhw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*machhwuc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_dup 1)
- (const_int 16))
- (lshiftrt:SI
- (match_dup 2)
- (const_int 16)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "machhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*machhwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "machhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*maclhwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (sign_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (sign_extend:SI
- (match_dup 1))
- (sign_extend:SI
- (match_dup 2)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "maclhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*maclhw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (sign_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "maclhw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*maclhwuc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (zero_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (zero_extend:SI
- (match_dup 1))
- (zero_extend:SI
- (match_dup 2)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "maclhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*maclhwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (zero_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "maclhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*nmacchwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
- (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r"))))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_dup 4)
- (mult:SI (ashiftrt:SI
- (match_dup 2)
- (const_int 16))
- (sign_extend:SI
- (match_dup 1)))))]
- "TARGET_MULHW"
- "nmacchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*nmacchw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
- (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))))]
- "TARGET_MULHW"
- "nmacchw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*nmachhwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
- (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_dup 4)
- (mult:SI (ashiftrt:SI
- (match_dup 1)
- (const_int 16))
- (ashiftrt:SI
- (match_dup 2)
- (const_int 16)))))]
- "TARGET_MULHW"
- "nmachhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*nmachhw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
- (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))))]
- "TARGET_MULHW"
- "nmachhw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*nmaclhwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
- (mult:SI (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (sign_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r"))))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_dup 4)
- (mult:SI (sign_extend:SI
- (match_dup 1))
- (sign_extend:SI
- (match_dup 2)))))]
- "TARGET_MULHW"
- "nmaclhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*nmaclhw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
- (mult:SI (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (sign_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))))]
- "TARGET_MULHW"
- "nmaclhw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulchwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (ashiftrt:SI
- (match_dup 2)
- (const_int 16))
- (sign_extend:SI
- (match_dup 1))))]
- "TARGET_MULHW"
- "mulchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulchw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r"))))]
- "TARGET_MULHW"
- "mulchw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulchwuc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (mult:SI (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (lshiftrt:SI
- (match_dup 2)
- (const_int 16))
- (zero_extend:SI
- (match_dup 1))))]
- "TARGET_MULHW"
- "mulchwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulchwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r"))))]
- "TARGET_MULHW"
- "mulchwu %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulhhwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (ashiftrt:SI
- (match_dup 1)
- (const_int 16))
- (ashiftrt:SI
- (match_dup 2)
- (const_int 16))))]
- "TARGET_MULHW"
- "mulhhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulhhw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))))]
- "TARGET_MULHW"
- "mulhhw %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulhhwuc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (mult:SI (lshiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (lshiftrt:SI
- (match_dup 1)
- (const_int 16))
- (lshiftrt:SI
- (match_dup 2)
- (const_int 16))))]
- "TARGET_MULHW"
- "mulhhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
-
-(define_insn "*mulhhwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (lshiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))))]
- "TARGET_MULHW"
- "mulhhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+;;(define_insn "*macchwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r")))
+;; (match_operand:SI 4 "gpc_reg_operand" "0"))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (ashiftrt:SI
+;; (match_dup 2)
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_dup 1)))
+;; (match_dup 4)))]
+;; "TARGET_MULHW"
+;; "macchw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*macchw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r")))
+;; (match_operand:SI 3 "gpc_reg_operand" "0")))]
+;; "TARGET_MULHW"
+;; "macchw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*macchwuc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (zero_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r")))
+;; (match_operand:SI 4 "gpc_reg_operand" "0"))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (lshiftrt:SI
+;; (match_dup 2)
+;; (const_int 16))
+;; (zero_extend:SI
+;; (match_dup 1)))
+;; (match_dup 4)))]
+;; "TARGET_MULHW"
+;; "macchwu. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*macchwu"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (zero_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r")))
+;; (match_operand:SI 3 "gpc_reg_operand" "0")))]
+;; "TARGET_MULHW"
+;; "macchwu %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*machhwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16)))
+;; (match_operand:SI 4 "gpc_reg_operand" "0"))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (ashiftrt:SI
+;; (match_dup 1)
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_dup 2)
+;; (const_int 16)))
+;; (match_dup 4)))]
+;; "TARGET_MULHW"
+;; "machhw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*machhw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (ashiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16)))
+;; (match_operand:SI 3 "gpc_reg_operand" "0")))]
+;; "TARGET_MULHW"
+;; "machhw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*machhwuc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16)))
+;; (match_operand:SI 4 "gpc_reg_operand" "0"))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (lshiftrt:SI
+;; (match_dup 1)
+;; (const_int 16))
+;; (lshiftrt:SI
+;; (match_dup 2)
+;; (const_int 16)))
+;; (match_dup 4)))]
+;; "TARGET_MULHW"
+;; "machhwu. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*machhwu"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (lshiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16)))
+;; (match_operand:SI 3 "gpc_reg_operand" "0")))]
+;; "TARGET_MULHW"
+;; "machhwu %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*maclhwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (plus:SI (mult:SI (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "%r"))
+;; (sign_extend:SI
+;; (match_operand:HI 2 "gpc_reg_operand" "r")))
+;; (match_operand:SI 4 "gpc_reg_operand" "0"))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (sign_extend:SI
+;; (match_dup 1))
+;; (sign_extend:SI
+;; (match_dup 2)))
+;; (match_dup 4)))]
+;; "TARGET_MULHW"
+;; "maclhw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*maclhw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "%r"))
+;; (sign_extend:SI
+;; (match_operand:HI 2 "gpc_reg_operand" "r")))
+;; (match_operand:SI 3 "gpc_reg_operand" "0")))]
+;; "TARGET_MULHW"
+;; "maclhw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+;;
+;;(define_insn "*maclhwuc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (plus:SI (mult:SI (zero_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "%r"))
+;; (zero_extend:SI
+;; (match_operand:HI 2 "gpc_reg_operand" "r")))
+;; (match_operand:SI 4 "gpc_reg_operand" "0"))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (zero_extend:SI
+;; (match_dup 1))
+;; (zero_extend:SI
+;; (match_dup 2)))
+;; (match_dup 4)))]
+;; "TARGET_MULHW"
+;; "maclhwu. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*maclhwu"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (plus:SI (mult:SI (zero_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "%r"))
+;; (zero_extend:SI
+;; (match_operand:HI 2 "gpc_reg_operand" "r")))
+;; (match_operand:SI 3 "gpc_reg_operand" "0")))]
+;; "TARGET_MULHW"
+;; "maclhwu %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*nmacchwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+;; (mult:SI (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r"))))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (minus:SI (match_dup 4)
+;; (mult:SI (ashiftrt:SI
+;; (match_dup 2)
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_dup 1)))))]
+;; "TARGET_MULHW"
+;; "nmacchw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*nmacchw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+;; (mult:SI (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r")))))]
+;; "TARGET_MULHW"
+;; "nmacchw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*nmachhwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+;; (mult:SI (ashiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (minus:SI (match_dup 4)
+;; (mult:SI (ashiftrt:SI
+;; (match_dup 1)
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_dup 2)
+;; (const_int 16)))))]
+;; "TARGET_MULHW"
+;; "nmachhw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*nmachhw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+;; (mult:SI (ashiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16)))))]
+;; "TARGET_MULHW"
+;; "nmachhw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*nmaclhwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+;; (mult:SI (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "%r"))
+;; (sign_extend:SI
+;; (match_operand:HI 2 "gpc_reg_operand" "r"))))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (minus:SI (match_dup 4)
+;; (mult:SI (sign_extend:SI
+;; (match_dup 1))
+;; (sign_extend:SI
+;; (match_dup 2)))))]
+;; "TARGET_MULHW"
+;; "nmaclhw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*nmaclhw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+;; (mult:SI (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "%r"))
+;; (sign_extend:SI
+;; (match_operand:HI 2 "gpc_reg_operand" "r")))))]
+;; "TARGET_MULHW"
+;; "nmaclhw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulchwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (mult:SI (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r")))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (ashiftrt:SI
+;; (match_dup 2)
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_dup 1))))]
+;; "TARGET_MULHW"
+;; "mulchw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulchw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (sign_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+;; "TARGET_MULHW"
+;; "mulchw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulchwuc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (mult:SI (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (zero_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r")))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (lshiftrt:SI
+;; (match_dup 2)
+;; (const_int 16))
+;; (zero_extend:SI
+;; (match_dup 1))))]
+;; "TARGET_MULHW"
+;; "mulchwu. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulchwu"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))
+;; (zero_extend:SI
+;; (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+;; "TARGET_MULHW"
+;; "mulchwu %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulhhwc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (mult:SI (ashiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16)))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (ashiftrt:SI
+;; (match_dup 1)
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_dup 2)
+;; (const_int 16))))]
+;; "TARGET_MULHW"
+;; "mulhhw. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulhhw"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (ashiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (ashiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))))]
+;; "TARGET_MULHW"
+;; "mulhhw %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulhhwuc"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+;; (compare:CC (mult:SI (lshiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16)))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (lshiftrt:SI
+;; (match_dup 1)
+;; (const_int 16))
+;; (lshiftrt:SI
+;; (match_dup 2)
+;; (const_int 16))))]
+;; "TARGET_MULHW"
+;; "mulhhwu. %0,%1,%2"
+;; [(set_attr "type" "imul3")])
+
+;;(define_insn "*mulhhwu"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (mult:SI (lshiftrt:SI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r")
+;; (const_int 16))
+;; (lshiftrt:SI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")
+;; (const_int 16))))]
+;; "TARGET_MULHW"
+;; "mulhhwu %0,%1,%2"
+;; [(set_attr "type" "imul3")])
(define_insn "*mullhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -2277,14 +2277,14 @@
[(set_attr "length" "4")
(set_attr "type" "load")])
-(define_insn "*bswaphi2_extendsi"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
- ""
- "lhbrx %0,%y1"
- [(set_attr "length" "4")
- (set_attr "type" "load")])
+;;(define_insn "*bswaphi2_extendsi"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (zero_extend:SI
+;; (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
+;; ""
+;; "lhbrx %0,%y1"
+;; [(set_attr "length" "4")
+;; (set_attr "type" "load")])
(define_expand "bswaphi2"
[(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
@@ -2297,18 +2297,18 @@
operands[1] = force_reg (HImode, operands[1]);
})
-(define_insn "bswaphi2_internal"
- [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
- (bswap:HI
- (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
- (clobber (match_scratch:SI 2 "=X,X,&r"))]
- ""
- "@
- lhbrx %0,%y1
- sthbrx %1,%y0
- #"
- [(set_attr "length" "4,4,12")
- (set_attr "type" "load,store,*")])
+;;(define_insn "bswaphi2_internal"
+;; [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
+;; (bswap:HI
+;; (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
+;; (clobber (match_scratch:SI 2 "=X,X,&r"))]
+;; ""
+;; "@
+;; lhbrx %0,%y1
+;; sthbrx %1,%y0
+;; #"
+;; [(set_attr "length" "4,4,12")
+;; (set_attr "type" "load,store,*")])
;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
;; correct for -mlittle as well as -mbig.
@@ -2353,17 +2353,17 @@
operands[1] = force_reg (SImode, operands[1]);
})
-(define_insn "*bswapsi2_internal"
- [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
- (bswap:SI
- (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
- ""
- "@
- lwbrx %0,%y1
- stwbrx %1,%y0
- #"
- [(set_attr "length" "4,4,12")
- (set_attr "type" "load,store,*")])
+;;(define_insn "*bswapsi2_internal"
+;; [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
+;; (bswap:SI
+;; (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
+;; ""
+;; "@
+;; lwbrx %0,%y1
+;; stwbrx %1,%y0
+;; #"
+;; [(set_attr "length" "4,4,12")
+;; (set_attr "type" "load,store,*")])
;; We are always BITS_BIG_ENDIAN, so the bit positions below in
;; zero_extract insns do not change for -mlittle.
@@ -2711,33 +2711,33 @@
emit_insn (gen_bswapsi2 (dest2, src1));
}")
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
- ""
- "@
- mullw %0,%1,%2
- mulli %0,%1,%2"
- [(set (attr "type")
- (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "imul3")
- (match_operand:SI 2 "short_cint_operand" "")
- (const_string "imul2")]
- (const_string "imul")))])
-
-(define_insn "*mulsi3_internal1"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_32BIT"
- "@
- mullw. %3,%1,%2
- #"
- [(set_attr "type" "imul_compare")
- (set_attr "length" "4,8")])
+;;(define_insn "mulsi3"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+;; (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+;; (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
+;; ""
+;; "@
+;; mullhw %0,%1,%2
+;; mulli %0,%1,%2"
+;; [(set (attr "type")
+;; (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
+;; (const_string "imul3")
+;; (match_operand:SI 2 "short_cint_operand" "")
+;; (const_string "imul2")]
+;; (const_string "imul")))])
+
+;;(define_insn "*mulsi3_internal1"
+;; [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
+;; (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+;; (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+;; (const_int 0)))
+;; (clobber (match_scratch:SI 3 "=r,r"))]
+;; "TARGET_32BIT"
+;; "@
+;; mullw. %3,%1,%2
+;; #"
+;; [(set_attr "type" "imul_compare")
+;; (set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
@@ -2753,19 +2753,19 @@
(const_int 0)))]
"")
-(define_insn "*mulsi3_internal2"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT"
- "@
- mullw. %0,%1,%2
- #"
- [(set_attr "type" "imul_compare")
- (set_attr "length" "4,8")])
+;;(define_insn "*mulsi3_internal2"
+;; [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+;; (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+;; (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+;; (const_int 0)))
+;; (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+;; (mult:SI (match_dup 1) (match_dup 2)))]
+;; "TARGET_32BIT"
+;; "@
+;; mullw. %0,%1,%2
+;; #"
+;; [(set_attr "type" "imul_compare")
+;; (set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
@@ -2783,62 +2783,64 @@
"")
-(define_insn "udiv<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
- (match_operand:GPR 2 "gpc_reg_operand" "r")))]
- ""
- "div<wd>u %0,%1,%2"
- [(set_attr "type" "<idiv_ldiv>")])
+;;(define_insn "udiv<mode>3"
+;; [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+;; (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+;; (match_operand:GPR 2 "gpc_reg_operand" "r")))]
+;; ""
+;;;; "div<wd>u %0,%1,%2"
+;; "*return \"mr 3,%1\;mr 4,%2\;bl __udiv<mode>3\;mr %0,3\";"
+;; [(set_attr "type" "<idiv_ldiv>")])
;; For powers of two we can do srai/aze for divide and then adjust for
;; modulus. If it isn't a power of two, force operands into register and do
;; a normal divide.
-(define_expand "div<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "reg_or_cint_operand" "")))]
- ""
-{
- if (GET_CODE (operands[2]) != CONST_INT
- || INTVAL (operands[2]) <= 0
- || exact_log2 (INTVAL (operands[2])) < 0)
- operands[2] = force_reg (<MODE>mode, operands[2]);
-})
-
-(define_insn "*div<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
- (match_operand:GPR 2 "gpc_reg_operand" "r")))]
- ""
- "div<wd> %0,%1,%2"
- [(set_attr "type" "<idiv_ldiv>")])
-
-(define_expand "mod<mode>3"
- [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
- (use (match_operand:GPR 1 "gpc_reg_operand" ""))
- (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
- ""
- "
-{
- int i;
- rtx temp1;
- rtx temp2;
-
- if (GET_CODE (operands[2]) != CONST_INT
- || INTVAL (operands[2]) <= 0
- || (i = exact_log2 (INTVAL (operands[2]))) < 0)
- FAIL;
-
- temp1 = gen_reg_rtx (<MODE>mode);
- temp2 = gen_reg_rtx (<MODE>mode);
-
- emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
- emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
- emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
- DONE;
-}")
+;;(define_expand "div<mode>3"
+;; [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+;; (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+;; (match_operand:GPR 2 "reg_or_cint_operand" "")))]
+;; ""
+;;{
+;; if (GET_CODE (operands[2]) != CONST_INT
+;; || INTVAL (operands[2]) <= 0
+;; || exact_log2 (INTVAL (operands[2])) < 0)
+;; operands[2] = force_reg (<MODE>mode, operands[2]);
+;;})
+
+;;(define_insn "*div<mode>3"
+;; [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+;; (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+;; (match_operand:GPR 2 "gpc_reg_operand" "r")))]
+;; ""
+;; "div<wd> %0,%1,%2"
+;; "*return \"mr 3,%1\;mr 4,%2\;bl __div<mode>3\;mr %0,3\";"
+;; [(set_attr "type" "<idiv_ldiv>")])
+
+;;(define_expand "mod<mode>3"
+;; [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
+;; (use (match_operand:GPR 1 "gpc_reg_operand" ""))
+;; (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
+;; ""
+;; "
+;;{
+;; int i;
+;; rtx temp1;
+;; rtx temp2;
+;;
+;; if (GET_CODE (operands[2]) != CONST_INT
+;; || INTVAL (operands[2]) <= 0
+;; || (i = exact_log2 (INTVAL (operands[2]))) < 0)
+;; FAIL;
+;;
+;; temp1 = gen_reg_rtx (<MODE>mode);
+;; temp2 = gen_reg_rtx (<MODE>mode);
+;;
+;; emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
+;; emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
+;; emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
+;; DONE;
+;;}")
(define_insn ""
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
@@ -6662,18 +6664,18 @@
[(set_attr "type" "two")
(set_attr "length" "8")])
-(define_insn "mulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "! TARGET_POWERPC64"
-{
- return (WORDS_BIG_ENDIAN)
- ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
- : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
-}
- [(set_attr "type" "imul")
- (set_attr "length" "8")])
+;;(define_insn "mulsidi3"
+;; [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+;; (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+;; (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+;; "! TARGET_POWERPC64"
+;;{
+;; return (WORDS_BIG_ENDIAN)
+;; ? \"mulhw %0,%1,%2\;mullhw %L0,%1,%2\"
+;; : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
+;;}
+;; [(set_attr "type" "imul")
+;; (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -6695,19 +6697,19 @@
operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
}")
-(define_insn "umulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "! TARGET_POWERPC64"
- "*
-{
- return (WORDS_BIG_ENDIAN)
- ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
- : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "length" "8")])
+;;(define_insn "umulsidi3"
+;; [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+;; (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+;; (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+;; "! TARGET_POWERPC64"
+;; "*
+;;{
+;; return (WORDS_BIG_ENDIAN)
+;; ? \"mulhwu %0,%1,%2\;mullhw %L0,%1,%2\"
+;; : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
+;;}"
+;; [(set_attr "type" "imul")
+;; (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -6729,29 +6731,29 @@
operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
}")
-(define_insn "smulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))]
- ""
- "mulhw %0,%1,%2"
- [(set_attr "type" "imul")])
-
-(define_insn "umulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))]
- ""
- "mulhwu %0,%1,%2"
- [(set_attr "type" "imul")])
+;;(define_insn "smulsi3_highpart"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (truncate:SI
+;; (lshiftrt:DI (mult:DI (sign_extend:DI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r"))
+;; (sign_extend:DI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")))
+;; (const_int 32))))]
+;; ""
+;; "mulhw %0,%1,%2"
+;; [(set_attr "type" "imul")])
+
+;;(define_insn "umulsi3_highpart"
+;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+;; (truncate:SI
+;; (lshiftrt:DI (mult:DI (zero_extend:DI
+;; (match_operand:SI 1 "gpc_reg_operand" "%r"))
+;; (zero_extend:DI
+;; (match_operand:SI 2 "gpc_reg_operand" "r")))
+;; (const_int 32))))]
+;; ""
+;; "*return \"mr 3,%2\;mr 4,%1\;bl __umulsi3_highpart\;mr %0,3\";"
+;; [(set_attr "type" "imul")])
;; Shift by a variable amount is too complex to be worth open-coding. We
;; just handle shifts by constants.
@@ -10374,41 +10376,41 @@
;; TImode/PTImode is similar, except that we usually want to compute the
;; address into a register and use lsi/stsi (the exception is during reload).
-(define_insn "*mov<mode>_string"
- [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
- (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
- "! TARGET_POWERPC64
- && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
- && (gpc_reg_operand (operands[0], <MODE>mode)
- || gpc_reg_operand (operands[1], <MODE>mode))"
- "*
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (TARGET_STRING)
- return \"stswi %1,%P0,16\";
- case 1:
- return \"#\";
- case 2:
- /* If the address is not used in the output, we can use lsi. Otherwise,
- fall through to generating four loads. */
- if (TARGET_STRING
- && ! reg_overlap_mentioned_p (operands[0], operands[1]))
- return \"lswi %0,%P1,16\";
- /* ... fall through ... */
- case 3:
- case 4:
- case 5:
- return \"#\";
- }
-}"
- [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
- (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
- (const_string "always")
- (const_string "conditional")))])
+;;(define_insn "*mov<mode>_string"
+;; [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
+;; (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
+;; "! TARGET_POWERPC64
+;; && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
+;; && (gpc_reg_operand (operands[0], <MODE>mode)
+;; || gpc_reg_operand (operands[1], <MODE>mode))"
+;; "*
+;;{
+;; switch (which_alternative)
+;; {
+;; default:
+;; gcc_unreachable ();
+;; case 0:
+;; if (TARGET_STRING)
+;; return \"stswi %1,%P0,16\";
+;; case 1:
+;; return \"#\";
+;; case 2:
+;; /* If the address is not used in the output, we can use lsi. Otherwise,
+;; fall through to generating four loads. */
+;; if (TARGET_STRING
+;; && ! reg_overlap_mentioned_p (operands[0], operands[1]))
+;; return \"lswi %0,%P1,16\";
+;; /* ... fall through ... */
+;; case 3:
+;; case 4:
+;; case 5:
+;; return \"#\";
+;; }
+;;}"
+;; [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
+;; (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
+;; (const_string "always")
+;; (const_string "conditional")))])
(define_insn "*mov<mode>_ppc64"
[(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
@@ -10809,172 +10811,172 @@
;; Move up to 32 bytes at a time. The fixed registers are needed because the
;; register allocator doesn't have a clue about allocating 8 word registers.
;; rD/rS = r5 is preferred, efficient form.
-(define_expand "movmemsi_8reg"
- [(parallel [(set (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))
- (clobber (reg:SI 5))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (reg:SI 11))
- (clobber (reg:SI 12))
- (clobber (match_scratch:SI 4 ""))])]
- "TARGET_STRING"
- "")
-
-(define_insn ""
- [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (reg:SI 11))
- (clobber (reg:SI 12))
- (clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING
- && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
- || INTVAL (operands[2]) == 0)
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
- && REGNO (operands[4]) == 5"
- "lswi %4,%1,%2\;stswi %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
+;;(define_expand "movmemsi_8reg"
+;; [(parallel [(set (match_operand 0 "" "")
+;; (match_operand 1 "" ""))
+;; (use (match_operand 2 "" ""))
+;; (use (match_operand 3 "" ""))
+;; (clobber (reg:SI 5))
+;; (clobber (reg:SI 6))
+;; (clobber (reg:SI 7))
+;; (clobber (reg:SI 8))
+;; (clobber (reg:SI 9))
+;; (clobber (reg:SI 10))
+;; (clobber (reg:SI 11))
+;; (clobber (reg:SI 12))
+;; (clobber (match_scratch:SI 4 ""))])]
+;; "TARGET_STRING"
+;; "")
+
+;;(define_insn ""
+;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
+;; (use (match_operand:SI 2 "immediate_operand" "i"))
+;; (use (match_operand:SI 3 "immediate_operand" "i"))
+;; (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
+;; (clobber (reg:SI 6))
+;; (clobber (reg:SI 7))
+;; (clobber (reg:SI 8))
+;; (clobber (reg:SI 9))
+;; (clobber (reg:SI 10))
+;; (clobber (reg:SI 11))
+;; (clobber (reg:SI 12))
+;; (clobber (match_scratch:SI 5 "=X"))]
+;; "TARGET_STRING
+;; && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
+;; || INTVAL (operands[2]) == 0)
+;; && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
+;; && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
+;; && REGNO (operands[4]) == 5"
+;; "lswi %4,%1,%2\;stswi %4,%0,%2"
+;; [(set_attr "type" "store_ux")
+;; (set_attr "cell_micro" "always")
+;; (set_attr "length" "8")])
;; Move up to 24 bytes at a time. The fixed registers are needed because the
;; register allocator doesn't have a clue about allocating 6 word registers.
;; rD/rS = r5 is preferred, efficient form.
-(define_expand "movmemsi_6reg"
- [(parallel [(set (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))
- (clobber (reg:SI 5))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (match_scratch:SI 4 ""))])]
- "TARGET_STRING"
- "")
-
-(define_insn ""
- [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING
- && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
- && REGNO (operands[4]) == 5"
- "lswi %4,%1,%2\;stswi %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
+;;(define_expand "movmemsi_6reg"
+;; [(parallel [(set (match_operand 0 "" "")
+;; (match_operand 1 "" ""))
+;; (use (match_operand 2 "" ""))
+;; (use (match_operand 3 "" ""))
+;; (clobber (reg:SI 5))
+;; (clobber (reg:SI 6))
+;; (clobber (reg:SI 7))
+;; (clobber (reg:SI 8))
+;; (clobber (reg:SI 9))
+;; (clobber (reg:SI 10))
+;; (clobber (match_scratch:SI 4 ""))])]
+;; "TARGET_STRING"
+;; "")
+
+;;(define_insn ""
+;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
+;; (use (match_operand:SI 2 "immediate_operand" "i"))
+;; (use (match_operand:SI 3 "immediate_operand" "i"))
+;; (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
+;; (clobber (reg:SI 6))
+;; (clobber (reg:SI 7))
+;; (clobber (reg:SI 8))
+;; (clobber (reg:SI 9))
+;; (clobber (reg:SI 10))
+;; (clobber (match_scratch:SI 5 "=X"))]
+;; "TARGET_STRING
+;; && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
+;; && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
+;; && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
+;; && REGNO (operands[4]) == 5"
+;; "lswi %4,%1,%2\;stswi %4,%0,%2"
+;; [(set_attr "type" "store_ux")
+;; (set_attr "cell_micro" "always")
+;; (set_attr "length" "8")])
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
;; problems with TImode.
;; rD/rS = r5 is preferred, efficient form.
-(define_expand "movmemsi_4reg"
- [(parallel [(set (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))
- (clobber (reg:SI 5))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (match_scratch:SI 4 ""))])]
- "TARGET_STRING"
- "")
-
-(define_insn ""
- [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING
- && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
- && REGNO (operands[4]) == 5"
- "lswi %4,%1,%2\;stswi %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
+;;(define_expand "movmemsi_4reg"
+;; [(parallel [(set (match_operand 0 "" "")
+;; (match_operand 1 "" ""))
+;; (use (match_operand 2 "" ""))
+;; (use (match_operand 3 "" ""))
+;; (clobber (reg:SI 5))
+;; (clobber (reg:SI 6))
+;; (clobber (reg:SI 7))
+;; (clobber (reg:SI 8))
+;; (clobber (match_scratch:SI 4 ""))])]
+;; "TARGET_STRING"
+;; "")
+
+;;(define_insn ""
+;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
+;; (use (match_operand:SI 2 "immediate_operand" "i"))
+;; (use (match_operand:SI 3 "immediate_operand" "i"))
+;; (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
+;; (clobber (reg:SI 6))
+;; (clobber (reg:SI 7))
+;; (clobber (reg:SI 8))
+;; (clobber (match_scratch:SI 5 "=X"))]
+;; "TARGET_STRING
+;; && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
+;; && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
+;; && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
+;; && REGNO (operands[4]) == 5"
+;; "lswi %4,%1,%2\;stswi %4,%0,%2"
+;; [(set_attr "type" "store_ux")
+;; (set_attr "cell_micro" "always")
+;; (set_attr "length" "8")])
;; Move up to 8 bytes at a time.
-(define_expand "movmemsi_2reg"
- [(parallel [(set (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))
- (clobber (match_scratch:DI 4 ""))
- (clobber (match_scratch:SI 5 ""))])]
- "TARGET_STRING && ! TARGET_POWERPC64"
- "")
-
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_scratch:DI 4 "=&r"))
- (clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWERPC64
- && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
- "lswi %4,%1,%2\;stswi %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
+;;(define_expand "movmemsi_2reg"
+;; [(parallel [(set (match_operand 0 "" "")
+;; (match_operand 1 "" ""))
+;; (use (match_operand 2 "" ""))
+;; (use (match_operand 3 "" ""))
+;; (clobber (match_scratch:DI 4 ""))
+;; (clobber (match_scratch:SI 5 ""))])]
+;; "TARGET_STRING && ! TARGET_POWERPC64"
+;; "")
+
+;;(define_insn ""
+;; [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
+;; (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
+;; (use (match_operand:SI 2 "immediate_operand" "i"))
+;; (use (match_operand:SI 3 "immediate_operand" "i"))
+;; (clobber (match_scratch:DI 4 "=&r"))
+;; (clobber (match_scratch:SI 5 "=X"))]
+;; "TARGET_STRING && ! TARGET_POWERPC64
+;; && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
+;; "lswi %4,%1,%2\;stswi %4,%0,%2"
+;; [(set_attr "type" "store_ux")
+;; (set_attr "cell_micro" "always")
+;; (set_attr "length" "8")])
;; Move up to 4 bytes at a time.
-(define_expand "movmemsi_1reg"
- [(parallel [(set (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))])]
- "TARGET_STRING"
- "")
-
-(define_insn ""
- [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_scratch:SI 4 "=&r"))
- (clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
- "lswi %4,%1,%2\;stswi %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
+;;(define_expand "movmemsi_1reg"
+;; [(parallel [(set (match_operand 0 "" "")
+;; (match_operand 1 "" ""))
+;; (use (match_operand 2 "" ""))
+;; (use (match_operand 3 "" ""))
+;; (clobber (match_scratch:SI 4 ""))
+;; (clobber (match_scratch:SI 5 ""))])]
+;; "TARGET_STRING"
+;; "")
+
+;;(define_insn ""
+;; [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+;; (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
+;; (use (match_operand:SI 2 "immediate_operand" "i"))
+;; (use (match_operand:SI 3 "immediate_operand" "i"))
+;; (clobber (match_scratch:SI 4 "=&r"))
+;; (clobber (match_scratch:SI 5 "=X"))]
+;; "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+;; "lswi %4,%1,%2\;stswi %4,%0,%2"
+;; [(set_attr "type" "store_ux")
+;; (set_attr "cell_micro" "always")
+;; (set_attr "length" "8")])
;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also
@@ -11039,7 +11041,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- lwzux %3,%0,%2
+ lwzx %3,%0,%2\;add %0,%0,%2
lwzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
@@ -11067,7 +11069,7 @@
|| (REG_P (operands[0])
&& REGNO (operands[0]) == STACK_POINTER_REGNUM))"
"@
- stwux %3,%0,%2
+ stwx %3,%0,%2\;add %0,%0,%2
stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
@@ -11081,7 +11083,7 @@
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- stwux %3,%0,%2
+ stwx %3,%0,%2\;add %0,%0,%2
stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
@@ -11095,7 +11097,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- lhzux %3,%0,%2
+ lhzx %3,%0,%2\;add %0,%0,%2
lhzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
@@ -11110,7 +11112,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- lhzux %3,%0,%2
+ lhzx %3,%0,%2\;add %0,%0,%2
lhzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
@@ -11125,8 +11127,8 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- lhaux %3,%0,%2
- lhau %3,%2(%0)"
+ lhzx %3,%0,%2\;add %0,%0,%2\;extsh %3,%3
+ lhzu %3,%2(%0)\;extsh %3,%3"
[(set_attr "type" "load_ext_ux,load_ext_u")])
(define_insn "*movhi_update4"
@@ -11139,7 +11141,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- sthux %3,%0,%2
+ sthx %3,%0,%2\;add %0,%0,%2
sthu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
@@ -11153,7 +11155,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- lbzux %3,%0,%2
+ lbzx %3, %0, %2\;add %0,%0,%2
lbzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
@@ -11168,7 +11170,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- lbzux %3,%0,%2
+ lbzx %3,%0,%2\;add %0,%0,%2
lbzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
@@ -11182,7 +11184,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- stbux %3,%0,%2
+ stbx %3,%0,%2\;add %0,%0,%2
stbu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
@@ -11224,7 +11226,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- lwzux %3,%0,%2
+ lwzx %3,%0,%2\;add %0,%0,%2
lwzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
@@ -11238,7 +11240,7 @@
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- stwux %3,%0,%2
+ stwx %3,%0,%2\;add %0,%0,%2
stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
@@ -15134,13 +15136,13 @@
"stw %2,%1"
[(set_attr "type" "store")])
-(define_insn "*stmw"
- [(match_parallel 0 "stmw_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
- (match_operand:SI 2 "gpc_reg_operand" "r"))])]
- "TARGET_MULTIPLE"
- "stmw %2,%1"
- [(set_attr "type" "store_ux")])
+;;(define_insn "*stmw"
+;; [(match_parallel 0 "stmw_operation"
+;; [(set (match_operand:SI 1 "memory_operand" "=m")
+;; (match_operand:SI 2 "gpc_reg_operand" "r"))])]
+;; "TARGET_MULTIPLE"
+;; "stmw %2,%1"
+;; [(set_attr "type" "store_ux")])
; The following comment applies to:
; save_gpregs_*
@@ -15155,13 +15157,13 @@
; MATCH_OPERAND for that argument. That way the register rename
; optimization will not try to rename this register.
; Each pattern is repeated for each possible register number used in
-; various ABIs (r11, r1, and for some functions r12)
+; various ABIs (r9, r1, and for some functions r10)
-(define_insn "*save_gpregs_<mode>_r11"
+(define_insn "*save_gpregs_<mode>_r9"
[(match_parallel 0 "any_parallel_operand"
[(clobber (reg:P 65))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
- (use (reg:P 11))
+ (use (reg:P 9))
(set (match_operand:P 2 "memory_operand" "=m")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
@@ -15169,11 +15171,11 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*save_gpregs_<mode>_r12"
+(define_insn "*save_gpregs_<mode>_r10"
[(match_parallel 0 "any_parallel_operand"
[(clobber (reg:P 65))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
- (use (reg:P 12))
+ (use (reg:P 10))
(set (match_operand:P 2 "memory_operand" "=m")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
@@ -15193,11 +15195,11 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*save_fpregs_<mode>_r11"
+(define_insn "*save_fpregs_<mode>_r9"
[(match_parallel 0 "any_parallel_operand"
[(clobber (reg:P 65))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
- (use (reg:P 11))
+ (use (reg:P 9))
(set (match_operand:DF 2 "memory_operand" "=m")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
@@ -15325,13 +15327,13 @@
; MATCH_OPERAND for that argument. That way the register rename
; optimization will not try to rename this register.
; Each pattern is repeated for each possible register number used in
-; various ABIs (r11, r1, and for some functions r12)
+; various ABIs (r9, r1, and for some functions r12)
-(define_insn "*restore_gpregs_<mode>_r11"
+(define_insn "*restore_gpregs_<mode>_r9"
[(match_parallel 0 "any_parallel_operand"
[(clobber (match_operand:P 1 "register_operand" "=l"))
(use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 11))
+ (use (reg:P 9))
(set (match_operand:P 3 "gpc_reg_operand" "=r")
(match_operand:P 4 "memory_operand" "m"))])]
""
@@ -15339,11 +15341,11 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*restore_gpregs_<mode>_r12"
+(define_insn "*restore_gpregs_<mode>_r10"
[(match_parallel 0 "any_parallel_operand"
[(clobber (match_operand:P 1 "register_operand" "=l"))
(use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 12))
+ (use (reg:P 10))
(set (match_operand:P 3 "gpc_reg_operand" "=r")
(match_operand:P 4 "memory_operand" "m"))])]
""
@@ -15363,12 +15365,12 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*return_and_restore_gpregs_<mode>_r11"
+(define_insn "*return_and_restore_gpregs_<mode>_r9"
[(match_parallel 0 "any_parallel_operand"
[(return)
(clobber (match_operand:P 1 "register_operand" "=l"))
(use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 11))
+ (use (reg:P 9))
(set (match_operand:P 3 "gpc_reg_operand" "=r")
(match_operand:P 4 "memory_operand" "m"))])]
""
@@ -15376,12 +15378,12 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*return_and_restore_gpregs_<mode>_r12"
+(define_insn "*return_and_restore_gpregs_<mode>_r10"
[(match_parallel 0 "any_parallel_operand"
[(return)
(clobber (match_operand:P 1 "register_operand" "=l"))
(use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 12))
+ (use (reg:P 10))
(set (match_operand:P 3 "gpc_reg_operand" "=r")
(match_operand:P 4 "memory_operand" "m"))])]
""
@@ -15402,12 +15404,12 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*return_and_restore_fpregs_<mode>_r11"
+(define_insn "*return_and_restore_fpregs_<mode>_r9"
[(match_parallel 0 "any_parallel_operand"
[(return)
(clobber (match_operand:P 1 "register_operand" "=l"))
(use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 11))
+ (use (reg:P 9))
(set (match_operand:DF 3 "gpc_reg_operand" "=d")
(match_operand:DF 4 "memory_operand" "m"))])]
""
@@ -15441,12 +15443,12 @@
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
+(define_insn "*return_and_restore_fpregs_aix_<mode>_r9"
[(match_parallel 0 "any_parallel_operand"
[(return)
(use (match_operand:P 1 "register_operand" "l"))
(use (match_operand:P 2 "symbol_ref_operand" "s"))
- (use (reg:P 11))
+ (use (reg:P 9))
(set (match_operand:DF 3 "gpc_reg_operand" "=d")
(match_operand:DF 4 "memory_operand" "m"))])]
""
OpenPOWER on IntegriCloud