/* Xtensa configuration-specific ISA information. Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #include "ansidecl.h" #include #include "xtensa-isa-internal.h" /* Sysregs. */ static xtensa_sysreg_internal sysregs[] = { { "LBEG", 0, 0 }, { "LEND", 1, 0 }, { "LCOUNT", 2, 0 }, { "PTEVADDR", 83, 0 }, { "MMID", 89, 0 }, { "DDR", 104, 0 }, { "176", 176, 0 }, { "208", 208, 0 }, { "INTERRUPT", 226, 0 }, { "INTCLEAR", 227, 0 }, { "CCOUNT", 234, 0 }, { "PRID", 235, 0 }, { "ICOUNT", 236, 0 }, { "CCOMPARE0", 240, 0 }, { "CCOMPARE1", 241, 0 }, { "CCOMPARE2", 242, 0 }, { "VECBASE", 231, 0 }, { "EPC1", 177, 0 }, { "EPC2", 178, 0 }, { "EPC3", 179, 0 }, { "EPC4", 180, 0 }, { "EPC5", 181, 0 }, { "EPC6", 182, 0 }, { "EPC7", 183, 0 }, { "EXCSAVE1", 209, 0 }, { "EXCSAVE2", 210, 0 }, { "EXCSAVE3", 211, 0 }, { "EXCSAVE4", 212, 0 }, { "EXCSAVE5", 213, 0 }, { "EXCSAVE6", 214, 0 }, { "EXCSAVE7", 215, 0 }, { "EPS2", 194, 0 }, { "EPS3", 195, 0 }, { "EPS4", 196, 0 }, { "EPS5", 197, 0 }, { "EPS6", 198, 0 }, { "EPS7", 199, 0 }, { "EXCCAUSE", 232, 0 }, { "DEPC", 192, 0 }, { "EXCVADDR", 238, 0 }, { "WINDOWBASE", 72, 0 }, { "WINDOWSTART", 73, 0 }, { "SAR", 3, 0 }, { "LITBASE", 5, 0 }, { "PS", 230, 0 }, { "MISC0", 244, 0 }, { "MISC1", 245, 0 }, { "INTENABLE", 228, 0 }, { "DBREAKA0", 144, 0 }, { "DBREAKC0", 160, 0 }, { "DBREAKA1", 145, 0 }, { "DBREAKC1", 161, 0 }, { "IBREAKA0", 128, 0 }, { "IBREAKA1", 129, 0 }, { "IBREAKENABLE", 96, 0 }, { "ICOUNTLEVEL", 237, 0 }, { "DEBUGCAUSE", 233, 0 }, { "RASID", 90, 0 }, { "ITLBCFG", 91, 0 }, { "DTLBCFG", 92, 0 }, { "CPENABLE", 224, 0 }, { "SCOMPARE1", 12, 0 }, { "THREADPTR", 231, 1 } }; #define NUM_SYSREGS 63 #define MAX_SPECIAL_REG 245 #define MAX_USER_REG 231 /* Processor states. */ static xtensa_state_internal states[] = { { "LCOUNT", 32, 0 }, { "PC", 32, 0 }, { "ICOUNT", 32, 0 }, { "DDR", 32, 0 }, { "INTERRUPT", 22, 0 }, { "CCOUNT", 32, 0 }, { "XTSYNC", 1, 0 }, { "VECBASE", 22, 0 }, { "EPC1", 32, 0 }, { "EPC2", 32, 0 }, { "EPC3", 32, 0 }, { "EPC4", 32, 0 }, { "EPC5", 32, 0 }, { "EPC6", 32, 0 }, { "EPC7", 32, 0 }, { "EXCSAVE1", 32, 0 }, { "EXCSAVE2", 32, 0 }, { "EXCSAVE3", 32, 0 }, { "EXCSAVE4", 32, 0 }, { "EXCSAVE5", 32, 0 }, { "EXCSAVE6", 32, 0 }, { "EXCSAVE7", 32, 0 }, { "EPS2", 15, 0 }, { "EPS3", 15, 0 }, { "EPS4", 15, 0 }, { "EPS5", 15, 0 }, { "EPS6", 15, 0 }, { "EPS7", 15, 0 }, { "EXCCAUSE", 6, 0 }, { "PSINTLEVEL", 4, 0 }, { "PSUM", 1, 0 }, { "PSWOE", 1, 0 }, { "PSRING", 2, 0 }, { "PSEXCM", 1, 0 }, { "DEPC", 32, 0 }, { "EXCVADDR", 32, 0 }, { "WindowBase", 3, 0 }, { "WindowStart", 8, 0 }, { "PSCALLINC", 2, 0 }, { "PSOWB", 4, 0 }, { "LBEG", 32, 0 }, { "LEND", 32, 0 }, { "SAR", 6, 0 }, { "THREADPTR", 32, 0 }, { "LITBADDR", 20, 0 }, { "LITBEN", 1, 0 }, { "MISC0", 32, 0 }, { "MISC1", 32, 0 }, { "InOCDMode", 1, 0 }, { "INTENABLE", 22, 0 }, { "DBREAKA0", 32, 0 }, { "DBREAKC0", 8, 0 }, { "DBREAKA1", 32, 0 }, { "DBREAKC1", 8, 0 }, { "IBREAKA0", 32, 0 }, { "IBREAKA1", 32, 0 }, { "IBREAKENABLE", 2, 0 }, { "ICOUNTLEVEL", 4, 0 }, { "DEBUGCAUSE", 6, 0 }, { "DBNUM", 4, 0 }, { "CCOMPARE0", 32, 0 }, { "CCOMPARE1", 32, 0 }, { "CCOMPARE2", 32, 0 }, { "ASID3", 8, 0 }, { "ASID2", 8, 0 }, { "ASID1", 8, 0 }, { "INSTPGSZID4", 2, 0 }, { "DATAPGSZID4", 2, 0 }, { "PTBASE", 10, 0 }, { "CPENABLE", 8, 0 }, { "SCOMPARE1", 32, 0 } }; #define NUM_STATES 71 enum xtensa_state_id { STATE_LCOUNT, STATE_PC, STATE_ICOUNT, STATE_DDR, STATE_INTERRUPT, STATE_CCOUNT, STATE_XTSYNC, STATE_VECBASE, STATE_EPC1, STATE_EPC2, STATE_EPC3, STATE_EPC4, STATE_EPC5, STATE_EPC6, STATE_EPC7, STATE_EXCSAVE1, STATE_EXCSAVE2, STATE_EXCSAVE3, STATE_EXCSAVE4, STATE_EXCSAVE5, STATE_EXCSAVE6, STATE_EXCSAVE7, STATE_EPS2, STATE_EPS3, STATE_EPS4, STATE_EPS5, STATE_EPS6, STATE_EPS7, STATE_EXCCAUSE, STATE_PSINTLEVEL, STATE_PSUM, STATE_PSWOE, STATE_PSRING, STATE_PSEXCM, STATE_DEPC, STATE_EXCVADDR, STATE_WindowBase, STATE_WindowStart, STATE_PSCALLINC, STATE_PSOWB, STATE_LBEG, STATE_LEND, STATE_SAR, STATE_THREADPTR, STATE_LITBADDR, STATE_LITBEN, STATE_MISC0, STATE_MISC1, STATE_InOCDMode, STATE_INTENABLE, STATE_DBREAKA0, STATE_DBREAKC0, STATE_DBREAKA1, STATE_DBREAKC1, STATE_IBREAKA0, STATE_IBREAKA1, STATE_IBREAKENABLE, STATE_ICOUNTLEVEL, STATE_DEBUGCAUSE, STATE_DBNUM, STATE_CCOMPARE0, STATE_CCOMPARE1, STATE_CCOMPARE2, STATE_ASID3, STATE_ASID2, STATE_ASID1, STATE_INSTPGSZID4, STATE_DATAPGSZID4, STATE_PTBASE, STATE_CPENABLE, STATE_SCOMPARE1 }; /* Field definitions. */ static unsigned Field_t_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } static void Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); } static unsigned Field_s_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned Field_r_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned Field_op2_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_op1_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); return tie_t; } static void Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned Field_op0_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); return tie_t; } static void Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); } static unsigned Field_n_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); return tie_t; } static void Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 30) >> 30; insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); } static unsigned Field_m_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); return tie_t; } static void Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 30) >> 30; insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); } static unsigned Field_sr_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); tie_t = (val << 24) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned Field_st_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } static void Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); tie_t = (val << 24) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); return tie_t; } static void Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 29) >> 29; insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); } static unsigned Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); return tie_t; } static void Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x400) | (tie_t << 10); } static unsigned Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); return tie_t; } static void Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x800) | (tie_t << 11); } static unsigned Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); return tie_t; } static void Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); return tie_t; } static void Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x100) | (tie_t << 8); } static unsigned Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } static void Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); tie_t = (val << 27) >> 31; insn[0] = (insn[0] & ~0x100) | (tie_t << 8); } static unsigned Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); return tie_t; } static void Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 20) >> 20; insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); } static unsigned Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); return tie_t; } static void Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 24) >> 24; insn[0] = (insn[0] & ~0xff) | (tie_t << 0); } static unsigned Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); return tie_t; } static void Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); return tie_t; } static void Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 24) >> 24; insn[0] = (insn[0] & ~0xff) | (tie_t << 0); tie_t = (val << 20) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); } static unsigned Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); return tie_t; } static void Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 16) >> 16; insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); } static unsigned Field_offset_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); return tie_t; } static void Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 14) >> 14; insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); } static unsigned Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); return tie_t; } static void Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x1) | (tie_t << 0); } static unsigned Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); return tie_t; } static void Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x10) | (tie_t << 4); } static unsigned Field_sae_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); tie_t = (val << 27) >> 31; insn[0] = (insn[0] & ~0x10) | (tie_t << 4); } static unsigned Field_sal_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); return tie_t; } static void Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); tie_t = (val << 27) >> 31; insn[0] = (insn[0] & ~0x1) | (tie_t << 0); } static unsigned Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); tie_t = (val << 27) >> 31; insn[0] = (insn[0] & ~0x1) | (tie_t << 0); } static unsigned Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); return tie_t; } static void Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); } static unsigned Field_sas_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); return tie_t; } static void Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); tie_t = (val << 27) >> 31; insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); } static unsigned Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); tie_t = (val << 24) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); tie_t = (val << 24) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); tie_t = (val << 24) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); tie_t = (val << 24) >> 28; insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); } static unsigned Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); return tie_t; } static void Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); } static unsigned Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_mn_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); return tie_t; } static void Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 30) >> 30; insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); tie_t = (val << 28) >> 30; insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); } static unsigned Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); return tie_t; } static void Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x800) | (tie_t << 11); } static unsigned Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); return tie_t; } static void Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 30) >> 30; insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); return tie_t; } static void Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 30) >> 30; insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); } static unsigned Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); return tie_t; } static void Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 29) >> 29; insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); return tie_t; } static void Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 29) >> 29; insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); return tie_t; } static void Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 31) >> 31; insn[0] = (insn[0] & ~0x400) | (tie_t << 10); } static unsigned Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); tie_t = (val << 26) >> 30; insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); tie_t = (val << 26) >> 30; insn[0] = (insn[0] & ~0x300) | (tie_t << 8); } static unsigned Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); tie_t = (val << 25) >> 29; insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); return tie_t; } static void Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 28) >> 28; insn[0] = (insn[0] & ~0xf) | (tie_t << 0); tie_t = (val << 25) >> 29; insn[0] = (insn[0] & ~0x700) | (tie_t << 8); } static unsigned Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); return tie_t; } static void Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 17) >> 17; insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); } static unsigned Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); return tie_t; } static void Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) { uint32 tie_t; tie_t = (val << 14) >> 14; insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); } static void Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, uint32 val ATTRIBUTE_UNUSED) { /* Do nothing. */ } static unsigned Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { return 0; } static unsigned Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { return 4; } static unsigned Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { return 8; } static unsigned Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) { return 12; } enum xtensa_field_id { FIELD_t, FIELD_bbi4, FIELD_bbi, FIELD_imm12, FIELD_imm8, FIELD_s, FIELD_imm12b, FIELD_imm16, FIELD_m, FIELD_n, FIELD_offset, FIELD_op0, FIELD_op1, FIELD_op2, FIELD_r, FIELD_sa4, FIELD_sae4, FIELD_sae, FIELD_sal, FIELD_sargt, FIELD_sas4, FIELD_sas, FIELD_sr, FIELD_st, FIELD_thi3, FIELD_imm4, FIELD_mn, FIELD_i, FIELD_imm6lo, FIELD_imm6hi, FIELD_imm7lo, FIELD_imm7hi, FIELD_z, FIELD_imm6, FIELD_imm7, FIELD_xt_wbr15_imm, FIELD_xt_wbr18_imm, FIELD__ar0, FIELD__ar4, FIELD__ar8, FIELD__ar12 }; /* Functional units. */ static xtensa_funcUnit_internal funcUnits[] = { }; /* Register files. */ enum xtensa_regfile_id { REGFILE_AR }; static xtensa_regfile_internal regfiles[] = { { "AR", "a", REGFILE_AR, 32, 32 } }; /* Interfaces. */ static xtensa_interface_internal interfaces[] = { }; /* Constant tables. */ /* constant table ai4c */ static const unsigned CONST_TBL_ai4c_0[] = { 0xffffffff, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0 }; /* constant table b4c */ static const unsigned CONST_TBL_b4c_0[] = { 0xffffffff, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0xa, 0xc, 0x10, 0x20, 0x40, 0x80, 0x100, 0 }; /* constant table b4cu */ static const unsigned CONST_TBL_b4cu_0[] = { 0x8000, 0x10000, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0xa, 0xc, 0x10, 0x20, 0x40, 0x80, 0x100, 0 }; /* Instruction operands. */ static int Operand_soffsetx4_decode (uint32 *valp) { unsigned soffsetx4_0, offset_0; offset_0 = *valp & 0x3ffff; soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); *valp = soffsetx4_0; return 0; } static int Operand_soffsetx4_encode (uint32 *valp) { unsigned offset_0, soffsetx4_0; soffsetx4_0 = *valp; offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; *valp = offset_0; return 0; } static int Operand_soffsetx4_ator (uint32 *valp, uint32 pc) { *valp -= (pc & ~0x3); return 0; } static int Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) { *valp += (pc & ~0x3); return 0; } static int Operand_uimm12x8_decode (uint32 *valp) { unsigned uimm12x8_0, imm12_0; imm12_0 = *valp & 0xfff; uimm12x8_0 = imm12_0 << 3; *valp = uimm12x8_0; return 0; } static int Operand_uimm12x8_encode (uint32 *valp) { unsigned imm12_0, uimm12x8_0; uimm12x8_0 = *valp; imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); *valp = imm12_0; return 0; } static int Operand_simm4_decode (uint32 *valp) { unsigned simm4_0, mn_0; mn_0 = *valp & 0xf; simm4_0 = ((int) mn_0 << 28) >> 28; *valp = simm4_0; return 0; } static int Operand_simm4_encode (uint32 *valp) { unsigned mn_0, simm4_0; simm4_0 = *valp; mn_0 = (simm4_0 & 0xf); *valp = mn_0; return 0; } static int Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_arr_encode (uint32 *valp) { int error; error = (*valp & ~0xf) != 0; return error; } static int Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_ars_encode (uint32 *valp) { int error; error = (*valp & ~0xf) != 0; return error; } static int Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_art_encode (uint32 *valp) { int error; error = (*valp & ~0xf) != 0; return error; } static int Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_ar0_encode (uint32 *valp) { int error; error = (*valp & ~0x1f) != 0; return error; } static int Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_ar4_encode (uint32 *valp) { int error; error = (*valp & ~0x1f) != 0; return error; } static int Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_ar8_encode (uint32 *valp) { int error; error = (*valp & ~0x1f) != 0; return error; } static int Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_ar12_encode (uint32 *valp) { int error; error = (*valp & ~0x1f) != 0; return error; } static int Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int Operand_ars_entry_encode (uint32 *valp) { int error; error = (*valp & ~0x1f) != 0; return error; } static int Operand_immrx4_decode (uint32 *valp) { unsigned immrx4_0, r_0; r_0 = *valp & 0xf; immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; *valp = immrx4_0; return 0; } static int Operand_immrx4_encode (uint32 *valp) { unsigned r_0, immrx4_0; immrx4_0 = *valp; r_0 = ((immrx4_0 >> 2) & 0xf); *valp = r_0; return 0; } static int Operand_lsi4x4_decode (uint32 *valp) { unsigned lsi4x4_0, r_0; r_0 = *valp & 0xf; lsi4x4_0 = r_0 << 2; *valp = lsi4x4_0; return 0; } static int Operand_lsi4x4_encode (uint32 *valp) { unsigned r_0, lsi4x4_0; lsi4x4_0 = *valp; r_0 = ((lsi4x4_0 >> 2) & 0xf); *valp = r_0; return 0; } static int Operand_simm7_decode (uint32 *valp) { unsigned simm7_0, imm7_0; imm7_0 = *valp & 0x7f; simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; *valp = simm7_0; return 0; } static int Operand_simm7_encode (uint32 *valp) { unsigned imm7_0, simm7_0; simm7_0 = *valp; imm7_0 = (simm7_0 & 0x7f); *valp = imm7_0; return 0; } static int Operand_uimm6_decode (uint32 *valp) { unsigned uimm6_0, imm6_0; imm6_0 = *valp & 0x3f; uimm6_0 = 0x4 + (((0) << 6) | imm6_0); *valp = uimm6_0; return 0; } static int Operand_uimm6_encode (uint32 *valp) { unsigned imm6_0, uimm6_0; uimm6_0 = *valp; imm6_0 = (uimm6_0 - 0x4) & 0x3f; *valp = imm6_0; return 0; } static int Operand_uimm6_ator (uint32 *valp, uint32 pc) { *valp -= pc; return 0; } static int Operand_uimm6_rtoa (uint32 *valp, uint32 pc) { *valp += pc; return 0; } static int Operand_ai4const_decode (uint32 *valp) { unsigned ai4const_0, t_0; t_0 = *valp & 0xf; ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; *valp = ai4const_0; return 0; } static int Operand_ai4const_encode (uint32 *valp) { unsigned t_0, ai4const_0; ai4const_0 = *valp; switch (ai4const_0) { case 0xffffffff: t_0 = 0; break; case 0x1: t_0 = 0x1; break; case 0x2: t_0 = 0x2; break; case 0x3: t_0 = 0x3; break; case 0x4: t_0 = 0x4; break; case 0x5: t_0 = 0x5; break; case 0x6: t_0 = 0x6; break; case 0x7: t_0 = 0x7; break; case 0x8: t_0 = 0x8; break; case 0x9: t_0 = 0x9; break; case 0xa: t_0 = 0xa; break; case 0xb: t_0 = 0xb; break; case 0xc: t_0 = 0xc; break; case 0xd: t_0 = 0xd; break; case 0xe: t_0 = 0xe; break; default: t_0 = 0xf; break; } *valp = t_0; return 0; } static int Operand_b4const_decode (uint32 *valp) { unsigned b4const_0, r_0; r_0 = *valp & 0xf; b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; *valp = b4const_0; return 0; } static int Operand_b4const_encode (uint32 *valp) { unsigned r_0, b4const_0; b4const_0 = *valp; switch (b4const_0) { case 0xffffffff: r_0 = 0; break; case 0x1: r_0 = 0x1; break; case 0x2: r_0 = 0x2; break; case 0x3: r_0 = 0x3; break; case 0x4: r_0 = 0x4; break; case 0x5: r_0 = 0x5; break; case 0x6: r_0 = 0x6; break; case 0x7: r_0 = 0x7; break; case 0x8: r_0 = 0x8; break; case 0xa: r_0 = 0x9; break; case 0xc: r_0 = 0xa; break; case 0x10: r_0 = 0xb; break; case 0x20: r_0 = 0xc; break; case 0x40: r_0 = 0xd; break; case 0x80: r_0 = 0xe; break; default: r_0 = 0xf; break; } *valp = r_0; return 0; } static int Operand_b4constu_decode (uint32 *valp) { unsigned b4constu_0, r_0; r_0 = *valp & 0xf; b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; *valp = b4constu_0; return 0; } static int Operand_b4constu_encode (uint32 *valp) { unsigned r_0, b4constu_0; b4constu_0 = *valp; switch (b4constu_0) { case 0x8000: r_0 = 0; break; case 0x10000: r_0 = 0x1; break; case 0x2: r_0 = 0x2; break; case 0x3: r_0 = 0x3; break; case 0x4: r_0 = 0x4; break; case 0x5: r_0 = 0x5; break; case 0x6: r_0 = 0x6; break; case 0x7: r_0 = 0x7; break; case 0x8: r_0 = 0x8; break; case 0xa: r_0 = 0x9; break; case 0xc: r_0 = 0xa; break; case 0x10: r_0 = 0xb; break; case 0x20: r_0 = 0xc; break; case 0x40: r_0 = 0xd; break; case 0x80: r_0 = 0xe; break; default: r_0 = 0xf; break; } *valp = r_0; return 0; } static int Operand_uimm8_decode (uint32 *valp) { unsigned uimm8_0, imm8_0; imm8_0 = *valp & 0xff; uimm8_0 = imm8_0; *valp = uimm8_0; return 0; } static int Operand_uimm8_encode (uint32 *valp) { unsigned imm8_0, uimm8_0; uimm8_0 = *valp; imm8_0 = (uimm8_0 & 0xff); *valp = imm8_0; return 0; } static int Operand_uimm8x2_decode (uint32 *valp) { unsigned uimm8x2_0, imm8_0; imm8_0 = *valp & 0xff; uimm8x2_0 = imm8_0 << 1; *valp = uimm8x2_0; return 0; } static int Operand_uimm8x2_encode (uint32 *valp) { unsigned imm8_0, uimm8x2_0; uimm8x2_0 = *valp; imm8_0 = ((uimm8x2_0 >> 1) & 0xff); *valp = imm8_0; return 0; } static int Operand_uimm8x4_decode (uint32 *valp) { unsigned uimm8x4_0, imm8_0; imm8_0 = *valp & 0xff; uimm8x4_0 = imm8_0 << 2; *valp = uimm8x4_0; return 0; } static int Operand_uimm8x4_encode (uint32 *valp) { unsigned imm8_0, uimm8x4_0; uimm8x4_0 = *valp; imm8_0 = ((uimm8x4_0 >> 2) & 0xff); *valp = imm8_0; return 0; } static int Operand_uimm4x16_decode (uint32 *valp) { unsigned uimm4x16_0, op2_0; op2_0 = *valp & 0xf; uimm4x16_0 = op2_0 << 4; *valp = uimm4x16_0; return 0; } static int Operand_uimm4x16_encode (uint32 *valp) { unsigned op2_0, uimm4x16_0; uimm4x16_0 = *valp; op2_0 = ((uimm4x16_0 >> 4) & 0xf); *valp = op2_0; return 0; } static int Operand_simm8_decode (uint32 *valp) { unsigned simm8_0, imm8_0; imm8_0 = *valp & 0xff; simm8_0 = ((int) imm8_0 << 24) >> 24; *valp = simm8_0; return 0; } static int Operand_simm8_encode (uint32 *valp) { unsigned imm8_0, simm8_0; simm8_0 = *valp; imm8_0 = (simm8_0 & 0xff); *valp = imm8_0; return 0; } static int Operand_simm8x256_decode (uint32 *valp) { unsigned simm8x256_0, imm8_0; imm8_0 = *valp & 0xff; simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; *valp = simm8x256_0; return 0; } static int Operand_simm8x256_encode (uint32 *valp) { unsigned imm8_0, simm8x256_0; simm8x256_0 = *valp; imm8_0 = ((simm8x256_0 >> 8) & 0xff); *valp = imm8_0; return 0; } static int Operand_simm12b_decode (uint32 *valp) { unsigned simm12b_0, imm12b_0; imm12b_0 = *valp & 0xfff; simm12b_0 = ((int) imm12b_0 << 20) >> 20; *valp = simm12b_0; return 0; } static int Operand_simm12b_encode (uint32 *valp) { unsigned imm12b_0, simm12b_0; simm12b_0 = *valp; imm12b_0 = (simm12b_0 & 0xfff); *valp = imm12b_0; return 0; } static int Operand_msalp32_decode (uint32 *valp) { unsigned msalp32_0, sal_0; sal_0 = *valp & 0x1f; msalp32_0 = 0x20 - sal_0; *valp = msalp32_0; return 0; } static int Operand_msalp32_encode (uint32 *valp) { unsigned sal_0, msalp32_0; msalp32_0 = *valp; sal_0 = (0x20 - msalp32_0) & 0x1f; *valp = sal_0; return 0; } static int Operand_op2p1_decode (uint32 *valp) { unsigned op2p1_0, op2_0; op2_0 = *valp & 0xf; op2p1_0 = op2_0 + 0x1; *valp = op2p1_0; return 0; } static int Operand_op2p1_encode (uint32 *valp) { unsigned op2_0, op2p1_0; op2p1_0 = *valp; op2_0 = (op2p1_0 - 0x1) & 0xf; *valp = op2_0; return 0; } static int Operand_label8_decode (uint32 *valp) { unsigned label8_0, imm8_0; imm8_0 = *valp & 0xff; label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); *valp = label8_0; return 0; } static int Operand_label8_encode (uint32 *valp) { unsigned imm8_0, label8_0; label8_0 = *valp; imm8_0 = (label8_0 - 0x4) & 0xff; *valp = imm8_0; return 0; } static int Operand_label8_ator (uint32 *valp, uint32 pc) { *valp -= pc; return 0; } static int Operand_label8_rtoa (uint32 *valp, uint32 pc) { *valp += pc; return 0; } static int Operand_ulabel8_decode (uint32 *valp) { unsigned ulabel8_0, imm8_0; imm8_0 = *valp & 0xff; ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); *valp = ulabel8_0; return 0; } static int Operand_ulabel8_encode (uint32 *valp) { unsigned imm8_0, ulabel8_0; ulabel8_0 = *valp; imm8_0 = (ulabel8_0 - 0x4) & 0xff; *valp = imm8_0; return 0; } static int Operand_ulabel8_ator (uint32 *valp, uint32 pc) { *valp -= pc; return 0; } static int Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) { *valp += pc; return 0; } static int Operand_label12_decode (uint32 *valp) { unsigned label12_0, imm12_0; imm12_0 = *valp & 0xfff; label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); *valp = label12_0; return 0; } static int Operand_label12_encode (uint32 *valp) { unsigned imm12_0, label12_0; label12_0 = *valp; imm12_0 = (label12_0 - 0x4) & 0xfff; *valp = imm12_0; return 0; } static int Operand_label12_ator (uint32 *valp, uint32 pc) { *valp -= pc; return 0; } static int Operand_label12_rtoa (uint32 *valp, uint32 pc) { *valp += pc; return 0; } static int Operand_soffset_decode (uint32 *valp) { unsigned soffset_0, offset_0; offset_0 = *valp & 0x3ffff; soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); *valp = soffset_0; return 0; } static int Operand_soffset_encode (uint32 *valp) { unsigned offset_0, soffset_0; soffset_0 = *valp; offset_0 = (soffset_0 - 0x4) & 0x3ffff; *valp = offset_0; return 0; } static int Operand_soffset_ator (uint32 *valp, uint32 pc) { *valp -= pc; return 0; } static int Operand_soffset_rtoa (uint32 *valp, uint32 pc) { *valp += pc; return 0; } static int Operand_uimm16x4_decode (uint32 *valp) { unsigned uimm16x4_0, imm16_0; imm16_0 = *valp & 0xffff; uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; *valp = uimm16x4_0; return 0; } static int Operand_uimm16x4_encode (uint32 *valp) { unsigned imm16_0, uimm16x4_0; uimm16x4_0 = *valp; imm16_0 = (uimm16x4_0 >> 2) & 0xffff; *valp = imm16_0; return 0; } static int Operand_uimm16x4_ator (uint32 *valp, uint32 pc) { *valp -= ((pc + 3) & ~0x3); return 0; } static int Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) { *valp += ((pc + 3) & ~0x3); return 0; } static int Operand_immt_decode (uint32 *valp) { unsigned immt_0, t_0; t_0 = *valp & 0xf; immt_0 = t_0; *valp = immt_0; return 0; } static int Operand_immt_encode (uint32 *valp) { unsigned t_0, immt_0; immt_0 = *valp; t_0 = immt_0 & 0xf; *valp = t_0; return 0; } static int Operand_imms_decode (uint32 *valp) { unsigned imms_0, s_0; s_0 = *valp & 0xf; imms_0 = s_0; *valp = imms_0; return 0; } static int Operand_imms_encode (uint32 *valp) { unsigned s_0, imms_0; imms_0 = *valp; s_0 = imms_0 & 0xf; *valp = s_0; return 0; } static int Operand_tp7_decode (uint32 *valp) { unsigned tp7_0, t_0; t_0 = *valp & 0xf; tp7_0 = t_0 + 0x7; *valp = tp7_0; return 0; } static int Operand_tp7_encode (uint32 *valp) { unsigned t_0, tp7_0; tp7_0 = *valp; t_0 = (tp7_0 - 0x7) & 0xf; *valp = t_0; return 0; } static int Operand_xt_wbr15_label_decode (uint32 *valp) { unsigned xt_wbr15_label_0, xt_wbr15_imm_0; xt_wbr15_imm_0 = *valp & 0x7fff; xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); *valp = xt_wbr15_label_0; return 0; } static int Operand_xt_wbr15_label_encode (uint32 *valp) { unsigned xt_wbr15_imm_0, xt_wbr15_label_0; xt_wbr15_label_0 = *valp; xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; *valp = xt_wbr15_imm_0; return 0; } static int Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) { *valp -= pc; return 0; } static int Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) { *valp += pc; return 0; } static int Operand_xt_wbr18_label_decode (uint32 *valp) { unsigned xt_wbr18_label_0, xt_wbr18_imm_0; xt_wbr18_imm_0 = *valp & 0x3ffff; xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); *valp = xt_wbr18_label_0; return 0; } static int Operand_xt_wbr18_label_encode (uint32 *valp) { unsigned xt_wbr18_imm_0, xt_wbr18_label_0; xt_wbr18_label_0 = *valp; xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; *valp = xt_wbr18_imm_0; return 0; } static int Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) { *valp -= pc; return 0; } static int Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) { *valp += pc; return 0; } static xtensa_operand_internal operands[] = { { "soffsetx4", FIELD_offset, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_soffsetx4_encode, Operand_soffsetx4_decode, Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, { "uimm12x8", FIELD_imm12, -1, 0, 0, Operand_uimm12x8_encode, Operand_uimm12x8_decode, 0, 0 }, { "simm4", FIELD_mn, -1, 0, 0, Operand_simm4_encode, Operand_simm4_decode, 0, 0 }, { "arr", FIELD_r, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, Operand_arr_encode, Operand_arr_decode, 0, 0 }, { "ars", FIELD_s, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, Operand_ars_encode, Operand_ars_decode, 0, 0 }, { "*ars_invisible", FIELD_s, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, Operand_ars_encode, Operand_ars_decode, 0, 0 }, { "art", FIELD_t, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, Operand_art_encode, Operand_art_decode, 0, 0 }, { "ar0", FIELD__ar0, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, Operand_ar0_encode, Operand_ar0_decode, 0, 0 }, { "ar4", FIELD__ar4, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, Operand_ar4_encode, Operand_ar4_decode, 0, 0 }, { "ar8", FIELD__ar8, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, Operand_ar8_encode, Operand_ar8_decode, 0, 0 }, { "ar12", FIELD__ar12, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, Operand_ar12_encode, Operand_ar12_decode, 0, 0 }, { "ars_entry", FIELD_s, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, Operand_ars_entry_encode, Operand_ars_entry_decode, 0, 0 }, { "immrx4", FIELD_r, -1, 0, 0, Operand_immrx4_encode, Operand_immrx4_decode, 0, 0 }, { "lsi4x4", FIELD_r, -1, 0, 0, Operand_lsi4x4_encode, Operand_lsi4x4_decode, 0, 0 }, { "simm7", FIELD_imm7, -1, 0, 0, Operand_simm7_encode, Operand_simm7_decode, 0, 0 }, { "uimm6", FIELD_imm6, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_uimm6_encode, Operand_uimm6_decode, Operand_uimm6_ator, Operand_uimm6_rtoa }, { "ai4const", FIELD_t, -1, 0, 0, Operand_ai4const_encode, Operand_ai4const_decode, 0, 0 }, { "b4const", FIELD_r, -1, 0, 0, Operand_b4const_encode, Operand_b4const_decode, 0, 0 }, { "b4constu", FIELD_r, -1, 0, 0, Operand_b4constu_encode, Operand_b4constu_decode, 0, 0 }, { "uimm8", FIELD_imm8, -1, 0, 0, Operand_uimm8_encode, Operand_uimm8_decode, 0, 0 }, { "uimm8x2", FIELD_imm8, -1, 0, 0, Operand_uimm8x2_encode, Operand_uimm8x2_decode, 0, 0 }, { "uimm8x4", FIELD_imm8, -1, 0, 0, Operand_uimm8x4_encode, Operand_uimm8x4_decode, 0, 0 }, { "uimm4x16", FIELD_op2, -1, 0, 0, Operand_uimm4x16_encode, Operand_uimm4x16_decode, 0, 0 }, { "simm8", FIELD_imm8, -1, 0, 0, Operand_simm8_encode, Operand_simm8_decode, 0, 0 }, { "simm8x256", FIELD_imm8, -1, 0, 0, Operand_simm8x256_encode, Operand_simm8x256_decode, 0, 0 }, { "simm12b", FIELD_imm12b, -1, 0, 0, Operand_simm12b_encode, Operand_simm12b_decode, 0, 0 }, { "msalp32", FIELD_sal, -1, 0, 0, Operand_msalp32_encode, Operand_msalp32_decode, 0, 0 }, { "op2p1", FIELD_op2, -1, 0, 0, Operand_op2p1_encode, Operand_op2p1_decode, 0, 0 }, { "label8", FIELD_imm8, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_label8_encode, Operand_label8_decode, Operand_label8_ator, Operand_label8_rtoa }, { "ulabel8", FIELD_imm8, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_ulabel8_encode, Operand_ulabel8_decode, Operand_ulabel8_ator, Operand_ulabel8_rtoa }, { "label12", FIELD_imm12, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_label12_encode, Operand_label12_decode, Operand_label12_ator, Operand_label12_rtoa }, { "soffset", FIELD_offset, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_soffset_encode, Operand_soffset_decode, Operand_soffset_ator, Operand_soffset_rtoa }, { "uimm16x4", FIELD_imm16, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_uimm16x4_encode, Operand_uimm16x4_decode, Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, { "immt", FIELD_t, -1, 0, 0, Operand_immt_encode, Operand_immt_decode, 0, 0 }, { "imms", FIELD_s, -1, 0, 0, Operand_imms_encode, Operand_imms_decode, 0, 0 }, { "tp7", FIELD_t, -1, 0, 0, Operand_tp7_encode, Operand_tp7_decode, 0, 0 }, { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 } }; enum xtensa_operand_id { OPERAND_soffsetx4, OPERAND_uimm12x8, OPERAND_simm4, OPERAND_arr, OPERAND_ars, OPERAND__ars_invisible, OPERAND_art, OPERAND_ar0, OPERAND_ar4, OPERAND_ar8, OPERAND_ar12, OPERAND_ars_entry, OPERAND_immrx4, OPERAND_lsi4x4, OPERAND_simm7, OPERAND_uimm6, OPERAND_ai4const, OPERAND_b4const, OPERAND_b4constu, OPERAND_uimm8, OPERAND_uimm8x2, OPERAND_uimm8x4, OPERAND_uimm4x16, OPERAND_simm8, OPERAND_simm8x256, OPERAND_simm12b, OPERAND_msalp32, OPERAND_op2p1, OPERAND_label8, OPERAND_ulabel8, OPERAND_label12, OPERAND_soffset, OPERAND_uimm16x4, OPERAND_immt, OPERAND_imms, OPERAND_tp7, OPERAND_xt_wbr15_label, OPERAND_xt_wbr18_label, OPERAND_t, OPERAND_bbi4, OPERAND_bbi, OPERAND_imm12, OPERAND_imm8, OPERAND_s, OPERAND_imm12b, OPERAND_imm16, OPERAND_m, OPERAND_n, OPERAND_offset, OPERAND_op0, OPERAND_op1, OPERAND_op2, OPERAND_r, OPERAND_sa4, OPERAND_sae4, OPERAND_sae, OPERAND_sal, OPERAND_sargt, OPERAND_sas4, OPERAND_sas, OPERAND_sr, OPERAND_st, OPERAND_thi3, OPERAND_imm4, OPERAND_mn, OPERAND_i, OPERAND_imm6lo, OPERAND_imm6hi, OPERAND_imm7lo, OPERAND_imm7hi, OPERAND_z, OPERAND_imm6, OPERAND_imm7, OPERAND_xt_wbr15_imm, OPERAND_xt_wbr18_imm }; /* Iclass table. */ static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { { { STATE_PSRING }, 'i' }, { { STATE_PSEXCM }, 'm' }, { { STATE_EPC1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { { { OPERAND_soffsetx4 }, 'i' }, { { OPERAND_ar12 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { { { STATE_PSCALLINC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { { { OPERAND_soffsetx4 }, 'i' }, { { OPERAND_ar8 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { { { STATE_PSCALLINC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { { { OPERAND_soffsetx4 }, 'i' }, { { OPERAND_ar4 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { { { STATE_PSCALLINC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_ar12 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { { { STATE_PSCALLINC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_ar8 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { { { STATE_PSCALLINC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_ar4 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { { { STATE_PSCALLINC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { { { OPERAND_ars_entry }, 's' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm12x8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { { { STATE_PSCALLINC }, 'i' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSWOE }, 'i' }, { { STATE_WindowBase }, 'm' }, { { STATE_WindowStart }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { { { STATE_WindowBase }, 'i' }, { { STATE_WindowStart }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { { { OPERAND_simm4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { { { OPERAND__ars_invisible }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { { { STATE_WindowBase }, 'm' }, { { STATE_WindowStart }, 'm' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSWOE }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { { { STATE_EPC1 }, 'i' }, { { STATE_PSEXCM }, 'm' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'm' }, { { STATE_WindowStart }, 'm' }, { { STATE_PSOWB }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_immrx4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' }, { { OPERAND_immrx4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowStart }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowStart }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_WindowStart }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_ai4const }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm6 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_lsi4x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { { { OPERAND_ars }, 'o' }, { { OPERAND_simm7 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { { { OPERAND__ars_invisible }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' }, { { OPERAND_lsi4x4 }, 'i' } }; static xtensa_arg_internal Iclass_rur_threadptr_args[] = { { { OPERAND_arr }, 'o' } }; static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { { { STATE_THREADPTR }, 'i' } }; static xtensa_arg_internal Iclass_wur_threadptr_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { { { STATE_THREADPTR }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_simm8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_simm8x256 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_b4const }, 'i' }, { { OPERAND_label8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_bbi }, 'i' }, { { OPERAND_label8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_b4constu }, 'i' }, { { OPERAND_label8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' }, { { OPERAND_label8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_label12 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { { { OPERAND_soffsetx4 }, 'i' }, { { OPERAND_ar0 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_ar0 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_art }, 'i' }, { { OPERAND_sae }, 'i' }, { { OPERAND_op2p1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { { { OPERAND_soffset }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x2 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x2 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_uimm16x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { { { STATE_LITBADDR }, 'i' }, { { STATE_LITBEN }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_ulabel8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { { { STATE_LBEG }, 'o' }, { { STATE_LEND }, 'o' }, { { STATE_LCOUNT }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_ulabel8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { { { STATE_LBEG }, 'o' }, { { STATE_LEND }, 'o' }, { { STATE_LCOUNT }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_simm12b }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { { { OPERAND_arr }, 'm' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { { { OPERAND__ars_invisible }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x2 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { { { STATE_SAR }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { { { OPERAND_sas }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { { { STATE_SAR }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { { { STATE_SAR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { { { STATE_SAR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { { { STATE_SAR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_msalp32 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_art }, 'i' }, { { OPERAND_sargt }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_art }, 'i' }, { { OPERAND_s }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { { { STATE_XTSYNC }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_s }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { { { STATE_PSWOE }, 'i' }, { { STATE_PSCALLINC }, 'i' }, { { STATE_PSOWB }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_PSUM }, 'i' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSINTLEVEL }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { { { STATE_LEND }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { { { STATE_LEND }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { { { STATE_LEND }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { { { STATE_LCOUNT }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_LCOUNT }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_LCOUNT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { { { STATE_LBEG }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { { { STATE_LBEG }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { { { STATE_LBEG }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { { { STATE_SAR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { { { STATE_SAR }, 'o' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { { { STATE_SAR }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { { { STATE_LITBADDR }, 'i' }, { { STATE_LITBEN }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { { { STATE_LITBADDR }, 'o' }, { { STATE_LITBEN }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { { { STATE_LITBADDR }, 'm' }, { { STATE_LITBEN }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { { { STATE_PSWOE }, 'i' }, { { STATE_PSCALLINC }, 'i' }, { { STATE_PSOWB }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_PSUM }, 'i' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSINTLEVEL }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { { { STATE_PSWOE }, 'o' }, { { STATE_PSCALLINC }, 'o' }, { { STATE_PSOWB }, 'o' }, { { STATE_PSRING }, 'm' }, { { STATE_PSUM }, 'o' }, { { STATE_PSEXCM }, 'm' }, { { STATE_PSINTLEVEL }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { { { STATE_PSWOE }, 'm' }, { { STATE_PSCALLINC }, 'm' }, { { STATE_PSOWB }, 'm' }, { { STATE_PSRING }, 'm' }, { { STATE_PSUM }, 'm' }, { { STATE_PSEXCM }, 'm' }, { { STATE_PSINTLEVEL }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC1 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC1 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE1 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE1 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC2 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC2 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC2 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE2 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE2 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE2 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC3 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC3 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC3 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE3 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE3 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE3 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC4 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC4 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE4 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE4 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC5 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC5 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC5 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE5 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE5 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE5 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC6 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC6 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC6 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE6 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE6 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE6 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC7 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC7 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPC7 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE7 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE7 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE7 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS2 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS2 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS2 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS3 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS3 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS3 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS4 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS4 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS5 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS5 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS5 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS6 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS6 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS6 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS7 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS7 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EPS7 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCVADDR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCVADDR }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCVADDR }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCCAUSE }, 'i' }, { { STATE_XTSYNC }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCCAUSE }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_EXCCAUSE }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_MISC0 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_MISC0 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_MISC0 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_MISC1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_MISC1 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_MISC1 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_VECBASE }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_VECBASE }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_VECBASE }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { { { OPERAND_s }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { { { STATE_PSWOE }, 'o' }, { { STATE_PSCALLINC }, 'o' }, { { STATE_PSOWB }, 'o' }, { { STATE_PSRING }, 'm' }, { { STATE_PSUM }, 'o' }, { { STATE_PSEXCM }, 'm' }, { { STATE_PSINTLEVEL }, 'o' }, { { STATE_EPC1 }, 'i' }, { { STATE_EPC2 }, 'i' }, { { STATE_EPC3 }, 'i' }, { { STATE_EPC4 }, 'i' }, { { STATE_EPC5 }, 'i' }, { { STATE_EPC6 }, 'i' }, { { STATE_EPC7 }, 'i' }, { { STATE_EPS2 }, 'i' }, { { STATE_EPS3 }, 'i' }, { { STATE_EPS4 }, 'i' }, { { STATE_EPS5 }, 'i' }, { { STATE_EPS6 }, 'i' }, { { STATE_EPS7 }, 'i' }, { { STATE_InOCDMode }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { { { OPERAND_s }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_PSINTLEVEL }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_INTERRUPT }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_INTENABLE }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_INTENABLE }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_INTENABLE }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { { { OPERAND_imms }, 'i' }, { { OPERAND_immt }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSINTLEVEL }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { { { OPERAND_imms }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSINTLEVEL }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA0 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA0 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA0 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC0 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC0 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC0 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA1 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA1 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC1 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC1 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA0 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA0 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA0 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA1 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA1 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKENABLE }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKENABLE }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_IBREAKENABLE }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DEBUGCAUSE }, 'i' }, { { STATE_DBNUM }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DEBUGCAUSE }, 'o' }, { { STATE_DBNUM }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DEBUGCAUSE }, 'm' }, { { STATE_DBNUM }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_ICOUNT }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_ICOUNT }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_ICOUNT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_ICOUNTLEVEL }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_ICOUNTLEVEL }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_ICOUNTLEVEL }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DDR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_DDR }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_DDR }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { { { OPERAND_imms }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { { { STATE_InOCDMode }, 'm' }, { { STATE_EPC6 }, 'i' }, { { STATE_PSWOE }, 'o' }, { { STATE_PSCALLINC }, 'o' }, { { STATE_PSOWB }, 'o' }, { { STATE_PSRING }, 'o' }, { { STATE_PSUM }, 'o' }, { { STATE_PSEXCM }, 'o' }, { { STATE_PSINTLEVEL }, 'o' }, { { STATE_EPS6 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { { { STATE_InOCDMode }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOUNT }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_CCOUNT }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_CCOUNT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE0 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE0 }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE0 }, 'm' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE1 }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE1 }, 'm' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE2 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE2 }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE2 }, 'm' }, { { STATE_INTERRUPT }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm4x16 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm4x16 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { { { OPERAND_ars }, 'i' }, { { OPERAND_uimm4x16 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_PTBASE }, 'o' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_PTBASE }, 'i' }, { { STATE_EXCVADDR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_PTBASE }, 'm' }, { { STATE_EXCVADDR }, 'i' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_ASID3 }, 'i' }, { { STATE_ASID2 }, 'i' }, { { STATE_ASID1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_ASID3 }, 'o' }, { { STATE_ASID2 }, 'o' }, { { STATE_ASID1 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_ASID3 }, 'm' }, { { STATE_ASID2 }, 'm' }, { { STATE_ASID1 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_INSTPGSZID4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_INSTPGSZID4 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_INSTPGSZID4 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DATAPGSZID4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DATAPGSZID4 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { { { STATE_XTSYNC }, 'o' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_DATAPGSZID4 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { { { STATE_PTBASE }, 'i' }, { { STATE_EXCVADDR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { { { STATE_EXCVADDR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { { { STATE_EXCVADDR }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CPENABLE }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CPENABLE }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' }, { { STATE_CPENABLE }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_tp7 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_tp7 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { { { OPERAND_art }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { { { OPERAND_art }, 'i' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { { { OPERAND_art }, 'm' }, { { OPERAND_ars }, 'i' }, { { OPERAND_uimm8x4 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { { { STATE_SCOMPARE1 }, 'i' }, { { STATE_SCOMPARE1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { { { OPERAND_art }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { { { STATE_SCOMPARE1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { { { STATE_SCOMPARE1 }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { { { OPERAND_art }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { { { STATE_SCOMPARE1 }, 'm' } }; static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_arg_internal Iclass_xt_mul32_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, { { OPERAND_art }, 'i' } }; static xtensa_iclass_internal iclasses[] = { { 0, 0 /* xt_iclass_excw */, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_rfe */, 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_rfde */, 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_syscall */, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_simcall */, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_call12_args, 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_call8_args, 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_call4_args, 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_callx12_args, 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_callx8_args, 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_callx4_args, 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_entry_args, 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_movsp_args, 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rotw_args, 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_retw_args, 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_rfwou */, 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_l32e_args, 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_s32e_args, 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_windowbase_args, 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_windowbase_args, 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_windowbase_args, 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_windowstart_args, 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_windowstart_args, 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_windowstart_args, 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_add_n_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_addi_n_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_bz6_args, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_ill_n */, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_loadi4_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_mov_n_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_movi_n_args, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_nopn */, 0, 0, 0, 0 }, { 1, Iclass_xt_iclass_retn_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_storei4_args, 0, 0, 0, 0 }, { 1, Iclass_rur_threadptr_args, 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, { 1, Iclass_wur_threadptr_args, 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_addi_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_addmi_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_addsub_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_bit_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_bsi8_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_bsi8b_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_bsi8u_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_bst8_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_bsz12_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_call0_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_callx0_args, 0, 0, 0, 0 }, { 4, Iclass_xt_iclass_exti_args, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_ill */, 0, 0, 0, 0 }, { 1, Iclass_xt_iclass_jump_args, 0, 0, 0, 0 }, { 1, Iclass_xt_iclass_jumpx_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_l16ui_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_l16si_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_l32i_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_l32r_args, 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_l8i_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_loop_args, 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_loopz_args, 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_movi_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_movz_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_neg_args, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_nop */, 0, 0, 0, 0 }, { 1, Iclass_xt_iclass_return_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_s16i_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_s32i_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_s8i_args, 0, 0, 0, 0 }, { 1, Iclass_xt_iclass_sar_args, 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_sari_args, 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_shifts_args, 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_shiftst_args, 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_shiftt_args, 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_slli_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_srai_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_srli_args, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_memw */, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_extw */, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_isync */, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_sync */, 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_rsil_args, 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_lend_args, 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_lend_args, 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_lend_args, 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_lcount_args, 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_lcount_args, 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_lcount_args, 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_lbeg_args, 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_lbeg_args, 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_lbeg_args, 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_sar_args, 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_sar_args, 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_sar_args, 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_litbase_args, 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_litbase_args, 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_litbase_args, 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_176_args, 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_176_args, 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_208_args, 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ps_args, 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ps_args, 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ps_args, 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc1_args, 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc1_args, 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc1_args, 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave1_args, 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave1_args, 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave1_args, 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc2_args, 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc2_args, 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc2_args, 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave2_args, 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave2_args, 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave2_args, 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc3_args, 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc3_args, 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc3_args, 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave3_args, 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave3_args, 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave3_args, 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc4_args, 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc4_args, 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc4_args, 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave4_args, 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave4_args, 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave4_args, 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc5_args, 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc5_args, 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc5_args, 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave5_args, 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave5_args, 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave5_args, 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc6_args, 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc6_args, 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc6_args, 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave6_args, 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave6_args, 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave6_args, 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc7_args, 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc7_args, 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc7_args, 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave7_args, 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave7_args, 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave7_args, 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps2_args, 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps2_args, 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps2_args, 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps3_args, 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps3_args, 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps3_args, 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps4_args, 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps4_args, 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps4_args, 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps5_args, 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps5_args, 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps5_args, 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps6_args, 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps6_args, 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps6_args, 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps7_args, 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps7_args, 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps7_args, 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excvaddr_args, 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excvaddr_args, 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excvaddr_args, 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_depc_args, 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_depc_args, 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_depc_args, 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_exccause_args, 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_exccause_args, 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_exccause_args, 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_misc0_args, 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_misc0_args, 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_misc0_args, 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_misc1_args, 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_misc1_args, 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_misc1_args, 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_prid_args, 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_vecbase_args, 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_vecbase_args, 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_vecbase_args, 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_mul16_args, 0, 0, 0, 0 }, { 1, Iclass_xt_iclass_rfi_args, 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wait_args, 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_interrupt_args, 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_intset_args, 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_intclear_args, 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_intenable_args, 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_intenable_args, 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_intenable_args, 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_break_args, 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_break_n_args, 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreaka0_args, 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreaka0_args, 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreaka0_args, 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreakc0_args, 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreakc0_args, 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreakc0_args, 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreaka1_args, 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreaka1_args, 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreaka1_args, 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreakc1_args, 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreakc1_args, 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreakc1_args, 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ibreaka0_args, 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ibreaka0_args, 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ibreaka0_args, 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ibreaka1_args, 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ibreaka1_args, 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ibreaka1_args, 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ibreakenable_args, 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ibreakenable_args, 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ibreakenable_args, 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_debugcause_args, 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_debugcause_args, 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_debugcause_args, 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_icount_args, 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_icount_args, 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_icount_args, 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_icountlevel_args, 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_icountlevel_args, 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_icountlevel_args, 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ddr_args, 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ddr_args, 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ddr_args, 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rfdo_args, 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_rfdd */, 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_mmid_args, 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccount_args, 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccount_args, 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccount_args, 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccompare0_args, 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccompare0_args, 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccompare0_args, 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccompare1_args, 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccompare1_args, 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccompare1_args, 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccompare2_args, 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccompare2_args, 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccompare2_args, 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_icache_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_icache_lock_args, 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_icache_inv_args, 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_licx_args, 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_sicx_args, 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_dcache_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_dcache_ind_args, 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_dcache_inv_args, 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_dpf_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_dcache_lock_args, 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_sdct_args, 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_ldct_args, 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ptevaddr_args, 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ptevaddr_args, 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ptevaddr_args, 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_rasid_args, 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_rasid_args, 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_rasid_args, 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_itlbcfg_args, 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_itlbcfg_args, 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_itlbcfg_args, 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_idtlb_args, 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_rdtlb_args, 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_wdtlb_args, 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_iitlb_args, 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_ritlb_args, 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_witlb_args, 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_ldpte */, 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_hwwitlba */, 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_hwwdtlba */, 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_cpenable_args, 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_cpenable_args, 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_cpenable_args, 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_clamp_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_minmax_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_nsa_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_sx_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_l32ai_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_s32ri_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_s32c1i_args, 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_scompare1_args, 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_scompare1_args, 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_scompare1_args, 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_div_args, 0, 0, 0, 0 }, { 3, Iclass_xt_mul32_args, 0, 0, 0, 0 } }; enum xtensa_iclass_id { ICLASS_xt_iclass_excw, ICLASS_xt_iclass_rfe, ICLASS_xt_iclass_rfde, ICLASS_xt_iclass_syscall, ICLASS_xt_iclass_simcall, ICLASS_xt_iclass_call12, ICLASS_xt_iclass_call8, ICLASS_xt_iclass_call4, ICLASS_xt_iclass_callx12, ICLASS_xt_iclass_callx8, ICLASS_xt_iclass_callx4, ICLASS_xt_iclass_entry, ICLASS_xt_iclass_movsp, ICLASS_xt_iclass_rotw, ICLASS_xt_iclass_retw, ICLASS_xt_iclass_rfwou, ICLASS_xt_iclass_l32e, ICLASS_xt_iclass_s32e, ICLASS_xt_iclass_rsr_windowbase, ICLASS_xt_iclass_wsr_windowbase, ICLASS_xt_iclass_xsr_windowbase, ICLASS_xt_iclass_rsr_windowstart, ICLASS_xt_iclass_wsr_windowstart, ICLASS_xt_iclass_xsr_windowstart, ICLASS_xt_iclass_add_n, ICLASS_xt_iclass_addi_n, ICLASS_xt_iclass_bz6, ICLASS_xt_iclass_ill_n, ICLASS_xt_iclass_loadi4, ICLASS_xt_iclass_mov_n, ICLASS_xt_iclass_movi_n, ICLASS_xt_iclass_nopn, ICLASS_xt_iclass_retn, ICLASS_xt_iclass_storei4, ICLASS_rur_threadptr, ICLASS_wur_threadptr, ICLASS_xt_iclass_addi, ICLASS_xt_iclass_addmi, ICLASS_xt_iclass_addsub, ICLASS_xt_iclass_bit, ICLASS_xt_iclass_bsi8, ICLASS_xt_iclass_bsi8b, ICLASS_xt_iclass_bsi8u, ICLASS_xt_iclass_bst8, ICLASS_xt_iclass_bsz12, ICLASS_xt_iclass_call0, ICLASS_xt_iclass_callx0, ICLASS_xt_iclass_exti, ICLASS_xt_iclass_ill, ICLASS_xt_iclass_jump, ICLASS_xt_iclass_jumpx, ICLASS_xt_iclass_l16ui, ICLASS_xt_iclass_l16si, ICLASS_xt_iclass_l32i, ICLASS_xt_iclass_l32r, ICLASS_xt_iclass_l8i, ICLASS_xt_iclass_loop, ICLASS_xt_iclass_loopz, ICLASS_xt_iclass_movi, ICLASS_xt_iclass_movz, ICLASS_xt_iclass_neg, ICLASS_xt_iclass_nop, ICLASS_xt_iclass_return, ICLASS_xt_iclass_s16i, ICLASS_xt_iclass_s32i, ICLASS_xt_iclass_s8i, ICLASS_xt_iclass_sar, ICLASS_xt_iclass_sari, ICLASS_xt_iclass_shifts, ICLASS_xt_iclass_shiftst, ICLASS_xt_iclass_shiftt, ICLASS_xt_iclass_slli, ICLASS_xt_iclass_srai, ICLASS_xt_iclass_srli, ICLASS_xt_iclass_memw, ICLASS_xt_iclass_extw, ICLASS_xt_iclass_isync, ICLASS_xt_iclass_sync, ICLASS_xt_iclass_rsil, ICLASS_xt_iclass_rsr_lend, ICLASS_xt_iclass_wsr_lend, ICLASS_xt_iclass_xsr_lend, ICLASS_xt_iclass_rsr_lcount, ICLASS_xt_iclass_wsr_lcount, ICLASS_xt_iclass_xsr_lcount, ICLASS_xt_iclass_rsr_lbeg, ICLASS_xt_iclass_wsr_lbeg, ICLASS_xt_iclass_xsr_lbeg, ICLASS_xt_iclass_rsr_sar, ICLASS_xt_iclass_wsr_sar, ICLASS_xt_iclass_xsr_sar, ICLASS_xt_iclass_rsr_litbase, ICLASS_xt_iclass_wsr_litbase, ICLASS_xt_iclass_xsr_litbase, ICLASS_xt_iclass_rsr_176, ICLASS_xt_iclass_wsr_176, ICLASS_xt_iclass_rsr_208, ICLASS_xt_iclass_rsr_ps, ICLASS_xt_iclass_wsr_ps, ICLASS_xt_iclass_xsr_ps, ICLASS_xt_iclass_rsr_epc1, ICLASS_xt_iclass_wsr_epc1, ICLASS_xt_iclass_xsr_epc1, ICLASS_xt_iclass_rsr_excsave1, ICLASS_xt_iclass_wsr_excsave1, ICLASS_xt_iclass_xsr_excsave1, ICLASS_xt_iclass_rsr_epc2, ICLASS_xt_iclass_wsr_epc2, ICLASS_xt_iclass_xsr_epc2, ICLASS_xt_iclass_rsr_excsave2, ICLASS_xt_iclass_wsr_excsave2, ICLASS_xt_iclass_xsr_excsave2, ICLASS_xt_iclass_rsr_epc3, ICLASS_xt_iclass_wsr_epc3, ICLASS_xt_iclass_xsr_epc3, ICLASS_xt_iclass_rsr_excsave3, ICLASS_xt_iclass_wsr_excsave3, ICLASS_xt_iclass_xsr_excsave3, ICLASS_xt_iclass_rsr_epc4, ICLASS_xt_iclass_wsr_epc4, ICLASS_xt_iclass_xsr_epc4, ICLASS_xt_iclass_rsr_excsave4, ICLASS_xt_iclass_wsr_excsave4, ICLASS_xt_iclass_xsr_excsave4, ICLASS_xt_iclass_rsr_epc5, ICLASS_xt_iclass_wsr_epc5, ICLASS_xt_iclass_xsr_epc5, ICLASS_xt_iclass_rsr_excsave5, ICLASS_xt_iclass_wsr_excsave5, ICLASS_xt_iclass_xsr_excsave5, ICLASS_xt_iclass_rsr_epc6, ICLASS_xt_iclass_wsr_epc6, ICLASS_xt_iclass_xsr_epc6, ICLASS_xt_iclass_rsr_excsave6, ICLASS_xt_iclass_wsr_excsave6, ICLASS_xt_iclass_xsr_excsave6, ICLASS_xt_iclass_rsr_epc7, ICLASS_xt_iclass_wsr_epc7, ICLASS_xt_iclass_xsr_epc7, ICLASS_xt_iclass_rsr_excsave7, ICLASS_xt_iclass_wsr_excsave7, ICLASS_xt_iclass_xsr_excsave7, ICLASS_xt_iclass_rsr_eps2, ICLASS_xt_iclass_wsr_eps2, ICLASS_xt_iclass_xsr_eps2, ICLASS_xt_iclass_rsr_eps3, ICLASS_xt_iclass_wsr_eps3, ICLASS_xt_iclass_xsr_eps3, ICLASS_xt_iclass_rsr_eps4, ICLASS_xt_iclass_wsr_eps4, ICLASS_xt_iclass_xsr_eps4, ICLASS_xt_iclass_rsr_eps5, ICLASS_xt_iclass_wsr_eps5, ICLASS_xt_iclass_xsr_eps5, ICLASS_xt_iclass_rsr_eps6, ICLASS_xt_iclass_wsr_eps6, ICLASS_xt_iclass_xsr_eps6, ICLASS_xt_iclass_rsr_eps7, ICLASS_xt_iclass_wsr_eps7, ICLASS_xt_iclass_xsr_eps7, ICLASS_xt_iclass_rsr_excvaddr, ICLASS_xt_iclass_wsr_excvaddr, ICLASS_xt_iclass_xsr_excvaddr, ICLASS_xt_iclass_rsr_depc, ICLASS_xt_iclass_wsr_depc, ICLASS_xt_iclass_xsr_depc, ICLASS_xt_iclass_rsr_exccause, ICLASS_xt_iclass_wsr_exccause, ICLASS_xt_iclass_xsr_exccause, ICLASS_xt_iclass_rsr_misc0, ICLASS_xt_iclass_wsr_misc0, ICLASS_xt_iclass_xsr_misc0, ICLASS_xt_iclass_rsr_misc1, ICLASS_xt_iclass_wsr_misc1, ICLASS_xt_iclass_xsr_misc1, ICLASS_xt_iclass_rsr_prid, ICLASS_xt_iclass_rsr_vecbase, ICLASS_xt_iclass_wsr_vecbase, ICLASS_xt_iclass_xsr_vecbase, ICLASS_xt_iclass_mul16, ICLASS_xt_iclass_rfi, ICLASS_xt_iclass_wait, ICLASS_xt_iclass_rsr_interrupt, ICLASS_xt_iclass_wsr_intset, ICLASS_xt_iclass_wsr_intclear, ICLASS_xt_iclass_rsr_intenable, ICLASS_xt_iclass_wsr_intenable, ICLASS_xt_iclass_xsr_intenable, ICLASS_xt_iclass_break, ICLASS_xt_iclass_break_n, ICLASS_xt_iclass_rsr_dbreaka0, ICLASS_xt_iclass_wsr_dbreaka0, ICLASS_xt_iclass_xsr_dbreaka0, ICLASS_xt_iclass_rsr_dbreakc0, ICLASS_xt_iclass_wsr_dbreakc0, ICLASS_xt_iclass_xsr_dbreakc0, ICLASS_xt_iclass_rsr_dbreaka1, ICLASS_xt_iclass_wsr_dbreaka1, ICLASS_xt_iclass_xsr_dbreaka1, ICLASS_xt_iclass_rsr_dbreakc1, ICLASS_xt_iclass_wsr_dbreakc1, ICLASS_xt_iclass_xsr_dbreakc1, ICLASS_xt_iclass_rsr_ibreaka0, ICLASS_xt_iclass_wsr_ibreaka0, ICLASS_xt_iclass_xsr_ibreaka0, ICLASS_xt_iclass_rsr_ibreaka1, ICLASS_xt_iclass_wsr_ibreaka1, ICLASS_xt_iclass_xsr_ibreaka1, ICLASS_xt_iclass_rsr_ibreakenable, ICLASS_xt_iclass_wsr_ibreakenable, ICLASS_xt_iclass_xsr_ibreakenable, ICLASS_xt_iclass_rsr_debugcause, ICLASS_xt_iclass_wsr_debugcause, ICLASS_xt_iclass_xsr_debugcause, ICLASS_xt_iclass_rsr_icount, ICLASS_xt_iclass_wsr_icount, ICLASS_xt_iclass_xsr_icount, ICLASS_xt_iclass_rsr_icountlevel, ICLASS_xt_iclass_wsr_icountlevel, ICLASS_xt_iclass_xsr_icountlevel, ICLASS_xt_iclass_rsr_ddr, ICLASS_xt_iclass_wsr_ddr, ICLASS_xt_iclass_xsr_ddr, ICLASS_xt_iclass_rfdo, ICLASS_xt_iclass_rfdd, ICLASS_xt_iclass_wsr_mmid, ICLASS_xt_iclass_rsr_ccount, ICLASS_xt_iclass_wsr_ccount, ICLASS_xt_iclass_xsr_ccount, ICLASS_xt_iclass_rsr_ccompare0, ICLASS_xt_iclass_wsr_ccompare0, ICLASS_xt_iclass_xsr_ccompare0, ICLASS_xt_iclass_rsr_ccompare1, ICLASS_xt_iclass_wsr_ccompare1, ICLASS_xt_iclass_xsr_ccompare1, ICLASS_xt_iclass_rsr_ccompare2, ICLASS_xt_iclass_wsr_ccompare2, ICLASS_xt_iclass_xsr_ccompare2, ICLASS_xt_iclass_icache, ICLASS_xt_iclass_icache_lock, ICLASS_xt_iclass_icache_inv, ICLASS_xt_iclass_licx, ICLASS_xt_iclass_sicx, ICLASS_xt_iclass_dcache, ICLASS_xt_iclass_dcache_ind, ICLASS_xt_iclass_dcache_inv, ICLASS_xt_iclass_dpf, ICLASS_xt_iclass_dcache_lock, ICLASS_xt_iclass_sdct, ICLASS_xt_iclass_ldct, ICLASS_xt_iclass_wsr_ptevaddr, ICLASS_xt_iclass_rsr_ptevaddr, ICLASS_xt_iclass_xsr_ptevaddr, ICLASS_xt_iclass_rsr_rasid, ICLASS_xt_iclass_wsr_rasid, ICLASS_xt_iclass_xsr_rasid, ICLASS_xt_iclass_rsr_itlbcfg, ICLASS_xt_iclass_wsr_itlbcfg, ICLASS_xt_iclass_xsr_itlbcfg, ICLASS_xt_iclass_rsr_dtlbcfg, ICLASS_xt_iclass_wsr_dtlbcfg, ICLASS_xt_iclass_xsr_dtlbcfg, ICLASS_xt_iclass_idtlb, ICLASS_xt_iclass_rdtlb, ICLASS_xt_iclass_wdtlb, ICLASS_xt_iclass_iitlb, ICLASS_xt_iclass_ritlb, ICLASS_xt_iclass_witlb, ICLASS_xt_iclass_ldpte, ICLASS_xt_iclass_hwwitlba, ICLASS_xt_iclass_hwwdtlba, ICLASS_xt_iclass_rsr_cpenable, ICLASS_xt_iclass_wsr_cpenable, ICLASS_xt_iclass_xsr_cpenable, ICLASS_xt_iclass_clamp, ICLASS_xt_iclass_minmax, ICLASS_xt_iclass_nsa, ICLASS_xt_iclass_sx, ICLASS_xt_iclass_l32ai, ICLASS_xt_iclass_s32ri, ICLASS_xt_iclass_s32c1i, ICLASS_xt_iclass_rsr_scompare1, ICLASS_xt_iclass_wsr_scompare1, ICLASS_xt_iclass_xsr_scompare1, ICLASS_xt_iclass_div, ICLASS_xt_mul32 }; /* Opcode encodings. */ static void Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x80200; } static void Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x300; } static void Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2300; } static void Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x500; } static void Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1500; } static void Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5c0000; } static void Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x580000; } static void Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x540000; } static void Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf0000; } static void Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb0000; } static void Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x70000; } static void Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6c0000; } static void Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x100; } static void Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x804; } static void Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x60000; } static void Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd10f; } static void Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4300; } static void Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5300; } static void Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x90; } static void Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x94; } static void Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4830; } static void Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4831; } static void Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4816; } static void Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4930; } static void Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4931; } static void Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4916; } static void Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa000; } static void Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb000; } static void Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc800; } static void Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xcc00; } static void Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd60f; } static void Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8000; } static void Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd000; } static void Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc000; } static void Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd30f; } static void Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd00f; } static void Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9000; } static void Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x7e03e; } static void Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe73f; } static void Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200c00; } static void Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200d00; } static void Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8; } static void Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc; } static void Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9; } static void Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa; } static void Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb; } static void Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd; } static void Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe; } static void Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf; } static void Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1; } static void Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2; } static void Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x3; } static void Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x680000; } static void Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x690000; } static void Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6b0000; } static void Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6a0000; } static void Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700600; } static void Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700e00; } static void Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6f0000; } static void Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6e0000; } static void Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700100; } static void Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700900; } static void Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700a00; } static void Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700200; } static void Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700b00; } static void Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700300; } static void Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700800; } static void Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700000; } static void Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700400; } static void Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700c00; } static void Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700500; } static void Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700d00; } static void Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x640000; } static void Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x650000; } static void Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x670000; } static void Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x660000; } static void Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x500000; } static void Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x30000; } static void Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x40; } static void Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0; } static void Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x600000; } static void Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa0000; } static void Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200100; } static void Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200900; } static void Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200200; } static void Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x100000; } static void Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200000; } static void Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6d0800; } static void Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6d0900; } static void Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6d0a00; } static void Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200a00; } static void Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x38; } static void Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x39; } static void Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x3a; } static void Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x3b; } static void Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6; } static void Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1006; } static void Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf0200; } static void Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x20000; } static void Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200500; } static void Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200600; } static void Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200400; } static void Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x4; } static void Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x104; } static void Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x204; } static void Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x304; } static void Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x404; } static void Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1a; } static void Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x18; } static void Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x19; } static void Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1b; } static void Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x10; } static void Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x12; } static void Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x14; } static void Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc0200; } static void Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd0200; } static void Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200; } static void Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x10200; } static void Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x20200; } static void Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x30200; } static void Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x600; } static void Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x130; } static void Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x131; } static void Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x116; } static void Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x230; } static void Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x231; } static void Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x216; } static void Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x30; } static void Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x31; } static void Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x16; } static void Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x330; } static void Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x331; } static void Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x316; } static void Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x530; } static void Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x531; } static void Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x516; } static void Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb030; } static void Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb031; } static void Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd030; } static void Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe630; } static void Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe631; } static void Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe616; } static void Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb130; } static void Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb131; } static void Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb116; } static void Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd130; } static void Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd131; } static void Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd116; } static void Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb230; } static void Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb231; } static void Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb216; } static void Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd230; } static void Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd231; } static void Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd216; } static void Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb330; } static void Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb331; } static void Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb316; } static void Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd330; } static void Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd331; } static void Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd316; } static void Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb430; } static void Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb431; } static void Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb416; } static void Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd430; } static void Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd431; } static void Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd416; } static void Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb530; } static void Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb531; } static void Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb516; } static void Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd530; } static void Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd531; } static void Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd516; } static void Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb630; } static void Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb631; } static void Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb616; } static void Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd630; } static void Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd631; } static void Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd616; } static void Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb730; } static void Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb731; } static void Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb716; } static void Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd730; } static void Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd731; } static void Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd716; } static void Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc230; } static void Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc231; } static void Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc216; } static void Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc330; } static void Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc331; } static void Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc316; } static void Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc430; } static void Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc431; } static void Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc416; } static void Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc530; } static void Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc531; } static void Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc516; } static void Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc630; } static void Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc631; } static void Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc616; } static void Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc730; } static void Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc731; } static void Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc716; } static void Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xee30; } static void Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xee31; } static void Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xee16; } static void Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc030; } static void Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc031; } static void Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc016; } static void Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe830; } static void Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe831; } static void Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe816; } static void Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf430; } static void Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf431; } static void Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf416; } static void Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf530; } static void Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf531; } static void Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf516; } static void Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xeb30; } static void Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe730; } static void Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe731; } static void Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe716; } static void Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1c; } static void Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1d; } static void Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x10300; } static void Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x700; } static void Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe230; } static void Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe231; } static void Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe331; } static void Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe430; } static void Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe431; } static void Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe416; } static void Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x400; } static void Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd20f; } static void Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9030; } static void Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9031; } static void Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9016; } static void Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa030; } static void Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa031; } static void Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa016; } static void Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9130; } static void Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9131; } static void Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x9116; } static void Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa130; } static void Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa131; } static void Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xa116; } static void Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8030; } static void Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8031; } static void Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8016; } static void Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8130; } static void Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8131; } static void Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x8116; } static void Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6030; } static void Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6031; } static void Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6016; } static void Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe930; } static void Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe931; } static void Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe916; } static void Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xec30; } static void Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xec31; } static void Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xec16; } static void Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xed30; } static void Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xed31; } static void Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xed16; } static void Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6830; } static void Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6831; } static void Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x6816; } static void Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe1f; } static void Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x10e1f; } static void Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5931; } static void Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xea30; } static void Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xea31; } static void Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xea16; } static void Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf030; } static void Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf031; } static void Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf016; } static void Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf130; } static void Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf131; } static void Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf116; } static void Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf230; } static void Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf231; } static void Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf216; } static void Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2c0700; } static void Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2e0700; } static void Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2d0700; } static void Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2d0720; } static void Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2d0730; } static void Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2f0700; } static void Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x1f; } static void Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x21f; } static void Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x11f; } static void Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x31f; } static void Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x240700; } static void Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x250700; } static void Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x280740; } static void Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x280750; } static void Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x260700; } static void Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x270700; } static void Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200700; } static void Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x210700; } static void Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x220700; } static void Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x230700; } static void Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x280700; } static void Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x280720; } static void Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x280730; } static void Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x91f; } static void Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x81f; } static void Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5331; } static void Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5330; } static void Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5316; } static void Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5a30; } static void Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5a31; } static void Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5a16; } static void Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5b30; } static void Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5b31; } static void Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5b16; } static void Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5c30; } static void Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5c31; } static void Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5c16; } static void Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc05; } static void Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xd05; } static void Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xb05; } static void Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf05; } static void Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe05; } static void Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x405; } static void Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x505; } static void Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x305; } static void Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x705; } static void Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x605; } static void Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf1f; } static void Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x105; } static void Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x905; } static void Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe030; } static void Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe031; } static void Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe016; } static void Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x33; } static void Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x34; } static void Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x35; } static void Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x36; } static void Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x37; } static void Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe04; } static void Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xf04; } static void Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x32; } static void Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200b00; } static void Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200f00; } static void Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x200e00; } static void Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc30; } static void Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc31; } static void Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc16; } static void Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2c; } static void Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2d; } static void Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2e; } static void Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x2f; } static void Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x28; } xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { Opcode_excw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { Opcode_rfe_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { Opcode_rfde_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { Opcode_syscall_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { Opcode_simcall_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { Opcode_call12_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { Opcode_call8_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { Opcode_call4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { Opcode_callx12_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { Opcode_callx8_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { Opcode_callx4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { Opcode_entry_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { Opcode_movsp_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { Opcode_rotw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { Opcode_retw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 0, 0, Opcode_retw_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { Opcode_rfwo_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { Opcode_rfwu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { Opcode_l32e_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { Opcode_s32e_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 0, Opcode_add_n_Slot_inst16a_encode, 0 }; xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 0, Opcode_addi_n_Slot_inst16a_encode, 0 }; xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 0, 0, Opcode_beqz_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 0, 0, Opcode_bnez_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 0, 0, Opcode_ill_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 0, Opcode_l32i_n_Slot_inst16a_encode, 0 }; xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 0, 0, Opcode_mov_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 0, 0, Opcode_movi_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 0, 0, Opcode_nop_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 0, 0, Opcode_ret_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 0, Opcode_s32i_n_Slot_inst16a_encode, 0 }; xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { Opcode_rur_threadptr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { Opcode_wur_threadptr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { Opcode_addi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { Opcode_addmi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { Opcode_add_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { Opcode_sub_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { Opcode_addx2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { Opcode_addx4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { Opcode_addx8_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { Opcode_subx2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { Opcode_subx4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { Opcode_subx8_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { Opcode_and_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { Opcode_or_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { Opcode_xor_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { Opcode_beqi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { Opcode_bnei_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { Opcode_bgei_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { Opcode_blti_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { Opcode_bbci_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { Opcode_bbsi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { Opcode_bgeui_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { Opcode_bltui_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { Opcode_beq_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { Opcode_bne_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { Opcode_bge_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { Opcode_blt_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { Opcode_bgeu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { Opcode_bltu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { Opcode_bany_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { Opcode_bnone_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { Opcode_ball_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { Opcode_bnall_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { Opcode_bbc_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { Opcode_bbs_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { Opcode_beqz_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { Opcode_bnez_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { Opcode_bgez_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { Opcode_bltz_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { Opcode_call0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { Opcode_callx0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { Opcode_extui_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { Opcode_ill_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { Opcode_j_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { Opcode_jx_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { Opcode_l16ui_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { Opcode_l16si_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { Opcode_l32i_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { Opcode_l32r_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { Opcode_l8ui_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { Opcode_loop_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { Opcode_loopnez_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { Opcode_loopgtz_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { Opcode_movi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { Opcode_moveqz_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { Opcode_movnez_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { Opcode_movltz_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { Opcode_movgez_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { Opcode_neg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { Opcode_abs_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { Opcode_nop_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { Opcode_ret_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { Opcode_s16i_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { Opcode_s32i_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { Opcode_s8i_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { Opcode_ssr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { Opcode_ssl_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { Opcode_ssa8l_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { Opcode_ssa8b_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { Opcode_ssai_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { Opcode_sll_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { Opcode_src_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { Opcode_srl_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { Opcode_sra_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { Opcode_slli_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { Opcode_srai_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { Opcode_srli_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { Opcode_memw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { Opcode_extw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { Opcode_isync_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { Opcode_rsync_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { Opcode_esync_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { Opcode_dsync_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { Opcode_rsil_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { Opcode_rsr_lend_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { Opcode_wsr_lend_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { Opcode_xsr_lend_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { Opcode_rsr_lcount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { Opcode_wsr_lcount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { Opcode_xsr_lcount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { Opcode_rsr_sar_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { Opcode_wsr_sar_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { Opcode_xsr_sar_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { Opcode_rsr_litbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { Opcode_wsr_litbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { Opcode_xsr_litbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { Opcode_rsr_176_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { Opcode_wsr_176_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { Opcode_rsr_208_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { Opcode_rsr_ps_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { Opcode_wsr_ps_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { Opcode_xsr_ps_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { Opcode_rsr_epc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { Opcode_wsr_epc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { Opcode_xsr_epc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { Opcode_rsr_epc2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { Opcode_wsr_epc2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { Opcode_xsr_epc2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { Opcode_rsr_epc3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { Opcode_wsr_epc3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { Opcode_xsr_epc3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { Opcode_rsr_epc4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { Opcode_wsr_epc4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { Opcode_xsr_epc4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { Opcode_rsr_epc5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { Opcode_wsr_epc5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { Opcode_xsr_epc5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { Opcode_rsr_epc6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { Opcode_wsr_epc6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { Opcode_xsr_epc6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { Opcode_rsr_epc7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { Opcode_wsr_epc7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { Opcode_xsr_epc7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { Opcode_rsr_eps2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { Opcode_wsr_eps2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { Opcode_xsr_eps2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { Opcode_rsr_eps3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { Opcode_wsr_eps3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { Opcode_xsr_eps3_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { Opcode_rsr_eps4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { Opcode_wsr_eps4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { Opcode_xsr_eps4_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { Opcode_rsr_eps5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { Opcode_wsr_eps5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { Opcode_xsr_eps5_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { Opcode_rsr_eps6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { Opcode_wsr_eps6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { Opcode_xsr_eps6_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { Opcode_rsr_eps7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { Opcode_wsr_eps7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { Opcode_xsr_eps7_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { Opcode_rsr_depc_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { Opcode_wsr_depc_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { Opcode_xsr_depc_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { Opcode_rsr_exccause_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { Opcode_wsr_exccause_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { Opcode_xsr_exccause_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { Opcode_rsr_misc0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { Opcode_wsr_misc0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { Opcode_xsr_misc0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { Opcode_rsr_misc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { Opcode_wsr_misc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { Opcode_xsr_misc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { Opcode_rsr_prid_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { Opcode_mul16u_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { Opcode_mul16s_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { Opcode_rfi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { Opcode_waiti_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { Opcode_wsr_intset_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { Opcode_wsr_intclear_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { Opcode_rsr_intenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { Opcode_wsr_intenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { Opcode_xsr_intenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { Opcode_break_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 0, 0, Opcode_break_n_Slot_inst16b_encode }; xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { Opcode_rsr_icount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { Opcode_wsr_icount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { Opcode_xsr_icount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { Opcode_rsr_ddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { Opcode_wsr_ddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { Opcode_xsr_ddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { Opcode_rfdo_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { Opcode_rfdd_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { Opcode_wsr_mmid_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { Opcode_rsr_ccount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { Opcode_wsr_ccount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { Opcode_xsr_ccount_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { Opcode_ipf_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { Opcode_ihi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { Opcode_ipfl_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { Opcode_ihu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { Opcode_iiu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { Opcode_iii_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { Opcode_lict_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { Opcode_licw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { Opcode_sict_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { Opcode_sicw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { Opcode_dhwb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { Opcode_dhwbi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { Opcode_diwb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { Opcode_diwbi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { Opcode_dhi_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { Opcode_dii_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { Opcode_dpfr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { Opcode_dpfw_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { Opcode_dpfro_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { Opcode_dpfwo_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { Opcode_dpfl_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { Opcode_dhu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { Opcode_diu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { Opcode_sdct_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { Opcode_ldct_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { Opcode_rsr_rasid_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { Opcode_wsr_rasid_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { Opcode_xsr_rasid_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { Opcode_idtlb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { Opcode_pdtlb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { Opcode_rdtlb0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { Opcode_rdtlb1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { Opcode_wdtlb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { Opcode_iitlb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { Opcode_pitlb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { Opcode_ritlb0_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { Opcode_ritlb1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { Opcode_witlb_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { Opcode_ldpte_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { Opcode_hwwitlba_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { Opcode_hwwdtlba_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { Opcode_clamps_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { Opcode_min_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { Opcode_max_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { Opcode_minu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { Opcode_maxu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { Opcode_nsa_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { Opcode_nsau_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { Opcode_sext_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { Opcode_l32ai_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { Opcode_s32ri_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { Opcode_s32c1i_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { Opcode_quou_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { Opcode_quos_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { Opcode_remu_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { Opcode_rems_Slot_inst_encode, 0, 0 }; xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { Opcode_mull_Slot_inst_encode, 0, 0 }; /* Opcode table. */ static xtensa_opcode_internal opcodes[] = { { "excw", ICLASS_xt_iclass_excw, 0, Opcode_excw_encode_fns, 0, 0 }, { "rfe", ICLASS_xt_iclass_rfe, XTENSA_OPCODE_IS_JUMP, Opcode_rfe_encode_fns, 0, 0 }, { "rfde", ICLASS_xt_iclass_rfde, XTENSA_OPCODE_IS_JUMP, Opcode_rfde_encode_fns, 0, 0 }, { "syscall", ICLASS_xt_iclass_syscall, 0, Opcode_syscall_encode_fns, 0, 0 }, { "simcall", ICLASS_xt_iclass_simcall, 0, Opcode_simcall_encode_fns, 0, 0 }, { "call12", ICLASS_xt_iclass_call12, XTENSA_OPCODE_IS_CALL, Opcode_call12_encode_fns, 0, 0 }, { "call8", ICLASS_xt_iclass_call8, XTENSA_OPCODE_IS_CALL, Opcode_call8_encode_fns, 0, 0 }, { "call4", ICLASS_xt_iclass_call4, XTENSA_OPCODE_IS_CALL, Opcode_call4_encode_fns, 0, 0 }, { "callx12", ICLASS_xt_iclass_callx12, XTENSA_OPCODE_IS_CALL, Opcode_callx12_encode_fns, 0, 0 }, { "callx8", ICLASS_xt_iclass_callx8, XTENSA_OPCODE_IS_CALL, Opcode_callx8_encode_fns, 0, 0 }, { "callx4", ICLASS_xt_iclass_callx4, XTENSA_OPCODE_IS_CALL, Opcode_callx4_encode_fns, 0, 0 }, { "entry", ICLASS_xt_iclass_entry, 0, Opcode_entry_encode_fns, 0, 0 }, { "movsp", ICLASS_xt_iclass_movsp, 0, Opcode_movsp_encode_fns, 0, 0 }, { "rotw", ICLASS_xt_iclass_rotw, 0, Opcode_rotw_encode_fns, 0, 0 }, { "retw", ICLASS_xt_iclass_retw, XTENSA_OPCODE_IS_JUMP, Opcode_retw_encode_fns, 0, 0 }, { "retw.n", ICLASS_xt_iclass_retw, XTENSA_OPCODE_IS_JUMP, Opcode_retw_n_encode_fns, 0, 0 }, { "rfwo", ICLASS_xt_iclass_rfwou, XTENSA_OPCODE_IS_JUMP, Opcode_rfwo_encode_fns, 0, 0 }, { "rfwu", ICLASS_xt_iclass_rfwou, XTENSA_OPCODE_IS_JUMP, Opcode_rfwu_encode_fns, 0, 0 }, { "l32e", ICLASS_xt_iclass_l32e, 0, Opcode_l32e_encode_fns, 0, 0 }, { "s32e", ICLASS_xt_iclass_s32e, 0, Opcode_s32e_encode_fns, 0, 0 }, { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, 0, Opcode_rsr_windowbase_encode_fns, 0, 0 }, { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, 0, Opcode_wsr_windowbase_encode_fns, 0, 0 }, { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, 0, Opcode_xsr_windowbase_encode_fns, 0, 0 }, { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, 0, Opcode_rsr_windowstart_encode_fns, 0, 0 }, { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, 0, Opcode_wsr_windowstart_encode_fns, 0, 0 }, { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, 0, Opcode_xsr_windowstart_encode_fns, 0, 0 }, { "add.n", ICLASS_xt_iclass_add_n, 0, Opcode_add_n_encode_fns, 0, 0 }, { "addi.n", ICLASS_xt_iclass_addi_n, 0, Opcode_addi_n_encode_fns, 0, 0 }, { "beqz.n", ICLASS_xt_iclass_bz6, XTENSA_OPCODE_IS_BRANCH, Opcode_beqz_n_encode_fns, 0, 0 }, { "bnez.n", ICLASS_xt_iclass_bz6, XTENSA_OPCODE_IS_BRANCH, Opcode_bnez_n_encode_fns, 0, 0 }, { "ill.n", ICLASS_xt_iclass_ill_n, 0, Opcode_ill_n_encode_fns, 0, 0 }, { "l32i.n", ICLASS_xt_iclass_loadi4, 0, Opcode_l32i_n_encode_fns, 0, 0 }, { "mov.n", ICLASS_xt_iclass_mov_n, 0, Opcode_mov_n_encode_fns, 0, 0 }, { "movi.n", ICLASS_xt_iclass_movi_n, 0, Opcode_movi_n_encode_fns, 0, 0 }, { "nop.n", ICLASS_xt_iclass_nopn, 0, Opcode_nop_n_encode_fns, 0, 0 }, { "ret.n", ICLASS_xt_iclass_retn, XTENSA_OPCODE_IS_JUMP, Opcode_ret_n_encode_fns, 0, 0 }, { "s32i.n", ICLASS_xt_iclass_storei4, 0, Opcode_s32i_n_encode_fns, 0, 0 }, { "rur.threadptr", ICLASS_rur_threadptr, 0, Opcode_rur_threadptr_encode_fns, 0, 0 }, { "wur.threadptr", ICLASS_wur_threadptr, 0, Opcode_wur_threadptr_encode_fns, 0, 0 }, { "addi", ICLASS_xt_iclass_addi, 0, Opcode_addi_encode_fns, 0, 0 }, { "addmi", ICLASS_xt_iclass_addmi, 0, Opcode_addmi_encode_fns, 0, 0 }, { "add", ICLASS_xt_iclass_addsub, 0, Opcode_add_encode_fns, 0, 0 }, { "sub", ICLASS_xt_iclass_addsub, 0, Opcode_sub_encode_fns, 0, 0 }, { "addx2", ICLASS_xt_iclass_addsub, 0, Opcode_addx2_encode_fns, 0, 0 }, { "addx4", ICLASS_xt_iclass_addsub, 0, Opcode_addx4_encode_fns, 0, 0 }, { "addx8", ICLASS_xt_iclass_addsub, 0, Opcode_addx8_encode_fns, 0, 0 }, { "subx2", ICLASS_xt_iclass_addsub, 0, Opcode_subx2_encode_fns, 0, 0 }, { "subx4", ICLASS_xt_iclass_addsub, 0, Opcode_subx4_encode_fns, 0, 0 }, { "subx8", ICLASS_xt_iclass_addsub, 0, Opcode_subx8_encode_fns, 0, 0 }, { "and", ICLASS_xt_iclass_bit, 0, Opcode_and_encode_fns, 0, 0 }, { "or", ICLASS_xt_iclass_bit, 0, Opcode_or_encode_fns, 0, 0 }, { "xor", ICLASS_xt_iclass_bit, 0, Opcode_xor_encode_fns, 0, 0 }, { "beqi", ICLASS_xt_iclass_bsi8, XTENSA_OPCODE_IS_BRANCH, Opcode_beqi_encode_fns, 0, 0 }, { "bnei", ICLASS_xt_iclass_bsi8, XTENSA_OPCODE_IS_BRANCH, Opcode_bnei_encode_fns, 0, 0 }, { "bgei", ICLASS_xt_iclass_bsi8, XTENSA_OPCODE_IS_BRANCH, Opcode_bgei_encode_fns, 0, 0 }, { "blti", ICLASS_xt_iclass_bsi8, XTENSA_OPCODE_IS_BRANCH, Opcode_blti_encode_fns, 0, 0 }, { "bbci", ICLASS_xt_iclass_bsi8b, XTENSA_OPCODE_IS_BRANCH, Opcode_bbci_encode_fns, 0, 0 }, { "bbsi", ICLASS_xt_iclass_bsi8b, XTENSA_OPCODE_IS_BRANCH, Opcode_bbsi_encode_fns, 0, 0 }, { "bgeui", ICLASS_xt_iclass_bsi8u, XTENSA_OPCODE_IS_BRANCH, Opcode_bgeui_encode_fns, 0, 0 }, { "bltui", ICLASS_xt_iclass_bsi8u, XTENSA_OPCODE_IS_BRANCH, Opcode_bltui_encode_fns, 0, 0 }, { "beq", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_beq_encode_fns, 0, 0 }, { "bne", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bne_encode_fns, 0, 0 }, { "bge", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bge_encode_fns, 0, 0 }, { "blt", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_blt_encode_fns, 0, 0 }, { "bgeu", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bgeu_encode_fns, 0, 0 }, { "bltu", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bltu_encode_fns, 0, 0 }, { "bany", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bany_encode_fns, 0, 0 }, { "bnone", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bnone_encode_fns, 0, 0 }, { "ball", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_ball_encode_fns, 0, 0 }, { "bnall", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bnall_encode_fns, 0, 0 }, { "bbc", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bbc_encode_fns, 0, 0 }, { "bbs", ICLASS_xt_iclass_bst8, XTENSA_OPCODE_IS_BRANCH, Opcode_bbs_encode_fns, 0, 0 }, { "beqz", ICLASS_xt_iclass_bsz12, XTENSA_OPCODE_IS_BRANCH, Opcode_beqz_encode_fns, 0, 0 }, { "bnez", ICLASS_xt_iclass_bsz12, XTENSA_OPCODE_IS_BRANCH, Opcode_bnez_encode_fns, 0, 0 }, { "bgez", ICLASS_xt_iclass_bsz12, XTENSA_OPCODE_IS_BRANCH, Opcode_bgez_encode_fns, 0, 0 }, { "bltz", ICLASS_xt_iclass_bsz12, XTENSA_OPCODE_IS_BRANCH, Opcode_bltz_encode_fns, 0, 0 }, { "call0", ICLASS_xt_iclass_call0, XTENSA_OPCODE_IS_CALL, Opcode_call0_encode_fns, 0, 0 }, { "callx0", ICLASS_xt_iclass_callx0, XTENSA_OPCODE_IS_CALL, Opcode_callx0_encode_fns, 0, 0 }, { "extui", ICLASS_xt_iclass_exti, 0, Opcode_extui_encode_fns, 0, 0 }, { "ill", ICLASS_xt_iclass_ill, 0, Opcode_ill_encode_fns, 0, 0 }, { "j", ICLASS_xt_iclass_jump, XTENSA_OPCODE_IS_JUMP, Opcode_j_encode_fns, 0, 0 }, { "jx", ICLASS_xt_iclass_jumpx, XTENSA_OPCODE_IS_JUMP, Opcode_jx_encode_fns, 0, 0 }, { "l16ui", ICLASS_xt_iclass_l16ui, 0, Opcode_l16ui_encode_fns, 0, 0 }, { "l16si", ICLASS_xt_iclass_l16si, 0, Opcode_l16si_encode_fns, 0, 0 }, { "l32i", ICLASS_xt_iclass_l32i, 0, Opcode_l32i_encode_fns, 0, 0 }, { "l32r", ICLASS_xt_iclass_l32r, 0, Opcode_l32r_encode_fns, 0, 0 }, { "l8ui", ICLASS_xt_iclass_l8i, 0, Opcode_l8ui_encode_fns, 0, 0 }, { "loop", ICLASS_xt_iclass_loop, XTENSA_OPCODE_IS_LOOP, Opcode_loop_encode_fns, 0, 0 }, { "loopnez", ICLASS_xt_iclass_loopz, XTENSA_OPCODE_IS_LOOP, Opcode_loopnez_encode_fns, 0, 0 }, { "loopgtz", ICLASS_xt_iclass_loopz, XTENSA_OPCODE_IS_LOOP, Opcode_loopgtz_encode_fns, 0, 0 }, { "movi", ICLASS_xt_iclass_movi, 0, Opcode_movi_encode_fns, 0, 0 }, { "moveqz", ICLASS_xt_iclass_movz, 0, Opcode_moveqz_encode_fns, 0, 0 }, { "movnez", ICLASS_xt_iclass_movz, 0, Opcode_movnez_encode_fns, 0, 0 }, { "movltz", ICLASS_xt_iclass_movz, 0, Opcode_movltz_encode_fns, 0, 0 }, { "movgez", ICLASS_xt_iclass_movz, 0, Opcode_movgez_encode_fns, 0, 0 }, { "neg", ICLASS_xt_iclass_neg, 0, Opcode_neg_encode_fns, 0, 0 }, { "abs", ICLASS_xt_iclass_neg, 0, Opcode_abs_encode_fns, 0, 0 }, { "nop", ICLASS_xt_iclass_nop, 0, Opcode_nop_encode_fns, 0, 0 }, { "ret", ICLASS_xt_iclass_return, XTENSA_OPCODE_IS_JUMP, Opcode_ret_encode_fns, 0, 0 }, { "s16i", ICLASS_xt_iclass_s16i, 0, Opcode_s16i_encode_fns, 0, 0 }, { "s32i", ICLASS_xt_iclass_s32i, 0, Opcode_s32i_encode_fns, 0, 0 }, { "s8i", ICLASS_xt_iclass_s8i, 0, Opcode_s8i_encode_fns, 0, 0 }, { "ssr", ICLASS_xt_iclass_sar, 0, Opcode_ssr_encode_fns, 0, 0 }, { "ssl", ICLASS_xt_iclass_sar, 0, Opcode_ssl_encode_fns, 0, 0 }, { "ssa8l", ICLASS_xt_iclass_sar, 0, Opcode_ssa8l_encode_fns, 0, 0 }, { "ssa8b", ICLASS_xt_iclass_sar, 0, Opcode_ssa8b_encode_fns, 0, 0 }, { "ssai", ICLASS_xt_iclass_sari, 0, Opcode_ssai_encode_fns, 0, 0 }, { "sll", ICLASS_xt_iclass_shifts, 0, Opcode_sll_encode_fns, 0, 0 }, { "src", ICLASS_xt_iclass_shiftst, 0, Opcode_src_encode_fns, 0, 0 }, { "srl", ICLASS_xt_iclass_shiftt, 0, Opcode_srl_encode_fns, 0, 0 }, { "sra", ICLASS_xt_iclass_shiftt, 0, Opcode_sra_encode_fns, 0, 0 }, { "slli", ICLASS_xt_iclass_slli, 0, Opcode_slli_encode_fns, 0, 0 }, { "srai", ICLASS_xt_iclass_srai, 0, Opcode_srai_encode_fns, 0, 0 }, { "srli", ICLASS_xt_iclass_srli, 0, Opcode_srli_encode_fns, 0, 0 }, { "memw", ICLASS_xt_iclass_memw, 0, Opcode_memw_encode_fns, 0, 0 }, { "extw", ICLASS_xt_iclass_extw, 0, Opcode_extw_encode_fns, 0, 0 }, { "isync", ICLASS_xt_iclass_isync, 0, Opcode_isync_encode_fns, 0, 0 }, { "rsync", ICLASS_xt_iclass_sync, 0, Opcode_rsync_encode_fns, 0, 0 }, { "esync", ICLASS_xt_iclass_sync, 0, Opcode_esync_encode_fns, 0, 0 }, { "dsync", ICLASS_xt_iclass_sync, 0, Opcode_dsync_encode_fns, 0, 0 }, { "rsil", ICLASS_xt_iclass_rsil, 0, Opcode_rsil_encode_fns, 0, 0 }, { "rsr.lend", ICLASS_xt_iclass_rsr_lend, 0, Opcode_rsr_lend_encode_fns, 0, 0 }, { "wsr.lend", ICLASS_xt_iclass_wsr_lend, 0, Opcode_wsr_lend_encode_fns, 0, 0 }, { "xsr.lend", ICLASS_xt_iclass_xsr_lend, 0, Opcode_xsr_lend_encode_fns, 0, 0 }, { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, 0, Opcode_rsr_lcount_encode_fns, 0, 0 }, { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, 0, Opcode_wsr_lcount_encode_fns, 0, 0 }, { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, 0, Opcode_xsr_lcount_encode_fns, 0, 0 }, { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, 0, Opcode_rsr_lbeg_encode_fns, 0, 0 }, { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, 0, Opcode_wsr_lbeg_encode_fns, 0, 0 }, { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, 0, Opcode_xsr_lbeg_encode_fns, 0, 0 }, { "rsr.sar", ICLASS_xt_iclass_rsr_sar, 0, Opcode_rsr_sar_encode_fns, 0, 0 }, { "wsr.sar", ICLASS_xt_iclass_wsr_sar, 0, Opcode_wsr_sar_encode_fns, 0, 0 }, { "xsr.sar", ICLASS_xt_iclass_xsr_sar, 0, Opcode_xsr_sar_encode_fns, 0, 0 }, { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, 0, Opcode_rsr_litbase_encode_fns, 0, 0 }, { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, 0, Opcode_wsr_litbase_encode_fns, 0, 0 }, { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, 0, Opcode_xsr_litbase_encode_fns, 0, 0 }, { "rsr.176", ICLASS_xt_iclass_rsr_176, 0, Opcode_rsr_176_encode_fns, 0, 0 }, { "wsr.176", ICLASS_xt_iclass_wsr_176, 0, Opcode_wsr_176_encode_fns, 0, 0 }, { "rsr.208", ICLASS_xt_iclass_rsr_208, 0, Opcode_rsr_208_encode_fns, 0, 0 }, { "rsr.ps", ICLASS_xt_iclass_rsr_ps, 0, Opcode_rsr_ps_encode_fns, 0, 0 }, { "wsr.ps", ICLASS_xt_iclass_wsr_ps, 0, Opcode_wsr_ps_encode_fns, 0, 0 }, { "xsr.ps", ICLASS_xt_iclass_xsr_ps, 0, Opcode_xsr_ps_encode_fns, 0, 0 }, { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, 0, Opcode_rsr_epc1_encode_fns, 0, 0 }, { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, 0, Opcode_wsr_epc1_encode_fns, 0, 0 }, { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, 0, Opcode_xsr_epc1_encode_fns, 0, 0 }, { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, 0, Opcode_rsr_excsave1_encode_fns, 0, 0 }, { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, 0, Opcode_wsr_excsave1_encode_fns, 0, 0 }, { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, 0, Opcode_xsr_excsave1_encode_fns, 0, 0 }, { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, 0, Opcode_rsr_epc2_encode_fns, 0, 0 }, { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, 0, Opcode_wsr_epc2_encode_fns, 0, 0 }, { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, 0, Opcode_xsr_epc2_encode_fns, 0, 0 }, { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, 0, Opcode_rsr_excsave2_encode_fns, 0, 0 }, { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, 0, Opcode_wsr_excsave2_encode_fns, 0, 0 }, { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, 0, Opcode_xsr_excsave2_encode_fns, 0, 0 }, { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, 0, Opcode_rsr_epc3_encode_fns, 0, 0 }, { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, 0, Opcode_wsr_epc3_encode_fns, 0, 0 }, { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, 0, Opcode_xsr_epc3_encode_fns, 0, 0 }, { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, 0, Opcode_rsr_excsave3_encode_fns, 0, 0 }, { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, 0, Opcode_wsr_excsave3_encode_fns, 0, 0 }, { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, 0, Opcode_xsr_excsave3_encode_fns, 0, 0 }, { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, 0, Opcode_rsr_epc4_encode_fns, 0, 0 }, { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, 0, Opcode_wsr_epc4_encode_fns, 0, 0 }, { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, 0, Opcode_xsr_epc4_encode_fns, 0, 0 }, { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, 0, Opcode_rsr_excsave4_encode_fns, 0, 0 }, { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, 0, Opcode_wsr_excsave4_encode_fns, 0, 0 }, { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, 0, Opcode_xsr_excsave4_encode_fns, 0, 0 }, { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, 0, Opcode_rsr_epc5_encode_fns, 0, 0 }, { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, 0, Opcode_wsr_epc5_encode_fns, 0, 0 }, { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, 0, Opcode_xsr_epc5_encode_fns, 0, 0 }, { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, 0, Opcode_rsr_excsave5_encode_fns, 0, 0 }, { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, 0, Opcode_wsr_excsave5_encode_fns, 0, 0 }, { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, 0, Opcode_xsr_excsave5_encode_fns, 0, 0 }, { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, 0, Opcode_rsr_epc6_encode_fns, 0, 0 }, { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, 0, Opcode_wsr_epc6_encode_fns, 0, 0 }, { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, 0, Opcode_xsr_epc6_encode_fns, 0, 0 }, { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, 0, Opcode_rsr_excsave6_encode_fns, 0, 0 }, { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, 0, Opcode_wsr_excsave6_encode_fns, 0, 0 }, { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, 0, Opcode_xsr_excsave6_encode_fns, 0, 0 }, { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, 0, Opcode_rsr_epc7_encode_fns, 0, 0 }, { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, 0, Opcode_wsr_epc7_encode_fns, 0, 0 }, { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, 0, Opcode_xsr_epc7_encode_fns, 0, 0 }, { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, 0, Opcode_rsr_excsave7_encode_fns, 0, 0 }, { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, 0, Opcode_wsr_excsave7_encode_fns, 0, 0 }, { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, 0, Opcode_xsr_excsave7_encode_fns, 0, 0 }, { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, 0, Opcode_rsr_eps2_encode_fns, 0, 0 }, { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, 0, Opcode_wsr_eps2_encode_fns, 0, 0 }, { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, 0, Opcode_xsr_eps2_encode_fns, 0, 0 }, { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, 0, Opcode_rsr_eps3_encode_fns, 0, 0 }, { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, 0, Opcode_wsr_eps3_encode_fns, 0, 0 }, { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, 0, Opcode_xsr_eps3_encode_fns, 0, 0 }, { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, 0, Opcode_rsr_eps4_encode_fns, 0, 0 }, { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, 0, Opcode_wsr_eps4_encode_fns, 0, 0 }, { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, 0, Opcode_xsr_eps4_encode_fns, 0, 0 }, { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, 0, Opcode_rsr_eps5_encode_fns, 0, 0 }, { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, 0, Opcode_wsr_eps5_encode_fns, 0, 0 }, { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, 0, Opcode_xsr_eps5_encode_fns, 0, 0 }, { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, 0, Opcode_rsr_eps6_encode_fns, 0, 0 }, { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, 0, Opcode_wsr_eps6_encode_fns, 0, 0 }, { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, 0, Opcode_xsr_eps6_encode_fns, 0, 0 }, { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, 0, Opcode_rsr_eps7_encode_fns, 0, 0 }, { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, 0, Opcode_wsr_eps7_encode_fns, 0, 0 }, { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, 0, Opcode_xsr_eps7_encode_fns, 0, 0 }, { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, 0, Opcode_rsr_excvaddr_encode_fns, 0, 0 }, { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, 0, Opcode_wsr_excvaddr_encode_fns, 0, 0 }, { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, 0, Opcode_xsr_excvaddr_encode_fns, 0, 0 }, { "rsr.depc", ICLASS_xt_iclass_rsr_depc, 0, Opcode_rsr_depc_encode_fns, 0, 0 }, { "wsr.depc", ICLASS_xt_iclass_wsr_depc, 0, Opcode_wsr_depc_encode_fns, 0, 0 }, { "xsr.depc", ICLASS_xt_iclass_xsr_depc, 0, Opcode_xsr_depc_encode_fns, 0, 0 }, { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, 0, Opcode_rsr_exccause_encode_fns, 0, 0 }, { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, 0, Opcode_wsr_exccause_encode_fns, 0, 0 }, { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, 0, Opcode_xsr_exccause_encode_fns, 0, 0 }, { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, 0, Opcode_rsr_misc0_encode_fns, 0, 0 }, { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, 0, Opcode_wsr_misc0_encode_fns, 0, 0 }, { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, 0, Opcode_xsr_misc0_encode_fns, 0, 0 }, { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, 0, Opcode_rsr_misc1_encode_fns, 0, 0 }, { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, 0, Opcode_wsr_misc1_encode_fns, 0, 0 }, { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, 0, Opcode_xsr_misc1_encode_fns, 0, 0 }, { "rsr.prid", ICLASS_xt_iclass_rsr_prid, 0, Opcode_rsr_prid_encode_fns, 0, 0 }, { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, 0, Opcode_rsr_vecbase_encode_fns, 0, 0 }, { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, 0, Opcode_wsr_vecbase_encode_fns, 0, 0 }, { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, 0, Opcode_xsr_vecbase_encode_fns, 0, 0 }, { "mul16u", ICLASS_xt_iclass_mul16, 0, Opcode_mul16u_encode_fns, 0, 0 }, { "mul16s", ICLASS_xt_iclass_mul16, 0, Opcode_mul16s_encode_fns, 0, 0 }, { "rfi", ICLASS_xt_iclass_rfi, XTENSA_OPCODE_IS_JUMP, Opcode_rfi_encode_fns, 0, 0 }, { "waiti", ICLASS_xt_iclass_wait, 0, Opcode_waiti_encode_fns, 0, 0 }, { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, 0, Opcode_rsr_interrupt_encode_fns, 0, 0 }, { "wsr.intset", ICLASS_xt_iclass_wsr_intset, 0, Opcode_wsr_intset_encode_fns, 0, 0 }, { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, 0, Opcode_wsr_intclear_encode_fns, 0, 0 }, { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, 0, Opcode_rsr_intenable_encode_fns, 0, 0 }, { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, 0, Opcode_wsr_intenable_encode_fns, 0, 0 }, { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, 0, Opcode_xsr_intenable_encode_fns, 0, 0 }, { "break", ICLASS_xt_iclass_break, 0, Opcode_break_encode_fns, 0, 0 }, { "break.n", ICLASS_xt_iclass_break_n, 0, Opcode_break_n_encode_fns, 0, 0 }, { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, 0, Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, 0, Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, 0, Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, 0, Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, 0, Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, 0, Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, 0, Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, 0, Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, 0, Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, 0, Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, 0, Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, 0, Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, 0, Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, 0, Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, 0, Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, 0, Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, 0, Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, 0, Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, 0, Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, 0, Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, 0, Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, 0, Opcode_rsr_debugcause_encode_fns, 0, 0 }, { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, 0, Opcode_wsr_debugcause_encode_fns, 0, 0 }, { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, 0, Opcode_xsr_debugcause_encode_fns, 0, 0 }, { "rsr.icount", ICLASS_xt_iclass_rsr_icount, 0, Opcode_rsr_icount_encode_fns, 0, 0 }, { "wsr.icount", ICLASS_xt_iclass_wsr_icount, 0, Opcode_wsr_icount_encode_fns, 0, 0 }, { "xsr.icount", ICLASS_xt_iclass_xsr_icount, 0, Opcode_xsr_icount_encode_fns, 0, 0 }, { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, 0, Opcode_rsr_icountlevel_encode_fns, 0, 0 }, { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, 0, Opcode_wsr_icountlevel_encode_fns, 0, 0 }, { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, 0, Opcode_xsr_icountlevel_encode_fns, 0, 0 }, { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, 0, Opcode_rsr_ddr_encode_fns, 0, 0 }, { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, 0, Opcode_wsr_ddr_encode_fns, 0, 0 }, { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, 0, Opcode_xsr_ddr_encode_fns, 0, 0 }, { "rfdo", ICLASS_xt_iclass_rfdo, XTENSA_OPCODE_IS_JUMP, Opcode_rfdo_encode_fns, 0, 0 }, { "rfdd", ICLASS_xt_iclass_rfdd, XTENSA_OPCODE_IS_JUMP, Opcode_rfdd_encode_fns, 0, 0 }, { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, 0, Opcode_wsr_mmid_encode_fns, 0, 0 }, { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, 0, Opcode_rsr_ccount_encode_fns, 0, 0 }, { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, 0, Opcode_wsr_ccount_encode_fns, 0, 0 }, { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, 0, Opcode_xsr_ccount_encode_fns, 0, 0 }, { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, 0, Opcode_rsr_ccompare0_encode_fns, 0, 0 }, { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, 0, Opcode_wsr_ccompare0_encode_fns, 0, 0 }, { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, 0, Opcode_xsr_ccompare0_encode_fns, 0, 0 }, { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, 0, Opcode_rsr_ccompare1_encode_fns, 0, 0 }, { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, 0, Opcode_wsr_ccompare1_encode_fns, 0, 0 }, { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, 0, Opcode_xsr_ccompare1_encode_fns, 0, 0 }, { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, 0, Opcode_rsr_ccompare2_encode_fns, 0, 0 }, { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, 0, Opcode_wsr_ccompare2_encode_fns, 0, 0 }, { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, 0, Opcode_xsr_ccompare2_encode_fns, 0, 0 }, { "ipf", ICLASS_xt_iclass_icache, 0, Opcode_ipf_encode_fns, 0, 0 }, { "ihi", ICLASS_xt_iclass_icache, 0, Opcode_ihi_encode_fns, 0, 0 }, { "ipfl", ICLASS_xt_iclass_icache_lock, 0, Opcode_ipfl_encode_fns, 0, 0 }, { "ihu", ICLASS_xt_iclass_icache_lock, 0, Opcode_ihu_encode_fns, 0, 0 }, { "iiu", ICLASS_xt_iclass_icache_lock, 0, Opcode_iiu_encode_fns, 0, 0 }, { "iii", ICLASS_xt_iclass_icache_inv, 0, Opcode_iii_encode_fns, 0, 0 }, { "lict", ICLASS_xt_iclass_licx, 0, Opcode_lict_encode_fns, 0, 0 }, { "licw", ICLASS_xt_iclass_licx, 0, Opcode_licw_encode_fns, 0, 0 }, { "sict", ICLASS_xt_iclass_sicx, 0, Opcode_sict_encode_fns, 0, 0 }, { "sicw", ICLASS_xt_iclass_sicx, 0, Opcode_sicw_encode_fns, 0, 0 }, { "dhwb", ICLASS_xt_iclass_dcache, 0, Opcode_dhwb_encode_fns, 0, 0 }, { "dhwbi", ICLASS_xt_iclass_dcache, 0, Opcode_dhwbi_encode_fns, 0, 0 }, { "diwb", ICLASS_xt_iclass_dcache_ind, 0, Opcode_diwb_encode_fns, 0, 0 }, { "diwbi", ICLASS_xt_iclass_dcache_ind, 0, Opcode_diwbi_encode_fns, 0, 0 }, { "dhi", ICLASS_xt_iclass_dcache_inv, 0, Opcode_dhi_encode_fns, 0, 0 }, { "dii", ICLASS_xt_iclass_dcache_inv, 0, Opcode_dii_encode_fns, 0, 0 }, { "dpfr", ICLASS_xt_iclass_dpf, 0, Opcode_dpfr_encode_fns, 0, 0 }, { "dpfw", ICLASS_xt_iclass_dpf, 0, Opcode_dpfw_encode_fns, 0, 0 }, { "dpfro", ICLASS_xt_iclass_dpf, 0, Opcode_dpfro_encode_fns, 0, 0 }, { "dpfwo", ICLASS_xt_iclass_dpf, 0, Opcode_dpfwo_encode_fns, 0, 0 }, { "dpfl", ICLASS_xt_iclass_dcache_lock, 0, Opcode_dpfl_encode_fns, 0, 0 }, { "dhu", ICLASS_xt_iclass_dcache_lock, 0, Opcode_dhu_encode_fns, 0, 0 }, { "diu", ICLASS_xt_iclass_dcache_lock, 0, Opcode_diu_encode_fns, 0, 0 }, { "sdct", ICLASS_xt_iclass_sdct, 0, Opcode_sdct_encode_fns, 0, 0 }, { "ldct", ICLASS_xt_iclass_ldct, 0, Opcode_ldct_encode_fns, 0, 0 }, { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, 0, Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, 0, Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, 0, Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, 0, Opcode_rsr_rasid_encode_fns, 0, 0 }, { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, 0, Opcode_wsr_rasid_encode_fns, 0, 0 }, { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, 0, Opcode_xsr_rasid_encode_fns, 0, 0 }, { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, 0, Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, 0, Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, 0, Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, 0, Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, 0, Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, 0, Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, { "idtlb", ICLASS_xt_iclass_idtlb, 0, Opcode_idtlb_encode_fns, 0, 0 }, { "pdtlb", ICLASS_xt_iclass_rdtlb, 0, Opcode_pdtlb_encode_fns, 0, 0 }, { "rdtlb0", ICLASS_xt_iclass_rdtlb, 0, Opcode_rdtlb0_encode_fns, 0, 0 }, { "rdtlb1", ICLASS_xt_iclass_rdtlb, 0, Opcode_rdtlb1_encode_fns, 0, 0 }, { "wdtlb", ICLASS_xt_iclass_wdtlb, 0, Opcode_wdtlb_encode_fns, 0, 0 }, { "iitlb", ICLASS_xt_iclass_iitlb, 0, Opcode_iitlb_encode_fns, 0, 0 }, { "pitlb", ICLASS_xt_iclass_ritlb, 0, Opcode_pitlb_encode_fns, 0, 0 }, { "ritlb0", ICLASS_xt_iclass_ritlb, 0, Opcode_ritlb0_encode_fns, 0, 0 }, { "ritlb1", ICLASS_xt_iclass_ritlb, 0, Opcode_ritlb1_encode_fns, 0, 0 }, { "witlb", ICLASS_xt_iclass_witlb, 0, Opcode_witlb_encode_fns, 0, 0 }, { "ldpte", ICLASS_xt_iclass_ldpte, 0, Opcode_ldpte_encode_fns, 0, 0 }, { "hwwitlba", ICLASS_xt_iclass_hwwitlba, XTENSA_OPCODE_IS_BRANCH, Opcode_hwwitlba_encode_fns, 0, 0 }, { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, 0, Opcode_hwwdtlba_encode_fns, 0, 0 }, { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, 0, Opcode_rsr_cpenable_encode_fns, 0, 0 }, { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, 0, Opcode_wsr_cpenable_encode_fns, 0, 0 }, { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, 0, Opcode_xsr_cpenable_encode_fns, 0, 0 }, { "clamps", ICLASS_xt_iclass_clamp, 0, Opcode_clamps_encode_fns, 0, 0 }, { "min", ICLASS_xt_iclass_minmax, 0, Opcode_min_encode_fns, 0, 0 }, { "max", ICLASS_xt_iclass_minmax, 0, Opcode_max_encode_fns, 0, 0 }, { "minu", ICLASS_xt_iclass_minmax, 0, Opcode_minu_encode_fns, 0, 0 }, { "maxu", ICLASS_xt_iclass_minmax, 0, Opcode_maxu_encode_fns, 0, 0 }, { "nsa", ICLASS_xt_iclass_nsa, 0, Opcode_nsa_encode_fns, 0, 0 }, { "nsau", ICLASS_xt_iclass_nsa, 0, Opcode_nsau_encode_fns, 0, 0 }, { "sext", ICLASS_xt_iclass_sx, 0, Opcode_sext_encode_fns, 0, 0 }, { "l32ai", ICLASS_xt_iclass_l32ai, 0, Opcode_l32ai_encode_fns, 0, 0 }, { "s32ri", ICLASS_xt_iclass_s32ri, 0, Opcode_s32ri_encode_fns, 0, 0 }, { "s32c1i", ICLASS_xt_iclass_s32c1i, 0, Opcode_s32c1i_encode_fns, 0, 0 }, { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, 0, Opcode_rsr_scompare1_encode_fns, 0, 0 }, { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, 0, Opcode_wsr_scompare1_encode_fns, 0, 0 }, { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, 0, Opcode_xsr_scompare1_encode_fns, 0, 0 }, { "quou", ICLASS_xt_iclass_div, 0, Opcode_quou_encode_fns, 0, 0 }, { "quos", ICLASS_xt_iclass_div, 0, Opcode_quos_encode_fns, 0, 0 }, { "remu", ICLASS_xt_iclass_div, 0, Opcode_remu_encode_fns, 0, 0 }, { "rems", ICLASS_xt_iclass_div, 0, Opcode_rems_encode_fns, 0, 0 }, { "mull", ICLASS_xt_mul32, 0, Opcode_mull_encode_fns, 0, 0 } }; enum xtensa_opcode_id { OPCODE_EXCW, OPCODE_RFE, OPCODE_RFDE, OPCODE_SYSCALL, OPCODE_SIMCALL, OPCODE_CALL12, OPCODE_CALL8, OPCODE_CALL4, OPCODE_CALLX12, OPCODE_CALLX8, OPCODE_CALLX4, OPCODE_ENTRY, OPCODE_MOVSP, OPCODE_ROTW, OPCODE_RETW, OPCODE_RETW_N, OPCODE_RFWO, OPCODE_RFWU, OPCODE_L32E, OPCODE_S32E, OPCODE_RSR_WINDOWBASE, OPCODE_WSR_WINDOWBASE, OPCODE_XSR_WINDOWBASE, OPCODE_RSR_WINDOWSTART, OPCODE_WSR_WINDOWSTART, OPCODE_XSR_WINDOWSTART, OPCODE_ADD_N, OPCODE_ADDI_N, OPCODE_BEQZ_N, OPCODE_BNEZ_N, OPCODE_ILL_N, OPCODE_L32I_N, OPCODE_MOV_N, OPCODE_MOVI_N, OPCODE_NOP_N, OPCODE_RET_N, OPCODE_S32I_N, OPCODE_RUR_THREADPTR, OPCODE_WUR_THREADPTR, OPCODE_ADDI, OPCODE_ADDMI, OPCODE_ADD, OPCODE_SUB, OPCODE_ADDX2, OPCODE_ADDX4, OPCODE_ADDX8, OPCODE_SUBX2, OPCODE_SUBX4, OPCODE_SUBX8, OPCODE_AND, OPCODE_OR, OPCODE_XOR, OPCODE_BEQI, OPCODE_BNEI, OPCODE_BGEI, OPCODE_BLTI, OPCODE_BBCI, OPCODE_BBSI, OPCODE_BGEUI, OPCODE_BLTUI, OPCODE_BEQ, OPCODE_BNE, OPCODE_BGE, OPCODE_BLT, OPCODE_BGEU, OPCODE_BLTU, OPCODE_BANY, OPCODE_BNONE, OPCODE_BALL, OPCODE_BNALL, OPCODE_BBC, OPCODE_BBS, OPCODE_BEQZ, OPCODE_BNEZ, OPCODE_BGEZ, OPCODE_BLTZ, OPCODE_CALL0, OPCODE_CALLX0, OPCODE_EXTUI, OPCODE_ILL, OPCODE_J, OPCODE_JX, OPCODE_L16UI, OPCODE_L16SI, OPCODE_L32I, OPCODE_L32R, OPCODE_L8UI, OPCODE_LOOP, OPCODE_LOOPNEZ, OPCODE_LOOPGTZ, OPCODE_MOVI, OPCODE_MOVEQZ, OPCODE_MOVNEZ, OPCODE_MOVLTZ, OPCODE_MOVGEZ, OPCODE_NEG, OPCODE_ABS, OPCODE_NOP, OPCODE_RET, OPCODE_S16I, OPCODE_S32I, OPCODE_S8I, OPCODE_SSR, OPCODE_SSL, OPCODE_SSA8L, OPCODE_SSA8B, OPCODE_SSAI, OPCODE_SLL, OPCODE_SRC, OPCODE_SRL, OPCODE_SRA, OPCODE_SLLI, OPCODE_SRAI, OPCODE_SRLI, OPCODE_MEMW, OPCODE_EXTW, OPCODE_ISYNC, OPCODE_RSYNC, OPCODE_ESYNC, OPCODE_DSYNC, OPCODE_RSIL, OPCODE_RSR_LEND, OPCODE_WSR_LEND, OPCODE_XSR_LEND, OPCODE_RSR_LCOUNT, OPCODE_WSR_LCOUNT, OPCODE_XSR_LCOUNT, OPCODE_RSR_LBEG, OPCODE_WSR_LBEG, OPCODE_XSR_LBEG, OPCODE_RSR_SAR, OPCODE_WSR_SAR, OPCODE_XSR_SAR, OPCODE_RSR_LITBASE, OPCODE_WSR_LITBASE, OPCODE_XSR_LITBASE, OPCODE_RSR_176, OPCODE_WSR_176, OPCODE_RSR_208, OPCODE_RSR_PS, OPCODE_WSR_PS, OPCODE_XSR_PS, OPCODE_RSR_EPC1, OPCODE_WSR_EPC1, OPCODE_XSR_EPC1, OPCODE_RSR_EXCSAVE1, OPCODE_WSR_EXCSAVE1, OPCODE_XSR_EXCSAVE1, OPCODE_RSR_EPC2, OPCODE_WSR_EPC2, OPCODE_XSR_EPC2, OPCODE_RSR_EXCSAVE2, OPCODE_WSR_EXCSAVE2, OPCODE_XSR_EXCSAVE2, OPCODE_RSR_EPC3, OPCODE_WSR_EPC3, OPCODE_XSR_EPC3, OPCODE_RSR_EXCSAVE3, OPCODE_WSR_EXCSAVE3, OPCODE_XSR_EXCSAVE3, OPCODE_RSR_EPC4, OPCODE_WSR_EPC4, OPCODE_XSR_EPC4, OPCODE_RSR_EXCSAVE4, OPCODE_WSR_EXCSAVE4, OPCODE_XSR_EXCSAVE4, OPCODE_RSR_EPC5, OPCODE_WSR_EPC5, OPCODE_XSR_EPC5, OPCODE_RSR_EXCSAVE5, OPCODE_WSR_EXCSAVE5, OPCODE_XSR_EXCSAVE5, OPCODE_RSR_EPC6, OPCODE_WSR_EPC6, OPCODE_XSR_EPC6, OPCODE_RSR_EXCSAVE6, OPCODE_WSR_EXCSAVE6, OPCODE_XSR_EXCSAVE6, OPCODE_RSR_EPC7, OPCODE_WSR_EPC7, OPCODE_XSR_EPC7, OPCODE_RSR_EXCSAVE7, OPCODE_WSR_EXCSAVE7, OPCODE_XSR_EXCSAVE7, OPCODE_RSR_EPS2, OPCODE_WSR_EPS2, OPCODE_XSR_EPS2, OPCODE_RSR_EPS3, OPCODE_WSR_EPS3, OPCODE_XSR_EPS3, OPCODE_RSR_EPS4, OPCODE_WSR_EPS4, OPCODE_XSR_EPS4, OPCODE_RSR_EPS5, OPCODE_WSR_EPS5, OPCODE_XSR_EPS5, OPCODE_RSR_EPS6, OPCODE_WSR_EPS6, OPCODE_XSR_EPS6, OPCODE_RSR_EPS7, OPCODE_WSR_EPS7, OPCODE_XSR_EPS7, OPCODE_RSR_EXCVADDR, OPCODE_WSR_EXCVADDR, OPCODE_XSR_EXCVADDR, OPCODE_RSR_DEPC, OPCODE_WSR_DEPC, OPCODE_XSR_DEPC, OPCODE_RSR_EXCCAUSE, OPCODE_WSR_EXCCAUSE, OPCODE_XSR_EXCCAUSE, OPCODE_RSR_MISC0, OPCODE_WSR_MISC0, OPCODE_XSR_MISC0, OPCODE_RSR_MISC1, OPCODE_WSR_MISC1, OPCODE_XSR_MISC1, OPCODE_RSR_PRID, OPCODE_RSR_VECBASE, OPCODE_WSR_VECBASE, OPCODE_XSR_VECBASE, OPCODE_MUL16U, OPCODE_MUL16S, OPCODE_RFI, OPCODE_WAITI, OPCODE_RSR_INTERRUPT, OPCODE_WSR_INTSET, OPCODE_WSR_INTCLEAR, OPCODE_RSR_INTENABLE, OPCODE_WSR_INTENABLE, OPCODE_XSR_INTENABLE, OPCODE_BREAK, OPCODE_BREAK_N, OPCODE_RSR_DBREAKA0, OPCODE_WSR_DBREAKA0, OPCODE_XSR_DBREAKA0, OPCODE_RSR_DBREAKC0, OPCODE_WSR_DBREAKC0, OPCODE_XSR_DBREAKC0, OPCODE_RSR_DBREAKA1, OPCODE_WSR_DBREAKA1, OPCODE_XSR_DBREAKA1, OPCODE_RSR_DBREAKC1, OPCODE_WSR_DBREAKC1, OPCODE_XSR_DBREAKC1, OPCODE_RSR_IBREAKA0, OPCODE_WSR_IBREAKA0, OPCODE_XSR_IBREAKA0, OPCODE_RSR_IBREAKA1, OPCODE_WSR_IBREAKA1, OPCODE_XSR_IBREAKA1, OPCODE_RSR_IBREAKENABLE, OPCODE_WSR_IBREAKENABLE, OPCODE_XSR_IBREAKENABLE, OPCODE_RSR_DEBUGCAUSE, OPCODE_WSR_DEBUGCAUSE, OPCODE_XSR_DEBUGCAUSE, OPCODE_RSR_ICOUNT, OPCODE_WSR_ICOUNT, OPCODE_XSR_ICOUNT, OPCODE_RSR_ICOUNTLEVEL, OPCODE_WSR_ICOUNTLEVEL, OPCODE_XSR_ICOUNTLEVEL, OPCODE_RSR_DDR, OPCODE_WSR_DDR, OPCODE_XSR_DDR, OPCODE_RFDO, OPCODE_RFDD, OPCODE_WSR_MMID, OPCODE_RSR_CCOUNT, OPCODE_WSR_CCOUNT, OPCODE_XSR_CCOUNT, OPCODE_RSR_CCOMPARE0, OPCODE_WSR_CCOMPARE0, OPCODE_XSR_CCOMPARE0, OPCODE_RSR_CCOMPARE1, OPCODE_WSR_CCOMPARE1, OPCODE_XSR_CCOMPARE1, OPCODE_RSR_CCOMPARE2, OPCODE_WSR_CCOMPARE2, OPCODE_XSR_CCOMPARE2, OPCODE_IPF, OPCODE_IHI, OPCODE_IPFL, OPCODE_IHU, OPCODE_IIU, OPCODE_III, OPCODE_LICT, OPCODE_LICW, OPCODE_SICT, OPCODE_SICW, OPCODE_DHWB, OPCODE_DHWBI, OPCODE_DIWB, OPCODE_DIWBI, OPCODE_DHI, OPCODE_DII, OPCODE_DPFR, OPCODE_DPFW, OPCODE_DPFRO, OPCODE_DPFWO, OPCODE_DPFL, OPCODE_DHU, OPCODE_DIU, OPCODE_SDCT, OPCODE_LDCT, OPCODE_WSR_PTEVADDR, OPCODE_RSR_PTEVADDR, OPCODE_XSR_PTEVADDR, OPCODE_RSR_RASID, OPCODE_WSR_RASID, OPCODE_XSR_RASID, OPCODE_RSR_ITLBCFG, OPCODE_WSR_ITLBCFG, OPCODE_XSR_ITLBCFG, OPCODE_RSR_DTLBCFG, OPCODE_WSR_DTLBCFG, OPCODE_XSR_DTLBCFG, OPCODE_IDTLB, OPCODE_PDTLB, OPCODE_RDTLB0, OPCODE_RDTLB1, OPCODE_WDTLB, OPCODE_IITLB, OPCODE_PITLB, OPCODE_RITLB0, OPCODE_RITLB1, OPCODE_WITLB, OPCODE_LDPTE, OPCODE_HWWITLBA, OPCODE_HWWDTLBA, OPCODE_RSR_CPENABLE, OPCODE_WSR_CPENABLE, OPCODE_XSR_CPENABLE, OPCODE_CLAMPS, OPCODE_MIN, OPCODE_MAX, OPCODE_MINU, OPCODE_MAXU, OPCODE_NSA, OPCODE_NSAU, OPCODE_SEXT, OPCODE_L32AI, OPCODE_S32RI, OPCODE_S32C1I, OPCODE_RSR_SCOMPARE1, OPCODE_WSR_SCOMPARE1, OPCODE_XSR_SCOMPARE1, OPCODE_QUOU, OPCODE_QUOS, OPCODE_REMU, OPCODE_REMS, OPCODE_MULL }; /* Slot-specific opcode decode functions. */ static int Slot_inst_decode (const xtensa_insnbuf insn) { switch (Field_op0_Slot_inst_get (insn)) { case 0: switch (Field_op1_Slot_inst_get (insn)) { case 0: switch (Field_op2_Slot_inst_get (insn)) { case 0: switch (Field_r_Slot_inst_get (insn)) { case 0: switch (Field_m_Slot_inst_get (insn)) { case 0: if (Field_s_Slot_inst_get (insn) == 0 && Field_n_Slot_inst_get (insn) == 0) return OPCODE_ILL; break; case 2: switch (Field_n_Slot_inst_get (insn)) { case 0: return OPCODE_RET; case 1: return OPCODE_RETW; case 2: return OPCODE_JX; } break; case 3: switch (Field_n_Slot_inst_get (insn)) { case 0: return OPCODE_CALLX0; case 1: return OPCODE_CALLX4; case 2: return OPCODE_CALLX8; case 3: return OPCODE_CALLX12; } break; } break; case 1: return OPCODE_MOVSP; case 2: if (Field_s_Slot_inst_get (insn) == 0) { switch (Field_t_Slot_inst_get (insn)) { case 0: return OPCODE_ISYNC; case 1: return OPCODE_RSYNC; case 2: return OPCODE_ESYNC; case 3: return OPCODE_DSYNC; case 8: return OPCODE_EXCW; case 12: return OPCODE_MEMW; case 13: return OPCODE_EXTW; case 15: return OPCODE_NOP; } } break; case 3: switch (Field_t_Slot_inst_get (insn)) { case 0: switch (Field_s_Slot_inst_get (insn)) { case 0: return OPCODE_RFE; case 2: return OPCODE_RFDE; case 4: return OPCODE_RFWO; case 5: return OPCODE_RFWU; } break; case 1: return OPCODE_RFI; } break; case 4: return OPCODE_BREAK; case 5: switch (Field_s_Slot_inst_get (insn)) { case 0: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_SYSCALL; break; case 1: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_SIMCALL; break; } break; case 6: return OPCODE_RSIL; case 7: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_WAITI; break; } break; case 1: return OPCODE_AND; case 2: return OPCODE_OR; case 3: return OPCODE_XOR; case 4: switch (Field_r_Slot_inst_get (insn)) { case 0: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_SSR; break; case 1: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_SSL; break; case 2: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_SSA8L; break; case 3: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_SSA8B; break; case 4: if (Field_thi3_Slot_inst_get (insn) == 0) return OPCODE_SSAI; break; case 8: if (Field_s_Slot_inst_get (insn) == 0) return OPCODE_ROTW; break; case 14: return OPCODE_NSA; case 15: return OPCODE_NSAU; } break; case 5: switch (Field_r_Slot_inst_get (insn)) { case 1: return OPCODE_HWWITLBA; case 3: return OPCODE_RITLB0; case 4: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_IITLB; break; case 5: return OPCODE_PITLB; case 6: return OPCODE_WITLB; case 7: return OPCODE_RITLB1; case 9: return OPCODE_HWWDTLBA; case 11: return OPCODE_RDTLB0; case 12: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_IDTLB; break; case 13: return OPCODE_PDTLB; case 14: return OPCODE_WDTLB; case 15: return OPCODE_RDTLB1; } break; case 6: switch (Field_s_Slot_inst_get (insn)) { case 0: return OPCODE_NEG; case 1: return OPCODE_ABS; } break; case 8: return OPCODE_ADD; case 9: return OPCODE_ADDX2; case 10: return OPCODE_ADDX4; case 11: return OPCODE_ADDX8; case 12: return OPCODE_SUB; case 13: return OPCODE_SUBX2; case 14: return OPCODE_SUBX4; case 15: return OPCODE_SUBX8; } break; case 1: switch (Field_op2_Slot_inst_get (insn)) { case 0: case 1: return OPCODE_SLLI; case 2: case 3: return OPCODE_SRAI; case 4: return OPCODE_SRLI; case 6: switch (Field_sr_Slot_inst_get (insn)) { case 0: return OPCODE_XSR_LBEG; case 1: return OPCODE_XSR_LEND; case 2: return OPCODE_XSR_LCOUNT; case 3: return OPCODE_XSR_SAR; case 5: return OPCODE_XSR_LITBASE; case 12: return OPCODE_XSR_SCOMPARE1; case 72: return OPCODE_XSR_WINDOWBASE; case 73: return OPCODE_XSR_WINDOWSTART; case 83: return OPCODE_XSR_PTEVADDR; case 90: return OPCODE_XSR_RASID; case 91: return OPCODE_XSR_ITLBCFG; case 92: return OPCODE_XSR_DTLBCFG; case 96: return OPCODE_XSR_IBREAKENABLE; case 104: return OPCODE_XSR_DDR; case 128: return OPCODE_XSR_IBREAKA0; case 129: return OPCODE_XSR_IBREAKA1; case 144: return OPCODE_XSR_DBREAKA0; case 145: return OPCODE_XSR_DBREAKA1; case 160: return OPCODE_XSR_DBREAKC0; case 161: return OPCODE_XSR_DBREAKC1; case 177: return OPCODE_XSR_EPC1; case 178: return OPCODE_XSR_EPC2; case 179: return OPCODE_XSR_EPC3; case 180: return OPCODE_XSR_EPC4; case 181: return OPCODE_XSR_EPC5; case 182: return OPCODE_XSR_EPC6; case 183: return OPCODE_XSR_EPC7; case 192: return OPCODE_XSR_DEPC; case 194: return OPCODE_XSR_EPS2; case 195: return OPCODE_XSR_EPS3; case 196: return OPCODE_XSR_EPS4; case 197: return OPCODE_XSR_EPS5; case 198: return OPCODE_XSR_EPS6; case 199: return OPCODE_XSR_EPS7; case 209: return OPCODE_XSR_EXCSAVE1; case 210: return OPCODE_XSR_EXCSAVE2; case 211: return OPCODE_XSR_EXCSAVE3; case 212: return OPCODE_XSR_EXCSAVE4; case 213: return OPCODE_XSR_EXCSAVE5; case 214: return OPCODE_XSR_EXCSAVE6; case 215: return OPCODE_XSR_EXCSAVE7; case 224: return OPCODE_XSR_CPENABLE; case 228: return OPCODE_XSR_INTENABLE; case 230: return OPCODE_XSR_PS; case 231: return OPCODE_XSR_VECBASE; case 232: return OPCODE_XSR_EXCCAUSE; case 233: return OPCODE_XSR_DEBUGCAUSE; case 234: return OPCODE_XSR_CCOUNT; case 236: return OPCODE_XSR_ICOUNT; case 237: return OPCODE_XSR_ICOUNTLEVEL; case 238: return OPCODE_XSR_EXCVADDR; case 240: return OPCODE_XSR_CCOMPARE0; case 241: return OPCODE_XSR_CCOMPARE1; case 242: return OPCODE_XSR_CCOMPARE2; case 244: return OPCODE_XSR_MISC0; case 245: return OPCODE_XSR_MISC1; } break; case 8: return OPCODE_SRC; case 9: if (Field_s_Slot_inst_get (insn) == 0) return OPCODE_SRL; break; case 10: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_SLL; break; case 11: if (Field_s_Slot_inst_get (insn) == 0) return OPCODE_SRA; break; case 12: return OPCODE_MUL16U; case 13: return OPCODE_MUL16S; case 15: switch (Field_r_Slot_inst_get (insn)) { case 0: return OPCODE_LICT; case 1: return OPCODE_SICT; case 2: return OPCODE_LICW; case 3: return OPCODE_SICW; case 8: return OPCODE_LDCT; case 9: return OPCODE_SDCT; case 14: if (Field_t_Slot_inst_get (insn) == 0) return OPCODE_RFDO; if (Field_t_Slot_inst_get (insn) == 1) return OPCODE_RFDD; break; case 15: return OPCODE_LDPTE; } break; } break; case 2: switch (Field_op2_Slot_inst_get (insn)) { case 8: return OPCODE_MULL; case 12: return OPCODE_QUOU; case 13: return OPCODE_QUOS; case 14: return OPCODE_REMU; case 15: return OPCODE_REMS; } break; case 3: switch (Field_op2_Slot_inst_get (insn)) { case 0: switch (Field_sr_Slot_inst_get (insn)) { case 0: return OPCODE_RSR_LBEG; case 1: return OPCODE_RSR_LEND; case 2: return OPCODE_RSR_LCOUNT; case 3: return OPCODE_RSR_SAR; case 5: return OPCODE_RSR_LITBASE; case 12: return OPCODE_RSR_SCOMPARE1; case 72: return OPCODE_RSR_WINDOWBASE; case 73: return OPCODE_RSR_WINDOWSTART; case 83: return OPCODE_RSR_PTEVADDR; case 90: return OPCODE_RSR_RASID; case 91: return OPCODE_RSR_ITLBCFG; case 92: return OPCODE_RSR_DTLBCFG; case 96: return OPCODE_RSR_IBREAKENABLE; case 104: return OPCODE_RSR_DDR; case 128: return OPCODE_RSR_IBREAKA0; case 129: return OPCODE_RSR_IBREAKA1; case 144: return OPCODE_RSR_DBREAKA0; case 145: return OPCODE_RSR_DBREAKA1; case 160: return OPCODE_RSR_DBREAKC0; case 161: return OPCODE_RSR_DBREAKC1; case 176: return OPCODE_RSR_176; case 177: return OPCODE_RSR_EPC1; case 178: return OPCODE_RSR_EPC2; case 179: return OPCODE_RSR_EPC3; case 180: return OPCODE_RSR_EPC4; case 181: return OPCODE_RSR_EPC5; case 182: return OPCODE_RSR_EPC6; case 183: return OPCODE_RSR_EPC7; case 192: return OPCODE_RSR_DEPC; case 194: return OPCODE_RSR_EPS2; case 195: return OPCODE_RSR_EPS3; case 196: return OPCODE_RSR_EPS4; case 197: return OPCODE_RSR_EPS5; case 198: return OPCODE_RSR_EPS6; case 199: return OPCODE_RSR_EPS7; case 208: return OPCODE_RSR_208; case 209: return OPCODE_RSR_EXCSAVE1; case 210: return OPCODE_RSR_EXCSAVE2; case 211: return OPCODE_RSR_EXCSAVE3; case 212: return OPCODE_RSR_EXCSAVE4; case 213: return OPCODE_RSR_EXCSAVE5; case 214: return OPCODE_RSR_EXCSAVE6; case 215: return OPCODE_RSR_EXCSAVE7; case 224: return OPCODE_RSR_CPENABLE; case 226: return OPCODE_RSR_INTERRUPT; case 228: return OPCODE_RSR_INTENABLE; case 230: return OPCODE_RSR_PS; case 231: return OPCODE_RSR_VECBASE; case 232: return OPCODE_RSR_EXCCAUSE; case 233: return OPCODE_RSR_DEBUGCAUSE; case 234: return OPCODE_RSR_CCOUNT; case 235: return OPCODE_RSR_PRID; case 236: return OPCODE_RSR_ICOUNT; case 237: return OPCODE_RSR_ICOUNTLEVEL; case 238: return OPCODE_RSR_EXCVADDR; case 240: return OPCODE_RSR_CCOMPARE0; case 241: return OPCODE_RSR_CCOMPARE1; case 242: return OPCODE_RSR_CCOMPARE2; case 244: return OPCODE_RSR_MISC0; case 245: return OPCODE_RSR_MISC1; } break; case 1: switch (Field_sr_Slot_inst_get (insn)) { case 0: return OPCODE_WSR_LBEG; case 1: return OPCODE_WSR_LEND; case 2: return OPCODE_WSR_LCOUNT; case 3: return OPCODE_WSR_SAR; case 5: return OPCODE_WSR_LITBASE; case 12: return OPCODE_WSR_SCOMPARE1; case 72: return OPCODE_WSR_WINDOWBASE; case 73: return OPCODE_WSR_WINDOWSTART; case 83: return OPCODE_WSR_PTEVADDR; case 89: return OPCODE_WSR_MMID; case 90: return OPCODE_WSR_RASID; case 91: return OPCODE_WSR_ITLBCFG; case 92: return OPCODE_WSR_DTLBCFG; case 96: return OPCODE_WSR_IBREAKENABLE; case 104: return OPCODE_WSR_DDR; case 128: return OPCODE_WSR_IBREAKA0; case 129: return OPCODE_WSR_IBREAKA1; case 144: return OPCODE_WSR_DBREAKA0; case 145: return OPCODE_WSR_DBREAKA1; case 160: return OPCODE_WSR_DBREAKC0; case 161: return OPCODE_WSR_DBREAKC1; case 176: return OPCODE_WSR_176; case 177: return OPCODE_WSR_EPC1; case 178: return OPCODE_WSR_EPC2; case 179: return OPCODE_WSR_EPC3; case 180: return OPCODE_WSR_EPC4; case 181: return OPCODE_WSR_EPC5; case 182: return OPCODE_WSR_EPC6; case 183: return OPCODE_WSR_EPC7; case 192: return OPCODE_WSR_DEPC; case 194: return OPCODE_WSR_EPS2; case 195: return OPCODE_WSR_EPS3; case 196: return OPCODE_WSR_EPS4; case 197: return OPCODE_WSR_EPS5; case 198: return OPCODE_WSR_EPS6; case 199: return OPCODE_WSR_EPS7; case 209: return OPCODE_WSR_EXCSAVE1; case 210: return OPCODE_WSR_EXCSAVE2; case 211: return OPCODE_WSR_EXCSAVE3; case 212: return OPCODE_WSR_EXCSAVE4; case 213: return OPCODE_WSR_EXCSAVE5; case 214: return OPCODE_WSR_EXCSAVE6; case 215: return OPCODE_WSR_EXCSAVE7; case 224: return OPCODE_WSR_CPENABLE; case 226: return OPCODE_WSR_INTSET; case 227: return OPCODE_WSR_INTCLEAR; case 228: return OPCODE_WSR_INTENABLE; case 230: return OPCODE_WSR_PS; case 231: return OPCODE_WSR_VECBASE; case 232: return OPCODE_WSR_EXCCAUSE; case 233: return OPCODE_WSR_DEBUGCAUSE; case 234: return OPCODE_WSR_CCOUNT; case 236: return OPCODE_WSR_ICOUNT; case 237: return OPCODE_WSR_ICOUNTLEVEL; case 238: return OPCODE_WSR_EXCVADDR; case 240: return OPCODE_WSR_CCOMPARE0; case 241: return OPCODE_WSR_CCOMPARE1; case 242: return OPCODE_WSR_CCOMPARE2; case 244: return OPCODE_WSR_MISC0; case 245: return OPCODE_WSR_MISC1; } break; case 2: return OPCODE_SEXT; case 3: return OPCODE_CLAMPS; case 4: return OPCODE_MIN; case 5: return OPCODE_MAX; case 6: return OPCODE_MINU; case 7: return OPCODE_MAXU; case 8: return OPCODE_MOVEQZ; case 9: return OPCODE_MOVNEZ; case 10: return OPCODE_MOVLTZ; case 11: return OPCODE_MOVGEZ; case 14: if (Field_st_Slot_inst_get (insn) == 231) return OPCODE_RUR_THREADPTR; break; case 15: if (Field_sr_Slot_inst_get (insn) == 231) return OPCODE_WUR_THREADPTR; break; } break; case 4: case 5: return OPCODE_EXTUI; case 9: switch (Field_op2_Slot_inst_get (insn)) { case 0: return OPCODE_L32E; case 4: return OPCODE_S32E; } break; } break; case 1: return OPCODE_L32R; case 2: switch (Field_r_Slot_inst_get (insn)) { case 0: return OPCODE_L8UI; case 1: return OPCODE_L16UI; case 2: return OPCODE_L32I; case 4: return OPCODE_S8I; case 5: return OPCODE_S16I; case 6: return OPCODE_S32I; case 7: switch (Field_t_Slot_inst_get (insn)) { case 0: return OPCODE_DPFR; case 1: return OPCODE_DPFW; case 2: return OPCODE_DPFRO; case 3: return OPCODE_DPFWO; case 4: return OPCODE_DHWB; case 5: return OPCODE_DHWBI; case 6: return OPCODE_DHI; case 7: return OPCODE_DII; case 8: switch (Field_op1_Slot_inst_get (insn)) { case 0: return OPCODE_DPFL; case 2: return OPCODE_DHU; case 3: return OPCODE_DIU; case 4: return OPCODE_DIWB; case 5: return OPCODE_DIWBI; } break; case 12: return OPCODE_IPF; case 13: switch (Field_op1_Slot_inst_get (insn)) { case 0: return OPCODE_IPFL; case 2: return OPCODE_IHU; case 3: return OPCODE_IIU; } break; case 14: return OPCODE_IHI; case 15: return OPCODE_III; } break; case 9: return OPCODE_L16SI; case 10: return OPCODE_MOVI; case 11: return OPCODE_L32AI; case 12: return OPCODE_ADDI; case 13: return OPCODE_ADDMI; case 14: return OPCODE_S32C1I; case 15: return OPCODE_S32RI; } break; case 5: switch (Field_n_Slot_inst_get (insn)) { case 0: return OPCODE_CALL0; case 1: return OPCODE_CALL4; case 2: return OPCODE_CALL8; case 3: return OPCODE_CALL12; } break; case 6: switch (Field_n_Slot_inst_get (insn)) { case 0: return OPCODE_J; case 1: switch (Field_m_Slot_inst_get (insn)) { case 0: return OPCODE_BEQZ; case 1: return OPCODE_BNEZ; case 2: return OPCODE_BLTZ; case 3: return OPCODE_BGEZ; } break; case 2: switch (Field_m_Slot_inst_get (insn)) { case 0: return OPCODE_BEQI; case 1: return OPCODE_BNEI; case 2: return OPCODE_BLTI; case 3: return OPCODE_BGEI; } break; case 3: switch (Field_m_Slot_inst_get (insn)) { case 0: return OPCODE_ENTRY; case 1: switch (Field_r_Slot_inst_get (insn)) { case 8: return OPCODE_LOOP; case 9: return OPCODE_LOOPNEZ; case 10: return OPCODE_LOOPGTZ; } break; case 2: return OPCODE_BLTUI; case 3: return OPCODE_BGEUI; } break; } break; case 7: switch (Field_r_Slot_inst_get (insn)) { case 0: return OPCODE_BNONE; case 1: return OPCODE_BEQ; case 2: return OPCODE_BLT; case 3: return OPCODE_BLTU; case 4: return OPCODE_BALL; case 5: return OPCODE_BBC; case 6: case 7: return OPCODE_BBCI; case 8: return OPCODE_BANY; case 9: return OPCODE_BNE; case 10: return OPCODE_BGE; case 11: return OPCODE_BGEU; case 12: return OPCODE_BNALL; case 13: return OPCODE_BBS; case 14: case 15: return OPCODE_BBSI; } break; } return 0; } static int Slot_inst16b_decode (const xtensa_insnbuf insn) { switch (Field_op0_Slot_inst16b_get (insn)) { case 12: switch (Field_i_Slot_inst16b_get (insn)) { case 0: return OPCODE_MOVI_N; case 1: switch (Field_z_Slot_inst16b_get (insn)) { case 0: return OPCODE_BEQZ_N; case 1: return OPCODE_BNEZ_N; } break; } break; case 13: switch (Field_r_Slot_inst16b_get (insn)) { case 0: return OPCODE_MOV_N; case 15: switch (Field_t_Slot_inst16b_get (insn)) { case 0: return OPCODE_RET_N; case 1: return OPCODE_RETW_N; case 2: return OPCODE_BREAK_N; case 3: if (Field_s_Slot_inst16b_get (insn) == 0) return OPCODE_NOP_N; break; case 6: if (Field_s_Slot_inst16b_get (insn) == 0) return OPCODE_ILL_N; break; } break; } break; } return 0; } static int Slot_inst16a_decode (const xtensa_insnbuf insn) { switch (Field_op0_Slot_inst16a_get (insn)) { case 8: return OPCODE_L32I_N; case 9: return OPCODE_S32I_N; case 10: return OPCODE_ADD_N; case 11: return OPCODE_ADDI_N; } return 0; } /* Instruction slots. */ static void Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) { slotbuf[0] = (insn[0] & 0xffffff); } static void Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) { insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); } static void Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) { slotbuf[0] = ((insn[0] & 0xffff00) >> 8); } static void Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) { insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); } static void Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) { slotbuf[0] = ((insn[0] & 0xffff00) >> 8); } static void Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) { insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); } static xtensa_get_field_fn Slot_inst_get_field_fns[] = { Field_t_Slot_inst_get, Field_bbi4_Slot_inst_get, Field_bbi_Slot_inst_get, Field_imm12_Slot_inst_get, Field_imm8_Slot_inst_get, Field_s_Slot_inst_get, Field_imm12b_Slot_inst_get, Field_imm16_Slot_inst_get, Field_m_Slot_inst_get, Field_n_Slot_inst_get, Field_offset_Slot_inst_get, Field_op0_Slot_inst_get, Field_op1_Slot_inst_get, Field_op2_Slot_inst_get, Field_r_Slot_inst_get, Field_sa4_Slot_inst_get, Field_sae4_Slot_inst_get, Field_sae_Slot_inst_get, Field_sal_Slot_inst_get, Field_sargt_Slot_inst_get, Field_sas4_Slot_inst_get, Field_sas_Slot_inst_get, Field_sr_Slot_inst_get, Field_st_Slot_inst_get, Field_thi3_Slot_inst_get, Field_imm4_Slot_inst_get, Field_mn_Slot_inst_get, 0, 0, 0, 0, 0, 0, 0, 0, Field_xt_wbr15_imm_Slot_inst_get, Field_xt_wbr18_imm_Slot_inst_get, Implicit_Field_ar0_get, Implicit_Field_ar4_get, Implicit_Field_ar8_get, Implicit_Field_ar12_get }; static xtensa_set_field_fn Slot_inst_set_field_fns[] = { Field_t_Slot_inst_set, Field_bbi4_Slot_inst_set, Field_bbi_Slot_inst_set, Field_imm12_Slot_inst_set, Field_imm8_Slot_inst_set, Field_s_Slot_inst_set, Field_imm12b_Slot_inst_set, Field_imm16_Slot_inst_set, Field_m_Slot_inst_set, Field_n_Slot_inst_set, Field_offset_Slot_inst_set, Field_op0_Slot_inst_set, Field_op1_Slot_inst_set, Field_op2_Slot_inst_set, Field_r_Slot_inst_set, Field_sa4_Slot_inst_set, Field_sae4_Slot_inst_set, Field_sae_Slot_inst_set, Field_sal_Slot_inst_set, Field_sargt_Slot_inst_set, Field_sas4_Slot_inst_set, Field_sas_Slot_inst_set, Field_sr_Slot_inst_set, Field_st_Slot_inst_set, Field_thi3_Slot_inst_set, Field_imm4_Slot_inst_set, Field_mn_Slot_inst_set, 0, 0, 0, 0, 0, 0, 0, 0, Field_xt_wbr15_imm_Slot_inst_set, Field_xt_wbr18_imm_Slot_inst_set, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set }; static xtensa_get_field_fn Slot_inst16a_get_field_fns[] = { Field_t_Slot_inst16a_get, 0, 0, 0, 0, Field_s_Slot_inst16a_get, 0, 0, 0, 0, 0, Field_op0_Slot_inst16a_get, 0, 0, Field_r_Slot_inst16a_get, 0, 0, 0, 0, 0, 0, 0, Field_sr_Slot_inst16a_get, Field_st_Slot_inst16a_get, 0, Field_imm4_Slot_inst16a_get, 0, Field_i_Slot_inst16a_get, Field_imm6lo_Slot_inst16a_get, Field_imm6hi_Slot_inst16a_get, Field_imm7lo_Slot_inst16a_get, Field_imm7hi_Slot_inst16a_get, Field_z_Slot_inst16a_get, Field_imm6_Slot_inst16a_get, Field_imm7_Slot_inst16a_get, 0, 0, Implicit_Field_ar0_get, Implicit_Field_ar4_get, Implicit_Field_ar8_get, Implicit_Field_ar12_get }; static xtensa_set_field_fn Slot_inst16a_set_field_fns[] = { Field_t_Slot_inst16a_set, 0, 0, 0, 0, Field_s_Slot_inst16a_set, 0, 0, 0, 0, 0, Field_op0_Slot_inst16a_set, 0, 0, Field_r_Slot_inst16a_set, 0, 0, 0, 0, 0, 0, 0, Field_sr_Slot_inst16a_set, Field_st_Slot_inst16a_set, 0, Field_imm4_Slot_inst16a_set, 0, Field_i_Slot_inst16a_set, Field_imm6lo_Slot_inst16a_set, Field_imm6hi_Slot_inst16a_set, Field_imm7lo_Slot_inst16a_set, Field_imm7hi_Slot_inst16a_set, Field_z_Slot_inst16a_set, Field_imm6_Slot_inst16a_set, Field_imm7_Slot_inst16a_set, 0, 0, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set }; static xtensa_get_field_fn Slot_inst16b_get_field_fns[] = { Field_t_Slot_inst16b_get, 0, 0, 0, 0, Field_s_Slot_inst16b_get, 0, 0, 0, 0, 0, Field_op0_Slot_inst16b_get, 0, 0, Field_r_Slot_inst16b_get, 0, 0, 0, 0, 0, 0, 0, Field_sr_Slot_inst16b_get, Field_st_Slot_inst16b_get, 0, Field_imm4_Slot_inst16b_get, 0, Field_i_Slot_inst16b_get, Field_imm6lo_Slot_inst16b_get, Field_imm6hi_Slot_inst16b_get, Field_imm7lo_Slot_inst16b_get, Field_imm7hi_Slot_inst16b_get, Field_z_Slot_inst16b_get, Field_imm6_Slot_inst16b_get, Field_imm7_Slot_inst16b_get, 0, 0, Implicit_Field_ar0_get, Implicit_Field_ar4_get, Implicit_Field_ar8_get, Implicit_Field_ar12_get }; static xtensa_set_field_fn Slot_inst16b_set_field_fns[] = { Field_t_Slot_inst16b_set, 0, 0, 0, 0, Field_s_Slot_inst16b_set, 0, 0, 0, 0, 0, Field_op0_Slot_inst16b_set, 0, 0, Field_r_Slot_inst16b_set, 0, 0, 0, 0, 0, 0, 0, Field_sr_Slot_inst16b_set, Field_st_Slot_inst16b_set, 0, Field_imm4_Slot_inst16b_set, 0, Field_i_Slot_inst16b_set, Field_imm6lo_Slot_inst16b_set, Field_imm6hi_Slot_inst16b_set, Field_imm7lo_Slot_inst16b_set, Field_imm7hi_Slot_inst16b_set, Field_z_Slot_inst16b_set, Field_imm6_Slot_inst16b_set, Field_imm7_Slot_inst16b_set, 0, 0, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set }; static xtensa_slot_internal slots[] = { { "Inst", "x24", 0, Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, Slot_inst_get_field_fns, Slot_inst_set_field_fns, Slot_inst_decode, "nop" }, { "Inst16a", "x16a", 0, Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, Slot_inst16a_decode, "" }, { "Inst16b", "x16b", 0, Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, Slot_inst16b_decode, "nop.n" } }; /* Instruction formats. */ static void Format_x24_encode (xtensa_insnbuf insn) { insn[0] = 0; } static void Format_x16a_encode (xtensa_insnbuf insn) { insn[0] = 0x800000; } static void Format_x16b_encode (xtensa_insnbuf insn) { insn[0] = 0xc00000; } static int Format_x24_slots[] = { 0 }; static int Format_x16a_slots[] = { 1 }; static int Format_x16b_slots[] = { 2 }; static xtensa_format_internal formats[] = { { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } }; static int format_decoder (const xtensa_insnbuf insn) { if ((insn[0] & 0x800000) == 0) return 0; /* x24 */ if ((insn[0] & 0xc00000) == 0x800000) return 1; /* x16a */ if ((insn[0] & 0xe00000) == 0xc00000) return 2; /* x16b */ return -1; } static int length_table[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, -1, -1 }; static int length_decoder (const unsigned char *insn) { int op0 = (insn[0] >> 4) & 0xf; return length_table[op0]; } /* Top-level ISA structure. */ xtensa_isa_internal xtensa_modules = { 1 /* big-endian */, 3 /* insn_size */, 0, 3, formats, format_decoder, length_decoder, 3, slots, 41 /* num_fields */, 75, operands, 286, iclasses, 353, opcodes, 0, 1, regfiles, NUM_STATES, states, 0, NUM_SYSREGS, sysregs, 0, { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, 0, interfaces, 0, 0, funcUnits, 0 };