From 0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc Mon Sep 17 00:00:00 2001 From: Michael Eager Date: Wed, 21 Nov 2012 17:34:14 +0000 Subject: Add stack high register and stack low register for MicroBlaze hardware assisted stack protection, stores stack low / stack high limits for detecting stack overflow / underflow binutils/opcodes * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK binutils/gas * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR binutils/gas * gas/microblaze/allinsn.s: Test use of SHR, SLR * gas/microblaze/allinsn.d: Likewise --- opcodes/microblaze-opcm.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'opcodes/microblaze-opcm.h') diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index 867263e396..a2a42d0b9d 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -79,6 +79,8 @@ enum microblaze_instr_type #define REG_BTR_MASK 0x800b #define REG_EDR_MASK 0x800d #define REG_PVR_MASK 0xa000 +#define REG_SLR_MASK 0x8800 +#define REG_SHR_MASK 0x8802 #define REG_PID_MASK 0x9000 #define REG_ZPR_MASK 0x9001 @@ -100,6 +102,8 @@ enum microblaze_instr_type #define REG_FSR 39 /* FPU Status reg. */ #define REG_BTR 43 /* Branch Target reg. */ #define REG_EDR 45 /* Exception reg. */ +#define REG_SHR 50 /* Stack High reg. */ +#define REG_SLR 51 /* Stack Low reg. */ #define REG_PVR 40960 /* Program Verification reg. */ #define REG_PID 36864 /* MMU: Process ID reg. */ -- cgit v1.2.1