From 3b16e843f2a75ccf8e7ecc5102e1217a122a05ad Mon Sep 17 00:00:00 2001
From: Nick Clifton <nickc@redhat.com>
Date: Thu, 31 Jan 2002 17:33:08 +0000
Subject: Add support for OpenRISC 32-bit embedded processor

---
 ld/scripttempl/or32.sc | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 ld/scripttempl/or32.sc

(limited to 'ld/scripttempl/or32.sc')

diff --git a/ld/scripttempl/or32.sc b/ld/scripttempl/or32.sc
new file mode 100644
index 0000000000..2825b1e83e
--- /dev/null
+++ b/ld/scripttempl/or32.sc
@@ -0,0 +1,37 @@
+cat <<EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}")
+${LIB_SEARCH_DIRS}
+
+SECTIONS
+{
+  .text : {
+    *(.text)
+    ${RELOCATING+ __etext  =  .};
+    ${CONSTRUCTING+ __CTOR_LIST__ = .;}
+    ${CONSTRUCTING+ LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)}
+    ${CONSTRUCTING+ *(.ctors)}
+    ${CONSTRUCTING+ LONG(0)}
+    ${CONSTRUCTING+ __CTOR_END__ = .;}
+    ${CONSTRUCTING+ __DTOR_LIST__ = .;}
+    ${CONSTRUCTING+ LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)}
+    ${CONSTRUCTING+ *(.dtors)}
+    ${CONSTRUCTING+ LONG(0)}
+    ${CONSTRUCTING+ __DTOR_END__ = .;}
+    *(.lit)
+    *(.shdata)
+  }
+  .shbss SIZEOF(.text) + ADDR(.text) :	{
+    *(.shbss)
+  } 
+  .data  : {
+    *(.data)
+    ${RELOCATING+ __edata  =  .};
+  }
+  .bss   SIZEOF(.data) + ADDR(.data) :
+  { 					
+   *(.bss)
+   *(COMMON)
+     ${RELOCATING+ __end = ALIGN(0x8)};
+  }
+}
+EOF
-- 
cgit v1.2.1