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* Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney2000-05-242-147/+162
* Add missing ChangeLog.Andrew Cagney2000-05-032-1/+25
* Add support for SIGILL (reserved-instruction-exception).Andrew Cagney2000-04-182-2/+12
* * moved misplaced ChangeLog entryFrank Ch. Eigler2000-03-041-0/+5
* When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracingAndrew Cagney2000-02-223-11/+8
* Report SIGBUS and halt simulation when ld/st detect a misaligned address.Andrew Cagney2000-02-093-34/+80
* import gdb-2000-01-05 snapshotJason Molenda2000-01-064-27/+200
* import gdb-1999-12-06 snapshotJason Molenda1999-12-072-0/+27
* import gdb-1999-11-16 snapshotJason Molenda1999-11-174-312/+707
* import gdb-1999-11-01 snapshotJason Molenda1999-11-022-2/+7
* import gdb-1999-09-21Jason Molenda1999-09-222-7/+5
* import gdb-1999-09-13 snapshotJason Molenda1999-09-133-20/+272
* import gdb-1999-09-08 snapshotStan Shebs1999-09-093-160/+176
* import gdb-1999-05-10Stan Shebs1999-05-112-174/+308
* import gdb-19990422 snapshotStan Shebs1999-04-264-2/+46
* Initial creation of sourceware repositoryStan Shebs1999-04-1611-0/+10212
* Initial creation of sourceware repositoryStan Shebs1999-04-1612-9576/+0
* 1999-01-26 Jason Molenda (jsm@bugshack.cygnus.com)Jason Molenda1999-01-272-868/+1058
* Fix PR 17387: ignore auto increment for loads where the destination registerNick Clifton1998-09-301-0/+10
* * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1998-04-265-120/+148
* * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1998-04-243-39/+1786
* * interp.c (struct hash_entry): OPCODE and MASK are unsigned.Andrew Cagney1998-04-241-0/+57
* * configure.in (SIM_AC_OPTION_WARNINGS): Add.Andrew Cagney1998-04-012-0/+8
* Do top level sim-hw module for device tree.Andrew Cagney1998-03-272-34/+136
* Implement "dbt" and "rtd" instructions.Andrew Cagney1998-02-162-15/+40
* Implement separate user (SPU) and interrupt (SPI) stack pointers.Andrew Cagney1998-02-133-0/+15
* Don't abort() when system call is unknown.Andrew Cagney1998-02-112-1/+4
* Ensure zero-hardwired bits in DPSW remain zero.Andrew Cagney1998-02-113-4/+77
* D10v memory map changed. Update.Andrew Cagney1998-02-101-136/+173
* Add config support for the size of the target address and OF cell.Andrew Cagney1998-01-311-0/+4
* Exit status is in r0, not r2Michael Meissner1998-01-261-0/+4
* If DEBUG has 0x20 set, turn traps into batch debuggingMichael Meissner1998-01-251-0/+7
* First round of d10v ABI changesMichael Meissner1998-01-232-68/+78
* * interp.c (UMEM_SEGMENTS): New define, set to 128.Fred Fish1998-01-222-54/+134
* * aclocal.m4: Recognize --enable-maintainer-mode.Doug Evans1998-01-202-43/+90
* Fix typo, REP_S was refering to REP_E register.Andrew Cagney1997-12-082-1/+5
* For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: SteppingAndrew Cagney1997-12-083-87/+165
* Regenerate configure files.Doug Evans1997-12-041-0/+4
* Add DM (bit 4) to PSW. See 7-1 for more info.Andrew Cagney1997-12-043-0/+10
* * d10v_sim.h (SEXT56): Define.Andrew Cagney1997-12-033-54/+48
* * interp.c (sim_resume): Call do_2_short with LEFT_FIRST orFred Fish1997-12-022-26/+36
* For "msbu", subtract unsigned product from ACC,Andrew Cagney1997-12-022-4/+9
* For "mulxu", store unsigned product in ACC.Andrew Cagney1997-12-022-3/+7
* For MACU add unsigned multiply to accumulator.Andrew Cagney1997-12-022-4/+13
* For sub2w, compute carry according to negated addition rules.Andrew Cagney1997-12-022-4/+6
* Rework sim/common/sim-alu.h to differentiate between direcctAndrew Cagney1997-12-012-11/+40
* * simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. SignAndrew Cagney1997-11-101-0/+6
* Correct name of file given in ChangeLog for change: Pass lma_p andAndrew Cagney1997-10-251-1/+1
* Address MSC compiler issues in d10v_sim.hAndrew Cagney1997-10-241-0/+8
* Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file().Andrew Cagney1997-10-222-2/+29
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