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* Add iWMMXt support to ARM simulatorNick Clifton2003-03-271-0/+25
* fix date on latest ChangeLog entry.Nick Clifton2003-03-201-1/+1
* Add Cirrus Maverick support to arm simulatorNick Clifton2003-03-201-0/+24
* (SWIWrite0): Catch big-endian bug when printing charactersNick Clifton2003-03-021-0/+5
* Index: arm/ChangeLogAndrew Cagney2003-02-271-0/+4
* 2003-01-10 Ben Elliston <bje@redhat.com>Ben Elliston2003-01-101-0/+5
* * remove duplicated entry from 2002-05-17 on 2002-05-20.Ben Elliston2003-01-101-23/+1
* Add support for -m option. Fix PR gdb/433.Andrew Cagney2002-09-271-0/+6
* Catch and ignore SWIs of -1, they can be caused by an interrupted systemNick Clifton2002-08-151-0/+5
* Add checks to catch invaliud XScale MIA, MIAPH and MIAxy instructions.Nick Clifton2002-07-051-0/+5
* Set correct value for ADP_Stopped_RunTimeErrorNick Clifton2002-06-211-0/+4
* Import current --enable-gdb-build-warnings.Andrew Cagney2002-06-161-0/+4
* Add the file include/gdb/sim-arm.h defining an enum that specifies theAndrew Cagney2002-06-121-0/+8
* Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney2002-06-091-0/+5
* Set the FSR and FAR registers if a Data Abort is detected.Nick Clifton2002-05-291-0/+5
* Only perform access checks if 'check' is set.Nick Clifton2002-05-271-0/+5
* Thumb BL instruction: Do not set LR to pc + 2, it has already been advanced.Nick Clifton2002-05-271-0/+5
* When decoding a BLX(1) instruction do not add in the second bit of the baseNick Clifton2002-05-231-0/+6
* Simulate XScale BCUMOD registerNick Clifton2002-05-211-0/+6
* Add support for target specific command line switches to old-style simualtors.Nick Clifton2002-05-201-0/+43
* Support the RedBoot SWI in ARM mode and some of its system calls.Nick Clifton2002-05-091-0/+5
* Increase default memory size to 8MB.Anthony Green2002-03-181-0/+4
* * armos.c (SWIWrite0): Use generic host_callback mechanismKeith Seitz2002-02-211-0/+10
* Modify previous patch so that it is only triggered for COFF format executables.Nick Clifton2002-02-051-3/+8
* If a v5 architecture is detected, assume it might be an XScale binary, sinceNick Clifton2002-02-041-0/+6
* Fix parameters passed to CPRead[13] and CPRead[14].Nick Clifton2002-01-101-0/+8
* General format tidy upsNick Clifton2002-01-091-0/+1
* Fix bug detected by GDB testsuite - when fetching registers more than 4Nick Clifton2002-01-091-0/+5
* 2001-11-16 Ben Harris <bjh21@netbsd.org>Ben Harris2001-11-161-0/+6
* Add support for XScale's coprocessor access check register.Nick Clifton2001-10-181-0/+19
* Fix handling of XScale LDRD and STRD instructions with post indexed addressin...Nick Clifton2001-05-111-0/+5
* Check Mode not Bank in order to determine rocesor mode.Nick Clifton2001-05-081-0/+5
* * XScale coprocessor support.Matthew Green2001-04-181-0/+41
* Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton2001-03-201-0/+5
* Fix BLX(1) for ThumbNick Clifton2001-03-061-0/+6
* Add support for disabling alignment checks when performing GDB interfaceNick Clifton2001-02-281-0/+30
* Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton2001-02-161-0/+5
* Add code to preserve processor mode when a prefetchNick Clifton2001-02-151-0/+3
* Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton2001-02-141-0/+5
* Prevent Aborts from happening whilst emulating a SWINick Clifton2001-02-141-0/+7
* Fix definition of NEGBRANCHNick Clifton2001-02-121-0/+4
* Update base address register after restoring register bank.Nick Clifton2001-02-011-0/+7
* Detect installation of SWI vector by running program as well as loading program.Nick Clifton2001-02-011-0/+9
* Fix test for StoreDouble Instruction.Nick Clifton2000-12-191-0/+5
* Add 0x91 as an FPE SWI.Nick Clifton2000-12-111-0/+4
* Add emulation of double word load and store instructions.Nick Clifton2000-12-081-0/+8
* Suppress support of DEMON swi's in XScale mode.Nick Clifton2000-12-031-0/+6
* Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton2000-11-301-1/+27
* Replace StrongARM property with v4 and v5 properties.Nick Clifton2000-09-151-0/+24
* Compute write back value for post increment loads beforeNick Clifton2000-08-151-0/+6
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