summaryrefslogtreecommitdiffstats
path: root/gas/testsuite
Commit message (Collapse)AuthorAgeFilesLines
* * config/tc-arm.c (do_t_strexd): RemoveJie Zhang2010-02-264-24/+32
| | | | | | | | | operand[1] != operand[2] contraint. testsuite/ * gas/arm/thumb32.s, gas/arm/thumb32.d: Add a new test for strexd. * gas/arm/thumb32.l: Adjust.
* 2010-02-26 Jie Zhang <jie@codesourcery.com>Jie Zhang2010-02-264-0/+14
| | | | | | | | | | * config/tc-arm.c (do_neon_ld_st_interleave): Reject bad alignment. testsuite/ * gas/arm/neon-ldst-align-bad.d: New test. * gas/arm/neon-ldst-align-bad.l: New test. * gas/arm/neon-ldst-align-bad.s: New test.
* * config/tc-mips.c (mips_fix_loongson2f, mips_fix_loongson2f_nop,Nick Clifton2010-02-256-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | mips_fix_loongson2f_jump): New variables. (md_longopts): Add New options -mfix-loongson2f-nop/jump, -mno-fix-loongson2f-nop/jump. (md_parse_option): Initialize variables via above options. (options): New enums for the above options. (md_begin): Initialize nop_insn from LOONGSON2F_NOP_INSN. (fix_loongson2f, fix_loongson2f_nop, fix_loongson2f_jump): New functions. (append_insn): call fix_loongson2f(). (mips_handle_align): Replace the implicit nops. * config/tc-mips.h (MAX_MEM_FOR_RS_ALIGN_CODE): Modified for the new mips_handle_align(). * doc/c-mips.texi: Document the new options. * gas/mips/loongson-2f-2.s: New test of -mfix-loongson2f-nop. * gas/mips/loongson-2f-2.d: Likewise. * gas/mips/loongson-2f-3.s: New test of -mfix-loongson2f-jump. * gas/mips/loongson-2f-3.d: Likewise. * gas/mips/mips.exp: Run the new tests. * opcode/mips.h (LOONGSON2F_NOP_INSN): New macro.
* PR binutils/6773Nick Clifton2010-02-244-75/+84
| | | | | | | | | | | | * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with <prefix>asx. Replace <prefix>subaddx with <prefix>sax. (thumb32_opcodes): Likewise. * gas/arm/arch7em.d: Replace expected disassembly of <prefix>addsubx with <prefix>asx. Also replace <prefix>subaddx with <prefix>sax. * gas/arm/archv6.d: Likewise. * gas/arm/thumb32.d: Likewise.
* gas/Daniel Gutson2010-02-234-0/+19
| | | | | | | | | * config/tc-arm.c (do_rd_rm_rn): Added warning. gas/testsuite/ * gas/arm/depr-swp.d: New test case. * gas/arm/depr-swp.s: New file. * gas/arm/depr-swp.l: New file.
* * gas/arm/thumb2_bcond.d: Allow for varying number of nops at theNick Clifton2010-02-232-2/+8
| | | | | end of the section depending upon the target of the arm assembler being tested.
* * bfd/elf32-arm.c (elf32_arm_merge_eabi_attributes): Add support forMatthew Gretton-Dann2010-02-182-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merging Tag_DIV_use, Tag_MPextension_use, and Tag_MPextension_use_legacy tags. * binutils/readelf.c (arm_attr_tag_Advanced_SIMD_arch): Add description of newly permitted attribute values. (arm_attr_tag_Virtualization_use): Likewise. (arm_attr_tag_DIV_use): Add description of new attribute. (arm_attr_tag_MPextension_use_legacy): Likewise. * gas/config/tc-arm.c (arm_convert_symbolic_attribute): Add Tag_DIV_use. * gas/doc/c-arm.texi: Likewise. * gas/testsuite/gas/arm/attr-order.d: Fix test for new names for attribute values. * include/elf/arm.h (Tag_MPextension_use): Renumber. (Tag_DIV_use): Add. (Tag_MPextension_use_legacy): Likewise. * ld/testsuite/ld-arm/attr-merge-3.attr: Fix test for new attribute values. * ld/testsuite/ld-arm/attr-merge-3b.s: Likewise. * ld/testsuite/ld-arm/attr-merge-unknown-1.d: Fix test now that 42 is a recognised attribute ID. * ld/testsuite/ld-arm/attr-merge-unknown-1.s: Likewise. * ld/testsuite/ld-arm/attr-merge-6.attr: New test. * ld/testsuite/ld-arm/attr-merge-6a.s: Likewise. * ld/testsuite/ld-arm/attr-merge-6b.s: Likewise. * ld/testsuite/ld-arm/attr-merge-7.attr: Likewise. * ld/testsuite/ld-arm/attr-merge-7a.s: Likewise. * ld/testsuite/ld-arm/attr-merge-7b.s: Likewise. * ld/testsuite/ld-arm/arm-elf.exp: Run the new tests.
* *** empty log message ***Daniel Gutson2010-02-121-0/+15
|
* gas/Daniel Gutson2010-02-1212-76/+1118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/tc-arm.c (asm_opcode): operands type change. (BAD_PC_ADDRESSING): New macro message. (BAD_PC_WRITEBACK): Likewise. (MIX_ARM_THUMB_OPERANDS): New macro. (operand_parse_code): Added enum values. (parse_operands): Added thumb/arm distinction, plus new enum values handling. (encode_arm_addr_mode_2): Validations enhanced. (encode_arm_addr_mode_3): Likewise. (do_rm_rd_rn): Likewise. (encode_thumb32_addr_mode): Likewise. (do_t_ldrex): Likewise. (do_t_ldst): Likewise. (do_t_strex): Likewise. (md_assemble): Call parse_operands with a new parameter. (OPS_1): New macro. (OPS_2): Likewise. (OPS_3): Likewise. (OPS_4): Likewise. (OPS_5): Likewise. (OPS_6): Likewise. (insns): Updated insns operands. gas/testsuite/ * gas/arm/sp-pc-validations-bad.d: New testcase. * gas/arm/sp-pc-validations-bad.l: New file. * gas/arm/sp-pc-validations-bad.s: New file. * gas/arm/sp-pc-validations-bad-t.d: New testcase. * gas/arm/sp-pc-validations-bad-t.l: New file. * gas/arm/sp-pc-validations-bad-t.s: New file. * gas/arm/sp-pc-usage-t.d: Removed invalid insns. * gas/arm/sp-pc-usage-t.s: Likewise. * gas/arm/unpredictable.d: Likewise. * gas/arm/unpredictable.s: Likewise. * gas/arm/thumb2_bcond.d: Added test. * gas/arm/thumb2_bcond.s: Likewise.
* gas/Tristan Gingold2010-02-124-0/+71
| | | | | | | | | | | | | | | | | | | | 2010-02-12 Tristan Gingold <gingold@adacore.com> Douglas B Rupp <rupp@gnat.com> * config/tc-ia64.c (enum reloc_func): Add FUNC_SLOTCOUNT_RELOC. (DUMMY_RELOC_IA64_SLOTCOUNT): Added. (pseudo_func): Add an entry for slotcount. (md_begin): Initialize slotcount pseudo symbol. (ia64_parse_name): Handle @slotcount parameter. (ia64_gen_real_reloc_type): Handle slotcount. (md_apply_fix): Ditto. * doc/c-ia64.texi (IA-64-Relocs): Document @slotcount. gas/testsuite/ 2010-02-12 Tristan Gingold <gingold@adacore.com> * gas/ia64/slotcount.s, gas/ia64/slotcount.s: New test. * gas/ia64/ia64.exp: Add slotcount test (vms only).
* 2010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2010-02-115-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sebastian Pop <sebastian.pop@amd.com> gas: * config/tc-i386.c (vec_imm4) New operand type. (fits_in_imm4): New. (VEX_check_operands): New. (check_reverse): Call VEX_check_operands. (build_modrm_byte): Reintroduce code for 5 operand insns. Fix whitespace. gas/testsuite: * gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests. * gas/i386/x86-64-xop.s: Likewise. * gas/i386/xop.d: Likewise. * gas/i386/xop.s: Likewise. opcodes: * i386-dis.c (OP_EX_VexImmW): Reintroduced function to handle 5th imm8 operand. (PREFIX_VEX_3A48): Added. (PREFIX_VEX_3A49): Added. (VEX_W_3A48_P_2): Added. (VEX_W_3A49_P_2): Added. (prefix table): Added entries for PREFIX_VEX_3A48 and PREFIX_VEX_3A49. (vex table): Added entries for VEX_W_3A48_P_2 and and VEX_W_3A49_P_2. * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4 for Vec_Imm4 operands. * i386-opc.h (enum): Added Vec_Imm4. (i386_operand_type): Added vec_imm4. * i386-opc.tbl: Add entries for vpermilp[ds]. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
* 2010-02-08 Christophe Lyon <christophe.lyon@st.com>Christophe Lyon2010-02-094-0/+186
| | | | | | | | | | | | | | gas/ * config/tc-arm.c (md_pcrel_from_section): Keep base to zero for non-local branches (BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BLX, BFD_RELOC_ARM_PCREL_BLX, BFD_RELOC_ARM_PCREL_CALL) gas/testsuite/ * gas/arm/branch-reloc.s, gas/arm/branch-reloc.d, gas/arm/branch-reloc.l: New tests and expected results with all variants of call: ARM/Thumb, local/global, inter/intra-section, using BL/BLX.
* * objdump.c (disassemble_bytes): Clear aux->reloc before printingNick Clifton2010-02-086-33/+41
| | | | | | | | a new address, so as not to reuse a previous, non-related reloc. * gas/arm/arm-it-auto.d, gas/arm/bl-local-v4t.d, gas/arm/blx-local.d, gas/arm/thumb-w-good.d: Update expected results.
* include/Alan Modra2010-02-084-0/+534
| | | | | | | | | | | | | | | | | | | * opcode/ppc.h (PPC_OPCODE_TITAN): Define. bfd/ * archures.c (bfd_mach_ppc_titan): Define. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add titan entry. opcodes/ * ppc-dis.c (ppc_opts): Add titan entry. * ppc-opc.c (TITAN, MULHW): Define. (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). gas/ * config/tc-ppc.c (md_show_usage): Mention -mtitan. Don't use tabs. (ppc_mach): Handle titan. * doc/c-ppc.texi: Mention -mtitan. gas/testsuite/ * gas/ppc/titan.d, * gas/ppc/titan.s: New test. * gas/ppc/ppc.exp: Run it.
* 2010-02-03 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2010-02-034-6/+14
| | | | | | | | | | | | | | | | | | | | gas/ * config/tc-i386.c (cpu_arch): Change amdfam15 to bdver1. (i386_align_code): Rename PROCESSOR_AMDFAM15 to PROCESSOR_BDVER1. * config/tc-i386.h (processor_type): Same. * doc/c-i386.texi: Change amdfam15 to bdver1. opcodes/ * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS to CPU_BDVER1_FLAGS * i386-init.h: Regenerated. testsuite/ * gas/i386/i386.exp: Rename amdfam15 test cases to bdver1. * gas/i386/x86-64-nops-1-amdfam15.d: Renamed test case to gas/i386/x86-64-nops-1-bdver1.d. * gas/i386/nops-1-amdfam15.d: Renamed test case to gas/i386/nops-1-bdver1.d.
* gas/testsuite/Daniel Jacobowitz2010-01-296-4/+48
| | | | | | | | | | | | | | | | | | * gas/arm/dis-data.d: Update test name. Do not expect .word output. * gas/arm/dis-data2.d, gas/arm/dis-data2.s, gas/arm/dis-data3.d, gas/arm/dis-data3.s: New tests. opcodes/ * opcodes/arm-dis.c (struct arm_private_data): New. (print_insn_coprocessor, print_insn_arm): Update to use struct arm_private_data. (is_mapping_symbol, get_map_sym_type): New functions. (get_sym_code_type): Check the symbol's section. Do not check mapping symbols. (print_insn): Default to disassembling ARM mode code. Check for mapping symbols separately from other symbols. Use struct arm_private_data.
* PR 11136Nick Clifton2010-01-293-0/+10
| | | | | | | * config/tc-arm.c (neon_check_type): Handle a neon_shape value of NS_NULL. * gas/arm/neon-omit.s: Add instruction that causes crash. * gas/arm/neon-omit.d: Add expected disassembly.
* * gas/pe/section-align-1.d: Don't test section flags.Dave Korn2010-01-283-25/+30
| | | | * gas/pe/section-align-2.d: Likewise.
* Allow VL=1 on scalar FMA instructions.H.J. Lu2010-01-288-0/+812
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-01-28 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/fma-scalar-intel.d: New. * gas/i386/fma-scalar.d: Likewise. * gas/i386/fma-scalar.s: Likewise. * gas/i386/x86-64-fma-scalar-intel.d: Likewise. * gas/i386/x86-64-fma-scalar.d: Likewise. * gas/i386/x86-64-fma-scalar.s: Likewise. * gas/i386/i386.exp: Run fma-scalar, fma-scalar-intel, x86-64-fma-scalar and x86-64-fma-scalar-intel. opcodes/ 2010-01-28 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (EXVexWdqScalar): New. (vex_scalar_w_dq_mode): Likewise. (prefix_table): Update entries for PREFIX_VEX_3899, PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F, PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD, PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB, PREFIX_VEX_38BD and PREFIX_VEX_38BF. (intel_operand_size): Handle vex_scalar_w_dq_mode. (OP_EX): Likewise.
* PR 11225Nick Clifton2010-01-283-8/+16
| | | | | | | | | | | | | | * objdump.c (only): Replace with linked list. (only_size, only_used): Replace with only_list. (process_section_p): Set seen field on matches sections. (add_only): New function. (free_only_list): New function. (disassemble_section): Check only_list. (main): Use add_only and free_only_list. * gas/pe/aligncomm-c.d: Dump all sections. * ld-sh/refdbg-0-dso.d: Dump all sections.
* gas/ChangeLog:Dave Korn2010-01-276-0/+119
| | | | | | | | | | | | | | | * NEWS: Mention new feature. * config/obj-coff.c (obj_coff_section): Accept digits and use to override default section alignment power if specified. * doc/as.texinfo (.section directive): Update documentation. gas/testsuite/ChangeLog: * gas/pe/section-align-1.s: New test source file. * gas/pe/section-align-1.d: Likewise control script. * gas/pe/section-align-2.s: Likewise ... * gas/pe/section-align-2.d: ... and likewise. * gas/pe/pe.exp: Invoke new testcases.
* Allow VL=1 on AVX scalar instructions.H.J. Lu2010-01-278-0/+3784
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (avxscalar): New. (OPTION_MAVXSCALAR): Likewise. (build_vex_prefix): Select vector_length for scalar instructions based on avxscalar. (md_longopts): Add OPTION_MAVXSCALAR. (md_parse_option): Handle OPTION_MAVXSCALAR. (md_show_usage): Add -mavxscalar=. * doc/c-i386.texi: Document -mavxscalar=. gas/testsuite/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/avx-scalar-intel.d: New. * gas/i386/avx-scalar.d: Likewise. * gas/i386/avx-scalar.s: Likewise. * gas/i386/x86-64-avx-scalar-intel.d: Likewise. * gas/i386/x86-64-avx-scalar.d: Likewise. * gas/i386/x86-64-avx-scalar.s: Likewise. * gas/i386/i386.exp: Run avx-scalar, avx-scalar-intel, x86-64-avx-scalar and x86-64-avx-scalar-intel. opcodes/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (XMScalar): New. (EXdScalar): Likewise. (EXqScalar): Likewise. (EXqScalarS): Likewise. (VexScalar): Likewise. (EXdVexScalarS): Likewise. (EXqVexScalarS): Likewise. (XMVexScalar): Likewise. (scalar_mode): Likewise. (d_scalar_mode): Likewise. (d_scalar_swap_mode): Likewise. (q_scalar_mode): Likewise. (q_scalar_swap_mode): Likewise. (vex_scalar_mode): Likewise. (vex_len_table): Duplcate entries for VEX_LEN_10_P_1, VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1, VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0, VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3, VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3, VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1, VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1, VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2, VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1, VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2. (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3, VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2, VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3, VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3, VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3, VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3, VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3, VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3, VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2. (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode, q_scalar_swap_mode. (OP_XMM): Handle scalar_mode. (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode and q_scalar_swap_mode. (OP_VEX): Handle vex_scalar_mode.
* Add more AVX tests.H.J. Lu2010-01-237-84/+282
| | | | | | | | | | | | 2010-01-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/avx.s: Add more tests. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/avx-intel.d: Updated. * gas/i386/avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise.
* bfd/Richard Sandiford2010-01-234-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * coff-rs6000.c (xcoff_howto_table): Change size to 0 and bitsize to 1. (_bfd_xcoff_reloc_type_lookup): Handle BFD_RELOC_NONE. * coff64-rs6000.c (xcoff64_howto_table): Change size to 0 and bitsize to 1. (xcoff64_reloc_type_lookup): Handle BFD_RELOC_NONE. gas/ * write.h (fix_at_start): Declare. * write.c (fix_new_internal): Add at_beginning parameter. Use it instead of REVERSE_SORT_RELOCS. Fix the handling of seg_fix_tailP for the at_beginning/REVERSE_SORT_RELOCS case. (fix_new, fix_new_exp): Update accordingly. (fix_at_start): New function. * config/tc-ppc.c (md_pseudo_table): Add .ref to the OBJ_XCOFF section. (ppc_ref): New function, for OBJ_XCOFF. (md_apply_fix): Handle BFD_RELOC_NONE for OBJ_XCOFF. * config/te-i386aix.h (REVERSE_SORT_RELOCS): Remove #undef. gas/testsuite/ * gas/ppc/xcoff-ref-1.s, gas/ppc/xcoff-ref-1.l: New test. * gas/ppc/aix.exp: Run it. ld/testsuite/ * ld-powerpc/aix-ref-1-32.od, ld-powerpc/aix-ref-1-64.od, ld-powerpc/aix-ref-1.s: New tests. * ld-powerpc/aix52.exp: Run them.
* Correct month.H.J. Lu2010-01-211-1/+1
|
* Add xsave64 and xrstor64.H.J. Lu2010-01-214-12/+122
| | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-xsave.s: Add tests for xsave64 and xrstor64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. * i386-opc.tbl: Add xsave64 and xrstor64. * i386-tbl.h: Regenerated.
* Add changelog entries for PR 11109. Patch itself was accidentally committed ↵Nick Clifton2010-01-201-0/+6
| | | | | | earlier. Remove Spurious whitespace in ChangeLog-2009.
* 2010-01-15 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop2010-01-155-0/+2057
| | | | | | | | | | | | | | | | gas/ * config/tc-i386.c (md_assemble): Before accessing the IMM field check that it's not an XOP insn. gas/testsuite/ * gas/i386/x86-64-xop.d: Add missing patterns. * gas/i386/x86-64-xop.s: Same. * gas/i386/xop.d: Same. * gas/i386/xop.s: Same. opcodes/ * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. * i386-tbl.h: Regenerated.
* gas/testsuite/Daniel Jacobowitz2010-01-132-0/+5
| | | | * gas/arm/thumb-nop.s: Add .syntax unified.
* gas/Daniel Jacobowitz2010-01-136-6/+29
| | | | | | | | | | | | | | * config/tc-arm.c (do_t_nop): Correct check for Thumb-2 NOP. gas/testsuite/ * gas/arm/thumb-nop.d, gas/arm/thumb-nop.s: New test. * gas/arm/relax_branch_align.d: Expect a default NOP instruction. * gas/arm/vfp1_t2.d, gas/arm/vfp1xD_t2.d: Specify a CPU with Thumb-2. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests): Assemble Cortex-A8 tests with -mcpu=cortex-a8.
* * config/tc-h8300.c (h8300_elf_section): New function - issue aNick Clifton2010-01-135-2/+27
| | | | | | | | | | | | | | | | | | warning message if a new section is created without setting any attributes for it. (md_pseudo_table): Intercept section creation pseudos. (md_pcrel_from): Replace abort with an error message. * config/obj-elf.c (obj_elf_section_name): Export this function. * config/obj-elf.h (obj_elf_section_name): Prototype. * gas/elf/section0.d: Skip this test for the h8300. * gas/elf/section1.d: Likewise. * gas/elf/section6.d: Likewise. * gas/elf/elf.exp: Skip section2 and section5 tests when the target is the h8300. * ld-scrips/sort.exp: Skip these tests when the target is the h8300.
* 2010-01-06 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2010-01-064-0/+332
| | | | | | | | | | | | | | | | gas/ * config/tc-i386.c (cpu_arch): Add amdfam15. (i386_align_code): Add PROCESSOR_AMDFAM15 cases. * config/tc-i386.h (processor_type): Add PROCESSOR_AMDFAM15. * doc/c-i386.texi: Add amdfam15. opcodes/ * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS. * i386-init.h: Regenerated. testsuite/ * gas/i386/i386.exp: Add new amdfam15 test cases. * gas/i386/nops-1-amdfam15.d: New.
* * arm-dis.c (print_insn): Fixed search for nextNick Clifton2010-01-065-16/+36
| | | | | | | | symbol and data dumping condition, and the initial mapping symbol state. * gas/arm/dis-data.d: New test case. * gas/arm/dis-data.s: New file.
* 2010-01-04 Daniel Gutson <dgutson@codesourcery.com>Daniel Gutson2010-01-043-0/+30
| | | | | | | | | | | | | | gas/ * config/tc-arm.c (do_neon_logic): Accept imm value in the third operand too. (operand_parse_code): OP_RNDQ_IMVNb renamed to OP_RNDQ_Ibig. (parse_operands): OP_NILO case removed, applied renaming. (insns): Neon shape changed for some logic instructions. gas/testsuite/ * gas/arm/neon-logic.d: New test case. * gas/arm/neon-logic.s: New file.
* 2010-01-04 Daniel Gutson <dgutson@codesourcery.com>Daniel Gutson2010-01-044-0/+51
| | | | | | | | | | | gas/ * config/tc-arm.c (do_neon_ldx_stx): Added validation for vector load/store insns. gas/testsuite/ * gas/arm/neon-addressing-bad.d: New test case. * gas/arm/neon-addressing-bad.s: New file. * gas/arm/neon-addressing-bad.l: New file.
* 2010-01-03 Daniel Gutson <dgutson@codesourcery.com>Daniel Gutson2010-01-044-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-arm.c (struct arm_it): New flag 'is_neon'. (NEON_ENC_*): Macros renamed to _NEON_ENC_*. (NEON_ENCODE): New macro. (check_neon_suffixes): New macro. (do_vfp_cond_or_thumb): Set the 'is_neon' flag. (do_vfp_nsyn_opcode): Likewise. (do_vfp_nsyn_nmul): Use the new 'NEON_ENCODE' macro. (do_vfp_nsyn_cmp): Likewise. (do_neon_shl_imm): Likewise. (do_neon_qshl_imm): Likewise. (neon_dyadic_misc): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_qdmulh): Likewise. (do_neon_qmovn): Likewise. (do_neon_qmovun): Likewise. (do_neon_movn): Likewise. (neon_mac_reg_scalar_long): Likewise. (do_neon_vmull): Likewise. (do_neon_trn): Likewise. (do_neon_ldx_stx): Likewise. (neon_dp_fixup): Changed signature and set the flag. (neon_three_same): Call the above with new signature. (neon_two_same): Likewise. (neon_imm_shift): Likewise. (neon_mul_mac): Likewise. (do_neon_abs_neg): Likewise. (neon_mixed_length): Likewise. (do_neon_ext): Likewise. (do_neon_mov): Likewise. (do_neon_tbl_tbx): Likewise. (do_neon_logic): Likewise, and use the new 'NEON_ENCODE' macro. (neon_compare): Likewise. (do_neon_shll): Likewise. (do_neon_cvt): Likewise. (do_neon_mvn): Likewise. (do_neon_dup): Likewise. (md_assemble): Call check_neon_suffixes (). gas/testsuite/ * gas/arm/neon-suffix-bad.d: New test case. * gas/arm/neon-suffix-bad.s: New file. * gas/arm/neon-suffix-bad.l: New file.
* Move 2009 binutils ChangeLog to ChangeLog-2009.H.J. Lu2010-01-012-1764/+1773
|
* * gas/xc16x/xc16x.exp (*): Add missing " in timeout cases.Doug Evans2009-12-192-41/+45
|
* * gas/mips/eret-2.s: Add an instruction to fill a branch delayMaciej W. Rozycki2009-12-193-1/+8
| | | | | slot. * gas/mips/eret-2.d: Adjust accordingly.
* gas/Maciej W. Rozycki2009-12-194-0/+41
| | | | | | | | | | * config/tc-mips.c (s_mips_ent): Also set BSF_FUNCTION for ".aent". gas/testsuite/ * gas/mips/aent.d: New test. * gas/mips/aent.s: Source for the new test. * gas/mips/mips.exp: Run it.
* PR binutils/10924Nick Clifton2009-12-173-29/+35
| | | | | | | | | | | | | | * config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination register. (do_mrs): Likewise. (do_mul): Likewise. * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce unique register numbers. Extend support for %<>R format to thumb32 and coprocessor instructions. * gas/arm/unpredictable.s: Add more unpredictable instructions. * gas/arm/unpredictable.d: Add expected disassemblies.
* PR binutils/10924Nick Clifton2009-12-143-0/+169
| | | | | | | | | | * arm-dis.c (arm_opcodes): Specify %R in cases where using r15 results in unpredictable behaviour. (print_insn_arm): Handle %R. * gas/arm/unpredictable.s: New test case - checks the disassembly of instructions with unpredictable behaviour. * gas/arm/unpredictable.d: New file - expected disassembly.
* 2009-12-11 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2009-12-115-0/+15
| | | | | | | | | | | | | gas/testsuite/ * gas/i386/fma4.d: Add test cases. * gas/i386/fma4.s: Add test cases. * gas/i386/x86-64-fma4.d: Add test cases. * gas/i386/x86-64-fma4.s: Add test cases. opcodes/ * i386-dis.c (get_vex_imm8): Extend logic to apply in all cases, to avoid fetching ahead for the immediate bytes when OP_E_memory has already been called. Fix indentation.
* Call symbol_same_p to check to if 2 symbols are the same.H.J. Lu2009-12-083-0/+25
| | | | | | | | | | | | | | | | | | | | | gas/ 2009-12-07 H.J. Lu <hongjiu.lu@intel.com> PR gas/11037 * expr.c (resolve_expression): Call symbol_same_p to check if 2 symbols are the same. * symbols.c (symbol_same_p): New. * symbols.h (symbol_same_p): Likewise. gas/testsuite/ 2009-12-07 H.J. Lu <hongjiu.lu@intel.com> PR gas/11037 * gas/i386/intelpic.s: Add testcases. * gas/i386/intelpic.d: Updated.
* Support fxsave64 and fxrstor64.H.J. Lu2009-12-046-4/+157
| | | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel. * gas/i386/rex.d: Updated for fxsave64. * gas/i386/x86-64-fxsave-intel.d: New. * gas/i386/x86-64-fxsave.d: Likewise. * gas/i386/x86-64-fxsave.s: Likewise. opcodes/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (FXSAVE_Fixup): New. (FXSAVE): Likewise. (mod_table): Use FXSAVE on fxsave and fxrstor. * i386-opc.tbl: Add fxsave64 and fxrstor64. * i386-tbl.h: Regenerated.
* PR gas/11013Nick Clifton2009-12-023-8/+15
| | | | | | | | | | | * arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB and QDSUB. * gas/arm/arch7em.d: Update expected disassembly. * gas/arm/thumb32.d: Likewise. * config/tc-arm.c (do_t_simd2): New function. (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
* 2009-11-17 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2009-11-254-9/+22
| | | | | | | | | | | | | | | Sebastian Pop <sebastian.pop@amd.com> gas/testsuite/ * gas/i386/x86-64-fma4.d: Add new patterns. * gas/i386/x86-64-fma4.s: Same. * gas/i386/x86-64-xop.d: Adjusted. opcodes/ * i386-dis.c (get_vex_imm8): Increase bytes_before_imm when decoding the second source operand from the immediate byte. (OP_EX_VexW): Pass an extra integer to identify the second and third source arguments.
* Allow lock on cmpxch16b.H.J. Lu2009-11-194-0/+12
| | | | | | | | | | | | | | | | | gas/testsuite/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/lock-1.s: Add cmpxchg16b test. * gas/i386/lock-1-intel.d: Updated. * gas/i386/lock-1.d: Likewise. opcodes/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add IsLockable to cmpxch16b. * i386-tbl.h: Regenerated.
* PR binutils/10924Nick Clifton2009-11-197-29/+41
| | | | | | | | | | | | | | | * gas/arm/arch4t-eabi.d: Restore previous expected dissambly of instructions using Immediate Offset addressing with an offset of zero. * gas/arm/arch4t.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/xscale.d: Likewise. * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and tst instructions. PR binutils/10924 * arm-dis.c (print_insn_arm): Do not print an offset of zero when decoding Immediaate Offset addressing.
* 2009-11-18 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop2009-11-192-84/+88
| | | | | | | | | | | | opcodes/ PR binutils/10973 * i386-dis.c (get_vex_imm8): Do not increment codep. Avoid incrementing bytes_before_imm when OP_E_memory has already forwarded the codep pointer. (OP_EX_VexW): Increment codep to skip mod/rm byte. gas/testsuite/ * gas/i386/x86-64-xop.d: Update patterns.
OpenPOWER on IntegriCloud